diff options
Diffstat (limited to 'drivers/net/wireless/ipw2200.h')
| -rw-r--r-- | drivers/net/wireless/ipw2200.h | 579 |
1 files changed, 412 insertions, 167 deletions
diff --git a/drivers/net/wireless/ipw2200.h b/drivers/net/wireless/ipw2200.h index 5b00882133f..1c98db0652c 100644 --- a/drivers/net/wireless/ipw2200.h +++ b/drivers/net/wireless/ipw2200.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved. + Copyright(c) 2003 - 2005 Intel Corporation. All rights reserved. This program is free software; you can redistribute it and/or modify it under the terms of version 2 of the GNU General Public License as @@ -34,7 +34,6 @@ #include <linux/config.h> #include <linux/init.h> -#include <linux/version.h> #include <linux/pci.h> #include <linux/netdevice.h> #include <linux/ethtool.h> @@ -50,6 +49,7 @@ #include <asm/io.h> #include <net/ieee80211.h> +#include <net/ieee80211_radiotap.h> #define DRV_NAME "ipw2200" @@ -161,6 +161,16 @@ enum connection_manager_assoc_states { * TX Queue Flag Definitions */ +/* tx wep key definition */ +#define DCT_WEP_KEY_NOT_IMMIDIATE 0x00 +#define DCT_WEP_KEY_64Bit 0x40 +#define DCT_WEP_KEY_128Bit 0x80 +#define DCT_WEP_KEY_128bitIV 0xC0 +#define DCT_WEP_KEY_SIZE_MASK 0xC0 + +#define DCT_WEP_KEY_INDEX_MASK 0x0F +#define DCT_WEP_INDEX_USE_IMMEDIATE 0x20 + /* abort attempt if mgmt frame is rx'd */ #define DCT_FLAG_ABORT_MGMT 0x01 @@ -168,7 +178,8 @@ enum connection_manager_assoc_states { #define DCT_FLAG_CTS_REQUIRED 0x02 /* use short preamble */ -#define DCT_FLAG_SHORT_PREMBL 0x04 +#define DCT_FLAG_LONG_PREAMBLE 0x00 +#define DCT_FLAG_SHORT_PREAMBLE 0x04 /* RTS/CTS first */ #define DCT_FLAG_RTS_REQD 0x08 @@ -185,9 +196,23 @@ enum connection_manager_assoc_states { /* ACK rx is expected to follow */ #define DCT_FLAG_ACK_REQD 0x80 +/* TX flags extension */ #define DCT_FLAG_EXT_MODE_CCK 0x01 #define DCT_FLAG_EXT_MODE_OFDM 0x00 +#define DCT_FLAG_EXT_SECURITY_WEP 0x00 +#define DCT_FLAG_EXT_SECURITY_NO DCT_FLAG_EXT_SECURITY_WEP +#define DCT_FLAG_EXT_SECURITY_CKIP 0x04 +#define DCT_FLAG_EXT_SECURITY_CCM 0x08 +#define DCT_FLAG_EXT_SECURITY_TKIP 0x0C +#define DCT_FLAG_EXT_SECURITY_MASK 0x0C + +#define DCT_FLAG_EXT_QOS_ENABLED 0x10 + +#define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00 +#define DCT_FLAG_EXT_HC_SIFS 0x20 +#define DCT_FLAG_EXT_HC_PIFS 0x40 + #define TX_RX_TYPE_MASK 0xFF #define TX_FRAME_TYPE 0x00 #define TX_HOST_COMMAND_TYPE 0x01 @@ -233,6 +258,117 @@ enum connection_manager_assoc_states { #define DCR_TYPE_SNIFFER 0x06 #define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS +/* QoS definitions */ + +#define CW_MIN_OFDM 15 +#define CW_MAX_OFDM 1023 +#define CW_MIN_CCK 31 +#define CW_MAX_CCK 1023 + +#define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM +#define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM +#define QOS_TX2_CW_MIN_OFDM ( (CW_MIN_OFDM + 1) / 2 - 1 ) +#define QOS_TX3_CW_MIN_OFDM ( (CW_MIN_OFDM + 1) / 4 - 1 ) + +#define QOS_TX0_CW_MIN_CCK CW_MIN_CCK +#define QOS_TX1_CW_MIN_CCK CW_MIN_CCK +#define QOS_TX2_CW_MIN_CCK ( (CW_MIN_CCK + 1) / 2 - 1 ) +#define QOS_TX3_CW_MIN_CCK ( (CW_MIN_CCK + 1) / 4 - 1 ) + +#define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM +#define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM +#define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM +#define QOS_TX3_CW_MAX_OFDM ( (CW_MIN_OFDM + 1) / 2 - 1 ) + +#define QOS_TX0_CW_MAX_CCK CW_MAX_CCK +#define QOS_TX1_CW_MAX_CCK CW_MAX_CCK +#define QOS_TX2_CW_MAX_CCK CW_MIN_CCK +#define QOS_TX3_CW_MAX_CCK ( (CW_MIN_CCK + 1) / 2 - 1 ) + +#define QOS_TX0_AIFS (3 - QOS_AIFSN_MIN_VALUE) +#define QOS_TX1_AIFS (7 - QOS_AIFSN_MIN_VALUE) +#define QOS_TX2_AIFS (2 - QOS_AIFSN_MIN_VALUE) +#define QOS_TX3_AIFS (2 - QOS_AIFSN_MIN_VALUE) + +#define QOS_TX0_ACM 0 +#define QOS_TX1_ACM 0 +#define QOS_TX2_ACM 0 +#define QOS_TX3_ACM 0 + +#define QOS_TX0_TXOP_LIMIT_CCK 0 +#define QOS_TX1_TXOP_LIMIT_CCK 0 +#define QOS_TX2_TXOP_LIMIT_CCK 6016 +#define QOS_TX3_TXOP_LIMIT_CCK 3264 + +#define QOS_TX0_TXOP_LIMIT_OFDM 0 +#define QOS_TX1_TXOP_LIMIT_OFDM 0 +#define QOS_TX2_TXOP_LIMIT_OFDM 3008 +#define QOS_TX3_TXOP_LIMIT_OFDM 1504 + +#define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM +#define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM +#define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM +#define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM + +#define DEF_TX0_CW_MIN_CCK CW_MIN_CCK +#define DEF_TX1_CW_MIN_CCK CW_MIN_CCK +#define DEF_TX2_CW_MIN_CCK CW_MIN_CCK +#define DEF_TX3_CW_MIN_CCK CW_MIN_CCK + +#define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM +#define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM +#define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM +#define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM + +#define DEF_TX0_CW_MAX_CCK CW_MAX_CCK +#define DEF_TX1_CW_MAX_CCK CW_MAX_CCK +#define DEF_TX2_CW_MAX_CCK CW_MAX_CCK +#define DEF_TX3_CW_MAX_CCK CW_MAX_CCK + +#define DEF_TX0_AIFS 0 +#define DEF_TX1_AIFS 0 +#define DEF_TX2_AIFS 0 +#define DEF_TX3_AIFS 0 + +#define DEF_TX0_ACM 0 +#define DEF_TX1_ACM 0 +#define DEF_TX2_ACM 0 +#define DEF_TX3_ACM 0 + +#define DEF_TX0_TXOP_LIMIT_CCK 0 +#define DEF_TX1_TXOP_LIMIT_CCK 0 +#define DEF_TX2_TXOP_LIMIT_CCK 0 +#define DEF_TX3_TXOP_LIMIT_CCK 0 + +#define DEF_TX0_TXOP_LIMIT_OFDM 0 +#define DEF_TX1_TXOP_LIMIT_OFDM 0 +#define DEF_TX2_TXOP_LIMIT_OFDM 0 +#define DEF_TX3_TXOP_LIMIT_OFDM 0 + +#define QOS_QOS_SETS 3 +#define QOS_PARAM_SET_ACTIVE 0 +#define QOS_PARAM_SET_DEF_CCK 1 +#define QOS_PARAM_SET_DEF_OFDM 2 + +#define CTRL_QOS_NO_ACK (0x0020) + +#define IPW_TX_QUEUE_1 1 +#define IPW_TX_QUEUE_2 2 +#define IPW_TX_QUEUE_3 3 +#define IPW_TX_QUEUE_4 4 + +/* QoS sturctures */ +struct ipw_qos_info { + int qos_enable; + struct ieee80211_qos_parameters *def_qos_parm_OFDM; + struct ieee80211_qos_parameters *def_qos_parm_CCK; + u32 burst_duration_CCK; + u32 burst_duration_OFDM; + u16 qos_no_ack_mask; + int burst_enable; +}; + +/**************************************************************/ /** * Generic queue structure * @@ -402,9 +538,9 @@ struct clx2_tx_queue { #define RX_FREE_BUFFERS 32 #define RX_LOW_WATERMARK 8 -#define SUP_RATE_11A_MAX_NUM_CHANNELS (8) -#define SUP_RATE_11B_MAX_NUM_CHANNELS (4) -#define SUP_RATE_11G_MAX_NUM_CHANNELS (12) +#define SUP_RATE_11A_MAX_NUM_CHANNELS 8 +#define SUP_RATE_11B_MAX_NUM_CHANNELS 4 +#define SUP_RATE_11G_MAX_NUM_CHANNELS 12 // Used for passing to driver number of successes and failures per rate struct rate_histogram { @@ -453,6 +589,9 @@ struct notif_channel_result { u8 uReserved; } __attribute__ ((packed)); +#define SCAN_COMPLETED_STATUS_COMPLETE 1 +#define SCAN_COMPLETED_STATUS_ABORTED 2 + struct notif_scan_complete { u8 scan_type; u8 num_channels; @@ -563,8 +702,8 @@ struct ipw_rx_packet { } __attribute__ ((packed)); #define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12 -#define IPW_RX_FRAME_SIZE sizeof(struct ipw_rx_header) + \ - sizeof(struct ipw_rx_frame) +#define IPW_RX_FRAME_SIZE (unsigned int)(sizeof(struct ipw_rx_header) + \ + sizeof(struct ipw_rx_frame)) struct ipw_rx_mem_buffer { dma_addr_t dma_addr; @@ -657,6 +796,19 @@ struct ipw_multicast_addr { u8 mac4[6]; } __attribute__ ((packed)); +#define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */ +#define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */ + +#define DCW_WEP_KEY_SEC_TYPE_WEP 0x00 +#define DCW_WEP_KEY_SEC_TYPE_CCM 0x20 +#define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30 + +#define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */ +#define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */ +#define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */ +#define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */ +//#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */ + struct ipw_wep_key { u8 cmd_id; u8 seq_num; @@ -818,14 +970,6 @@ struct ipw_tx_power { struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS]; } __attribute__ ((packed)); -struct ipw_qos_parameters { - u16 cw_min[4]; - u16 cw_max[4]; - u8 aifs[4]; - u8 flag[4]; - u16 tx_op_limit[4]; -} __attribute__ ((packed)); - struct ipw_rsn_capabilities { u8 id; u8 length; @@ -888,6 +1032,10 @@ struct ipw_cmd { #define STATUS_SCAN_PENDING (1<<20) #define STATUS_SCANNING (1<<21) #define STATUS_SCAN_ABORTING (1<<22) +#define STATUS_SCAN_FORCED (1<<23) + +#define STATUS_LED_LINK_ON (1<<24) +#define STATUS_LED_ACT_ON (1<<25) #define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */ #define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */ @@ -899,11 +1047,15 @@ struct ipw_cmd { #define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */ #define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */ #define CFG_CUSTOM_MAC (1<<3) -#define CFG_PREAMBLE (1<<4) +#define CFG_PREAMBLE_LONG (1<<4) #define CFG_ADHOC_PERSIST (1<<5) #define CFG_ASSOCIATE (1<<6) #define CFG_FIXED_RATE (1<<7) #define CFG_ADHOC_CREATE (1<<8) +#define CFG_NO_LED (1<<9) +#define CFG_BACKGROUND_SCAN (1<<10) +#define CFG_SPEED_SCAN (1<<11) +#define CFG_NET_STATS (1<<12) #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */ #define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */ @@ -925,13 +1077,50 @@ struct average { s32 sum; }; +#define MAX_SPEED_SCAN 100 +#define IPW_IBSS_MAC_HASH_SIZE 31 + +struct ipw_ibss_seq { + u8 mac[ETH_ALEN]; + u16 seq_num; + u16 frag_num; + unsigned long packet_time; + struct list_head list; +}; + +struct ipw_error_elem { + u32 desc; + u32 time; + u32 blink1; + u32 blink2; + u32 link1; + u32 link2; + u32 data; +}; + +struct ipw_event { + u32 event; + u32 time; + u32 data; +} __attribute__ ((packed)); + +struct ipw_fw_error { + unsigned long jiffies; + u32 status; + u32 config; + u32 elem_len; + u32 log_len; + struct ipw_error_elem *elem; + struct ipw_event *log; + u8 payload[0]; +} __attribute__ ((packed)); + struct ipw_priv { /* ieee device used by generic ieee processing code */ struct ieee80211_device *ieee; - struct ieee80211_security sec; - /* spinlock */ spinlock_t lock; + struct semaphore sem; /* basic pci-network driver stuff */ struct pci_dev *pci_dev; @@ -966,7 +1155,7 @@ struct ipw_priv { int rx_bufs_min; /**< minimum number of bufs in Rx queue */ int rx_pend_max; /**< maximum pending buffers for one IRQ */ u32 hcmd_seq; /**< sequence number for hcmd */ - u32 missed_beacon_threshold; + u32 disassociate_threshold; u32 roaming_threshold; struct ipw_associate assoc_request; @@ -1007,6 +1196,8 @@ struct ipw_priv { u8 mac_addr[ETH_ALEN]; u8 num_stations; u8 stations[MAX_STATIONS][ETH_ALEN]; + u8 short_retry_limit; + u8 long_retry_limit; u32 notif_missed_beacons; @@ -1024,17 +1215,29 @@ struct ipw_priv { u32 tx_packets; u32 quality; + u8 speed_scan[MAX_SPEED_SCAN]; + u8 speed_scan_pos; + + u16 last_seq_num; + u16 last_frag_num; + unsigned long last_packet_time; + struct list_head ibss_mac_hash[IPW_IBSS_MAC_HASH_SIZE]; + /* eeprom */ u8 eeprom[0x100]; /* 256 bytes of eeprom */ + u8 country[4]; int eeprom_delay; struct iw_statistics wstats; + struct iw_public_data wireless_data; + struct workqueue_struct *workqueue; struct work_struct adhoc_check; struct work_struct associate; struct work_struct disassociate; + struct work_struct system_config; struct work_struct rx_replenish; struct work_struct request_scan; struct work_struct adapter_restart; @@ -1045,25 +1248,51 @@ struct ipw_priv { struct work_struct abort_scan; struct work_struct roam; struct work_struct scan_check; + struct work_struct link_up; + struct work_struct link_down; struct tasklet_struct irq_tasklet; + /* LED related variables and work_struct */ + u8 nic_type; + u32 led_activity_on; + u32 led_activity_off; + u32 led_association_on; + u32 led_association_off; + u32 led_ofdm_on; + u32 led_ofdm_off; + + struct work_struct led_link_on; + struct work_struct led_link_off; + struct work_struct led_act_off; + struct work_struct merge_networks; + + struct ipw_cmd_log *cmdlog; + int cmdlog_len; + int cmdlog_pos; + #define IPW_2200BG 1 #define IPW_2915ABG 2 u8 adapter; -#define IPW_DEFAULT_TX_POWER 0x14 - u8 tx_power; + s8 tx_power; #ifdef CONFIG_PM u32 pm_state[16]; #endif + struct ipw_fw_error *error; + /* network state */ /* Used to pass the current INTA value from ISR to Tasklet */ u32 isr_inta; + /* QoS */ + struct ipw_qos_info qos_data; + struct work_struct qos_activate; + /*********************************/ + /* debugging info */ u32 indirect_dword; u32 direct_dword; @@ -1125,6 +1354,8 @@ do { if (ipw_debug_level & (level)) \ #define IPW_DL_RF_KILL (1<<17) #define IPW_DL_FW_ERRORS (1<<18) +#define IPW_DL_LED (1<<19) + #define IPW_DL_ORD (1<<20) #define IPW_DL_FRAG (1<<21) @@ -1137,6 +1368,8 @@ do { if (ipw_debug_level & (level)) \ #define IPW_DL_TRACE (1<<28) #define IPW_DL_STATS (1<<29) +#define IPW_DL_MERGE (1<<30) +#define IPW_DL_QOS (1<<31) #define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a) #define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a) @@ -1150,6 +1383,7 @@ do { if (ipw_debug_level & (level)) \ #define IPW_DEBUG_TX(f, a...) IPW_DEBUG(IPW_DL_TX, f, ## a) #define IPW_DEBUG_ISR(f, a...) IPW_DEBUG(IPW_DL_ISR, f, ## a) #define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a) +#define IPW_DEBUG_LED(f, a...) IPW_DEBUG(IPW_DL_LED, f, ## a) #define IPW_DEBUG_WEP(f, a...) IPW_DEBUG(IPW_DL_WEP, f, ## a) #define IPW_DEBUG_HC(f, a...) IPW_DEBUG(IPW_DL_HOST_COMMAND, f, ## a) #define IPW_DEBUG_FRAG(f, a...) IPW_DEBUG(IPW_DL_FRAG, f, ## a) @@ -1163,6 +1397,8 @@ do { if (ipw_debug_level & (level)) \ #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a) #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a) #define IPW_DEBUG_STATS(f, a...) IPW_DEBUG(IPW_DL_STATS, f, ## a) +#define IPW_DEBUG_MERGE(f, a...) IPW_DEBUG(IPW_DL_MERGE, f, ## a) +#define IPW_DEBUG_QOS(f, a...) IPW_DEBUG(IPW_DL_QOS, f, ## a) #include <linux/ctype.h> @@ -1177,59 +1413,65 @@ do { if (ipw_debug_level & (level)) \ #define DINO_RXFIFO_DATA 0x01 #define DINO_CONTROL_REG 0x00200000 -#define CX2_INTA_RW 0x00000008 -#define CX2_INTA_MASK_R 0x0000000C -#define CX2_INDIRECT_ADDR 0x00000010 -#define CX2_INDIRECT_DATA 0x00000014 -#define CX2_AUTOINC_ADDR 0x00000018 -#define CX2_AUTOINC_DATA 0x0000001C -#define CX2_RESET_REG 0x00000020 -#define CX2_GP_CNTRL_RW 0x00000024 +#define IPW_INTA_RW 0x00000008 +#define IPW_INTA_MASK_R 0x0000000C +#define IPW_INDIRECT_ADDR 0x00000010 +#define IPW_INDIRECT_DATA 0x00000014 +#define IPW_AUTOINC_ADDR 0x00000018 +#define IPW_AUTOINC_DATA 0x0000001C +#define IPW_RESET_REG 0x00000020 +#define IPW_GP_CNTRL_RW 0x00000024 -#define CX2_READ_INT_REGISTER 0xFF4 +#define IPW_READ_INT_REGISTER 0xFF4 -#define CX2_GP_CNTRL_BIT_INIT_DONE 0x00000004 +#define IPW_GP_CNTRL_BIT_INIT_DONE 0x00000004 -#define CX2_REGISTER_DOMAIN1_END 0x00001000 -#define CX2_SRAM_READ_INT_REGISTER 0x00000ff4 +#define IPW_REGISTER_DOMAIN1_END 0x00001000 +#define IPW_SRAM_READ_INT_REGISTER 0x00000ff4 -#define CX2_SHARED_LOWER_BOUND 0x00000200 -#define CX2_INTERRUPT_AREA_LOWER_BOUND 0x00000f80 +#define IPW_SHARED_LOWER_BOUND 0x00000200 +#define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f80 -#define CX2_NIC_SRAM_LOWER_BOUND 0x00000000 -#define CX2_NIC_SRAM_UPPER_BOUND 0x00030000 +#define IPW_NIC_SRAM_LOWER_BOUND 0x00000000 +#define IPW_NIC_SRAM_UPPER_BOUND 0x00030000 -#define CX2_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29) -#define CX2_GP_CNTRL_BIT_CLOCK_READY 0x00000001 -#define CX2_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002 +#define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29) +#define IPW_GP_CNTRL_BIT_CLOCK_READY 0x00000001 +#define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002 /* * RESET Register Bit Indexes */ -#define CBD_RESET_REG_PRINCETON_RESET 0x00000001 /* Bit 0 (LSB) */ -#define CX2_RESET_REG_SW_RESET 0x00000080 /* Bit 7 */ -#define CX2_RESET_REG_MASTER_DISABLED 0x00000100 /* Bit 8 */ -#define CX2_RESET_REG_STOP_MASTER 0x00000200 /* Bit 9 */ -#define CX2_ARC_KESHET_CONFIG 0x08000000 /* Bit 27 */ -#define CX2_START_STANDBY 0x00000004 /* Bit 2 */ - -#define CX2_CSR_CIS_UPPER_BOUND 0x00000200 -#define CX2_DOMAIN_0_END 0x1000 +#define CBD_RESET_REG_PRINCETON_RESET (1<<0) +#define IPW_START_STANDBY (1<<2) +#define IPW_ACTIVITY_LED (1<<4) +#define IPW_ASSOCIATED_LED (1<<5) +#define IPW_OFDM_LED (1<<6) +#define IPW_RESET_REG_SW_RESET (1<<7) +#define IPW_RESET_REG_MASTER_DISABLED (1<<8) +#define IPW_RESET_REG_STOP_MASTER (1<<9) +#define IPW_GATE_ODMA (1<<25) +#define IPW_GATE_IDMA (1<<26) +#define IPW_ARC_KESHET_CONFIG (1<<27) +#define IPW_GATE_ADMA (1<<29) + +#define IPW_CSR_CIS_UPPER_BOUND 0x00000200 +#define IPW_DOMAIN_0_END 0x1000 #define CLX_MEM_BAR_SIZE 0x1000 -#define CX2_BASEBAND_CONTROL_STATUS 0X00200000 -#define CX2_BASEBAND_TX_FIFO_WRITE 0X00200004 -#define CX2_BASEBAND_RX_FIFO_READ 0X00200004 -#define CX2_BASEBAND_CONTROL_STORE 0X00200010 +#define IPW_BASEBAND_CONTROL_STATUS 0X00200000 +#define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004 +#define IPW_BASEBAND_RX_FIFO_READ 0X00200004 +#define IPW_BASEBAND_CONTROL_STORE 0X00200010 -#define CX2_INTERNAL_CMD_EVENT 0X00300004 -#define CX2_BASEBAND_POWER_DOWN 0x00000001 +#define IPW_INTERNAL_CMD_EVENT 0X00300004 +#define IPW_BASEBAND_POWER_DOWN 0x00000001 -#define CX2_MEM_HALT_AND_RESET 0x003000e0 +#define IPW_MEM_HALT_AND_RESET 0x003000e0 /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */ -#define CX2_BIT_HALT_RESET_ON 0x80000000 -#define CX2_BIT_HALT_RESET_OFF 0x00000000 +#define IPW_BIT_HALT_RESET_ON 0x80000000 +#define IPW_BIT_HALT_RESET_OFF 0x00000000 #define CB_LAST_VALID 0x20000000 #define CB_INT_ENABLED 0x40000000 @@ -1248,63 +1490,63 @@ do { if (ipw_debug_level & (level)) \ #define DMA_CB_STOP_AND_ABORT 0x00000C00 #define DMA_CB_START 0x00000100 -#define CX2_SHARED_SRAM_SIZE 0x00030000 -#define CX2_SHARED_SRAM_DMA_CONTROL 0x00027000 +#define IPW_SHARED_SRAM_SIZE 0x00030000 +#define IPW_SHARED_SRAM_DMA_CONTROL 0x00027000 #define CB_MAX_LENGTH 0x1FFF -#define CX2_HOST_EEPROM_DATA_SRAM_SIZE 0xA18 -#define CX2_EEPROM_IMAGE_SIZE 0x100 +#define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18 +#define IPW_EEPROM_IMAGE_SIZE 0x100 /* DMA defs */ -#define CX2_DMA_I_CURRENT_CB 0x003000D0 -#define CX2_DMA_O_CURRENT_CB 0x003000D4 -#define CX2_DMA_I_DMA_CONTROL 0x003000A4 -#define CX2_DMA_I_CB_BASE 0x003000A0 - -#define CX2_TX_CMD_QUEUE_BD_BASE (0x00000200) -#define CX2_TX_CMD_QUEUE_BD_SIZE (0x00000204) -#define CX2_TX_QUEUE_0_BD_BASE (0x00000208) -#define CX2_TX_QUEUE_0_BD_SIZE (0x0000020C) -#define CX2_TX_QUEUE_1_BD_BASE (0x00000210) -#define CX2_TX_QUEUE_1_BD_SIZE (0x00000214) -#define CX2_TX_QUEUE_2_BD_BASE (0x00000218) -#define CX2_TX_QUEUE_2_BD_SIZE (0x0000021C) -#define CX2_TX_QUEUE_3_BD_BASE (0x00000220) -#define CX2_TX_QUEUE_3_BD_SIZE (0x00000224) -#define CX2_RX_BD_BASE (0x00000240) -#define CX2_RX_BD_SIZE (0x00000244) -#define CX2_RFDS_TABLE_LOWER (0x00000500) - -#define CX2_TX_CMD_QUEUE_READ_INDEX (0x00000280) -#define CX2_TX_QUEUE_0_READ_INDEX (0x00000284) -#define CX2_TX_QUEUE_1_READ_INDEX (0x00000288) -#define CX2_TX_QUEUE_2_READ_INDEX (0x0000028C) -#define CX2_TX_QUEUE_3_READ_INDEX (0x00000290) -#define CX2_RX_READ_INDEX (0x000002A0) - -#define CX2_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80) -#define CX2_TX_QUEUE_0_WRITE_INDEX (0x00000F84) -#define CX2_TX_QUEUE_1_WRITE_INDEX (0x00000F88) -#define CX2_TX_QUEUE_2_WRITE_INDEX (0x00000F8C) -#define CX2_TX_QUEUE_3_WRITE_INDEX (0x00000F90) -#define CX2_RX_WRITE_INDEX (0x00000FA0) +#define IPW_DMA_I_CURRENT_CB 0x003000D0 +#define IPW_DMA_O_CURRENT_CB 0x003000D4 +#define IPW_DMA_I_DMA_CONTROL 0x003000A4 +#define IPW_DMA_I_CB_BASE 0x003000A0 + +#define IPW_TX_CMD_QUEUE_BD_BASE 0x00000200 +#define IPW_TX_CMD_QUEUE_BD_SIZE 0x00000204 +#define IPW_TX_QUEUE_0_BD_BASE 0x00000208 +#define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C) +#define IPW_TX_QUEUE_1_BD_BASE 0x00000210 +#define IPW_TX_QUEUE_1_BD_SIZE 0x00000214 +#define IPW_TX_QUEUE_2_BD_BASE 0x00000218 +#define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C) +#define IPW_TX_QUEUE_3_BD_BASE 0x00000220 +#define IPW_TX_QUEUE_3_BD_SIZE 0x00000224 +#define IPW_RX_BD_BASE 0x00000240 +#define IPW_RX_BD_SIZE 0x00000244 +#define IPW_RFDS_TABLE_LOWER 0x00000500 + +#define IPW_TX_CMD_QUEUE_READ_INDEX 0x00000280 +#define IPW_TX_QUEUE_0_READ_INDEX 0x00000284 +#define IPW_TX_QUEUE_1_READ_INDEX 0x00000288 +#define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C) +#define IPW_TX_QUEUE_3_READ_INDEX 0x00000290 +#define IPW_RX_READ_INDEX (0x000002A0) + +#define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80) +#define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84) +#define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88) +#define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C) +#define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90) +#define IPW_RX_WRITE_INDEX (0x00000FA0) /* * EEPROM Related Definitions */ -#define IPW_EEPROM_DATA_SRAM_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x814) -#define IPW_EEPROM_DATA_SRAM_SIZE (CX2_SHARED_LOWER_BOUND + 0x818) -#define IPW_EEPROM_LOAD_DISABLE (CX2_SHARED_LOWER_BOUND + 0x81C) -#define IPW_EEPROM_DATA (CX2_SHARED_LOWER_BOUND + 0x820) -#define IPW_EEPROM_UPPER_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x9E0) +#define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814) +#define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818) +#define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C) +#define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820) +#define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0) -#define IPW_STATION_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0xA0C) -#define IPW_STATION_TABLE_UPPER (CX2_SHARED_LOWER_BOUND + 0xB0C) -#define IPW_REQUEST_ATIM (CX2_SHARED_LOWER_BOUND + 0xB0C) -#define IPW_ATIM_SENT (CX2_SHARED_LOWER_BOUND + 0xB10) -#define IPW_WHO_IS_AWAKE (CX2_SHARED_LOWER_BOUND + 0xB14) -#define IPW_DURING_ATIM_WINDOW (CX2_SHARED_LOWER_BOUND + 0xB18) +#define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C) +#define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C) +#define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C) +#define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10) +#define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14) +#define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18) #define MSB 1 #define LSB 0 @@ -1326,15 +1568,15 @@ do { if (ipw_debug_level & (level)) \ #define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */ /* NIC type as found in the one byte EEPROM_NIC_TYPE offset*/ -#define EEPROM_NIC_TYPE_STANDARD 0 -#define EEPROM_NIC_TYPE_DELL 1 -#define EEPROM_NIC_TYPE_FUJITSU 2 -#define EEPROM_NIC_TYPE_IBM 3 -#define EEPROM_NIC_TYPE_HP 4 +#define EEPROM_NIC_TYPE_0 0 +#define EEPROM_NIC_TYPE_1 1 +#define EEPROM_NIC_TYPE_2 2 +#define EEPROM_NIC_TYPE_3 3 +#define EEPROM_NIC_TYPE_4 4 #define FW_MEM_REG_LOWER_BOUND 0x00300000 #define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40) - +#define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04) #define EEPROM_BIT_SK (1<<0) #define EEPROM_BIT_CS (1<<1) #define EEPROM_BIT_DI (1<<2) @@ -1343,50 +1585,47 @@ do { if (ipw_debug_level & (level)) \ #define EEPROM_CMD_READ 0x2 /* Interrupts masks */ -#define CX2_INTA_NONE 0x00000000 +#define IPW_INTA_NONE 0x00000000 -#define CX2_INTA_BIT_RX_TRANSFER 0x00000002 -#define CX2_INTA_BIT_STATUS_CHANGE 0x00000010 -#define CX2_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020 +#define IPW_INTA_BIT_RX_TRANSFER 0x00000002 +#define IPW_INTA_BIT_STATUS_CHANGE 0x00000010 +#define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020 //Inta Bits for CF -#define CX2_INTA_BIT_TX_CMD_QUEUE 0x00000800 -#define CX2_INTA_BIT_TX_QUEUE_1 0x00001000 -#define CX2_INTA_BIT_TX_QUEUE_2 0x00002000 -#define CX2_INTA_BIT_TX_QUEUE_3 0x00004000 -#define CX2_INTA_BIT_TX_QUEUE_4 0x00008000 +#define IPW_INTA_BIT_TX_CMD_QUEUE 0x00000800 +#define IPW_INTA_BIT_TX_QUEUE_1 0x00001000 +#define IPW_INTA_BIT_TX_QUEUE_2 0x00002000 +#define IPW_INTA_BIT_TX_QUEUE_3 0x00004000 +#define IPW_INTA_BIT_TX_QUEUE_4 0x00008000 -#define CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000 +#define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000 -#define CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000 -#define CX2_INTA_BIT_POWER_DOWN 0x00200000 +#define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000 +#define IPW_INTA_BIT_POWER_DOWN 0x00200000 -#define CX2_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000 -#define CX2_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000 -#define CX2_INTA_BIT_RF_KILL_DONE 0x04000000 -#define CX2_INTA_BIT_FATAL_ERROR 0x40000000 -#define CX2_INTA_BIT_PARITY_ERROR 0x80000000 +#define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000 +#define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000 +#define IPW_INTA_BIT_RF_KILL_DONE 0x04000000 +#define IPW_INTA_BIT_FATAL_ERROR 0x40000000 +#define IPW_INTA_BIT_PARITY_ERROR 0x80000000 /* Interrupts enabled at init time. */ -#define CX2_INTA_MASK_ALL \ - (CX2_INTA_BIT_TX_QUEUE_1 | \ - CX2_INTA_BIT_TX_QUEUE_2 | \ - CX2_INTA_BIT_TX_QUEUE_3 | \ - CX2_INTA_BIT_TX_QUEUE_4 | \ - CX2_INTA_BIT_TX_CMD_QUEUE | \ - CX2_INTA_BIT_RX_TRANSFER | \ - CX2_INTA_BIT_FATAL_ERROR | \ - CX2_INTA_BIT_PARITY_ERROR | \ - CX2_INTA_BIT_STATUS_CHANGE | \ - CX2_INTA_BIT_FW_INITIALIZATION_DONE | \ - CX2_INTA_BIT_BEACON_PERIOD_EXPIRED | \ - CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \ - CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN | \ - CX2_INTA_BIT_POWER_DOWN | \ - CX2_INTA_BIT_RF_KILL_DONE ) - -#define IPWSTATUS_ERROR_LOG (CX2_SHARED_LOWER_BOUND + 0x410) -#define IPW_EVENT_LOG (CX2_SHARED_LOWER_BOUND + 0x414) +#define IPW_INTA_MASK_ALL \ + (IPW_INTA_BIT_TX_QUEUE_1 | \ + IPW_INTA_BIT_TX_QUEUE_2 | \ + IPW_INTA_BIT_TX_QUEUE_3 | \ + IPW_INTA_BIT_TX_QUEUE_4 | \ + IPW_INTA_BIT_TX_CMD_QUEUE | \ + IPW_INTA_BIT_RX_TRANSFER | \ + IPW_INTA_BIT_FATAL_ERROR | \ + IPW_INTA_BIT_PARITY_ERROR | \ + IPW_INTA_BIT_STATUS_CHANGE | \ + IPW_INTA_BIT_FW_INITIALIZATION_DONE | \ + IPW_INTA_BIT_BEACON_PERIOD_EXPIRED | \ + IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \ + IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN | \ + IPW_INTA_BIT_POWER_DOWN | \ + IPW_INTA_BIT_RF_KILL_DONE ) /* FW event log definitions */ #define EVENT_ELEM_SIZE (3 * sizeof(u32)) @@ -1396,6 +1635,11 @@ do { if (ipw_debug_level & (level)) \ #define ERROR_ELEM_SIZE (7 * sizeof(u32)) #define ERROR_START_OFFSET (1 * sizeof(u32)) +/* TX power level (dbm) */ +#define IPW_TX_POWER_MIN -12 +#define IPW_TX_POWER_MAX 20 +#define IPW_TX_POWER_DEFAULT IPW_TX_POWER_MAX + enum { IPW_FW_ERROR_OK = 0, IPW_FW_ERROR_FAIL, @@ -1408,8 +1652,8 @@ enum { IPW_FW_ERROR_ALLOC_FAIL, IPW_FW_ERROR_DMA_UNDERRUN, IPW_FW_ERROR_DMA_STATUS, - IPW_FW_ERROR_DINOSTATUS_ERROR, - IPW_FW_ERROR_EEPROMSTATUS_ERROR, + IPW_FW_ERROR_DINO_ERROR, + IPW_FW_ERROR_EEPROM_ERROR, IPW_FW_ERROR_SYSASSERT, IPW_FW_ERROR_FATAL_ERROR }; @@ -1425,6 +1669,8 @@ enum { #define HC_IBSS_RECONF 4 #define HC_DISASSOC_QUIET 5 +#define HC_QOS_SUPPORT_ASSOC 0x01 + #define IPW_RATE_CAPABILITIES 1 #define IPW_RATE_CONNECT 0 @@ -1595,18 +1841,20 @@ enum { IPW_ORD_TABLE_7_LAST }; -#define IPW_ORDINALS_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0x500) -#define IPW_ORDINALS_TABLE_0 (CX2_SHARED_LOWER_BOUND + 0x180) -#define IPW_ORDINALS_TABLE_1 (CX2_SHARED_LOWER_BOUND + 0x184) -#define IPW_ORDINALS_TABLE_2 (CX2_SHARED_LOWER_BOUND + 0x188) -#define IPW_MEM_FIXED_OVERRIDE (CX2_SHARED_LOWER_BOUND + 0x41C) +#define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410) +#define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414) +#define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500) +#define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180) +#define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184) +#define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188) +#define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C) struct ipw_fixed_rate { u16 tx_rates; u16 reserved; } __attribute__ ((packed)); -#define CX2_INDIRECT_ADDR_MASK (~0x3ul) +#define IPW_INDIRECT_ADDR_MASK (~0x3ul) struct host_cmd { u8 cmd; @@ -1615,6 +1863,12 @@ struct host_cmd { u32 param[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH]; } __attribute__ ((packed)); +struct ipw_cmd_log { + unsigned long jiffies; + int retcode; + struct host_cmd cmd; +}; + #define CFG_BT_COEXISTENCE_MIN 0x00 #define CFG_BT_COEXISTENCE_DEFER 0x02 #define CFG_BT_COEXISTENCE_KILL 0x04 @@ -1643,23 +1897,14 @@ struct host_cmd { #define REG_CHANNEL_MASK 0x00003FFF #define IPW_IBSS_11B_DEFAULT_MASK 0x87ff -static const long ipw_frequencies[] = { - 2412, 2417, 2422, 2427, - 2432, 2437, 2442, 2447, - 2452, 2457, 2462, 2467, - 2472, 2484 -}; - -#define FREQ_COUNT ARRAY_SIZE(ipw_frequencies) - #define IPW_MAX_CONFIG_RETRIES 10 -static inline u32 frame_hdr_len(struct ieee80211_hdr *hdr) +static inline u32 frame_hdr_len(struct ieee80211_hdr_4addr *hdr) { u32 retval; u16 fc; - retval = sizeof(struct ieee80211_hdr); + retval = sizeof(struct ieee80211_hdr_3addr); fc = le16_to_cpu(hdr->frame_ctl); /* |