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-rw-r--r--drivers/net/wireless/b43/Makefile2
-rw-r--r--drivers/net/wireless/b43/b43.h3
-rw-r--r--drivers/net/wireless/b43/main.c30
-rw-r--r--drivers/net/wireless/b43/phy_common.c6
-rw-r--r--drivers/net/wireless/b43/phy_common.h5
-rw-r--r--drivers/net/wireless/b43/phy_n.c211
-rw-r--r--drivers/net/wireless/b43/phy_n.h218
-rw-r--r--drivers/net/wireless/b43/radio_2055.c1332
-rw-r--r--drivers/net/wireless/b43/radio_2055.h254
-rw-r--r--drivers/net/wireless/b43/radio_2056.c43
-rw-r--r--drivers/net/wireless/b43/radio_2056.h42
-rw-r--r--drivers/net/wireless/b43/tables_nphy.c1311
-rw-r--r--drivers/net/wireless/b43/tables_nphy.h59
13 files changed, 1833 insertions, 1683 deletions
diff --git a/drivers/net/wireless/b43/Makefile b/drivers/net/wireless/b43/Makefile
index 5e83b6f0a3a..69d4af09a6c 100644
--- a/drivers/net/wireless/b43/Makefile
+++ b/drivers/net/wireless/b43/Makefile
@@ -1,6 +1,8 @@
b43-y += main.o
b43-y += tables.o
b43-$(CONFIG_B43_NPHY) += tables_nphy.o
+b43-$(CONFIG_B43_NPHY) += radio_2055.o
+b43-$(CONFIG_B43_NPHY) += radio_2056.o
b43-y += phy_common.o
b43-y += phy_g.o
b43-y += phy_a.o
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index 8674a99356a..72821c456b0 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -186,7 +186,8 @@ enum {
#define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
#define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
#define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
-#define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */
+#define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */
+#define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */
#define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
/* TSSI information */
#define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 20631ae2ddd..a1186525c70 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -2280,6 +2280,7 @@ out:
static int b43_upload_microcode(struct b43_wldev *dev)
{
+ struct wiphy *wiphy = dev->wl->hw->wiphy;
const size_t hdr_len = sizeof(struct b43_fw_header);
const __be32 *data;
unsigned int i, len;
@@ -2405,6 +2406,10 @@ static int b43_upload_microcode(struct b43_wldev *dev)
}
}
+ snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
+ dev->fw.rev, dev->fw.patch);
+ wiphy->hw_version = dev->dev->id.coreid;
+
if (b43_is_old_txhdr_format(dev)) {
/* We're over the deadline, but we keep support for old fw
* until it turns out to be in major conflict with something new. */
@@ -3754,17 +3759,17 @@ static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
}
err = -EINVAL;
- switch (key->alg) {
- case ALG_WEP:
- if (key->keylen == WLAN_KEY_LEN_WEP40)
- algorithm = B43_SEC_ALGO_WEP40;
- else
- algorithm = B43_SEC_ALGO_WEP104;
+ switch (key->cipher) {
+ case WLAN_CIPHER_SUITE_WEP40:
+ algorithm = B43_SEC_ALGO_WEP40;
+ break;
+ case WLAN_CIPHER_SUITE_WEP104:
+ algorithm = B43_SEC_ALGO_WEP104;
break;
- case ALG_TKIP:
+ case WLAN_CIPHER_SUITE_TKIP:
algorithm = B43_SEC_ALGO_TKIP;
break;
- case ALG_CCMP:
+ case WLAN_CIPHER_SUITE_CCMP:
algorithm = B43_SEC_ALGO_AES;
break;
default:
@@ -4250,6 +4255,10 @@ static void b43_wireless_core_exit(struct b43_wldev *dev)
B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
return;
+
+ /* Unregister HW RNG driver */
+ b43_rng_exit(dev->wl);
+
b43_set_status(dev, B43_STAT_UNINIT);
/* Stop the microcode PSM. */
@@ -4379,6 +4388,9 @@ static int b43_wireless_core_init(struct b43_wldev *dev)
b43_set_status(dev, B43_STAT_INITIALIZED);
+ /* Register HW RNG driver */
+ b43_rng_init(dev->wl);
+
out:
return err;
@@ -4984,7 +4996,6 @@ static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
if (err)
goto err_one_core_detach;
b43_leds_register(wl->current_dev);
- b43_rng_init(wl);
}
out:
@@ -5020,7 +5031,6 @@ static void b43_remove(struct ssb_device *dev)
b43_one_core_detach(dev);
if (list_empty(&wl->devlist)) {
- b43_rng_exit(wl);
b43_leds_unregister(wl);
/* Last core on the chip unregistered.
* We can destroy common struct b43_wl.
diff --git a/drivers/net/wireless/b43/phy_common.c b/drivers/net/wireless/b43/phy_common.c
index 8f7d7eff2d8..7b2ea678145 100644
--- a/drivers/net/wireless/b43/phy_common.c
+++ b/drivers/net/wireless/b43/phy_common.c
@@ -294,8 +294,10 @@ int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
*/
channelcookie = new_channel;
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
- channelcookie |= 0x100;
- //FIXME set 40Mhz flag if required
+ channelcookie |= B43_SHM_SH_CHAN_5GHZ;
+ /* FIXME: set 40Mhz flag if required */
+ if (0)
+ channelcookie |= B43_SHM_SH_CHAN_40MHZ;
savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
diff --git a/drivers/net/wireless/b43/phy_common.h b/drivers/net/wireless/b43/phy_common.h
index bd480b481bf..0e619422884 100644
--- a/drivers/net/wireless/b43/phy_common.h
+++ b/drivers/net/wireless/b43/phy_common.h
@@ -2,6 +2,7 @@
#define LINUX_B43_PHY_COMMON_H_
#include <linux/types.h>
+#include <linux/nl80211.h>
struct b43_wldev;
@@ -250,8 +251,10 @@ struct b43_phy {
* check is needed. */
unsigned long next_txpwr_check_time;
- /* current channel */
+ /* Current channel */
unsigned int channel;
+ u16 channel_freq;
+ enum nl80211_channel_type channel_type;
/* PHY TX errors counter. */
atomic_t txerr_cnt;
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index 5a725703770..dfec5496055 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -29,6 +29,8 @@
#include "b43.h"
#include "phy_n.h"
#include "tables_nphy.h"
+#include "radio_2055.h"
+#include "radio_2056.h"
#include "main.h"
struct nphy_txgains {
@@ -73,21 +75,12 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
u16 value, u8 core, bool off);
static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
u16 value, u8 core);
-static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel);
-static inline bool b43_empty_chanspec(struct b43_chanspec *chanspec)
+static inline bool b43_channel_type_is_40mhz(
+ enum nl80211_channel_type channel_type)
{
- return !chanspec->channel && !chanspec->sideband &&
- !chanspec->b_width && !chanspec->b_freq;
-}
-
-static inline bool b43_eq_chanspecs(struct b43_chanspec *chanspec1,
- struct b43_chanspec *chanspec2)
-{
- return (chanspec1->channel == chanspec2->channel &&
- chanspec1->sideband == chanspec2->sideband &&
- chanspec1->b_width == chanspec2->b_width &&
- chanspec1->b_freq == chanspec2->b_freq);
+ return (channel_type == NL80211_CHAN_HT40MINUS ||
+ channel_type == NL80211_CHAN_HT40PLUS);
}
void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
@@ -223,7 +216,7 @@ static void b43_radio_init2055_post(struct b43_wldev *dev)
if (i)
b43err(dev->wl, "radio post init timeout\n");
b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
- nphy_channel_switch(dev, dev->phy.channel);
+ b43_switch_channel(dev, dev->phy.channel);
b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
@@ -782,7 +775,7 @@ static void b43_nphy_spur_workaround(struct b43_wldev *dev)
{
struct b43_phy_n *nphy = dev->phy.n;
- u8 channel = nphy->radio_chanspec.channel;
+ u8 channel = dev->phy.channel;
int tone[2] = { 57, 58 };
u32 noise[2] = { 0x3FF, 0x3FF };
@@ -856,9 +849,9 @@ static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
gain[0] = 6;
gain[1] = 6;
} else {
- tmp = 40370 - 315 * nphy->radio_chanspec.channel;
+ tmp = 40370 - 315 * dev->phy.channel;
gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
- tmp = 23242 - 224 * nphy->radio_chanspec.channel;
+ tmp = 23242 - 224 * dev->phy.channel;
gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
}
} else {
@@ -893,7 +886,7 @@ static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
-static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
+static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
{
struct b43_phy_n *nphy = dev->phy.n;
u8 i, j;
@@ -1094,11 +1087,12 @@ static void b43_nphy_workarounds(struct b43_wldev *dev)
b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
- b43_nphy_gain_crtl_workarounds(dev);
+ b43_nphy_gain_ctrl_workarounds(dev);
if (dev->phy.rev < 2) {
if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
- ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
+ b43_hf_write(dev, b43_hf_read(dev) |
+ B43_HF_MLADVW);
} else if (dev->phy.rev == 2) {
b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
@@ -1182,7 +1176,7 @@ static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
len = bw << 1;
}
- samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
+ samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
if (!samples) {
b43err(dev->wl, "allocation for samples generation failed\n");
return 0;
@@ -2083,12 +2077,12 @@ static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
u16 *rssical_phy_regs = NULL;
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
- if (b43_empty_chanspec(&nphy->rssical_chanspec_2G))
+ if (!nphy->rssical_chanspec_2G.center_freq)
return;
rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
} else {
- if (b43_empty_chanspec(&nphy->rssical_chanspec_5G))
+ if (!nphy->rssical_chanspec_5G.center_freq)
return;
rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
@@ -2544,8 +2538,9 @@ static void b43_nphy_save_cal(struct b43_wldev *dev)
txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
}
- *iqcal_chanspec = nphy->radio_chanspec;
- b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
+ iqcal_chanspec->center_freq = dev->phy.channel_freq;
+ iqcal_chanspec->channel_type = dev->phy.channel_type;
+ b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
if (nphy->hang_avoid)
b43_nphy_stay_in_carrier_search(dev, 0);
@@ -2565,12 +2560,12 @@ static void b43_nphy_restore_cal(struct b43_wldev *dev)
struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
- if (b43_empty_chanspec(&nphy->iqcal_chanspec_2G))
+ if (!nphy->iqcal_chanspec_2G.center_freq)
return;
table = nphy->cal_cache.txcal_coeffs_2G;
loft = &nphy->cal_cache.txcal_coeffs_2G[5];
} else {
- if (b43_empty_chanspec(&nphy->iqcal_chanspec_5G))
+ if (!nphy->iqcal_chanspec_5G.center_freq)
return;
table = nphy->cal_cache.txcal_coeffs_5G;
loft = &nphy->cal_cache.txcal_coeffs_5G[5];
@@ -2815,7 +2810,10 @@ static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
nphy->txiqlocal_bestc);
nphy->txiqlocal_coeffsvalid = true;
- nphy->txiqlocal_chanspec = nphy->radio_chanspec;
+ nphy->txiqlocal_chanspec.center_freq =
+ dev->phy.channel_freq;
+ nphy->txiqlocal_chanspec.channel_type =
+ dev->phy.channel_type;
} else {
length = 11;
if (dev->phy.rev < 3)
@@ -2851,7 +2849,8 @@ static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
bool equal = true;
if (!nphy->txiqlocal_coeffsvalid ||
- b43_eq_chanspecs(&nphy->txiqlocal_chanspec, &nphy->radio_chanspec))
+ nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
+ nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
return;
b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
@@ -3073,6 +3072,57 @@ static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
}
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
+static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
+{
+ u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
+ if (on)
+ tmslow |= SSB_TMSLOW_PHYCLK;
+ else
+ tmslow &= ~SSB_TMSLOW_PHYCLK;
+ ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
+}
+
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
+static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
+{
+ struct b43_phy *phy = &dev->phy;
+ struct b43_phy_n *nphy = phy->n;
+ u16 buf[16];
+
+ nphy->phyrxchain = mask;
+
+ if (0 /* FIXME clk */)
+ return;
+
+ b43_mac_suspend(dev);
+
+ if (nphy->hang_avoid)
+ b43_nphy_stay_in_carrier_search(dev, true);
+
+ b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
+ (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
+
+ if ((mask & 0x3) != 0x3) {
+ b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
+ if (dev->phy.rev >= 3) {
+ /* TODO */
+ }
+ } else {
+ b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
+ if (dev->phy.rev >= 3) {
+ /* TODO */
+ }
+ }
+
+ b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
+
+ if (nphy->hang_avoid)
+ b43_nphy_stay_in_carrier_search(dev, false);
+
+ b43_mac_enable(dev);
+}
+
/*
* Init N-PHY
* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
@@ -3173,7 +3223,7 @@ int b43_phy_initn(struct b43_wldev *dev)
b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
b43_nphy_bmac_clock_fgc(dev, 0);
- /* TODO N PHY MAC PHY Clock Set with argument 1 */
+ b43_nphy_mac_phy_clock_set(dev, true);
b43_nphy_pa_override(dev, false);
b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
@@ -3199,18 +3249,16 @@ int b43_phy_initn(struct b43_wldev *dev)
}
if (nphy->phyrxchain != 3)
- ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
+ b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
if (nphy->mphase_cal_phase_id > 0)
;/* TODO PHY Periodic Calibration Multi-Phase Restart */
do_rssi_cal = false;
if (phy->rev >= 3) {
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
- do_rssi_cal =
- b43_empty_chanspec(&nphy->rssical_chanspec_2G);
+ do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
else
- do_rssi_cal =
- b43_empty_chanspec(&nphy->rssical_chanspec_5G);
+ do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
if (do_rssi_cal)
b43_nphy_rssi_cal(dev);
@@ -3222,9 +3270,9 @@ int b43_phy_initn(struct b43_wldev *dev)
if (!((nphy->measure_hold & 0x6) != 0)) {
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
- do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_2G);
+ do_cal = !nphy->iqcal_chanspec_2G.center_freq;
else
- do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_5G);
+ do_cal = !nphy->iqcal_chanspec_5G.center_freq;
if (nphy->mute)
do_cal = false;
@@ -3272,24 +3320,25 @@ int b43_phy_initn(struct b43_wldev *dev)
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
-static void b43_nphy_chanspec_setup(struct b43_wldev *dev,
+static void b43_nphy_channel_setup(struct b43_wldev *dev,
const struct b43_phy_n_sfo_cfg *e,
- struct b43_chanspec chanspec)
+ struct ieee80211_channel *new_channel)
{
struct b43_phy *phy = &dev->phy;
struct b43_phy_n *nphy = dev->phy.n;
- u16 tmp;
+ u16 old_band_5ghz;
u32 tmp32;
- tmp = b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
- if (chanspec.b_freq == 1 && tmp == 0) {
+ old_band_5ghz =
+ b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
+ if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
- } else if (chanspec.b_freq == 1) {
+ } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
@@ -3299,19 +3348,12 @@ static void b43_nphy_chanspec_setup(struct b43_wldev *dev,
b43_chantab_phy_upload(dev, e);
- tmp = chanspec.channel;
- if (chanspec.b_freq == 1)
- tmp |= 0x0100;
- if (chanspec.b_width == 3)
- tmp |= 0x0200;
- b43_shm_write16(dev, B43_SHM_SHARED, 0xA0, tmp);
-
- if (nphy->radio_chanspec.channel == 14) {
+ if (new_channel->hw_value == 14) {
b43_nphy_classifier(dev, 2, 0);
b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
} else {
b43_nphy_classifier(dev, 2, 2);
- if (chanspec.b_freq == 2)
+ if (new_channel->band == IEEE80211_BAND_2GHZ)
b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
}
@@ -3334,70 +3376,62 @@ static void b43_nphy_chanspec_setup(struct b43_wldev *dev,
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
-static int b43_nphy_set_chanspec(struct b43_wldev *dev,
- struct b43_chanspec chanspec)
+static int b43_nphy_set_channel(struct b43_wldev *dev,
+ struct ieee80211_channel *channel,
+ enum nl80211_channel_type channel_type)
{
+ struct b43_phy *phy = &dev->phy;
struct b43_phy_n *nphy = dev->phy.n;
const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
u8 tmp;
- u8 channel = chanspec.channel;
if (dev->phy.rev >= 3) {
- /* TODO */
+ tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
+ channel->center_freq);
tabent_r3 = NULL;
if (!tabent_r3)
return -ESRCH;
} else {
- tabent_r2 = b43_nphy_get_chantabent_rev2(dev, channel);
+ tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
+ channel->hw_value);
if (!tabent_r2)
return -ESRCH;
}
- nphy->radio_chanspec = chanspec;
+ /* Channel is set later in common code, but we need to set it on our
+ own to let this function's subcalls work properly. */
+ phy->channel = channel->hw_value;
+ phy->channel_freq = channel->center_freq;
- if (chanspec.b_width != nphy->b_width)
- ; /* TODO: BMAC BW Set (chanspec.b_width) */
+ if (b43_channel_type_is_40mhz(phy->channel_type) !=
+ b43_channel_type_is_40mhz(channel_type))
+ ; /* TODO: BMAC BW Set (channel_type) */
- /* TODO: use defines */
- if (chanspec.b_width == 3) {
- if (chanspec.sideband == 2)
- b43_phy_set(dev, B43_NPHY_RXCTL,
- B43_NPHY_RXCTL_BSELU20);
- else
- b43_phy_mask(dev, B43_NPHY_RXCTL,
- ~B43_NPHY_RXCTL_BSELU20);
- }
+ if (channel_type == NL80211_CHAN_HT40PLUS)
+ b43_phy_set(dev, B43_NPHY_RXCTL,
+ B43_NPHY_RXCTL_BSELU20);
+ else if (channel_type == NL80211_CHAN_HT40MINUS)
+ b43_phy_mask(dev, B43_NPHY_RXCTL,
+ ~B43_NPHY_RXCTL_BSELU20);
if (dev->phy.rev >= 3) {
- tmp = (chanspec.b_freq == 1) ? 4 : 0;
+ tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
/* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
- b43_nphy_chanspec_setup(dev, &(tabent_r3->phy_regs), chanspec);
+ b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
} else {
- tmp = (chanspec.b_freq == 1) ? 0x0020 : 0x0050;
+ tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
b43_radio_2055_setup(dev, tabent_r2);
- b43_nphy_chanspec_setup(dev, &(tabent_r2->phy_regs), chanspec);
+ b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
}
return 0;
}
-/* Tune the hardware to a new channel */
-static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
-{
- struct b43_phy_n *nphy = dev->phy.n;
-
- struct b43_chanspec chanspec;
- chanspec = nphy->radio_chanspec;
- chanspec.channel = channel;
-
- return b43_nphy_set_chanspec(dev, chanspec);
-}
-
static int b43_nphy_op_allocate(struct b43_wldev *dev)
{
struct b43_phy_n *nphy;
@@ -3518,7 +3552,7 @@ static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
} else {
if (dev->phy.rev >= 3) {
b43_radio_init2056(dev);
- b43_nphy_set_chanspec(dev, nphy->radio_chanspec);
+ b43_switch_channel(dev, dev->phy.channel);
} else {
b43_radio_init2055(dev);
}
@@ -3534,6 +3568,9 @@ static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
unsigned int new_channel)
{
+ struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
+ enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
+
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
if ((new_channel < 1) || (new_channel > 14))
return -EINVAL;
@@ -3542,7 +3579,7 @@ static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
return -EINVAL;
}
- return nphy_channel_switch(dev, new_channel);
+ return b43_nphy_set_channel(dev, channel, channel_type);
}
static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
diff --git a/drivers/net/wireless/b43/phy_n.h b/drivers/net/wireless/b43/phy_n.h
index 8b6d570dd0a..c144e59a708 100644
--- a/drivers/net/wireless/b43/phy_n.h
+++ b/drivers/net/wireless/b43/phy_n.h
@@ -714,223 +714,11 @@
#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */
#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A)
-
-/* Broadcom 2055 radio registers */
-
-#define B2055_GEN_SPARE 0x00 /* GEN spare */
-#define B2055_SP_PINPD 0x02 /* SP PIN PD */
-#define B2055_C1_SP_RSSI 0x03 /* SP RSSI Core 1 */
-#define B2055_C1_SP_PDMISC 0x04 /* SP PD MISC Core 1 */
-#define B2055_C2_SP_RSSI 0x05 /* SP RSSI Core 2 */
-#define B2055_C2_SP_PDMISC 0x06 /* SP PD MISC Core 2 */
-#define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */
-#define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */
-#define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */
-#define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */
-#define B2055_C1_SP_LPFBWSEL 0x0B /* SP LPF BW select Core 1 */
-#define B2055_C2_SP_LPFBWSEL 0x0C /* SP LPF BW select Core 2 */
-#define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */
-#define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */
-#define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */
-#define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */
-#define B2055_MASTER1 0x11 /* Master control 1 */
-#define B2055_MASTER2 0x12 /* Master control 2 */
-#define B2055_PD_LGEN 0x13 /* PD LGEN */
-#define B2055_PD_PLLTS 0x14 /* PD PLL TS */
-#define B2055_C1_PD_LGBUF 0x15 /* PD Core 1 LGBUF */
-#define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */
-#define B2055_C1_PD_RXTX 0x17 /* PD Core 1 RXTX */
-#define B2055_C1_PD_RSSIMISC 0x18 /* PD Core 1 RSSI MISC */
-#define B2055_C2_PD_LGBUF 0x19 /* PD Core 2 LGBUF */
-#define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */
-#define B2055_C2_PD_RXTX 0x1B /* PD Core 2 RXTX */
-#define B2055_C2_PD_RSSIMISC 0x1C /* PD Core 2 RSSI MISC */
-#define B2055_PWRDET_LGEN 0x1D /* PWRDET LGEN */
-#define B2055_C1_PWRDET_LGBUF 0x1E /* PWRDET LGBUF Core 1 */
-#define B2055_C1_PWRDET_RXTX 0x1F /* PWRDET RXTX Core 1 */
-#define B2055_C2_PWRDET_LGBUF 0x20 /* PWRDET LGBUF Core 2 */
-#define B2055_C2_PWRDET_RXTX 0x21 /* PWRDET RXTX Core 2 */
-#define B2055_RRCCAL_CS 0x22 /* RRCCAL Control spare */
-#define B2055_RRCCAL_NOPTSEL 0x23 /* RRCCAL N OPT SEL */
-#define B2055_CAL_MISC 0x24 /* CAL MISC */
-#define B2055_CAL_COUT 0x25 /* CAL Counter out */
-#define B2055_CAL_COUT2 0x26 /* CAL Counter out 2 */
-#define B2055_CAL_CVARCTL 0x27 /* CAL CVAR Control */
-#define B2055_CAL_RVARCTL 0x28 /* CAL RVAR Control */
-#define B2055_CAL_LPOCTL 0x29 /* CAL LPO Control */
-#define B2055_CAL_TS 0x2A /* CAL TS */
-#define B2055_CAL_RCCALRTS 0x2B /* CAL RCCAL READ TS */
-#define B2055_CAL_RCALRTS 0x2C /* CAL RCAL READ TS */
-#define B2055_PADDRV 0x2D /* PAD driver */
-#define B2055_XOCTL1 0x2E /* XO Control 1 */
-#define B2055_XOCTL2 0x2F /* XO Control 2 */
-#define B2055_XOREGUL 0x30 /* XO Regulator */
-#define B2055_XOMISC 0x31 /* XO misc */
-#define B2055_PLL_LFC1 0x32 /* PLL LF C1 */
-#define B2055_PLL_CALVTH 0x33 /* PLL CAL VTH */
-#define B2055_PLL_LFC2 0x34 /* PLL LF C2 */
-#define B2055_PLL_REF 0x35 /* PLL reference */
-#define B2055_PLL_LFR1 0x36 /* PLL LF R1 */
-#define B2055_PLL_PFDCP 0x37 /* PLL PFD CP */
-#define B2055_PLL_IDAC_CPOPAMP 0x38 /* PLL IDAC CPOPAMP */
-#define B2055_PLL_CPREG 0x39 /* PLL CP Regulator */
-#define B2055_PLL_RCAL 0x3A /* PLL RCAL */
-#define B2055_RF_PLLMOD0 0x3B /* RF PLL MOD0 */
-#define B2055_RF_PLLMOD1 0x3C /* RF PLL MOD1 */
-#define B2055_RF_MMDIDAC1 0x3D /* RF MMD IDAC 1 */
-#define B2055_RF_MMDIDAC0 0x3E /* RF MMD IDAC 0 */
-#define B2055_RF_MMDSP 0x3F /* RF MMD spare */
-#define B2055_VCO_CAL1 0x40 /* VCO cal 1 */
-#define B2055_VCO_CAL2 0x41 /* VCO cal 2 */
-#define B2055_VCO_CAL3 0x42 /* VCO cal 3 */
-#define B2055_VCO_CAL4 0x43 /* VCO cal 4 */
-#define B2055_VCO_CAL5 0x44 /* VCO cal 5 */
-#define B2055_VCO_CAL6 0x45 /* VCO cal 6 */
-#define B2055_VCO_CAL7 0x46 /* VCO cal 7 */
-#define B2055_VCO_CAL8 0x47 /* VCO cal 8 */
-#define B2055_VCO_CAL9 0x48 /* VCO cal 9 */
-#define B2055_VCO_CAL10 0x49 /* VCO cal 10 */
-#define B2055_VCO_CAL11 0x4A /* VCO cal 11 */
-#define B2055_VCO_CAL12 0x4B /* VCO cal 12 */
-#define B2055_VCO_CAL13 0x4C /* VCO cal 13 */
-#define B2055_VCO_CAL14 0x4D /* VCO cal 14 */
-#define B2055_VCO_CAL15 0x4E /* VCO cal 15 */
-#define B2055_VCO_CAL16 0x4F /* VCO cal 16 */
-#define B2055_VCO_KVCO 0x50 /* VCO KVCO */
-#define B2055_VCO_CAPTAIL 0x51 /* VCO CAP TAIL */
-#define B2055_VCO_IDACVCO 0x52 /* VCO IDAC VCO */
-#define B2055_VCO_REG 0x53 /* VCO Regulator */
-#define B2055_PLL_RFVTH 0x54 /* PLL RF VTH */
-#define B2055_LGBUF_CENBUF 0x55 /* LGBUF CEN BUF */
-#define B2055_LGEN_TUNE1 0x56 /* LGEN tune 1 */
-#define B2055_LGEN_TUNE2 0x57 /* LGEN tune 2 */
-#define B2055_LGEN_IDAC1 0x58 /* LGEN IDAC 1 */
-#define B2055_LGEN_IDAC2 0x59 /* LGEN IDAC 2 */
-#define B2055_LGEN_BIASC 0x5A /* LGEN BIAS counter */
-#define B2055_LGEN_BIASIDAC 0x5B /* LGEN BIAS IDAC */
-#define B2055_LGEN_RCAL 0x5C /* LGEN RCAL */
-#define B2055_LGEN_DIV 0x5D /* LGEN div */
-#define B2055_LGEN_SPARE2 0x5E /* LGEN spare 2 */
-#define B2055_C1_LGBUF_ATUNE 0x5F /* Core 1 LGBUF A tune */
-#define B2055_C1_LGBUF_GTUNE 0x60 /* Core 1 LGBUF G tune */
-#define B2055_C1_LGBUF_DIV 0x61 /* Core 1 LGBUF div */
-#define B2055_C1_LGBUF_AIDAC 0x62 /* Core 1 LGBUF A IDAC */
-#define B2055_C1_LGBUF_GIDAC 0x63 /* Core 1 LGBUF G IDAC */
-#define B2055_C1_LGBUF_IDACFO 0x64 /* Core 1 LGBUF IDAC filter override */
-#define B2055_C1_LGBUF_SPARE 0x65 /* Core 1 LGBUF spare */
-#define B2055_C1_RX_RFSPC1 0x66 /* Core 1 RX RF SPC1 */
-#define B2055_C1_RX_RFR1 0x67 /* Core 1 RX RF reg 1 */
-#define B2055_C1_RX_RFR2 0x68 /* Core 1 RX RF reg 2 */
-#define B2055_C1_RX_RFRCAL 0x69 /* Core 1 RX RF RCAL */
-#define B2055_C1_RX_BB_BLCMP 0x6A /* Core 1 RX Baseband BUFI LPF CMP */
-#define B2055_C1_RX_BB_LPF 0x6B /* Core 1 RX Baseband LPF */
-#define B2055_C1_RX_BB_MIDACHP 0x6C /* Core 1 RX Baseband MIDAC High-pass */
-#define B2055_C1_RX_BB_VGA1IDAC 0x6D /* Core 1 RX Baseband VGA1 IDAC */
-#define B2055_C1_RX_BB_VGA2IDAC 0x6E /* Core 1 RX Baseband VGA2 IDAC */
-#define B2055_C1_RX_BB_VGA3IDAC 0x6F /* Core 1 RX Baseband VGA3 IDAC */
-#define B2055_C1_RX_BB_BUFOCTL 0x70 /* Core 1 RX Baseband BUFO Control */
-#define B2055_C1_RX_BB_RCCALCTL 0x71 /* Core 1 RX Baseband RCCAL Control */
-#define B2055_C1_RX_BB_RSSICTL1 0x72 /* Core 1 RX Baseband RSSI Control 1 */
-#define B2055_C1_RX_BB_RSSICTL2 0x73 /* Core 1 RX Baseband RSSI Control 2 */
-#define B2055_C1_RX_BB_RSSICTL3 0x74 /* Core 1 RX Baseband RSSI Control 3 */
-#define B2055_C1_RX_BB_RSSICTL4 0x75 /* Core 1 RX Baseband RSSI Control 4 */
-#define B2055_C1_RX_BB_RSSICTL5 0x76 /* Core 1 RX Baseband RSSI Control 5 */
-#define B2055_C1_RX_BB_REG 0x77 /* Core 1 RX Baseband Regulator */
-#define B2055_C1_RX_BB_SPARE1 0x78 /* Core 1 RX Baseband spare 1 */
-#define B2055_C1_RX_TXBBRCAL 0x79 /* Core 1 RX TX BB RCAL */
-#define B2055_C1_TX_RF_SPGA 0x7A /* Core 1 TX RF SGM PGA */
-#define B2055_C1_TX_RF_SPAD 0x7B /* Core 1 TX RF SGM PAD */
-#define B2055_C1_TX_RF_CNTPGA1 0x7C /* Core 1 TX RF counter PGA 1 */
-#define B2055_C1_TX_RF_CNTPAD1 0x7D /* Core 1 TX RF counter PAD 1 */
-#define B2055_C1_TX_RF_PGAIDAC 0x7E /* Core 1 TX RF PGA IDAC */
-#define B2055_C1_TX_PGAPADTN 0x7F /* Core 1 TX PGA PAD TN */
-#define B2055_C1_TX_PADIDAC1 0x80 /* Core 1 TX PAD IDAC 1 */
-#define B2055_C1_TX_PADIDAC2 0x81 /* Core 1 TX PAD IDAC 2 */
-#define B2055_C1_TX_MXBGTRIM 0x82 /* Core 1 TX MX B/G TRIM */
-#define B2055_C1_TX_RF_RCAL 0x83 /* Core 1 TX RF RCAL */
-#define B2055_C1_TX_RF_PADTSSI1 0x84 /* Core 1 TX RF PAD TSSI1 */
-#define B2055_C1_TX_RF_PADTSSI2 0x85 /* Core 1 TX RF PAD TSSI2 */
-#define B2055_C1_TX_RF_SPARE 0x86 /* Core 1 TX RF spare */
-#define B2055_C1_TX_RF_IQCAL1 0x87 /* Core 1 TX RF I/Q CAL 1 */
-#define B2055_C1_TX_RF_IQCAL2 0x88 /* Core 1 TX RF I/Q CAL 2 */
-#define B2055_C1_TXBB_RCCAL 0x89 /* Core 1 TXBB RC CAL Control */
-#define B2055_C1_TXBB_LPF1 0x8A /* Core 1 TXBB LPF 1 */
-#define B2055_C1_TX_VOSCNCL 0x8B /* Core 1 TX VOS CNCL */
-#define B2055_C1_TX_LPF_MXGMIDAC 0x8C /* Core 1 TX LPF MXGM IDAC */
-#define B2055_C1_TX_BB_MXGM 0x8D /* Core 1 TX BB MXGM */
-#define B2055_C2_LGBUF_ATUNE 0x8E /* Core 2 LGBUF A tune */
-#define B2055_C2_LGBUF_GTUNE 0x8F /* Core 2 LGBUF G tune */
-#define B2055_C2_LGBUF_DIV 0x90 /* Core 2 LGBUF div */
-#define B2055_C2_LGBUF_AIDAC 0x91 /* Core 2 LGBUF A IDAC */
-#define B2055_C2_LGBUF_GIDAC 0x92 /* Core 2 LGBUF G IDAC */
-#define B2055_C2_LGBUF_IDACFO 0x93 /* Core 2 LGBUF IDAC filter override */
-#define B2055_C2_LGBUF_SPARE 0x94 /* Core 2 LGBUF spare */
-#define B2055_C2_RX_RFSPC1 0x95 /* Core 2 RX RF SPC1 */
-#define B2055_C2_RX_RFR1 0x96 /* Core 2 RX RF reg 1 */
-#define B2055_C2_RX_RFR2 0x97 /* Core 2 RX RF reg 2 */
-#define B2055_C2_RX_RFRCAL 0x98 /* Core 2 RX RF RCAL */
-#define B2055_C2_RX_BB_BLCMP 0x99 /* Core 2 RX Baseband BUFI LPF CMP */
-#define B2055_C2_RX_BB_LPF 0x9A /* Core 2 RX Baseband LPF */
-#define B2055_C2_RX_BB_MIDACHP 0x9B /* Core 2 RX Baseband MIDAC High-pass */
-#define B2055_C2_RX_BB_VGA1IDAC 0x9C /* Core 2 RX Baseband VGA1 IDAC */
-#define B2055_C2_RX_BB_VGA2IDAC 0x9D /* Core 2 RX Baseband VGA2 IDAC */
-#define B2055_C2_RX_BB_VGA3IDAC 0x9E /* Core 2 RX Baseband VGA3 IDAC */
-#define B2055_C2_RX_BB_BUFOCTL 0x9F /* Core 2 RX Baseband BUFO Control */
-#define B2055_C2_RX_BB_RCCALCTL 0xA0 /* Core 2 RX Baseband RCCAL Control */
-#define B2055_C2_RX_BB_RSSICTL1 0xA1 /* Core 2 RX Baseband RSSI Control 1 */
-#define B2055_C2_RX_BB_RSSICTL2 0xA2 /* Core 2 RX Baseband RSSI Control 2 */
-#define B2055_C2_RX_BB_RSSICTL3 0xA3 /* Core 2 RX Baseband RSSI Control 3 */
-#define B2055_C2_RX_BB_RSSICTL4 0xA4 /* Core 2 RX Baseband RSSI Control 4 */
-#define B2055_C2_RX_BB_RSSICTL5 0xA5 /* Core 2 RX Baseband RSSI Control 5 */
-#define B2055_C2_RX_BB_REG 0xA6 /* Core 2 RX Baseband Regulator */
-#define B2055_C2_RX_BB_SPARE1 0xA7 /* Core 2 RX Baseband spare 1 */
-#define B2055_C2_RX_TXBBRCAL 0xA8 /* Core 2 RX TX BB RCAL */
-#define B2055_C2_TX_RF_SPGA 0xA9 /* Core 2 TX RF SGM PGA */
-#define B2055_C2_TX_RF_SPAD 0xAA /* Core 2 TX RF SGM PAD */
-#define B2055_C2_TX_RF_CNTPGA1 0xAB /* Core 2 TX RF counter PGA 1 */
-#define B2055_C2_TX_RF_CNTPAD1 0xAC /* Core 2 TX RF counter PAD 1 */
-#define B2055_C2_TX_RF_PGAIDAC 0xAD /* Core 2 TX RF PGA IDAC */
-#define B2055_C2_TX_PGAPADTN 0xAE /* Core 2 TX PGA PAD TN */
-#define B2055_C2_TX_PADIDAC1 0xAF /* Core 2 TX PAD IDAC 1 */
-#define B2055_C2_TX_PADIDAC2 0xB0 /* Core 2 TX PAD IDAC 2 */
-#define B2055_C2_TX_MXBGTRIM 0xB1 /* Core 2 TX MX B/G TRIM */
-#define B2055_C2_TX_RF_RCAL 0xB2 /* Core 2 TX RF RCAL */
-#define B2055_C2_TX_RF_PADTSSI1 0xB3 /* Core 2 TX RF PAD TSSI1 */
-#define B2055_C2_TX_RF_PADTSSI2 0xB4 /* Core 2 TX RF PAD TSSI2 */
-#define B2055_C2_TX_RF_SPARE 0xB5 /* Core 2 TX RF spare */
-#define B2055_C2_TX_RF_IQCAL1 0xB6 /* Core 2 TX RF I/Q CAL 1 */
-#define B2055_C2_TX_RF_IQCAL2 0xB7 /* Core 2 TX RF I/Q CAL 2 */
-#define B2055_C2_TXBB_RCCAL 0xB8 /* Core 2 TXBB RC CAL Control */
-#define B2055_C2_TXBB_LPF1 0xB9 /* Core 2 TXBB LPF 1 */
-#define B2055_C2_TX_VOSCNCL 0xBA /* Core 2 TX VOS CNCL */
-#define B2055_C2_TX_LPF_MXGMIDAC 0xBB /* Core 2 TX LPF MXGM IDAC */
-#define B2055_C2_TX_BB_MXGM 0xBC /* Core 2 TX BB MXGM */
-#define B2055_PRG_GCHP21 0xBD /* PRG GC HPVGA23 21 */
-#define B2055_PRG_GCHP22 0xBE /* PRG GC HPVGA23 22 */
-#define B2055_PRG_GCHP23 0xBF /* PRG GC HPVGA23 23 */
-#define B2055_PRG_GCHP24 0xC0 /* PRG GC HPVGA23 24 */
-#define B2055_PRG_GCHP25 0xC1 /* PRG GC HPVGA23 25 */
-#define B2055_PRG_GCHP26 0xC2 /* PRG GC HPVGA23 26 */
-#define B2055_PRG_GCHP27 0xC3 /* PRG GC HPVGA23 27 */
-#define B2055_PRG_GCHP28 0xC4 /* PRG GC HPVGA23 28 */
-#define B2055_PRG_GCHP29 0xC5 /* PRG GC HPVGA23 29 */
-#define B2055_PRG_GCHP30 0xC6 /* PRG GC HPVGA23 30 */
-#define B2055_C1_LNA_GAINBST 0xCD /* Core 1 LNA GAINBST */
-#define B2055_C1_B0NB_RSSIVCM 0xD2 /* Core 1 B0 narrow-band RSSI VCM */
-#define B2055_C1_GENSPARE2 0xD6 /* Core 1 GEN spare 2 */
-#define B2055_C2_LNA_GAINBST 0xD9 /* Core 2 LNA GAINBST */
-#define B2055_C2_B0NB_RSSIVCM 0xDE /* Core 2 B0 narrow-band RSSI VCM */
-#define B2055_C2_GENSPARE2 0xE2 /* Core 2 GEN spare 2 */
-
-
-
struct b43_wldev;
struct b43_chanspec {
- u8 channel;
- u8 sideband;
- u8 b_width;
- u8 b_freq;
+ u16 center_freq;
+ enum nl80211_channel_type channel_type;
};
struct b43_phy_n_iq_comp {
@@ -984,8 +772,6 @@ struct b43_phy_n {
u16 papd_epsilon_offset[2];
s32 preamble_override;
u32 bb_mult_save;
- u8 b_width;
- struct b43_chanspec radio_chanspec;
bool gain_boost;
bool elna_gain_config;
diff --git a/drivers/net/wireless/b43/radio_2055.c b/drivers/net/wireless/b43/radio_2055.c
new file mode 100644
index 00000000000..1b5316586cb
--- /dev/null
+++ b/drivers/net/wireless/b43/radio_2055.c
@@ -0,0 +1,1332 @@
+/*
+
+ Broadcom B43 wireless driver
+ IEEE 802.11n PHY and radio device dat