diff options
Diffstat (limited to 'drivers/net/tc35815.c')
| -rw-r--r-- | drivers/net/tc35815.c | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/net/tc35815.c b/drivers/net/tc35815.c index b6eec8cea20..7ca51cebcdd 100644 --- a/drivers/net/tc35815.c +++ b/drivers/net/tc35815.c @@ -119,13 +119,13 @@ struct tc35815_regs { /* * Bit assignments */ -/* DMA_Ctl bit asign ------------------------------------------------------- */ +/* DMA_Ctl bit assign ------------------------------------------------------- */ #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */ #define DMA_RxAlign_1 0x00400000 #define DMA_RxAlign_2 0x00800000 #define DMA_RxAlign_3 0x00c00000 #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */ -#define DMA_IntMask 0x00040000 /* 1:Interupt mask */ +#define DMA_IntMask 0x00040000 /* 1:Interrupt mask */ #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */ #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */ #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */ @@ -134,11 +134,11 @@ struct tc35815_regs { #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */ #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */ -/* RxFragSize bit asign ---------------------------------------------------- */ +/* RxFragSize bit assign ---------------------------------------------------- */ #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */ #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */ -/* MAC_Ctl bit asign ------------------------------------------------------- */ +/* MAC_Ctl bit assign ------------------------------------------------------- */ #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */ #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */ #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */ @@ -152,7 +152,7 @@ struct tc35815_regs { #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */ #define MAC_HaltReq 0x00000001 /* 1:Halt request */ -/* PROM_Ctl bit asign ------------------------------------------------------ */ +/* PROM_Ctl bit assign ------------------------------------------------------ */ #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */ #define PROM_Read 0x00004000 /*10:Read operation */ #define PROM_Write 0x00002000 /*01:Write operation */ @@ -162,7 +162,7 @@ struct tc35815_regs { #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */ /*00xxxx: disable */ -/* CAM_Ctl bit asign ------------------------------------------------------- */ +/* CAM_Ctl bit assign ------------------------------------------------------- */ #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */ #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/ /* accept other */ @@ -170,7 +170,7 @@ struct tc35815_regs { #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */ #define CAM_StationAcc 0x00000001 /* 1:unicast accept */ -/* CAM_Ena bit asign ------------------------------------------------------- */ +/* CAM_Ena bit assign ------------------------------------------------------- */ #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */ #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */ #define CAM_Ena_Bit(index) (1 << (index)) @@ -178,7 +178,7 @@ struct tc35815_regs { #define CAM_ENTRY_SOURCE 1 #define CAM_ENTRY_MACCTL 20 -/* Tx_Ctl bit asign -------------------------------------------------------- */ +/* Tx_Ctl bit assign -------------------------------------------------------- */ #define Tx_En 0x00000001 /* 1:Transmit enable */ #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */ #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */ @@ -192,7 +192,7 @@ struct tc35815_regs { #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */ #define Tx_EnComp 0x00004000 /* 1:Enable Completion */ -/* Tx_Stat bit asign ------------------------------------------------------- */ +/* Tx_Stat bit assign ------------------------------------------------------- */ #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */ #define Tx_ExColl 0x00000010 /* Excessive Collision */ #define Tx_TXDefer 0x00000020 /* Transmit Defered */ @@ -208,7 +208,7 @@ struct tc35815_regs { #define Tx_Halted 0x00008000 /* Tx Halted */ #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */ -/* Rx_Ctl bit asign -------------------------------------------------------- */ +/* Rx_Ctl bit assign -------------------------------------------------------- */ #define Rx_EnGood 0x00004000 /* 1:Enable Good */ #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */ #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */ @@ -222,7 +222,7 @@ struct tc35815_regs { #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */ #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */ -/* Rx_Stat bit asign ------------------------------------------------------- */ +/* Rx_Stat bit assign ------------------------------------------------------- */ #define Rx_Halted 0x00008000 /* Rx Halted */ #define Rx_Good 0x00004000 /* Rx Good */ #define Rx_RxPar 0x00002000 /* Rx Parity Error */ @@ -238,7 +238,7 @@ struct tc35815_regs { #define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */ -/* Int_En bit asign -------------------------------------------------------- */ +/* Int_En bit assign -------------------------------------------------------- */ #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */ #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */ #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */ @@ -253,7 +253,7 @@ struct tc35815_regs { #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */ /* Exhausted Enable */ -/* Int_Src bit asign ------------------------------------------------------- */ +/* Int_Src bit assign ------------------------------------------------------- */ #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */ #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */ #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */ @@ -270,8 +270,8 @@ struct tc35815_regs { #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */ #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */ -/* MD_CA bit asign --------------------------------------------------------- */ -#define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */ +/* MD_CA bit assign --------------------------------------------------------- */ +#define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */ #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */ #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */ @@ -296,7 +296,7 @@ struct BDesc { #define FD_ALIGN 16 -/* Frame Descripter bit asign ---------------------------------------------- */ +/* Frame Descripter bit assign ---------------------------------------------- */ #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */ #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */ #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */ @@ -309,8 +309,8 @@ struct BDesc { #define FD_Next_EOL 0x00000001 /* FD EOL indicator */ #define FD_BDCnt_SHIFT 16 -/* Buffer Descripter bit asign --------------------------------------------- */ -#define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */ +/* Buffer Descripter bit assign --------------------------------------------- */ +#define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */ #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */ #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */ #define BD_CownsBD 0x80000000 /* BD Controller owner bit */ @@ -339,7 +339,7 @@ struct BDesc { #define TX_THRESHOLD 1024 /* used threshold with packet max byte for low pci transfer ability.*/ #define TX_THRESHOLD_MAX 1536 -/* setting threshold max value when overrun error occured this count. */ +/* setting threshold max value when overrun error occurred this count. */ #define TX_THRESHOLD_KEEP_LIMIT 10 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */ |