diff options
Diffstat (limited to 'drivers/net/ixp2000')
| -rw-r--r-- | drivers/net/ixp2000/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/net/ixp2000/Makefile | 3 | ||||
| -rw-r--r-- | drivers/net/ixp2000/caleb.c | 137 | ||||
| -rw-r--r-- | drivers/net/ixp2000/caleb.h | 22 | ||||
| -rw-r--r-- | drivers/net/ixp2000/enp2611.c | 245 | ||||
| -rw-r--r-- | drivers/net/ixp2000/ixp2400-msf.c | 213 | ||||
| -rw-r--r-- | drivers/net/ixp2000/ixp2400-msf.h | 115 | ||||
| -rw-r--r-- | drivers/net/ixp2000/ixp2400_rx.uc | 408 | ||||
| -rw-r--r-- | drivers/net/ixp2000/ixp2400_rx.ucode | 130 | ||||
| -rw-r--r-- | drivers/net/ixp2000/ixp2400_tx.uc | 272 | ||||
| -rw-r--r-- | drivers/net/ixp2000/ixp2400_tx.ucode | 98 | ||||
| -rw-r--r-- | drivers/net/ixp2000/ixpdev.c | 421 | ||||
| -rw-r--r-- | drivers/net/ixp2000/ixpdev.h | 27 | ||||
| -rw-r--r-- | drivers/net/ixp2000/ixpdev_priv.h | 57 | ||||
| -rw-r--r-- | drivers/net/ixp2000/pm3386.c | 334 | ||||
| -rw-r--r-- | drivers/net/ixp2000/pm3386.h | 28 |
16 files changed, 2516 insertions, 0 deletions
diff --git a/drivers/net/ixp2000/Kconfig b/drivers/net/ixp2000/Kconfig new file mode 100644 index 00000000000..2fec2415651 --- /dev/null +++ b/drivers/net/ixp2000/Kconfig @@ -0,0 +1,6 @@ +config ENP2611_MSF_NET + tristate "Radisys ENP2611 MSF network interface support" + depends on ARCH_ENP2611 + help + This is a driver for the MSF network interface unit in + the IXP2400 on the Radisys ENP2611 platform. diff --git a/drivers/net/ixp2000/Makefile b/drivers/net/ixp2000/Makefile new file mode 100644 index 00000000000..fd38351ceaa --- /dev/null +++ b/drivers/net/ixp2000/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_ENP2611_MSF_NET) += enp2611_mod.o + +enp2611_mod-objs := caleb.o enp2611.o ixp2400-msf.o ixpdev.o pm3386.o diff --git a/drivers/net/ixp2000/caleb.c b/drivers/net/ixp2000/caleb.c new file mode 100644 index 00000000000..3595e107df2 --- /dev/null +++ b/drivers/net/ixp2000/caleb.c @@ -0,0 +1,137 @@ +/* + * Helper functions for the SPI-3 bridge FPGA on the Radisys ENP2611 + * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> + * Dedicated to Marija Kulikova. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/config.h> +#include <linux/module.h> +#include <linux/delay.h> +#include <asm/io.h> +#include "caleb.h" + +#define CALEB_IDLO 0x00 +#define CALEB_IDHI 0x01 +#define CALEB_RID 0x02 +#define CALEB_RESET 0x03 +#define CALEB_INTREN0 0x04 +#define CALEB_INTREN1 0x05 +#define CALEB_INTRSTAT0 0x06 +#define CALEB_INTRSTAT1 0x07 +#define CALEB_PORTEN 0x08 +#define CALEB_BURST 0x09 +#define CALEB_PORTPAUS 0x0A +#define CALEB_PORTPAUSD 0x0B +#define CALEB_PHY0RX 0x10 +#define CALEB_PHY1RX 0x11 +#define CALEB_PHY0TX 0x12 +#define CALEB_PHY1TX 0x13 +#define CALEB_IXPRX_HI_CNTR 0x15 +#define CALEB_PHY0RX_HI_CNTR 0x16 +#define CALEB_PHY1RX_HI_CNTR 0x17 +#define CALEB_IXPRX_CNTR 0x18 +#define CALEB_PHY0RX_CNTR 0x19 +#define CALEB_PHY1RX_CNTR 0x1A +#define CALEB_IXPTX_CNTR 0x1B +#define CALEB_PHY0TX_CNTR 0x1C +#define CALEB_PHY1TX_CNTR 0x1D +#define CALEB_DEBUG0 0x1E +#define CALEB_DEBUG1 0x1F + + +static u8 caleb_reg_read(int reg) +{ + u8 value; + + value = *((volatile u8 *)(ENP2611_CALEB_VIRT_BASE + reg)); + +// printk(KERN_INFO "caleb_reg_read(%d) = %.2x\n", reg, value); + + return value; +} + +static void caleb_reg_write(int reg, u8 value) +{ + u8 dummy; + +// printk(KERN_INFO "caleb_reg_write(%d, %.2x)\n", reg, value); + + *((volatile u8 *)(ENP2611_CALEB_VIRT_BASE + reg)) = value; + + dummy = *((volatile u8 *)ENP2611_CALEB_VIRT_BASE); + __asm__ __volatile__("mov %0, %0" : "+r" (dummy)); +} + + +void caleb_reset(void) +{ + /* + * Perform a chip reset. + */ + caleb_reg_write(CALEB_RESET, 0x02); + udelay(1); + + /* + * Enable all interrupt sources. This is needed to get + * meaningful results out of the status bits (register 6 + * and 7.) + */ + caleb_reg_write(CALEB_INTREN0, 0xff); + caleb_reg_write(CALEB_INTREN1, 0x07); + + /* + * Set RX and TX FIFO thresholds to 1.5kb. + */ + caleb_reg_write(CALEB_PHY0RX, 0x11); + caleb_reg_write(CALEB_PHY1RX, 0x11); + caleb_reg_write(CALEB_PHY0TX, 0x11); + caleb_reg_write(CALEB_PHY1TX, 0x11); + + /* + * Program SPI-3 burst size. + */ + caleb_reg_write(CALEB_BURST, 0); // 64-byte RBUF mpackets +// caleb_reg_write(CALEB_BURST, 1); // 128-byte RBUF mpackets +// caleb_reg_write(CALEB_BURST, 2); // 256-byte RBUF mpackets +} + +void caleb_enable_rx(int port) +{ + u8 temp; + + temp = caleb_reg_read(CALEB_PORTEN); + temp |= 1 << port; + caleb_reg_write(CALEB_PORTEN, temp); +} + +void caleb_disable_rx(int port) +{ + u8 temp; + + temp = caleb_reg_read(CALEB_PORTEN); + temp &= ~(1 << port); + caleb_reg_write(CALEB_PORTEN, temp); +} + +void caleb_enable_tx(int port) +{ + u8 temp; + + temp = caleb_reg_read(CALEB_PORTEN); + temp |= 1 << (port + 4); + caleb_reg_write(CALEB_PORTEN, temp); +} + +void caleb_disable_tx(int port) +{ + u8 temp; + + temp = caleb_reg_read(CALEB_PORTEN); + temp &= ~(1 << (port + 4)); + caleb_reg_write(CALEB_PORTEN, temp); +} diff --git a/drivers/net/ixp2000/caleb.h b/drivers/net/ixp2000/caleb.h new file mode 100644 index 00000000000..e93a1ef5b8a --- /dev/null +++ b/drivers/net/ixp2000/caleb.h @@ -0,0 +1,22 @@ +/* + * Helper functions for the SPI-3 bridge FPGA on the Radisys ENP2611 + * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> + * Dedicated to Marija Kulikova. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __CALEB_H +#define __CALEB_H + +void caleb_reset(void); +void caleb_enable_rx(int port); +void caleb_disable_rx(int port); +void caleb_enable_tx(int port); +void caleb_disable_tx(int port); + + +#endif diff --git a/drivers/net/ixp2000/enp2611.c b/drivers/net/ixp2000/enp2611.c new file mode 100644 index 00000000000..d82651a97ba --- /dev/null +++ b/drivers/net/ixp2000/enp2611.c @@ -0,0 +1,245 @@ +/* + * IXP2400 MSF network device driver for the Radisys ENP2611 + * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> + * Dedicated to Marija Kulikova. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/config.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/netdevice.h> +#include <linux/etherdevice.h> +#include <linux/init.h> +#include <linux/moduleparam.h> +#include <asm/arch/uengine.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include "ixpdev.h" +#include "caleb.h" +#include "ixp2400-msf.h" +#include "pm3386.h" + +/*********************************************************************** + * The Radisys ENP2611 is a PCI form factor board with three SFP GBIC + * slots, connected via two PMC/Sierra 3386s and an SPI-3 bridge FPGA + * to the IXP2400. + * + * +-------------+ + * SFP GBIC #0 ---+ | +---------+ + * | PM3386 #0 +-------+ | + * SFP GBIC #1 ---+ | | "Caleb" | +---------+ + * +-------------+ | | | | + * | SPI-3 +---------+ IXP2400 | + * +-------------+ | bridge | | | + * SFP GBIC #2 ---+ | | FPGA | +---------+ + * | PM3386 #1 +-------+ | + * | | +---------+ + * +-------------+ + * ^ ^ ^ + * | 1.25Gbaud | 104MHz | 104MHz + * | SERDES ea. | SPI-3 ea. | SPI-3 + * + ***********************************************************************/ +static struct ixp2400_msf_parameters enp2611_msf_parameters = +{ + .rx_mode = IXP2400_RX_MODE_UTOPIA_POS | + IXP2400_RX_MODE_1x32 | + IXP2400_RX_MODE_MPHY | + IXP2400_RX_MODE_MPHY_32 | + IXP2400_RX_MODE_MPHY_POLLED_STATUS | + IXP2400_RX_MODE_MPHY_LEVEL3 | + IXP2400_RX_MODE_RBUF_SIZE_64, + + .rxclk01_multiplier = IXP2400_PLL_MULTIPLIER_16, + + .rx_poll_ports = 3, + + .rx_channel_mode = { + IXP2400_PORT_RX_MODE_MASTER | + IXP2400_PORT_RX_MODE_POS_PHY | + IXP2400_PORT_RX_MODE_POS_PHY_L3 | + IXP2400_PORT_RX_MODE_ODD_PARITY | + IXP2400_PORT_RX_MODE_2_CYCLE_DECODE, + + IXP2400_PORT_RX_MODE_MASTER | + IXP2400_PORT_RX_MODE_POS_PHY | + IXP2400_PORT_RX_MODE_POS_PHY_L3 | + IXP2400_PORT_RX_MODE_ODD_PARITY | + IXP2400_PORT_RX_MODE_2_CYCLE_DECODE, + + IXP2400_PORT_RX_MODE_MASTER | + IXP2400_PORT_RX_MODE_POS_PHY | + IXP2400_PORT_RX_MODE_POS_PHY_L3 | + IXP2400_PORT_RX_MODE_ODD_PARITY | + IXP2400_PORT_RX_MODE_2_CYCLE_DECODE, + + IXP2400_PORT_RX_MODE_MASTER | + IXP2400_PORT_RX_MODE_POS_PHY | + IXP2400_PORT_RX_MODE_POS_PHY_L3 | + IXP2400_PORT_RX_MODE_ODD_PARITY | + IXP2400_PORT_RX_MODE_2_CYCLE_DECODE + }, + + .tx_mode = IXP2400_TX_MODE_UTOPIA_POS | + IXP2400_TX_MODE_1x32 | + IXP2400_TX_MODE_MPHY | + IXP2400_TX_MODE_MPHY_32 | + IXP2400_TX_MODE_MPHY_POLLED_STATUS | + IXP2400_TX_MODE_MPHY_LEVEL3 | + IXP2400_TX_MODE_TBUF_SIZE_64, + + .txclk01_multiplier = IXP2400_PLL_MULTIPLIER_16, + + .tx_poll_ports = 3, + + .tx_channel_mode = { + IXP2400_PORT_TX_MODE_MASTER | + IXP2400_PORT_TX_MODE_POS_PHY | + IXP2400_PORT_TX_MODE_ODD_PARITY | + IXP2400_PORT_TX_MODE_2_CYCLE_DECODE, + + IXP2400_PORT_TX_MODE_MASTER | + IXP2400_PORT_TX_MODE_POS_PHY | + IXP2400_PORT_TX_MODE_ODD_PARITY | + IXP2400_PORT_TX_MODE_2_CYCLE_DECODE, + + IXP2400_PORT_TX_MODE_MASTER | + IXP2400_PORT_TX_MODE_POS_PHY | + IXP2400_PORT_TX_MODE_ODD_PARITY | + IXP2400_PORT_TX_MODE_2_CYCLE_DECODE, + + IXP2400_PORT_TX_MODE_MASTER | + IXP2400_PORT_TX_MODE_POS_PHY | + IXP2400_PORT_TX_MODE_ODD_PARITY | + IXP2400_PORT_TX_MODE_2_CYCLE_DECODE + } +}; + +struct enp2611_ixpdev_priv +{ + struct ixpdev_priv ixpdev_priv; + struct net_device_stats stats; +}; + +static struct net_device *nds[3]; +static struct timer_list link_check_timer; + +static struct net_device_stats *enp2611_get_stats(struct net_device *dev) +{ + struct enp2611_ixpdev_priv *ip = netdev_priv(dev); + + pm3386_get_stats(ip->ixpdev_priv.channel, &(ip->stats)); + + return &(ip->stats); +} + +/* @@@ Poll the SFP moddef0 line too. */ +/* @@@ Try to use the pm3386 DOOL interrupt as well. */ +static void enp2611_check_link_status(unsigned long __dummy) +{ + int i; + + for (i = 0; i < 3; i++) { + struct net_device *dev; + int status; + + dev = nds[i]; + + status = pm3386_is_link_up(i); + if (status && !netif_carrier_ok(dev)) { + /* @@@ Should report autonegotiation status. */ + printk(KERN_INFO "%s: NIC Link is Up\n", dev->name); + + pm3386_enable_tx(i); + caleb_enable_tx(i); + netif_carrier_on(dev); + } else if (!status && netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: NIC Link is Down\n", dev->name); + + netif_carrier_off(dev); + caleb_disable_tx(i); + pm3386_disable_tx(i); + } + } + + link_check_timer.expires = jiffies + HZ / 10; + add_timer(&link_check_timer); +} + +static void enp2611_set_port_admin_status(int port, int up) +{ + if (up) { + caleb_enable_rx(port); + + pm3386_set_carrier(port, 1); + pm3386_enable_rx(port); + } else { + caleb_disable_tx(port); + pm3386_disable_tx(port); + /* @@@ Flush out pending packets. */ + pm3386_set_carrier(port, 0); + + pm3386_disable_rx(port); + caleb_disable_rx(port); + } +} + +static int __init enp2611_init_module(void) +{ + int i; + + if (!machine_is_enp2611()) + return -ENODEV; + + caleb_reset(); + pm3386_reset(); + + for (i = 0; i < 3; i++) { + nds[i] = ixpdev_alloc(i, sizeof(struct enp2611_ixpdev_priv)); + if (nds[i] == NULL) { + while (--i >= 0) + free_netdev(nds[i]); + return -ENOMEM; + } + + SET_MODULE_OWNER(nds[i]); + nds[i]->get_stats = enp2611_get_stats; + pm3386_init_port(i); + pm3386_get_mac(i, nds[i]->dev_addr); + } + + ixp2400_msf_init(&enp2611_msf_parameters); + + if (ixpdev_init(3, nds, enp2611_set_port_admin_status)) { + for (i = 0; i < 3; i++) + free_netdev(nds[i]); + return -EINVAL; + } + + init_timer(&link_check_timer); + link_check_timer.function = enp2611_check_link_status; + link_check_timer.expires = jiffies; + add_timer(&link_check_timer); + + return 0; +} + +static void __exit enp2611_cleanup_module(void) +{ + int i; + + del_timer_sync(&link_check_timer); + + ixpdev_deinit(); + for (i = 0; i < 3; i++) + free_netdev(nds[i]); +} + +module_init(enp2611_init_module); +module_exit(enp2611_cleanup_module); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/ixp2000/ixp2400-msf.c b/drivers/net/ixp2000/ixp2400-msf.c new file mode 100644 index 00000000000..48a3a891d3a --- /dev/null +++ b/drivers/net/ixp2000/ixp2400-msf.c @@ -0,0 +1,213 @@ +/* + * Generic library functions for the MSF (Media and Switch Fabric) unit + * found on the Intel IXP2400 network processor. + * + * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> + * Dedicated to Marija Kulikova. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation; either version 2.1 of the + * License, or (at your option) any later version. + */ + +#include <linux/config.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <asm/hardware.h> +#include <asm/arch/ixp2000-regs.h> +#include <asm/delay.h> +#include <asm/io.h> +#include "ixp2400-msf.h" + +/* + * This is the Intel recommended PLL init procedure as described on + * page 340 of the IXP2400/IXP2800 Programmer's Reference Manual. + */ +static void ixp2400_pll_init(struct ixp2400_msf_parameters *mp) +{ + int rx_dual_clock; + int tx_dual_clock; + u32 value; + + /* + * If the RX mode is not 1x32, we have to enable both RX PLLs + * (#0 and #1.) The same thing for the TX direction. + */ + rx_dual_clock = !!(mp->rx_mode & IXP2400_RX_MODE_WIDTH_MASK); + tx_dual_clock = !!(mp->tx_mode & IXP2400_TX_MODE_WIDTH_MASK); + + /* + * Read initial value. + */ + value = ixp2000_reg_read(IXP2000_MSF_CLK_CNTRL); + + /* + * Put PLLs in powerdown and bypass mode. + */ + value |= 0x0000f0f0; + ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value); + + /* + * Set single or dual clock mode bits. + */ + value &= ~0x03000000; + value |= (rx_dual_clock << 24) | (tx_dual_clock << 25); + + /* + * Set multipliers. + */ + value &= ~0x00ff0000; + value |= mp->rxclk01_multiplier << 16; + value |= mp->rxclk23_multiplier << 18; + value |= mp->txclk01_multiplier << 20; + value |= mp->txclk23_multiplier << 22; + + /* + * And write value. + */ + ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value); + + /* + * Disable PLL bypass mode. + */ + value &= ~(0x00005000 | rx_dual_clock << 13 | tx_dual_clock << 15); + ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value); + + /* + * Turn on PLLs. + */ + value &= ~(0x00000050 | rx_dual_clock << 5 | tx_dual_clock << 7); + ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value); + + /* + * Wait for PLLs to lock. There are lock status bits, but IXP2400 + * erratum #65 says that these lock bits should not be relied upon + * as they might not accurately reflect the true state of the PLLs. + */ + udelay(100); +} + +/* + * Needed according to p480 of Programmer's Reference Manual. + */ +static void ixp2400_msf_free_rbuf_entries(struct ixp2400_msf_parameters *mp) +{ + int size_bits; + int i; + + /* + * Work around IXP2400 erratum #69 (silent RBUF-to-DRAM transfer + * corruption) in the Intel-recommended way: do not add the RBUF + * elements susceptible to corruption to the freelist. + */ + size_bits = mp->rx_mode & IXP2400_RX_MODE_RBUF_SIZE_MASK; + if (size_bits == IXP2400_RX_MODE_RBUF_SIZE_64) { + for (i = 1; i < 128; i++) { + if (i == 9 || i == 18 || i == 27) + continue; + ixp2000_reg_write(IXP2000_MSF_RBUF_ELEMENT_DONE, i); + } + } else if (size_bits == IXP2400_RX_MODE_RBUF_SIZE_128) { + for (i = 1; i < 64; i++) { + if (i == 4 || i == 9 || i == 13) + continue; + ixp2000_reg_write(IXP2000_MSF_RBUF_ELEMENT_DONE, i); + } + } else if (size_bits == IXP2400_RX_MODE_RBUF_SIZE_256) { + for (i = 1; i < 32; i++) { + if (i == 2 || i == 4 || i == 6) + continue; + ixp2000_reg_write(IXP2000_MSF_RBUF_ELEMENT_DONE, i); + } + } +} + +static u32 ixp2400_msf_valid_channels(u32 reg) +{ + u32 channels; + + channels = 0; + switch (reg & IXP2400_RX_MODE_WIDTH_MASK) { + case IXP2400_RX_MODE_1x32: + channels = 0x1; + if (reg & IXP2400_RX_MODE_MPHY && + !(reg & IXP2400_RX_MODE_MPHY_32)) + channels = 0xf; + break; + + case IXP2400_RX_MODE_2x16: + channels = 0x5; + break; + + case IXP2400_RX_MODE_4x8: + channels = 0xf; + break; + + case IXP2400_RX_MODE_1x16_2x8: + channels = 0xd; + break; + } + + return channels; +} + +static void ixp2400_msf_enable_rx(struct ixp2400_msf_parameters *mp) +{ + u32 value; + + value = ixp2000_reg_read(IXP2000_MSF_RX_CONTROL) & 0x0fffffff; + value |= ixp2400_msf_valid_channels(mp->rx_mode) << 28; + ixp2000_reg_write(IXP2000_MSF_RX_CONTROL, value); +} + +static void ixp2400_msf_enable_tx(struct ixp2400_msf_parameters *mp) +{ + u32 value; + + value = ixp2000_reg_read(IXP2000_MSF_TX_CONTROL) & 0x0fffffff; + value |= ixp2400_msf_valid_channels(mp->tx_mode) << 28; + ixp2000_reg_write(IXP2000_MSF_TX_CONTROL, value); +} + + +void ixp2400_msf_init(struct ixp2400_msf_parameters *mp) +{ + u32 value; + int i; + + /* + * Init the RX/TX PLLs based on the passed parameter block. + */ + ixp2400_pll_init(mp); + + /* + * Reset MSF. Bit 7 in IXP_RESET_0 resets the MSF. + */ + value = ixp2000_reg_read(IXP2000_RESET0); + ixp2000_reg_write(IXP2000_RESET0, value | 0x80); + ixp2000_reg_write(IXP2000_RESET0, value & ~0x80); + + /* + * Initialise the RX section. + */ + ixp2000_reg_write(IXP2000_MSF_RX_MPHY_POLL_LIMIT, mp->rx_poll_ports - 1); + ixp2000_reg_write(IXP2000_MSF_RX_CONTROL, mp->rx_mode); + for (i = 0; i < 4; i++) { + ixp2000_reg_write(IXP2000_MSF_RX_UP_CONTROL_0 + i, + mp->rx_channel_mode[i]); + } + ixp2400_msf_free_rbuf_entries(mp); + ixp2400_msf_enable_rx(mp); + + /* + * Initialise the TX section. + */ + ixp2000_reg_write(IXP2000_MSF_TX_MPHY_POLL_LIMIT, mp->tx_poll_ports - 1); + ixp2000_reg_write(IXP2000_MSF_TX_CONTROL, mp->tx_mode); + for (i = 0; i < 4; i++) { + ixp2000_reg_write(IXP2000_MSF_TX_UP_CONTROL_0 + i, + mp->tx_channel_mode[i]); + } + ixp2400_msf_enable_tx(mp); +} diff --git a/drivers/net/ixp2000/ixp2400-msf.h b/drivers/net/ixp2000/ixp2400-msf.h new file mode 100644 index 00000000000..3ac1af2771d --- /dev/null +++ b/drivers/net/ixp2000/ixp2400-msf.h @@ -0,0 +1,115 @@ +/* + * Generic library functions for the MSF (Media and Switch Fabric) unit + * found on the Intel IXP2400 network processor. + * + * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> + * Dedicated to Marija Kulikova. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation; either version 2.1 of the + * License, or (at your option) any later version. + */ + +#ifndef __IXP2400_MSF_H +#define __IXP2400_MSF_H + +struct ixp2400_msf_parameters +{ + u32 rx_mode; + unsigned rxclk01_multiplier:2; + unsigned rxclk23_multiplier:2; + unsigned rx_poll_ports:6; + u32 rx_channel_mode[4]; + + u32 tx_mode; + unsigned txclk01_multiplier:2; + unsigned txclk23_multiplier:2; + unsigned tx_poll_ports:6; + u32 tx_channel_mode[4]; +}; + +void ixp2400_msf_init(struct ixp2400_msf_parameters *mp); + +#define IXP2400_PLL_MULTIPLIER_48 0x00 +#define IXP2400_PLL_MULTIPLIER_24 0x01 +#define IXP2400_PLL_MULTIPLIER_16 0x02 +#define IXP2400_PLL_MULTIPLIER_12 0x03 + +#define IXP2400_RX_MODE_CSIX 0x00400000 +#define IXP2400_RX_MODE_UTOPIA_POS 0x00000000 +#define IXP2400_RX_MODE_WIDTH_MASK 0x00300000 +#define IXP2400_RX_MODE_1x16_2x8 0x00300000 +#define IXP2400_RX_MODE_4x8 0x00200000 +#define IXP2400_RX_MODE_2x16 0x00100000 +#define IXP2400_RX_MODE_1x32 0x00000000 +#define IXP2400_RX_MODE_MPHY 0x00080000 +#define IXP2400_RX_MODE_SPHY 0x00000000 +#define IXP2400_RX_MODE_MPHY_32 0x00040000 +#define IXP2400_RX_MODE_MPHY_4 0x00000000 +#define IXP2400_RX_MODE_MPHY_POLLED_STATUS 0x00020000 +#define IXP2400_RX_MODE_MPHY_DIRECT_STATUS 0x00000000 +#define IXP2400_RX_MODE_CBUS_FULL_DUPLEX 0x00010000 +#define IXP2400_RX_MODE_CBUS_SIMPLEX 0x00000000 +#define IXP2400_RX_MODE_MPHY_LEVEL2 0x00004000 +#define IXP2400_RX_MODE_MPHY_LEVEL3 0x00000000 +#define IXP2400_RX_MODE_CBUS_8BIT 0x00002000 +#define IXP2400_RX_MODE_CBUS_4BIT 0x00000000 +#define IXP2400_RX_MODE_CSIX_SINGLE_FREELIST 0x00000200 +#define IXP2400_RX_MODE_CSIX_SPLIT_FREELISTS 0x00000000 +#define IXP2400_RX_MODE_RBUF_SIZE_MASK 0x0000000c +#define IXP2400_RX_MODE_RBUF_SIZE_256 0x00000008 +#define IXP2400_RX_MODE_RBUF_SIZE_128 0x00000004 +#define IXP2400_RX_MODE_RBUF_SIZE_64 0x00000000 + +#define IXP2400_PORT_RX_MODE_SLAVE 0x00000040 +#define IXP2400_PORT_RX_MODE_MASTER 0x00000000 +#define IXP2400_PORT_RX_MODE_POS_PHY_L3 0x00000020 +#define IXP2400_PORT_RX_MODE_POS_PHY_L2 0x00000000 +#define IXP2400_PORT_RX_MODE_POS_PHY 0x00000010 +#define IXP2400_PORT_RX_MODE_UTOPIA 0x00000000 +#define IXP2400_PORT_RX_MODE_EVEN_PARITY 0x0000000c +#define IXP2400_PORT_RX_MODE_ODD_PARITY 0x00000008 +#define IXP2400_PORT_RX_MODE_NO_PARITY 0x00000000 +#define IXP2400_PORT_RX_MODE_UTOPIA_BIG_CELLS 0x00000002 +#define IXP2400_PORT_RX_MODE_UTOPIA_NORMAL_CELLS 0x00000000 +#define IXP2400_PORT_RX_MODE_2_CYCLE_DECODE 0x00000001 +#define IXP2400_PORT_RX_MODE_1_CYCLE_DECODE 0x00000000 + +#define IXP2400_TX_MODE_CSIX 0x00400000 +#define IXP2400_TX_MODE_UTOPIA_POS 0x00000000 +#define IXP2400_TX_MODE_WIDTH_MASK 0x00300000 +#define IXP2400_TX_MODE_1x16_2x8 0x00300000 +#define IXP2400_TX_MODE_4x8 0x00200000 +#define IXP2400_TX_MODE_2x16 0x00100000 +#define IXP2400_TX_MODE_1x32 0x00000000 +#define IXP2400_TX_MODE_MPHY 0x00080000 +#define IXP2400_TX_MODE_SPHY 0x00000000 +#define IXP2400_TX_MODE_MPHY_32 0x00040000 +#define IXP2400_TX_MODE_MPHY_4 0x00000000 +#define IXP2400_TX_MODE_MPHY_POLLED_STATUS 0x00020000 +#define IXP2400_TX_MODE_MPHY_DIRECT_STATUS 0x00000000 +#define IXP2400_TX_MODE_CBUS_FULL_DUPLEX 0x00010000 +#define IXP2400_TX_MODE_CBUS_SIMPLEX 0x00000000 +#define IXP2400_TX_MODE_MPHY_LEVEL2 0x00004000 +#define IXP2400_TX_MODE_MPHY_LEVEL3 0x00000000 +#define IXP2400_TX_MODE_CBUS_8BIT 0x00002000 +#define IXP2400_TX_MODE_CBUS_4BIT 0x00000000 +#define IXP2400_TX_MODE_TBUF_SIZE_MASK 0x0000000c +#define IXP2400_TX_MODE_TBUF_SIZE_256 0x00000008 +#define IXP2400_TX_MODE_TBUF_SIZE_128 0x00000004 +#define IXP2400_TX_MODE_TBUF_SIZE_64 0x00000000 + +#define IXP2400_PORT_TX_MODE_SLAVE 0x00000040 +#define IXP2400_PORT_TX_MODE_MASTER 0x00000000 +#define IXP2400_PORT_TX_MODE_POS_PHY 0x00000010 +#define IXP2400_PORT_TX_MODE_UTOPIA 0x00000000 +#define IXP2400_PORT_TX_MODE_EVEN_PARITY 0x0000000c +#define IXP2400_PORT_TX_MODE_ODD_PARITY 0x00000008 +#define IXP2400_PORT_TX_MODE_NO_PARITY 0x00000000 +#define IXP2400_PORT_TX_MODE_UTOPIA_BIG_CELLS 0x00000002 +#define IXP2400_PORT_TX_MODE_2_CYCLE_DECODE 0x00000001 +#define IXP2400_PORT_TX_MODE_1_CYCLE_DECODE 0x00000000 + + +#endif diff --git a/drivers/net/ixp2000/ixp2400_rx.uc b/drivers/net/ixp2000/ixp2400_rx.uc new file mode 100644 index 00000000000..42a73e357af --- /dev/null +++ b/drivers/net/ixp2000/ixp2400_rx.uc @@ -0,0 +1,408 @@ +/* + * RX ucode for the Intel IXP2400 in POS-PHY mode. + * Copyright (C) 2004, 2005 Lennert Buytenhek + * Dedicated to Marija Kulikova. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Assumptions made in this code: + * - The IXP2400 MSF is configured for POS-PHY mode, in a mode where + * only one full element list is used. This includes, for example, + * 1x32 SPHY and 1x32 MPHY32, but not 4x8 SPHY or 1x32 MPHY4. (This + * is not an exhaustive list.) + * - The RBUF uses 64-byte mpackets. + * - RX descriptors reside in SRAM, and have the following format: + * struct rx_desc + * { + * // to uengine + * u32 buf_phys_addr; + * u32 buf_length; + * + * // from uengine + * u32 channel; + * u32 pkt_length; + * }; + * - Packet data resides in DRAM. + * - Packet buffer addresses are 8-byte aligned. + * - Scratch ring 0 is rx_pending. + * - Scratch ring 1 is rx_done, and has status condition 'full'. + * - The host triggers rx_done flush and rx_pending refill on seeing INTA. + * - This code is run on all eight threads of the microengine it runs on. + * + * Local memory is used for per-channel RX state. + */ + +#define RX_THREAD_FREELIST_0 0x0030 +#define RBUF_ELEMENT_DONE 0x0044 + +#define CHANNEL_FLAGS *l$index0[0] +#define CHANNEL_FLAG_RECEIVING 1 +#define PACKET_LENGTH *l$index0[1] +#define PACKET_CHECKSUM *l$index0[2] +#define BUFFER_HANDLE *l$index0[3] +#define BUFFER_START *l$index0[4] +#define BUFFER_LENGTH *l$index0[5] + +#define CHANNEL_STATE_SIZE 24 // in bytes +#define CHANNEL_STATE_SHIFT 5 // ceil(log2(state size)) + + + .sig volatile sig1 + .sig volatile sig2 + .sig volatile sig3 + + .sig mpacket_arrived + .reg add_to_rx_freelist + .reg read $rsw0, $rsw1 + .xfer_order $rsw0 $rsw1 + + .reg zero + + /* + * Initialise add_to_rx_freelist. + */ + .begin + .reg temp + .reg temp2 + + immed[add_to_rx_freelist, RX_THREAD_FREELIST_0] + immed_w1[add_to_rx_freelist, (&$rsw0 | (&mpacket_arrived << 12))] + + local_csr_rd[ACTIVE_CTX_STS] + immed[temp, 0] + alu[temp2, temp, and, 0x1f] + alu_shf[add_to_rx_freelist, add_to_rx_freelist, or, temp2, <<20] + alu[temp2, temp, and, 0x80] + alu_shf[add_to_rx_freelist, add_to_rx_freelist, or, temp2, <<18] + .end + + immed[zero, 0] + + /* + * Skip context 0 initialisation? + */ + .begin + br!=ctx[0, mpacket_receive_loop#] + .end + + /* + * Initialise local memory. + */ + .begin + .reg addr + .reg temp + + immed[temp, 0] + init_local_mem_loop#: + alu_shf[addr, --, b, temp, <<CHANNEL_STATE_SHIFT] + local_csr_wr[ACTIVE_LM_ADDR_0, addr] + nop + nop + nop + + immed[CHANNEL_FLAGS, 0] + + alu[temp, temp, +, 1] + alu[--, temp, and, 0x20] + beq[init_local_mem_loop#] + .end + + /* + * Initialise signal pipeline. + */ + .begin + local_csr_wr[SAME_ME_SIGNAL, (&sig1 << 3)] + .set_sig sig1 + + local_csr_wr[SAME_ME_SIGNAL, (&sig2 << 3)] + .set_sig sig2 + + local_csr_wr[SAME_ME_SIGNAL, (&sig3 << 3)] + .set_sig sig3 + .end + +mpacket_receive_loop#: + /* + * Synchronise and wait for mpacket. + */ + .begin + ctx_arb[sig1] + local_csr_wr[SAME_ME_SIGNAL, (0x80 | (&sig1 << 3))] + + msf[fast_wr, --, add_to_rx_freelist, 0] + .set_sig mpacket_arrived + ctx_arb[mpacket_arrived] + .set $rsw0 $rsw1 + .end + + /* + * We halt if we see {inbparerr,parerr,null,soperror}. + */ + .begin + alu_shf[--, 0x1b, and, $rsw0, >>8] + bne[abort_rswerr#] + .end + + /* + * Point local memory pointer to this channel's state area. + */ + .begin + .reg chanaddr + + alu[chanaddr, $rsw0, and, 0x1f] + alu_shf[chanaddr, --, b, chanaddr, <<CHANNEL_STATE_SHIFT] + local_csr_wr[ACTIVE_LM_ADDR_0, chanaddr] + nop + nop + nop + .end + + /* + * Check whether we received a SOP mpacket while we were already + * working on a packet, or a non-SOP mpacket while there was no + * packet pending. (SOP == RECEIVING -> abort) If everything's + * okay, update the RECEIVING flag to reflect our new state. + */ + .begin + .reg temp + .reg eop + + #if CHANNEL_FLAG_RECEIVING != 1 + #error CHANNEL_FLAG_RECEIVING is not 1 + #endif + + alu_shf[temp, 1, and, $rsw0, >>15] + alu[temp, temp, xor, CHANNEL_FLAGS] + alu[--, temp, and, CHANNEL_FLAG_RECEIVING] + beq[abort_proterr#] + + alu_shf[eop, 1, and, $rsw0, >>14] + alu[CHANNEL_FLAGS, temp, xor, eop] + .end + + /* + * Copy the mpacket into the right spot, and in case of EOP, + * write back the descriptor and pass the packet on. + */ + .begin + .reg buffer_offset + .reg _packet_length + .reg _packet_checksum + .reg _buffer_handle + .reg _buffer_start + .reg _buffer_length + + /* + * Determine buffer_offset, _packet_length and + * _packet_checksum. + */ + .begin + .reg temp + + alu[--, 1, and, $rsw0, >>15] + beq[not_sop#] + + immed[PACKET_LENGTH, 0] + immed[PACKET_CHECKSUM, 0] + + not_sop#: + alu[buffer_offset, --, b, PACKET_LENGTH] + alu_shf[temp, 0xff, and, $rsw0, >>16] + alu[_packet_length, buffer_offset, +, temp] + alu[PACKET_LENGTH, --, b, _packet_length] + + immed[temp, 0xffff] + alu[temp, $rsw1, and, temp] + alu[_packet_checksum, PACKET_CHECKSUM, +, temp] + alu[PACKET_CHECKSUM, --, b, _packet_checksum] + .end + + /* + * Allocate buffer in case of SOP. + */ + .begin + .reg temp + + alu[temp, 1, and, $rsw0, >>15] + beq[skip_buffer_alloc#] + + .begin + .sig zzz + .reg read $stemp $stemp2 + .xfer_order $stemp $stemp2 + + rx_nobufs#: + scratch[get, $stemp, zero, 0, 1], ctx_swap[zzz] + alu[_buffer_handle, --, b, $stemp] + beq[rx_nobufs#] + + sram[read, $stemp, _buffer_handle, 0, 2], + ctx_swap[zzz] + alu[_buffer_start, --, b, $stemp] + alu[_buffer_length, --, b, $stemp2] + .end + + skip_buffer_alloc#: + .end + + /* + * Resynchronise. + */ + .begin + ctx_arb[sig2] + local_csr_wr[SAME_ME_SIGNAL, (0x80 | (&sig2 << 3))] + .end + + /* + * Synchronise buffer state. + */ + .begin + .reg temp + + alu[temp, 1, and, $rsw0, >>15] + beq[copy_from_local_mem#] + + alu[BUFFER_HANDLE, --, b, _buffer_handle] + alu[BUFFER_START, --, b, _buffer_start] + alu[BUFFER_LENGTH, --, b, _buffer_length] + br[sync_state_done#] + + copy_from_local_mem#: + alu[_buffer_handle, --, b, BUFFER_HANDLE] + alu[_buffer_start, --, b, BUFFER_START] + alu |