diff options
Diffstat (limited to 'drivers/net/e1000e')
| -rw-r--r-- | drivers/net/e1000e/82571.c | 29 | ||||
| -rw-r--r-- | drivers/net/e1000e/defines.h | 9 | ||||
| -rw-r--r-- | drivers/net/e1000e/e1000.h | 26 | ||||
| -rw-r--r-- | drivers/net/e1000e/es2lan.c | 11 | ||||
| -rw-r--r-- | drivers/net/e1000e/ethtool.c | 48 | ||||
| -rw-r--r-- | drivers/net/e1000e/hw.h | 5 | ||||
| -rw-r--r-- | drivers/net/e1000e/ich8lan.c | 391 | ||||
| -rw-r--r-- | drivers/net/e1000e/lib.c | 60 | ||||
| -rw-r--r-- | drivers/net/e1000e/netdev.c | 866 | ||||
| -rw-r--r-- | drivers/net/e1000e/param.c | 25 | ||||
| -rw-r--r-- | drivers/net/e1000e/phy.c | 21 |
11 files changed, 1029 insertions, 462 deletions
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c index 90155552ea0..f654db9121d 100644 --- a/drivers/net/e1000e/82571.c +++ b/drivers/net/e1000e/82571.c @@ -234,9 +234,6 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) mac->mta_reg_count = 128; /* Set rar entry count */ mac->rar_entry_count = E1000_RAR_ENTRIES; - /* Set if manageability features are enabled. */ - mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) - ? true : false; /* Adaptive IFS supported */ mac->adaptive_ifs = true; @@ -271,6 +268,16 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) func->set_lan_id = e1000_set_lan_id_single_port; func->check_mng_mode = e1000e_check_mng_mode_generic; func->led_on = e1000e_led_on_generic; + + /* FWSM register */ + mac->has_fwsm = true; + /* + * ARC supported; valid only if manageability features are + * enabled. + */ + mac->arc_subsystem_valid = + (er32(FWSM) & E1000_FWSM_MODE_MASK) + ? true : false; break; case e1000_82574: case e1000_82583: @@ -281,6 +288,9 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) default: func->check_mng_mode = e1000e_check_mng_mode_generic; func->led_on = e1000e_led_on_generic; + + /* FWSM register */ + mac->has_fwsm = true; break; } @@ -323,7 +333,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) } /* - * Initialze device specific counter of SMBI acquisition + * Initialize device specific counter of SMBI acquisition * timeouts. */ hw->dev_spec.e82571.smb_counter = 0; @@ -993,9 +1003,10 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) /* ...for both queues. */ switch (mac->type) { case e1000_82573: + e1000e_enable_tx_pkt_filtering(hw); + /* fall through */ case e1000_82574: case e1000_82583: - e1000e_enable_tx_pkt_filtering(hw); reg_data = er32(GCR); reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; ew32(GCR, reg_data); @@ -1137,8 +1148,6 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) default: break; } - - return; } /** @@ -1642,8 +1651,6 @@ static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) /* If the management interface is not enabled, then power down */ if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) e1000_power_down_phy_copper(hw); - - return; } /** @@ -1845,7 +1852,7 @@ struct e1000_info e1000_82574_info = { | FLAG_HAS_SMART_POWER_DOWN | FLAG_HAS_AMT | FLAG_HAS_CTRLEXT_ON_LOAD, - .pba = 20, + .pba = 36, .max_hw_frame_size = DEFAULT_JUMBO, .get_variants = e1000_get_variants_82571, .mac_ops = &e82571_mac_ops, @@ -1862,7 +1869,7 @@ struct e1000_info e1000_82583_info = { | FLAG_HAS_SMART_POWER_DOWN | FLAG_HAS_AMT | FLAG_HAS_CTRLEXT_ON_LOAD, - .pba = 20, + .pba = 36, .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, .get_variants = e1000_get_variants_82571, .mac_ops = &e82571_mac_ops, diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index e301e26d689..4dc02c71ffd 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h @@ -138,6 +138,11 @@ /* Enable MNG packets to host memory */ #define E1000_MANC_EN_MNG2HOST 0x00200000 +#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ +#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ +#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ +#define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ + /* Receive Control */ #define E1000_RCTL_EN 0x00000002 /* enable */ #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ @@ -214,6 +219,8 @@ #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ +#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ @@ -622,6 +629,8 @@ #define NVM_ALT_MAC_ADDR_PTR 0x0037 #define NVM_CHECKSUM_REG 0x003F +#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ + #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h index ee32b9b27a9..c0b3db40bd7 100644 --- a/drivers/net/e1000e/e1000.h +++ b/drivers/net/e1000e/e1000.h @@ -43,25 +43,16 @@ struct e1000_info; -#define e_printk(level, adapter, format, arg...) \ - printk(level "%s: %s: " format, pci_name(adapter->pdev), \ - adapter->netdev->name, ## arg) - -#ifdef DEBUG #define e_dbg(format, arg...) \ - e_printk(KERN_DEBUG , hw->adapter, format, ## arg) -#else -#define e_dbg(format, arg...) do { (void)(hw); } while (0) -#endif - + netdev_dbg(hw->adapter->netdev, format, ## arg) #define e_err(format, arg...) \ - e_printk(KERN_ERR, adapter, format, ## arg) + netdev_err(adapter->netdev, format, ## arg) #define e_info(format, arg...) \ - e_printk(KERN_INFO, adapter, format, ## arg) + netdev_info(adapter->netdev, format, ## arg) #define e_warn(format, arg...) \ - e_printk(KERN_WARNING, adapter, format, ## arg) + netdev_warn(adapter->netdev, format, ## arg) #define e_notice(format, arg...) \ - e_printk(KERN_NOTICE, adapter, format, ## arg) + netdev_notice(adapter->netdev, format, ## arg) /* Interrupt modes, as used by the IntMode parameter */ @@ -159,6 +150,9 @@ struct e1000_info; #define HV_M_STATUS_SPEED_1000 0x0200 #define HV_M_STATUS_LINK_UP 0x0040 +/* Time to wait before putting the device into D3 if there's no link (in ms). */ +#define LINK_TIMEOUT 100 + enum e1000_boards { board_82571, board_82572, @@ -195,6 +189,8 @@ struct e1000_buffer { unsigned long time_stamp; u16 length; u16 next_to_watch; + unsigned int segs; + unsigned int bytecount; u16 mapped_as_page; }; /* Rx */ @@ -370,6 +366,8 @@ struct e1000_adapter { struct work_struct update_phy_task; struct work_struct led_blink_task; struct work_struct print_hang_task; + + bool idle_check; }; struct e1000_info { diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c index 27d21589a69..38d79a66905 100644 --- a/drivers/net/e1000e/es2lan.c +++ b/drivers/net/e1000e/es2lan.c @@ -221,9 +221,12 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter) mac->mta_reg_count = 128; /* Set rar entry count */ mac->rar_entry_count = E1000_RAR_ENTRIES; - /* Set if manageability features are enabled. */ - mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) - ? true : false; + /* FWSM register */ + mac->has_fwsm = true; + /* ARC supported; valid only if manageability features are enabled. */ + mac->arc_subsystem_valid = + (er32(FWSM) & E1000_FWSM_MODE_MASK) + ? true : false; /* Adaptive IFS not supported */ mac->adaptive_ifs = false; @@ -1380,8 +1383,6 @@ static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) if (!(hw->mac.ops.check_mng_mode(hw) || hw->phy.ops.check_reset_block(hw))) e1000_power_down_phy_copper(hw); - - return; } /** diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c index 983493f2330..2c521218102 100644 --- a/drivers/net/e1000e/ethtool.c +++ b/drivers/net/e1000e/ethtool.c @@ -412,7 +412,6 @@ static int e1000_set_tso(struct net_device *netdev, u32 data) netdev->features &= ~NETIF_F_TSO6; } - e_info("TSO is %s\n", data ? "Enabled" : "Disabled"); adapter->flags |= FLAG_TSO_FORCE; return 0; } @@ -1069,10 +1068,10 @@ static void e1000_free_desc_rings(struct e1000_adapter *adapter) if (tx_ring->desc && tx_ring->buffer_info) { for (i = 0; i < tx_ring->count; i++) { if (tx_ring->buffer_info[i].dma) - pci_unmap_single(pdev, + dma_unmap_single(&pdev->dev, tx_ring->buffer_info[i].dma, tx_ring->buffer_info[i].length, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); if (tx_ring->buffer_info[i].skb) dev_kfree_skb(tx_ring->buffer_info[i].skb); } @@ -1081,9 +1080,9 @@ static void e1000_free_desc_rings(struct e1000_adapter *adapter) if (rx_ring->desc && rx_ring->buffer_info) { for (i = 0; i < rx_ring->count; i++) { if (rx_ring->buffer_info[i].dma) - pci_unmap_single(pdev, + dma_unmap_single(&pdev->dev, rx_ring->buffer_info[i].dma, - 2048, PCI_DMA_FROMDEVICE); + 2048, DMA_FROM_DEVICE); if (rx_ring->buffer_info[i].skb) dev_kfree_skb(rx_ring->buffer_info[i].skb); } @@ -1163,9 +1162,10 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) tx_ring->buffer_info[i].skb = skb; tx_ring->buffer_info[i].length = skb->len; tx_ring->buffer_info[i].dma = - pci_map_single(pdev, skb->data, skb->len, - PCI_DMA_TODEVICE); - if (pci_dma_mapping_error(pdev, tx_ring->buffer_info[i].dma)) { + dma_map_single(&pdev->dev, skb->data, skb->len, + DMA_TO_DEVICE); + if (dma_mapping_error(&pdev->dev, + tx_ring->buffer_info[i].dma)) { ret_val = 4; goto err_nomem; } @@ -1226,9 +1226,10 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) skb_reserve(skb, NET_IP_ALIGN); rx_ring->buffer_info[i].skb = skb; rx_ring->buffer_info[i].dma = - pci_map_single(pdev, skb->data, 2048, - PCI_DMA_FROMDEVICE); - if (pci_dma_mapping_error(pdev, rx_ring->buffer_info[i].dma)) { + dma_map_single(&pdev->dev, skb->data, 2048, + DMA_FROM_DEVICE); + if (dma_mapping_error(&pdev->dev, + rx_ring->buffer_info[i].dma)) { ret_val = 8; goto err_nomem; } @@ -1556,10 +1557,10 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter) for (i = 0; i < 64; i++) { /* send the packets */ e1000_create_lbtest_frame(tx_ring->buffer_info[k].skb, 1024); - pci_dma_sync_single_for_device(pdev, + dma_sync_single_for_device(&pdev->dev, tx_ring->buffer_info[k].dma, tx_ring->buffer_info[k].length, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); k++; if (k == tx_ring->count) k = 0; @@ -1569,9 +1570,9 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter) time = jiffies; /* set the start time for the receive */ good_cnt = 0; do { /* receive the sent packets */ - pci_dma_sync_single_for_cpu(pdev, + dma_sync_single_for_cpu(&pdev->dev, rx_ring->buffer_info[l].dma, 2048, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); ret_val = e1000_check_lbtest_frame( rx_ring->buffer_info[l].skb, 1024); @@ -1736,6 +1737,12 @@ static void e1000_diag_test(struct net_device *netdev, if (if_running) dev_open(netdev); } else { + if (!if_running && (adapter->flags & FLAG_HAS_AMT)) { + clear_bit(__E1000_TESTING, &adapter->state); + dev_open(netdev); + set_bit(__E1000_TESTING, &adapter->state); + } + e_info("online testing starting\n"); /* Online tests */ if (e1000_link_test(adapter, &data[4])) @@ -1747,6 +1754,9 @@ static void e1000_diag_test(struct net_device *netdev, data[2] = 0; data[3] = 0; + if (!if_running && (adapter->flags & FLAG_HAS_AMT)) + dev_close(netdev); + clear_bit(__E1000_TESTING, &adapter->state); } msleep_interruptible(4 * 1000); @@ -1889,7 +1899,7 @@ static int e1000_get_coalesce(struct net_device *netdev, { struct e1000_adapter *adapter = netdev_priv(netdev); - if (adapter->itr_setting <= 3) + if (adapter->itr_setting <= 4) ec->rx_coalesce_usecs = adapter->itr_setting; else ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting; @@ -1904,12 +1914,14 @@ static int e1000_set_coalesce(struct net_device *netdev, struct e1000_hw *hw = &adapter->hw; if ((ec->rx_coalesce_usecs > E1000_MAX_ITR_USECS) || - ((ec->rx_coalesce_usecs > 3) && + ((ec->rx_coalesce_usecs > 4) && (ec->rx_coalesce_usecs < E1000_MIN_ITR_USECS)) || (ec->rx_coalesce_usecs == 2)) return -EINVAL; - if (ec->rx_coalesce_usecs <= 3) { + if (ec->rx_coalesce_usecs == 4) { + adapter->itr = adapter->itr_setting = 4; + } else if (ec->rx_coalesce_usecs <= 3) { adapter->itr = 20000; adapter->itr_setting = ec->rx_coalesce_usecs; } else { diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h index 8bdcd5f24ef..5d1220d188d 100644 --- a/drivers/net/e1000e/hw.h +++ b/drivers/net/e1000e/hw.h @@ -208,6 +208,8 @@ enum e1e_registers { E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */ E1000_MANC2H = 0x05860, /* Management Control To Host - RW */ + E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */ +#define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4)) E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */ E1000_GCR = 0x05B00, /* PCI-Ex Control */ E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */ @@ -380,6 +382,7 @@ enum e1e_registers { #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF +#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF @@ -828,6 +831,7 @@ struct e1000_mac_info { u8 forced_speed_duplex; bool adaptive_ifs; + bool has_fwsm; bool arc_subsystem_valid; bool autoneg; bool autoneg_failed; @@ -898,6 +902,7 @@ struct e1000_fc_info { u32 high_water; /* Flow control high-water mark */ u32 low_water; /* Flow control low-water mark */ u16 pause_time; /* Flow control pause timer */ + u16 refresh_time; /* Flow control refresh timer */ bool send_xon; /* Flow control send XON */ bool strict_ieee; /* Strict IEEE mode */ enum e1000_fc_mode current_mode; /* FC mode in effect */ diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index 8b5e157e9c8..b2507d93de9 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c @@ -83,6 +83,8 @@ #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ +/* FW established a valid mode */ +#define E1000_ICH_FWSM_FW_VALID 0x00008000 #define E1000_ICH_MNG_IAMT_MODE 0x2 @@ -259,6 +261,7 @@ static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; + u32 ctrl; s32 ret_val = 0; phy->addr = 1; @@ -274,6 +277,33 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { + /* + * The MAC-PHY interconnect may still be in SMBus mode + * after Sx->S0. Toggle the LANPHYPC Value bit to force + * the interconnect to PCIe mode, but only if there is no + * firmware present otherwise firmware will have done it. + */ + ctrl = er32(CTRL); + ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; + ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; + ew32(CTRL, ctrl); + udelay(10); + ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; + ew32(CTRL, ctrl); + msleep(50); + } + + /* + * Reset the PHY before any acccess to it. Doing so, ensures that + * the PHY is in a known good state before we read/write PHY registers. + * The generic reset is sufficient here, because we haven't determined + * the PHY type yet. + */ + ret_val = e1000e_phy_hw_reset_generic(hw); + if (ret_val) + goto out; + phy->id = e1000_phy_unknown; ret_val = e1000e_get_phy_id(hw); if (ret_val) @@ -300,6 +330,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) phy->ops.get_cable_length = e1000_get_cable_length_82577; phy->ops.get_info = e1000_get_phy_info_82577; phy->ops.commit = e1000e_phy_sw_reset; + break; case e1000_phy_82578: phy->ops.check_polarity = e1000_check_polarity_m88; phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; @@ -472,8 +503,10 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter) mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; if (mac->type == e1000_ich8lan) mac->rar_entry_count--; - /* Set if manageability features are enabled. */ - mac->arc_subsystem_valid = true; + /* FWSM register */ + mac->has_fwsm = true; + /* ARC subsystem not supported */ + mac->arc_subsystem_valid = false; /* Adaptive IFS supported */ mac->adaptive_ifs = true; @@ -657,8 +690,6 @@ static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) { mutex_unlock(&nvm_mutex); - - return; } static DEFINE_MUTEX(swflag_mutex); @@ -737,8 +768,6 @@ static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) ew32(EXTCNF_CTRL, extcnf_ctrl); mutex_unlock(&swflag_mutex); - - return; } /** @@ -785,11 +814,16 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) **/ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) { + struct e1000_adapter *adapter = hw->adapter; struct e1000_phy_info *phy = &hw->phy; u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; - s32 ret_val; + s32 ret_val = 0; u16 word_addr, reg_data, reg_addr, phy_page = 0; + if (!(hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) && + !(hw->mac.type == e1000_pchlan)) + return ret_val; + ret_val = hw->phy.ops.acquire(hw); if (ret_val) return ret_val; @@ -801,97 +835,87 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) * Therefore, after each PHY reset, we will load the * configuration data out of the NVM manually. */ - if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) || - (hw->mac.type == e1000_pchlan)) { - struct e1000_adapter *adapter = hw->adapter; - - /* Check if SW needs to configure the PHY */ - if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) || - (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) || - (hw->mac.type == e1000_pchlan)) - sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; - else - sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; + if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) || + (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) || + (hw->mac.type == e1000_pchlan)) + sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; + else + sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; - data = er32(FEXTNVM); - if (!(data & sw_cfg_mask)) - goto out; + data = er32(FEXTNVM); + if (!(data & sw_cfg_mask)) + goto out; - /* Wait for basic configuration completes before proceeding */ - e1000_lan_init_done_ich8lan(hw); + /* + * Make sure HW does not configure LCD from PHY + * extended configuration before SW configuration + */ + data = er32(EXTCNF_CTRL); + if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) + goto out; + + cnf_size = er32(EXTCNF_SIZE); + cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; + cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; + if (!cnf_size) + goto out; + + cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; + cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; + if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && + (hw->mac.type == e1000_pchlan)) { /* - * Make sure HW does not configure LCD from PHY - * extended configuration before SW configuration + * HW configures the SMBus address and LEDs when the + * OEM and LCD Write Enable bits are set in the NVM. + * When both NVM bits are cleared, SW will configure + * them instead. */ - data = er32(EXTCNF_CTRL); - if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) + data = er32(STRAP); + data &= E1000_STRAP_SMBUS_ADDRESS_MASK; + reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT; + reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; + ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, + reg_data); + if (ret_val) goto out; - cnf_size = er32(EXTCNF_SIZE); - cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; - cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; - if (!cnf_size) + data = er32(LEDCTL); + ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, + (u16)data); + if (ret_val) goto out; + } - cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; - cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; - - if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && - (hw->mac.type == e1000_pchlan)) { - /* - * HW configures the SMBus address and LEDs when the - * OEM and LCD Write Enable bits are set in the NVM. - * When both NVM bits are cleared, SW will configure - * them instead. - */ - data = er32(STRAP); - data &= E1000_STRAP_SMBUS_ADDRESS_MASK; - reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT; - reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; - ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, - reg_data); - if (ret_val) - goto out; - - data = er32(LEDCTL); - ret_val = e1000_write_phy_reg_hv_locked(hw, - HV_LED_CONFIG, - (u16)data); - if (ret_val) - goto out; - } - /* Configure LCD from extended configuration region. */ + /* Configure LCD from extended configuration region. */ - /* cnf_base_addr is in DWORD */ - word_addr = (u16)(cnf_base_addr << 1); + /* cnf_base_addr is in DWORD */ + word_addr = (u16)(cnf_base_addr << 1); - for (i = 0; i < cnf_size; i++) { - ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, - ®_data); - if (ret_val) - goto out; + for (i = 0; i < cnf_size; i++) { + ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, + ®_data); + if (ret_val) + goto out; - ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), - 1, ®_addr); - if (ret_val) - goto out; + ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), + 1, ®_addr); + if (ret_val) + goto out; - /* Save off the PHY page for future writes. */ - if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { - phy_page = reg_data; - continue; - } + /* Save off the PHY page for future writes. */ + if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { + phy_page = reg_data; + continue; + } - reg_addr &= PHY_REG_MASK; - reg_addr |= phy_page; + reg_addr &= PHY_REG_MASK; + reg_addr |= phy_page; - ret_val = phy->ops.write_reg_locked(hw, - (u32)reg_addr, - reg_data); - if (ret_val) - goto out; - } + ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, + reg_data); + if (ret_val) + goto out; } out: @@ -1229,30 +1253,26 @@ static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) } /** - * e1000_phy_hw_reset_ich8lan - Performs a PHY reset + * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset * @hw: pointer to the HW structure - * - * Resets the PHY - * This is a function pointer entry point called by drivers - * or other shared routines. **/ -static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) +static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) { s32 ret_val = 0; u16 reg; - ret_val = e1000e_phy_hw_reset_generic(hw); - if (ret_val) - return ret_val; - - /* Allow time for h/w to get to a quiescent state after reset */ - mdelay(10); + if (e1000_check_reset_block(hw)) + goto out; /* Perform any necessary post-reset workarounds */ - if (hw->mac.type == e1000_pchlan) { + switch (hw->mac.type) { + case e1000_pchlan: ret_val = e1000_hv_phy_workarounds_ich8lan(hw); if (ret_val) - return ret_val; + goto out; + break; + default: + break; } /* Dummy read to clear the phy wakeup bit after lcd reset */ @@ -1265,11 +1285,32 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) goto out; /* Configure the LCD with the OEM bits in NVM */ - if (hw->mac.type == e1000_pchlan) - ret_val = e1000_oem_bits_config_ich8lan(hw, true); + ret_val = e1000_oem_bits_config_ich8lan(hw, true); out: - return 0; + return ret_val; +} + +/** + * e1000_phy_hw_reset_ich8lan - Performs a PHY reset + * @hw: pointer to the HW structure + * + * Resets the PHY + * This is a function pointer entry point called by drivers + * or other shared routines. + **/ +static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) +{ + s32 ret_val = 0; + + ret_val = e1000e_phy_hw_reset_generic(hw); + if (ret_val) + goto out; + + ret_val = e1000_post_phy_reset_ich8lan(hw); + +out: + return ret_val; } /** @@ -1622,7 +1663,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) /* Check if the flash descriptor is valid */ if (hsfsts.hsf_status.fldesvalid == 0) { e_dbg("Flash descriptor invalid. " - "SW Sequencing must be used."); + "SW Sequencing must be used.\n"); return -E1000_ERR_NVM; } @@ -1671,7 +1712,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) hsfsts.hsf_status.flcdone = 1; ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); } else { - e_dbg("Flash controller busy, cannot get access"); + e_dbg("Flash controller busy, cannot get access\n"); } } @@ -1822,7 +1863,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, continue; } else if (hsfsts.hsf_status.flcdone == 0) { e_dbg("Timeout error - flash cycle " - "did not complete."); + "did not complete.\n"); break; } } @@ -1908,18 +1949,14 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) new_bank_offset = nvm->flash_bank_size; old_bank_offset = 0; ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); - if (ret_val) { - nvm->ops.release(hw); - goto out; - } + if (ret_val) + goto release; } else { old_bank_offset = nvm->flash_bank_size; new_bank_offset = 0; ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); - if (ret_val) { - nvm->ops.release(hw); - goto out; - } + if (ret_val) + goto release; } for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { @@ -1975,8 +2012,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) if (ret_val) { /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ e_dbg("Flash commit failed.\n"); - nvm->ops.release(hw); - goto out; + goto release; } /* @@ -1987,18 +2023,15 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) */ act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); - if (ret_val) { - nvm->ops.release(hw); - goto out; - } + if (ret_val) + goto release; + data &= 0xBFFF; ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1, (u8)(data >> 8)); - if (ret_val) { - nvm->ops.release(hw); - goto out; - } + if (ret_val) + goto release; /* * And invalidate the previously valid segment by setting @@ -2008,10 +2041,8 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) */ act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); - if (ret_val) { - nvm->ops.release(hw); - goto out; - } + if (ret_val) + goto release; /* Great! Everything worked, we can now clear the cached entries. */ for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { @@ -2019,14 +2050,17 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) dev_spec->shadow_ram[i].value = 0xFFFF; } +release: nvm->ops.release(hw); /* * Reload the EEPROM, or else modifications will not appear * until after the next adapter reset. */ - e1000e_reload_nvm(hw); - msleep(10); + if (!ret_val) { + e1000e_reload_nvm(hw); + msleep(10); + } out: if (ret_val) @@ -2487,9 +2521,8 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) * on the last TLP read/write transaction when MAC is reset. */ ret_val = e1000e_disable_pcie_master(hw); - if (ret_val) { + if (ret_val) e_dbg("PCI-E Master disable polling has failed.\n"); - } e_dbg("Masking off all interrupts\n"); ew32(IMC, 0xffffffff); @@ -2528,14 +2561,8 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) ctrl = er32(CTRL); if (!e1000_check_reset_block(hw)) { - /* Clear PHY Reset Asserted bit */ - if (hw->mac.type >= e1000_pchlan) { - u32 status = er32(STATUS); - ew32(STATUS, status & ~E1000_STATUS_PHYRA); - } - /* - * PHY HW reset requires MAC CORE reset at the same + * Full-chip reset requires MAC and PHY reset at the same * time to make sure the interface between MAC and the * external PHY is reset. */ @@ -2549,39 +2576,16 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) if (!ret_val) e1000_release_swflag_ich8lan(hw); - /* Perform any necessary post-reset workarounds */ - if (hw->mac.type == e1000_pchlan) - ret_val = e1000_hv_phy_workarounds_ich8lan(hw); - - if (ctrl & E1000_CTRL_PHY_RST) + if (ctrl & E1000_CTRL_PHY_RST) { ret_val = hw->phy.ops.get_cfg_done(hw); + if (ret_val) + goto out; - if (hw->mac.type >= e1000_ich10lan) { - e1000_lan_init_done_ich8lan(hw); - } else { - ret_val = e1000e_get_auto_rd_done(hw); - if (ret_val) { - /* - * When auto config read does not complete, do not - * return with an error. This can happen in situations - * where there is no eeprom and prevents getting link. - */ - e_dbg("Auto Read Done did not complete\n"); - } - } - /* Dummy read to clear the phy wakeup bit after lcd reset */ - if (hw->mac.type == e1000_pchlan) - e1e_rphy(hw, BM_WUC, ®); - - ret_val = e1000_sw_lcd_config_ich8lan(hw); - if (ret_val) - goto out; - - if (hw->mac.type == e1000_pchlan) { - ret_val = e1000_oem_bits_config_ich8lan(hw, true); + ret_val = e1000_post_phy_reset_ich8lan(hw); if (ret_val) goto out; } + /* * For PCH, this write will make sure that any noise * will be detected as a CRC error and be dropped rather than show up @@ -2748,8 +2752,6 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) reg = er32(RFCTL); reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); ew32(RFCTL, reg); - - return; } /** @@ -2799,6 +2801,8 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) ew32(FCTTV, hw->fc.pause_time); if ((hw->phy.type == e1000_phy_82578) || (hw->phy.type == e1000_phy_82577)) { + ew32(FCRTV_PCH, hw->fc.refresh_time); + ret_val = hw->phy.ops.write_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), hw->fc.pause_time); @@ -3127,8 +3131,6 @@ void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) default: break; } - - return; } /** @@ -3265,33 +3267,50 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw) } /** - * e1000_get_cfg_done_ich8lan - Read config done bit + * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset * @hw: pointer to the HW structure * - * Read the management control register for the config done bit for - * completion status. NOTE: silicon which is EEPROM-less will fail trying - * to read the config done bit, so an error is *ONLY* logged and returns - * 0. If we were to return with error, EEPROM-less silicon - * would not be able to be reset or change link. + * Read appropriate register for the config done bit for completion status + * and configure the PHY through s/w for EEPROM-less parts. + * + * NOTE: some silicon which is EEPROM-less will fail trying to read the + * config done bit, so only an error is logged and continues. If we were + * to return with error, EEPROM-less silicon would not be able to be reset |