1 files changed, 1046 insertions, 813 deletions

diff --git a/drivers/net/chelsio/sge.c b/drivers/net/chelsio/sge.c
index bcf8b1e939b..53b41d99b00 100644
--- a/drivers/net/chelsio/sge.c
+++ b/drivers/net/chelsio/sge.c
@@ -1,8 +1,8 @@
 /*****************************************************************************
  *                                                                           *
  * File: sge.c                                                               *
- * $Revision: 1.13 $                                                         *
- * $Date: 2005/03/23 07:41:27 $                                              *
+ * $Revision: 1.26 $                                                         *
+ * $Date: 2005/06/21 18:29:48 $                                              *
  * Description:                                                              *
  *  DMA engine.                                                              *
  *  part of the Chelsio 10Gb Ethernet Driver.                                *
@@ -58,59 +58,62 @@
 #include "regs.h"
 #include "espi.h"
 
+
+#ifdef NETIF_F_TSO
 #include <linux/tcp.h>
+#endif
 
 #define SGE_CMDQ_N		2
 #define SGE_FREELQ_N		2
-#define SGE_CMDQ0_E_N		512
+#define SGE_CMDQ0_E_N		1024
 #define SGE_CMDQ1_E_N		128
 #define SGE_FREEL_SIZE		4096
 #define SGE_JUMBO_FREEL_SIZE	512
 #define SGE_FREEL_REFILL_THRESH	16
 #define SGE_RESPQ_E_N		1024
-#define SGE_INTR_BUCKETSIZE	100
-#define SGE_INTR_LATBUCKETS	5
-#define SGE_INTR_MAXBUCKETS	11
-#define SGE_INTRTIMER0		1
-#define SGE_INTRTIMER1		50
-#define SGE_INTRTIMER_NRES	10000
-#define SGE_RX_COPY_THRESHOLD	256
+#define SGE_INTRTIMER_NRES	1000
+#define SGE_RX_COPY_THRES	256
 #define SGE_RX_SM_BUF_SIZE	1536
 
-#define SGE_RESPQ_REPLENISH_THRES ((3 * SGE_RESPQ_E_N) / 4)
+# define SGE_RX_DROP_THRES 2
+
+#define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4)
+
+/*
+ * Period of the TX buffer reclaim timer.  This timer does not need to run
+ * frequently as TX buffers are usually reclaimed by new TX packets.
+ */
+#define TX_RECLAIM_PERIOD (HZ / 4)
 
-#define SGE_RX_OFFSET 2
 #ifndef NET_IP_ALIGN
-# define NET_IP_ALIGN SGE_RX_OFFSET
+# define NET_IP_ALIGN 2
 #endif
 
+#define M_CMD_LEN       0x7fffffff
+#define V_CMD_LEN(v)    (v)
+#define G_CMD_LEN(v)    ((v) & M_CMD_LEN)
+#define V_CMD_GEN1(v)   ((v) << 31)
+#define V_CMD_GEN2(v)   (v)
+#define F_CMD_DATAVALID (1 << 1)
+#define F_CMD_SOP       (1 << 2)
+#define V_CMD_EOP(v)    ((v) << 3)
+
 /*
- * Memory Mapped HW Command, Freelist and Response Queue Descriptors
+ * Command queue, receive buffer list, and response queue descriptors.
  */
 #if defined(__BIG_ENDIAN_BITFIELD)
 struct cmdQ_e {
-	u32 AddrLow;
-	u32 GenerationBit	: 1;
-	u32 BufferLength	: 31;
-	u32 RespQueueSelector	: 4;
-	u32 ResponseTokens	: 12;
-	u32 CmdId		: 8;
-	u32 Reserved		: 3;
-	u32 TokenValid		: 1;
-	u32 Eop			: 1;
-	u32 Sop			: 1;
-	u32 DataValid		: 1;
-	u32 GenerationBit2	: 1;
-	u32 AddrHigh;
+	u32 addr_lo;
+	u32 len_gen;
+	u32 flags;
+	u32 addr_hi;
 };
 
 struct freelQ_e {
-	u32 AddrLow;
-	u32 GenerationBit	: 1;
-	u32 BufferLength	: 31;
-	u32 Reserved		: 31;
-	u32 GenerationBit2	: 1;
-	u32 AddrHigh;
+	u32 addr_lo;
+	u32 len_gen;
+	u32 gen2;
+	u32 addr_hi;
 };
 
 struct respQ_e {
@@ -128,31 +131,19 @@ struct respQ_e {
 	u32 GenerationBit	: 1;
 	u32 BufferLength;
 };
-
 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 struct cmdQ_e {
-	u32 BufferLength	: 31;
-	u32 GenerationBit	: 1;
-	u32 AddrLow;
-	u32 AddrHigh;
-	u32 GenerationBit2	: 1;
-	u32 DataValid		: 1;
-	u32 Sop			: 1;
-	u32 Eop			: 1;
-	u32 TokenValid		: 1;
-	u32 Reserved		: 3;
-	u32 CmdId		: 8;
-	u32 ResponseTokens	: 12;
-	u32 RespQueueSelector	: 4;
+	u32 len_gen;
+	u32 addr_lo;
+	u32 addr_hi;
+	u32 flags;
 };
 
 struct freelQ_e {
-	u32 BufferLength	: 31;
-	u32 GenerationBit	: 1;
-	u32 AddrLow;
-	u32 AddrHigh;
-	u32 GenerationBit2	: 1;
-	u32 Reserved		: 31;
+	u32 len_gen;
+	u32 addr_lo;
+	u32 addr_hi;
+	u32 gen2;
 };
 
 struct respQ_e {
@@ -179,7 +170,6 @@ struct cmdQ_ce {
 	struct sk_buff *skb;
 	DECLARE_PCI_UNMAP_ADDR(dma_addr);
 	DECLARE_PCI_UNMAP_LEN(dma_len);
-	unsigned int single;
 };
 
 struct freelQ_ce {
@@ -189,44 +179,52 @@ struct freelQ_ce {
 };
 
 /*
- * SW Command, Freelist and Response Queue
+ * SW command, freelist and response rings
  */
 struct cmdQ {
-	atomic_t	asleep;		/* HW DMA Fetch status */
-	atomic_t	credits;	/* # available descriptors for TX */
-	atomic_t	pio_pidx;	/* Variable updated on Doorbell */
-	u16		entries_n;	/* # descriptors for TX	*/
-	u16		pidx;		/* producer index (SW) */
-	u16		cidx;		/* consumer index (HW) */
-	u8		genbit;		/* current generation (=valid) bit */
-	struct cmdQ_e  *entries;	/* HW command descriptor Q */
-	struct cmdQ_ce *centries;	/* SW command context descriptor Q */
-	spinlock_t	Qlock;		/* Lock to protect cmdQ enqueuing */
-	dma_addr_t	dma_addr;	/* DMA addr HW command descriptor Q */
+	unsigned long   status;         /* HW DMA fetch status */
+	unsigned int    in_use;         /* # of in-use command descriptors */
+	unsigned int	size;	        /* # of descriptors */
+	unsigned int	processed;      /* total # of descs HW has processed */
+	unsigned int	cleaned;        /* total # of descs SW has reclaimed */
+	unsigned int	stop_thres;     /* SW TX queue suspend threshold */
+	u16		pidx;           /* producer index (SW) */
+	u16		cidx;           /* consumer index (HW) */
+	u8		genbit;         /* current generation (=valid) bit */
+	u8		sop;            /* is next entry start of packet? */
+	struct cmdQ_e  *entries;        /* HW command descriptor Q */
+	struct cmdQ_ce *centries;       /* SW command context descriptor Q */
+	spinlock_t	lock;           /* Lock to protect cmdQ enqueuing */
+	dma_addr_t	dma_addr;       /* DMA addr HW command descriptor Q */
 };
 
 struct freelQ {
-	unsigned int	credits;	/* # of available RX buffers */
-	unsigned int	entries_n;	/* free list capacity */
-	u16		pidx;		/* producer index (SW) */
-	u16		cidx;		/* consumer index (HW) */
+	unsigned int	credits;        /* # of available RX buffers */
+	unsigned int	size;	        /* free list capacity */
+	u16		pidx;           /* producer index (SW) */
+	u16		cidx;           /* consumer index (HW) */
 	u16		rx_buffer_size; /* Buffer size on this free list */
 	u16		dma_offset;     /* DMA offset to align IP headers */
-	u8		genbit;		/* current generation (=valid) bit */
-	struct freelQ_e	*entries;	/* HW freelist descriptor Q */
-	struct freelQ_ce *centries;	/* SW freelist conext descriptor Q */
-	dma_addr_t	dma_addr;	/* DMA addr HW freelist descriptor Q */
+	u16		recycleq_idx;   /* skb recycle q to use */
+	u8		genbit;	        /* current generation (=valid) bit */
+	struct freelQ_e	*entries;       /* HW freelist descriptor Q */
+	struct freelQ_ce *centries;     /* SW freelist context descriptor Q */
+	dma_addr_t	dma_addr;       /* DMA addr HW freelist descriptor Q */
 };
 
 struct respQ {
-	u16		credits;	/* # of available respQ descriptors */
-	u16		credits_pend;	/* # of not yet returned descriptors */
-	u16		entries_n;	/* # of response Q descriptors */
-	u16		pidx;		/* producer index (HW) */
-	u16		cidx;		/* consumer index (SW) */
-	u8		genbit;		/* current generation(=valid) bit */
+	unsigned int	credits;        /* credits to be returned to SGE */
+	unsigned int	size;	        /* # of response Q descriptors */
+	u16		cidx;	        /* consumer index (SW) */
+	u8		genbit;	        /* current generation(=valid) bit */
 	struct respQ_e *entries;        /* HW response descriptor Q */
-	dma_addr_t	dma_addr;	/* DMA addr HW response descriptor Q */
+	dma_addr_t	dma_addr;       /* DMA addr HW response descriptor Q */
+};
+
+/* Bit flags for cmdQ.status */
+enum {
+	CMDQ_STAT_RUNNING = 1,          /* fetch engine is running */
+	CMDQ_STAT_LAST_PKT_DB = 2       /* last packet rung the doorbell */
 };
 
 /*
@@ -239,134 +237,50 @@ struct respQ {
  */
 struct sge {
 	struct adapter *adapter; 	/* adapter backpointer */
-	struct freelQ 	freelQ[SGE_FREELQ_N]; /* freelist Q(s) */
-	struct respQ 	respQ;		/* response Q instatiation */
+	struct net_device *netdev;      /* netdevice backpointer */
+	struct freelQ 	freelQ[SGE_FREELQ_N]; /* buffer free lists */
+	struct respQ 	respQ;		/* response Q */
+	unsigned long   stopped_tx_queues; /* bitmap of suspended Tx queues */
 	unsigned int	rx_pkt_pad;     /* RX padding for L2 packets */
 	unsigned int	jumbo_fl;       /* jumbo freelist Q index */
-	u32		intrtimer[SGE_INTR_MAXBUCKETS];	/* ! */
-	u32		currIndex;	/* current index into intrtimer[] */
-	u32		intrtimer_nres;	/* no resource interrupt timer value */
-	u32		sge_control;	/* shadow content of sge control reg */
-	struct sge_intr_counts intr_cnt;
-	struct timer_list ptimer;
-	struct sk_buff  *pskb;
-	u32		ptimeout;
-	struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned; /* command Q(s)*/
+	unsigned int	intrtimer_nres;	/* no-resource interrupt timer */
+	unsigned int	fixed_intrtimer;/* non-adaptive interrupt timer */
+	struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
+	struct timer_list espibug_timer;
+	unsigned int	espibug_timeout;
+	struct sk_buff	*espibug_skb;
+	u32		sge_control;	/* shadow value of sge control reg */
+	struct sge_intr_counts stats;
+	struct sge_port_stats port_stats[MAX_NPORTS];
+	struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp;
 };
 
-static unsigned int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
-			unsigned int qid);
-
 /*
  * PIO to indicate that memory mapped Q contains valid descriptor(s).
  */
-static inline void doorbell_pio(struct sge *sge, u32 val)
+static inline void doorbell_pio(struct adapter *adapter, u32 val)
 {
 	wmb();
-	t1_write_reg_4(sge->adapter, A_SG_DOORBELL, val);
-}
-
-/*
- * Disables the DMA engine.
- */
-void t1_sge_stop(struct sge *sge)
-{
-	t1_write_reg_4(sge->adapter, A_SG_CONTROL, 0);
-	t1_read_reg_4(sge->adapter, A_SG_CONTROL);     /* flush write */
-	if (is_T2(sge->adapter))
-		del_timer_sync(&sge->ptimer);
-}
-
-static u8 ch_mac_addr[ETH_ALEN] = {0x0, 0x7, 0x43, 0x0, 0x0, 0x0};
-static void t1_espi_workaround(void *data)
-{
-	struct adapter *adapter = (struct adapter *)data;
-	struct sge *sge = adapter->sge;
-
-	if (netif_running(adapter->port[0].dev) &&
-		atomic_read(&sge->cmdQ[0].asleep)) {
-
-		u32 seop = t1_espi_get_mon(adapter, 0x930, 0);
-
-		if ((seop & 0xfff0fff) == 0xfff && sge->pskb) {
-			struct sk_buff *skb = sge->pskb;
-			if (!skb->cb[0]) {
-				memcpy(skb->data+sizeof(struct cpl_tx_pkt), ch_mac_addr, ETH_ALEN);
-				memcpy(skb->data+skb->len-10, ch_mac_addr, ETH_ALEN);
-
-				skb->cb[0] = 0xff;
-			}
-			t1_sge_tx(skb, adapter,0);
-		}
-	}
-	mod_timer(&adapter->sge->ptimer, jiffies + sge->ptimeout);
-}
-
-/*
- * Enables the DMA engine.
- */
-void t1_sge_start(struct sge *sge)
-{
-	t1_write_reg_4(sge->adapter, A_SG_CONTROL, sge->sge_control);
-	t1_read_reg_4(sge->adapter, A_SG_CONTROL);     /* flush write */
-	if (is_T2(sge->adapter)) {
-		init_timer(&sge->ptimer);
-		sge->ptimer.function = (void *)&t1_espi_workaround;
-		sge->ptimer.data = (unsigned long)sge->adapter;
-		sge->ptimer.expires = jiffies + sge->ptimeout;
-		add_timer(&sge->ptimer);
-	}
-}
-
-/*
- * Creates a t1_sge structure and returns suggested resource parameters.
- */
-struct sge * __devinit t1_sge_create(struct adapter *adapter,
-				     struct sge_params *p)
-{
-	struct sge *sge = kmalloc(sizeof(*sge), GFP_KERNEL);
-
-	if (!sge)
-		return NULL;
-	memset(sge, 0, sizeof(*sge));
-
-	if (is_T2(adapter))
-		sge->ptimeout = 1;	/* finest allowed */
-
-	sge->adapter = adapter;
-	sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : SGE_RX_OFFSET;
-	sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
-
-	p->cmdQ_size[0] = SGE_CMDQ0_E_N;
-	p->cmdQ_size[1] = SGE_CMDQ1_E_N;
-	p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE;
-	p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE;
-	p->rx_coalesce_usecs = SGE_INTRTIMER1;
-	p->last_rx_coalesce_raw = SGE_INTRTIMER1 *
-	  (board_info(sge->adapter)->clock_core / 1000000);
-	p->default_rx_coalesce_usecs = SGE_INTRTIMER1;
-	p->coalesce_enable = 0;	/* Turn off adaptive algorithm by default */
-	p->sample_interval_usecs = 0;
-	return sge;
+	writel(val, adapter->regs + A_SG_DOORBELL);
 }
 
 /*
  * Frees all RX buffers on the freelist Q. The caller must make sure that
  * the SGE is turned off before calling this function.
  */
-static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *Q)
+static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q)
 {
-	unsigned int cidx = Q->cidx, credits = Q->credits;
+	unsigned int cidx = q->cidx;
 
-	while (credits--) {
-		struct freelQ_ce *ce = &Q->centries[cidx];
+	while (q->credits--) {
+		struct freelQ_ce *ce = &q->centries[cidx];
 
 		pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr),
 				 pci_unmap_len(ce, dma_len),
 				 PCI_DMA_FROMDEVICE);
 		dev_kfree_skb(ce->skb);
 		ce->skb = NULL;
-		if (++cidx == Q->entries_n)
+		if (++cidx == q->size)
 			cidx = 0;
 	}
 }
@@ -380,29 +294,29 @@ static void free_rx_resources(struct sge *sge)
 	unsigned int size, i;
 
 	if (sge->respQ.entries) {
-		size = sizeof(struct respQ_e) * sge->respQ.entries_n;
+		size = sizeof(struct respQ_e) * sge->respQ.size;
 		pci_free_consistent(pdev, size, sge->respQ.entries,
 				    sge->respQ.dma_addr);
 	}
 
 	for (i = 0; i < SGE_FREELQ_N; i++) {
-		struct freelQ *Q = &sge->freelQ[i];
+		struct freelQ *q = &sge->freelQ[i];
 
-		if (Q->centries) {
-			free_freelQ_buffers(pdev, Q);
-			kfree(Q->centries);
+		if (q->centries) {
+			free_freelQ_buffers(pdev, q);
+			kfree(q->centries);
 		}
-		if (Q->entries) {
-			size = sizeof(struct freelQ_e) * Q->entries_n;
-			pci_free_consistent(pdev, size, Q->entries,
-					    Q->dma_addr);
+		if (q->entries) {
+			size = sizeof(struct freelQ_e) * q->size;
+			pci_free_consistent(pdev, size, q->entries,
+					    q->dma_addr);
 		}
 	}
 }
 
 /*
  * Allocates basic RX resources, consisting of memory mapped freelist Qs and a
- * response Q.
+ * response queue.
  */
 static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
 {
@@ -410,21 +324,22 @@ static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
 	unsigned int size, i;
 
 	for (i = 0; i < SGE_FREELQ_N; i++) {
-		struct freelQ *Q = &sge->freelQ[i];
-
-		Q->genbit = 1;
-		Q->entries_n = p->freelQ_size[i];
-		Q->dma_offset = SGE_RX_OFFSET - sge->rx_pkt_pad;
-		size = sizeof(struct freelQ_e) * Q->entries_n;
-		Q->entries = (struct freelQ_e *)
-			      pci_alloc_consistent(pdev, size, &Q->dma_addr);
-		if (!Q->entries)
+		struct freelQ *q = &sge->freelQ[i];
+
+		q->genbit = 1;
+		q->size = p->freelQ_size[i];
+		q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN;
+		size = sizeof(struct freelQ_e) * q->size;
+		q->entries = (struct freelQ_e *)
+			      pci_alloc_consistent(pdev, size, &q->dma_addr);
+		if (!q->entries)
 			goto err_no_mem;
-		memset(Q->entries, 0, size);
-		Q->centries = kcalloc(Q->entries_n, sizeof(struct freelQ_ce),
-				      GFP_KERNEL);
-		if (!Q->centries)
+		memset(q->entries, 0, size);
+		size = sizeof(struct freelQ_ce) * q->size;
+		q->centries = kmalloc(size, GFP_KERNEL);
+		if (!q->centries)
 			goto err_no_mem;
+		memset(q->centries, 0, size);
 	}
 
 	/*
@@ -440,10 +355,17 @@ static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
 	sge->freelQ[sge->jumbo_fl].rx_buffer_size = (16 * 1024) -
 		SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 
+	/*
+	 * Setup which skb recycle Q should be used when recycling buffers from
+	 * each free list.
+	 */
+	sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0;
+	sge->freelQ[sge->jumbo_fl].recycleq_idx = 1;
+
 	sge->respQ.genbit = 1;
-	sge->respQ.entries_n = SGE_RESPQ_E_N;
-	sge->respQ.credits = SGE_RESPQ_E_N;
-	size = sizeof(struct respQ_e) * sge->respQ.entries_n;
+	sge->respQ.size = SGE_RESPQ_E_N;
+	sge->respQ.credits = 0;
+	size = sizeof(struct respQ_e) * sge->respQ.size;
 	sge->respQ.entries = (struct respQ_e *)
 		pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr);
 	if (!sge->respQ.entries)
@@ -457,48 +379,37 @@ err_no_mem:
 }
 
 /*
- * Frees 'credits_pend' TX buffers and returns the credits to Q->credits.
- *
- * The adaptive algorithm receives the total size of the buffers freed
- * accumulated in @*totpayload. No initialization of this argument here.
- *
+ * Reclaims n TX descriptors and frees the buffers associated with them.
  */
-static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *Q,
-			      unsigned int credits_pend, unsigned int *totpayload)
+static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n)
 {
+	struct cmdQ_ce *ce;
 	struct pci_dev *pdev = sge->adapter->pdev;
-	struct sk_buff *skb;
-	struct cmdQ_ce *ce, *cq = Q->centries;
-	unsigned int entries_n = Q->entries_n, cidx = Q->cidx,
-		     i = credits_pend;
-
+	unsigned int cidx = q->cidx;
 
-	ce = &cq[cidx];
-	while (i--) {
-		if (ce->single)
+	q->in_use -= n;
+	ce = &q->centries[cidx];
+	while (n--) {
+		if (q->sop)
 			pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr),
-					 pci_unmap_len(ce, dma_len),
+			 		 pci_unmap_len(ce, dma_len),
 					 PCI_DMA_TODEVICE);
 		else
 			pci_unmap_page(pdev, pci_unmap_addr(ce, dma_addr),
-				       pci_unmap_len(ce, dma_len),
+			 	       pci_unmap_len(ce, dma_len),
 				       PCI_DMA_TODEVICE);
-		if (totpayload)
-			*totpayload += pci_unmap_len(ce, dma_len);
-
-		skb = ce->skb;
-		if (skb)
-			dev_kfree_skb_irq(skb);
-
+		q->sop = 0;
+		if (ce->skb) {
+			dev_kfree_skb(ce->skb);
+			q->sop = 1;
+		}
 		ce++;
-		if (++cidx == entries_n) {
+		if (++cidx == q->size) {
 			cidx = 0;
-			ce = cq;
+			ce = q->centries;
 		}
 	}
-
-	Q->cidx = cidx;
-	atomic_add(credits_pend, &Q->credits);
+	q->cidx = cidx;
 }
 
 /*
@@ -512,20 +423,17 @@ static void free_tx_resources(struct sge *sge)
 	unsigned int size, i;
 
 	for (i = 0; i < SGE_CMDQ_N; i++) {
-		struct cmdQ *Q = &sge->cmdQ[i];
+		struct cmdQ *q = &sge->cmdQ[i];
 
-		if (Q->centries) {
-			unsigned int pending = Q->entries_n -
-					       atomic_read(&Q->credits);
-
-			if (pending)
-				free_cmdQ_buffers(sge, Q, pending, NULL);
-			kfree(Q->centries);
+		if (q->centries) {
+			if (q->in_use)
+				free_cmdQ_buffers(sge, q, q->in_use);
+			kfree(q->centries);
 		}
-		if (Q->entries) {
-			size = sizeof(struct cmdQ_e) * Q->entries_n;
-			pci_free_consistent(pdev, size, Q->entries,
-					    Q->dma_addr);
+		if (q->entries) {
+			size = sizeof(struct cmdQ_e) * q->size;
+			pci_free_consistent(pdev, size, q->entries,
+					    q->dma_addr);
 		}
 	}
 }
@@ -539,25 +447,38 @@ static int alloc_tx_resources(struct sge *sge, struct sge_params *p)
 	unsigned int size, i;
 
 	for (i = 0; i < SGE_CMDQ_N; i++) {
-		struct cmdQ *Q = &sge->cmdQ[i];
-
-		Q->genbit = 1;
-		Q->entries_n = p->cmdQ_size[i];
-		atomic_set(&Q->credits, Q->entries_n);
-		atomic_set(&Q->asleep, 1);
-		spin_lock_init(&Q->Qlock);
-		size = sizeof(struct cmdQ_e) * Q->entries_n;
-		Q->entries = (struct cmdQ_e *)
-			      pci_alloc_consistent(pdev, size, &Q->dma_addr);
-		if (!Q->entries)
+		struct cmdQ *q = &sge->cmdQ[i];
+
+		q->genbit = 1;
+		q->sop = 1;
+		q->size = p->cmdQ_size[i];
+		q->in_use = 0;
+		q->status = 0;
+		q->processed = q->cleaned = 0;
+		q->stop_thres = 0;
+		spin_lock_init(&q->lock);
+		size = sizeof(struct cmdQ_e) * q->size;
+		q->entries = (struct cmdQ_e *)
+			      pci_alloc_consistent(pdev, size, &q->dma_addr);
+		if (!q->entries)
 			goto err_no_mem;
-		memset(Q->entries, 0, size);
-		Q->centries = kcalloc(Q->entries_n, sizeof(struct cmdQ_ce),
-				      GFP_KERNEL);
-		if (!Q->centries)
+		memset(q->entries, 0, size);
+		size = sizeof(struct cmdQ_ce) * q->size;
+		q->centries = kmalloc(size, GFP_KERNEL);
+		if (!q->centries)
 			goto err_no_mem;
+		memset(q->centries, 0, size);
 	}
 
+	/*
+	 * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE
+	 * only.  For queue 0 set the stop threshold so we can handle one more
+	 * packet from each port, plus reserve an additional 24 entries for
+	 * Ethernet packets only.  Queue 1 never suspends nor do we reserve
+	 * space for Ethernet packets.
+	 */
+	sge->cmdQ[0].stop_thres = sge->adapter->params.nports *
+		(MAX_SKB_FRAGS + 1);
 	return 0;
 
 err_no_mem:
@@ -569,9 +490,9 @@ static inline void setup_ring_params(struct adapter *adapter, u64 addr,
 				     u32 size, int base_reg_lo,
 				     int base_reg_hi, int size_reg)
 {
-	t1_write_reg_4(adapter, base_reg_lo, (u32)addr);
-	t1_write_reg_4(adapter, base_reg_hi, addr >> 32);
-	t1_write_reg_4(adapter, size_reg, size);
+	writel((u32)addr, adapter->regs + base_reg_lo);
+	writel(addr >> 32, adapter->regs + base_reg_hi);
+	writel(size, adapter->regs + size_reg);
 }
 
 /*
@@ -585,97 +506,52 @@ void t1_set_vlan_accel(struct adapter *adapter, int on_off)
 	if (on_off)
 		sge->sge_control |= F_VLAN_XTRACT;
 	if (adapter->open_device_map) {
-		t1_write_reg_4(adapter, A_SG_CONTROL, sge->sge_control);
-		t1_read_reg_4(adapter, A_SG_CONTROL);	/* flush */
+		writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
+		readl(adapter->regs + A_SG_CONTROL); /* flush */
 	}
 }
 
 /*
- * Sets the interrupt latency timer when the adaptive Rx coalescing
- * is turned off. Do nothing when it is turned on again.
- *
- * This routine relies on the fact that the caller has already set
- * the adaptive policy in adapter->sge_params before calling it.
-*/
-int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p)
-{
-	if (!p->coalesce_enable) {
-		u32 newTimer = p->rx_coalesce_usecs *
-			(board_info(sge->adapter)->clock_core / 1000000);
-
-		t1_write_reg_4(sge->adapter, A_SG_INTRTIMER, newTimer);
-	}
-	return 0;
-}
-
-/*
  * Programs the various SGE registers. However, the engine is not yet enabled,
  * but sge->sge_control is setup and ready to go.
  */
 static void configure_sge(struct sge *sge, struct sge_params *p)
 {
 	struct adapter *ap = sge->adapter;
-	int i;
-
-	t1_write_reg_4(ap, A_SG_CONTROL, 0);
-	setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].entries_n,
+	
+	writel(0, ap->regs + A_SG_CONTROL);
+	setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size,
 			  A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE);
-	setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].entries_n,
+	setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size,
 			  A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE);
 	setup_ring_params(ap, sge->freelQ[0].dma_addr,
-			  sge->freelQ[0].entries_n, A_SG_FL0BASELWR,
+			  sge->freelQ[0].size, A_SG_FL0BASELWR,
 			  A_SG_FL0BASEUPR, A_SG_FL0SIZE);
 	setup_ring_params(ap, sge->freelQ[1].dma_addr,
-			  sge->freelQ[1].entries_n, A_SG_FL1BASELWR,
+			  sge->freelQ[1].size, A_SG_FL1BASELWR,
 			  A_SG_FL1BASEUPR, A_SG_FL1SIZE);
 
 	/* The threshold comparison uses <. */
-	t1_write_reg_4(ap, A_SG_FLTHRESHOLD, SGE_RX_SM_BUF_SIZE + 1);
+	writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD);
 
-	setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.entries_n,
-			A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE);
-	t1_write_reg_4(ap, A_SG_RSPQUEUECREDIT, (u32)sge->respQ.entries_n);
+	setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size,
+			  A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE);
+	writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT);
 
 	sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE |
 		F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE |
 		V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE |
+		F_DISABLE_FL0_GTS | F_DISABLE_FL1_GTS |
 		V_RX_PKT_OFFSET(sge->rx_pkt_pad);
 
 #if defined(__BIG_ENDIAN_BITFIELD)
 	sge->sge_control |= F_ENABLE_BIG_ENDIAN;
 #endif
 
-	/*
-	 * Initialize the SGE Interrupt Timer arrray:
-	 * intrtimer[0]	      = (SGE_INTRTIMER0) usec
-	 * intrtimer[0<i<5]   = (SGE_INTRTIMER0 + i*2) usec
-	 * intrtimer[4<i<10]  = ((i - 3) * 6) usec
-	 * intrtimer[10]      = (SGE_INTRTIMER1) usec
-	 *
-	 */
-	sge->intrtimer[0] = board_info(sge->adapter)->clock_core / 1000000;
-	for (i = 1; i < SGE_INTR_LATBUCKETS; ++i) {
-		sge->intrtimer[i] = SGE_INTRTIMER0 + (2 * i);
-		sge->intrtimer[i] *= sge->intrtimer[0];
-	}
-	for (i = SGE_INTR_LATBUCKETS; i < SGE_INTR_MAXBUCKETS - 1; ++i) {
-		sge->intrtimer[i] = (i - 3) * 6;
-		sge->intrtimer[i] *= sge->intrtimer[0];
-	}
-	sge->intrtimer[SGE_INTR_MAXBUCKETS - 1] =
-	  sge->intrtimer[0] * SGE_INTRTIMER1;
-	/* Initialize resource timer */
-	sge->intrtimer_nres = sge->intrtimer[0] * SGE_INTRTIMER_NRES;
-	/* Finally finish initialization of intrtimer[0] */
-	sge->intrtimer[0] *= SGE_INTRTIMER0;
-	/* Initialize for a throughput oriented workload */
-	sge->currIndex = SGE_INTR_MAXBUCKETS - 1;
-
-	if (p->coalesce_enable)
-		t1_write_reg_4(ap, A_SG_INTRTIMER,
-			       sge->intrtimer[sge->currIndex]);
-	else
-		t1_sge_set_coalesce_params(sge, p);
+	/* Initialize no-resource timer */
+	sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap);
+
+	t1_sge_set_coalesce_params(sge, p);
 }
 
 /*
@@ -684,31 +560,8 @@ static void configure_sge(struct sge *sge, struct sge_params *p)
 static inline unsigned int jumbo_payload_capacity(const struct sge *sge)
 {
 	return sge->freelQ[sge->jumbo_fl].rx_buffer_size -
-		sizeof(struct cpl_rx_data) - SGE_RX_OFFSET + sge->rx_pkt_pad;
-}
-
-/*
- * Allocates both RX and TX resources and configures the SGE. However,
- * the hardware is not enabled yet.
- */
-int t1_sge_configure(struct sge *sge, struct sge_params *p)
-{
-	if (alloc_rx_resources(sge, p))
-		return -ENOMEM;
-	if (alloc_tx_resources(sge, p)) {
-		free_rx_resources(sge);
-		return -ENOMEM;
-	}
-	configure_sge(sge, p);
-
-	/*
-	 * Now that we have sized the free lists calculate the payload
-	 * capacity of the large buffers.  Other parts of the driver use
-	 * this to set the max offload coalescing size so that RX packets
-	 * do not overflow our large buffers.
-	 */
-	p->large_buf_capacity = jumbo_payload_capacity(sge);
-	return 0;
+		sge->freelQ[sge->jumbo_fl].dma_offset -
+		sizeof(struct cpl_rx_data);
 }
 
 /*
@@ -716,8 +569,9 @@ int t1_sge_configure(struct sge *sge, struct sge_params *p)
  */
 void t1_sge_destroy(struct sge *sge)
 {
-	if (sge->pskb)
-		dev_kfree_skb(sge->pskb);
+	if (sge->espibug_skb)
+		kfree_skb(sge->espibug_skb);
+
 	free_tx_resources(sge);
 	free_rx_resources(sge);
 	kfree(sge);
@@ -735,75 +589,75 @@ void t1_sge_destroy(struct sge *sge)
  * we specify a RX_OFFSET in order to make sure that the IP header is 4B
  * aligned.
  */
-static void refill_free_list(struct sge *sge, struct freelQ *Q)
+static void refill_free_list(struct sge *sge, struct freelQ *q)
 {
 	struct pci_dev *pdev = sge->adapter->pdev;
-	struct freelQ_ce *ce = &Q->centries[Q->pidx];
-	struct freelQ_e *e = &Q->entries[Q->pidx];
-	unsigned int dma_len = Q->rx_buffer_size - Q->dma_offset;
+	struct freelQ_ce *ce = &q->centries[q->pidx];
+	struct freelQ_e *e = &q->entries[q->pidx];
+	unsigned int dma_len = q->rx_buffer_size - q->dma_offset;
 
 
-	while (Q->credits < Q->entries_n) {
-		if (e->GenerationBit != Q->genbit) {
-			struct sk_buff *skb;
-			dma_addr_t mapping;
+	while (q->credits < q->size) {
+		struct sk_buff *skb;
+		dma_addr_t mapping;
 
-			skb = alloc_skb(Q->rx_buffer_size, GFP_ATOMIC);
-			if (!skb)
-				break;
-			if (Q->dma_offset)
-				skb_reserve(skb, Q->dma_offset);
-			mapping = pci_map_single(pdev, skb->data, dma_len,
-						 PCI_DMA_FROMDEVICE);
-			ce->skb = skb;
-			pci_unmap_addr_set(ce, dma_addr, mapping);
-			pci_unmap_len_set(ce, dma_len, dma_len);
-			e->AddrLow = (u32)mapping;
-			e->AddrHigh = (u64)mapping >> 32;
-			e->BufferLength = dma_len;
-			e->GenerationBit = e->GenerationBit2 = Q->genbit;
-		}
+		skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC);
+		if (!skb)
+			break;
+
+		skb_reserve(skb, q->dma_offset);
+		mapping = pci_map_single(pdev, skb->data, dma_len,
+					 PCI_DMA_FROMDEVICE);
+		ce->skb = skb;
+		pci_unmap_addr_set(ce, dma_addr, mapping);
+		pci_unmap_len_set(ce, dma_len, dma_len);
+		e->addr_lo = (u32)mapping;
+		e->addr_hi = (u64)mapping >> 32;
+		e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit);
+		wmb();
+		e->gen2 = V_CMD_GEN2(q->genbit);
 
 		e++;
 		ce++;
-		if (++Q->pidx == Q->entries_n) {
-			Q->pidx = 0;
-			Q->genbit ^= 1;
-			ce = Q->centries;
-			e = Q->entries;
+		if (++q->pidx == q->size) {
+			q->pidx = 0;
+			q->genbit ^= 1;
+			ce = q->centries;
+			e = q->entries;
 		}
-		Q->credits++;
+		q->credits++;
 	}
 
 }
 
 /*
- * Calls refill_free_list for both freelist Qs. If we cannot
- * fill at least 1/4 of both Qs, we go into 'few interrupt mode' in order
- * to give the system time to free up resources.
+ * Calls refill_free_list for both free lists. If we cannot fill at least 1/4
+ * of both rings, we go into 'few interrupt mode' in order to give the system
+ * time to free up resources.
  */
 static void freelQs_empty(struct sge *sge)
 {
-	u32 irq_reg = t1_read_reg_4(sge->adapter, A_SG_INT_ENABLE);
+	struct adapter *adapter = sge->adapter;
+	u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE);
 	u32 irqholdoff_reg;
 
 	refill_free_list(sge, &sge->freelQ[0]);
 	refill_free_list(sge, &sge->freelQ[1]);
 
-	if (sge->freelQ[0].credits > (sge->freelQ[0].entries_n >> 2) &&
-	    sge->freelQ[1].credits > (sge->freelQ[1].entries_n >> 2)) {
+	if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) &&
+	    sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) {
 		irq_reg |= F_FL_EXHAUSTED;
-		irqholdoff_reg = sge->intrtimer[sge->currIndex];
+		irqholdoff_reg = sge->fixed_intrtimer;
 	} else {
 		/* Clear the F_FL_EXHAUSTED interrupts for now */
 		irq_reg &= ~F_FL_EXHAUSTED;
 		irqholdoff_reg = sge->intrtimer_nres;
 	}
-	t1_write_reg_4(sge->adapter, A_SG_INTRTIMER, irqholdoff_reg);
-	t1_write_reg_4(sge->adapter, A_SG_INT_ENABLE, irq_reg);
+	writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER);
+	writel(irq_reg, adapter->regs + A_SG_INT_ENABLE);
 
 	/* We reenable the Qs to force a freelist GTS interrupt later */
-	doorbell_pio(sge, F_FL0_ENABLE | F_FL1_ENABLE);
+	doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE);
 }
 
 #define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA)
@@ -816,10 +670,10 @@ static void freelQs_empty(struct sge *sge)
  */
 void t1_sge_intr_disable(struct sge *sge)
 {
-	u32 val = t1_read_reg_4(sge->adapter, A_PL_ENABLE);
+	u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
 
-	t1_write_reg_4(sge->adapter, A_PL_ENABLE, val & ~SGE_PL_INTR_MASK);
-	t1_write_reg_4(sge->adapter, A_SG_INT_ENABLE, 0);
+	writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
+	writel(0, sge->adapter->regs + A_SG_INT_ENABLE);
 }
 
 /*
@@ -828,12 +682,12 @@ void t1_sge_intr_disable(struct sge *sge)
 void t1_sge_intr_enable(struct sge *sge)
 {
 	u32 en = SGE_INT_ENABLE;
-	u32 val = t1_read_reg_4(sge->adapter, A_PL_ENABLE);
+	u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
 
 	if (sge->adapter->flags & TSO_CAPABLE)
 		en &= ~F_PACKET_TOO_BIG;
-	t1_write_reg_4(sge->adapter, A_SG_INT_ENABLE, en);
-	t1_write_reg_4(sge->adapter, A_PL_ENABLE, val | SGE_PL_INTR_MASK);
+	writel(en, sge->adapter->regs + A_SG_INT_ENABLE);
+	writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
 }
 
 /*
@@ -841,8 +695,8 @@ void t1_sge_intr_enable(struct sge *sge)
  */
 void t1_sge_intr_clear(struct sge *sge)
 {
-	t1_write_reg_4(sge->adapter, A_PL_CAUSE, SGE_PL_INTR_MASK);
-	t1_write_reg_4(sge->adapter, A_SG_INT_CAUSE, 0xffffffff);
+	writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE);
+	writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE);
 }
 
 /*
@@ -851,464 +705,673 @@ void t1_sge_intr_clear(struct sge *sge)
 int t1_sge_intr_error_handler(struct sge *sge)
 {
 	struct adapter *adapter = sge->adapter;
-	u32 cause = t1_read_reg_4(adapter, A_SG_INT_CAUSE);
+	u32 cause = readl(adapter->regs + A_SG_INT_CAUSE);
 
 	if (adapter->flags & TSO_CAPABLE)
 		cause &= ~F_PACKET_TOO_BIG;
 	if (cause & F_RESPQ_EXHAUSTED)
-		sge->intr_cnt.respQ_empty++;
+		sge->stats.respQ_empty++;
 	if (cause & F_RESPQ_OVERFLOW) {
-		sge->intr_cnt.respQ_overflow++;
+		sge->stats.respQ_overflow++;
 		CH_ALERT("%s: SGE response queue overflow\n",
 			 adapter->name);
 	}
 	if (cause & F_FL_EXHAUSTED) {
-		sge->intr_cnt.freelistQ_empty++;
+		sge->stats.freelistQ_empty++;
 		freelQs_empty(sge);
 	}
 	if (cause & F_PACKET_TOO_BIG) {
-		sge->intr_cnt.pkt_too_big++;
+		sge->stats.pkt_too_big++;
 		CH_ALERT("%s: SGE max packet size exceeded\n",
 			 adapter->name);
 	}
 	if (cause & F_PACKET_MISMATCH) {
-		sge->intr_cnt.pkt_mismatch++;
+		sge->stats.pkt_mismatch++;
 		CH_ALERT("%s: SGE packet mismatch\n", adapter->name);
 	}
 	if (cause & SGE_INT_FATAL)
 		t1_fatal_err(adapter);
 
-	t1_write_reg_4(adapter, A_SG_INT_CAUSE, cause);
+	writel(cause, adapter->regs + A_SG_INT_CAUSE);
 	return 0;
 }
 
-/*
- * The following code is copied from 2.6, where the skb_pull is doing the
- * right thing and only pulls ETH_HLEN.
+const struct sge_intr_counts *t1_sge_get_intr_counts(struct sge *sge)
+{
+	return &sge->stats;
+}
+
+const struct sge_port_stats *t1_sge_get_port_stats(struct sge *sge, int port)
+{
+	return &sge->port_stats[port];
+}
+
+/**
+ *	recycle_fl_buf - recycle a free list buffer
+ *	@fl: the free list
+ *	@idx: index of buffer to recycle
  *
- *	Determine the packet's protocol ID. The rule here is that we
- *	assume 802.3 if the type field is short enough to be a length.
- *	This is normal practice and works for any 'now in use' protocol.
+ *	Recycles the specified buffer on the given free list by adding it at
+ *	the next available slot on the list.
  */
-static unsigned short sge_eth_type_trans(struct sk_buff *skb,
-					 struct net_device *dev)
+static void recycle_fl_buf(struct freelQ *fl, int idx)
 {
-	struct ethhdr *eth;
-	unsigned char *rawp;
+	struct freelQ_e *from = &fl->entries[idx];
+	struct freelQ_e *to = &fl->entries[fl->pidx];
 
-	skb->mac.raw = skb->data;
-	skb_pull(skb, ETH_HLEN);
-	eth = (struct ethhdr *)skb->mac.raw;
+	fl->centries[fl->pidx] = fl->centries[idx];
+	to->addr_lo = from->addr_lo;
+	to->addr_hi = from->addr_hi;
+	to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit);
+	wmb();
+	to->gen2 = V_CMD_GEN2(fl->genbit);
+	fl->credits++;
 
-	if (*eth->h_dest&1) {
-		if(memcmp(eth->h_dest, dev->broadcast, ETH_ALEN) == 0)
-			skb->pkt_type = PACKET_BROADCAST;
-		else
-			skb->pkt_type = PACKET_MULTICAST;
+	if (++fl->pidx == fl->size) {
+		fl->pidx = 0;
+		fl->genbit ^= 1;
 	}
+}
 
-	/*
-	 *	This ALLMULTI check should be redundant by 1.4
-	 *	so don't forget to remove it.
-	 *
-	 *	Seems, you forgot to remove it. All silly devices
-	 *	seems to set IFF_PROMISC.
-	 */
+/**
+ *	get_packet - return the next ingress packet buffer
+ *	@pdev: the PCI device that received the packet
+ *	@fl: the SGE free list holding the packet
+ *	@len: the actual packet length, excluding any