diff options
Diffstat (limited to 'drivers/net/bnx2x_reg.h')
| -rw-r--r-- | drivers/net/bnx2x_reg.h | 1969 |
1 files changed, 1484 insertions, 485 deletions
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index 5a1aa0b5504..15c9a994672 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h @@ -38,21 +38,19 @@ was asserted. */ #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc -#define BRB1_REG_NUM_OF_FULL_CYCLES_2 0x600d0 -#define BRB1_REG_NUM_OF_FULL_CYCLES_3 0x600d4 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was asserted. */ #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc -#define BRB1_REG_NUM_OF_PAUSE_CYCLES_2 0x600c0 -#define BRB1_REG_NUM_OF_PAUSE_CYCLES_3 0x600c4 /* [RW 10] Write client 0: De-assert pause threshold. */ #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c /* [RW 10] Write client 0: Assert pause threshold. */ #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c +/* [R 24] The number of full blocks occpied by port. */ +#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 /* [RW 1] Reset the design by software. */ #define BRB1_REG_SOFT_RESET 0x600dc /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ @@ -72,6 +70,8 @@ #define CCM_REG_CCM_INT_MASK 0xd01e4 /* [R 11] Interrupt register #0 read */ #define CCM_REG_CCM_INT_STS 0xd01d8 +/* [R 27] Parity register #0 read */ +#define CCM_REG_CCM_PRTY_STS 0xd01e8 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). Is used to determine the number of the AG context REG-pairs written back; @@ -190,25 +190,20 @@ weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define CCM_REG_PBF_WEIGHT 0xd00ac -/* [RW 6] The physical queue number of queue number 1 per port index. */ #define CCM_REG_PHYS_QNUM1_0 0xd0134 #define CCM_REG_PHYS_QNUM1_1 0xd0138 -/* [RW 6] The physical queue number of queue number 2 per port index. */ #define CCM_REG_PHYS_QNUM2_0 0xd013c #define CCM_REG_PHYS_QNUM2_1 0xd0140 -/* [RW 6] The physical queue number of queue number 3 per port index. */ #define CCM_REG_PHYS_QNUM3_0 0xd0144 -/* [RW 6] The physical queue number of queue number 0 with QOS equal 0 port - index 0. */ +#define CCM_REG_PHYS_QNUM3_1 0xd0148 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118 -/* [RW 6] The physical queue number of queue number 0 with QOS equal 1 port - index 0. */ #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120 -/* [RW 6] The physical queue number of queue number 0 with QOS equal 2 port - index 0. */ #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124 +#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128 +#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c +#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ @@ -253,6 +248,7 @@ mechanism. The fields are: [5:0] - message length; [12:6] - message pointer; 18:13] - next pointer. */ #define CCM_REG_XX_DESCR_TABLE 0xd0300 +#define CCM_REG_XX_DESCR_TABLE_SIZE 36 /* [R 7] Used to read the value of XX protection Free counter. */ #define CCM_REG_XX_FREE 0xd0184 /* [RW 6] Initial value for the credit counter; responsible for fulfilling @@ -296,6 +292,8 @@ /* [WB 24] MATT ram access. each entry has the following format:{RegionLength[11:0]; egionOffset[11:0]} */ #define CDU_REG_MATT 0x101100 +/* [RW 1] when this bit is set the CDU operates in e1hmf mode */ +#define CDU_REG_MF_MODE 0x101050 /* [R 1] indication the initializing the activity counter by the hardware was done. */ #define CFC_REG_AC_INIT_DONE 0x104078 @@ -330,6 +328,9 @@ field allows changing the priorities of the weighted-round-robin arbiter which selects which CFC load client should be served next */ #define CFC_REG_LCREQ_WEIGHTS 0x104084 +/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */ +#define CFC_REG_LINK_LIST 0x104c00 +#define CFC_REG_LINK_LIST_SIZE 256 /* [R 1] indication the initializing the link list by the hardware was done. */ #define CFC_REG_LL_INIT_DONE 0x104074 /* [R 9] Number of allocated LCIDs which are at empty state */ @@ -342,6 +343,45 @@ #define CFC_REG_NUM_LCIDS_LEAVING 0x104018 /* [RW 8] The event id for aggregated interrupt 0 */ #define CSDM_REG_AGG_INT_EVENT_0 0xc2038 +#define CSDM_REG_AGG_INT_EVENT_1 0xc203c +#define CSDM_REG_AGG_INT_EVENT_10 0xc2060 +#define CSDM_REG_AGG_INT_EVENT_11 0xc2064 +#define CSDM_REG_AGG_INT_EVENT_12 0xc2068 +#define CSDM_REG_AGG_INT_EVENT_13 0xc206c +#define CSDM_REG_AGG_INT_EVENT_14 0xc2070 +#define CSDM_REG_AGG_INT_EVENT_15 0xc2074 +#define CSDM_REG_AGG_INT_EVENT_16 0xc2078 +#define CSDM_REG_AGG_INT_EVENT_17 0xc207c +#define CSDM_REG_AGG_INT_EVENT_18 0xc2080 +#define CSDM_REG_AGG_INT_EVENT_19 0xc2084 +#define CSDM_REG_AGG_INT_EVENT_2 0xc2040 +#define CSDM_REG_AGG_INT_EVENT_20 0xc2088 +#define CSDM_REG_AGG_INT_EVENT_21 0xc208c +#define CSDM_REG_AGG_INT_EVENT_22 0xc2090 +#define CSDM_REG_AGG_INT_EVENT_23 0xc2094 +#define CSDM_REG_AGG_INT_EVENT_24 0xc2098 +#define CSDM_REG_AGG_INT_EVENT_25 0xc209c +#define CSDM_REG_AGG_INT_EVENT_26 0xc20a0 +#define CSDM_REG_AGG_INT_EVENT_27 0xc20a4 +#define CSDM_REG_AGG_INT_EVENT_28 0xc20a8 +#define CSDM_REG_AGG_INT_EVENT_29 0xc20ac +#define CSDM_REG_AGG_INT_EVENT_3 0xc2044 +#define CSDM_REG_AGG_INT_EVENT_30 0xc20b0 +#define CSDM_REG_AGG_INT_EVENT_31 0xc20b4 +#define CSDM_REG_AGG_INT_EVENT_4 0xc2048 +/* [RW 1] The T bit for aggregated interrupt 0 */ +#define CSDM_REG_AGG_INT_T_0 0xc20b8 +#define CSDM_REG_AGG_INT_T_1 0xc20bc +#define CSDM_REG_AGG_INT_T_10 0xc20e0 +#define CSDM_REG_AGG_INT_T_11 0xc20e4 +#define CSDM_REG_AGG_INT_T_12 0xc20e8 +#define CSDM_REG_AGG_INT_T_13 0xc20ec +#define CSDM_REG_AGG_INT_T_14 0xc20f0 +#define CSDM_REG_AGG_INT_T_15 0xc20f4 +#define CSDM_REG_AGG_INT_T_16 0xc20f8 +#define CSDM_REG_AGG_INT_T_17 0xc20fc +#define CSDM_REG_AGG_INT_T_18 0xc2100 +#define CSDM_REG_AGG_INT_T_19 0xc2104 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 /* [RW 16] The maximum value of the competion counter #0 */ @@ -358,6 +398,9 @@ /* [RW 32] Interrupt mask register #0 read/write */ #define CSDM_REG_CSDM_INT_MASK_0 0xc229c #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac +/* [R 32] Interrupt register #0 read */ +#define CSDM_REG_CSDM_INT_STS_0 0xc2290 +#define CSDM_REG_CSDM_INT_STS_1 0xc22a0 /* [RW 11] Parity mask register #0 read/write */ #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc /* [R 11] Parity register #0 read */ @@ -443,6 +486,9 @@ /* [RW 32] Interrupt mask register #0 read/write */ #define CSEM_REG_CSEM_INT_MASK_0 0x200110 #define CSEM_REG_CSEM_INT_MASK_1 0x200120 +/* [R 32] Interrupt register #0 read */ +#define CSEM_REG_CSEM_INT_STS_0 0x200104 +#define CSEM_REG_CSEM_INT_STS_1 0x200114 /* [RW 32] Parity mask register #0 read/write */ #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 @@ -453,9 +499,8 @@ #define CSEM_REG_ENABLE_OUT 0x2000a8 /* [RW 32] This address space contains all registers and memories that are placed in SEM_FAST block. The SEM_FAST registers are described in - appendix B. In order to access the SEM_FAST registers the base address - CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each - SEM_FAST register offset. */ + appendix B. In order to access the sem_fast registers the base address + ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ #define CSEM_REG_FAST_MEMORY 0x220000 /* [RW 1] Disables input messages from FIC0 May be updated during run_time by the microcode */ @@ -539,13 +584,10 @@ #define DBG_REG_DBG_PRTY_MASK 0xc0a8 /* [R 1] Parity register #0 read */ #define DBG_REG_DBG_PRTY_STS 0xc09c -/* [RW 2] debug only: These bits indicate the credit for PCI request type 4 - interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are - configured */ -#define DBG_REG_PCI_REQ_CREDIT 0xc120 /* [RW 32] Commands memory. The address to command X; row Y is to calculated as 14*X+Y. */ #define DMAE_REG_CMD_MEM 0x102400 +#define DMAE_REG_CMD_MEM_SIZE 224 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c initial value is all ones. */ #define DMAE_REG_CRC16C_INIT 0x10201c @@ -630,6 +672,8 @@ #define DORQ_REG_AGG_CMD3 0x17006c /* [RW 28] UCM Header. */ #define DORQ_REG_CMHEAD_RX 0x170050 +/* [RW 32] Doorbell address for RBC doorbells (function 0). */ +#define DORQ_REG_DB_ADDR0 0x17008c /* [RW 5] Interrupt mask register #0 read/write */ #define DORQ_REG_DORQ_INT_MASK 0x170180 /* [R 5] Interrupt register #0 read */ @@ -690,75 +734,33 @@ #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) #define HC_REG_AGG_INT_0 0x108050 #define HC_REG_AGG_INT_1 0x108054 -/* [RW 16] attention bit and attention acknowledge bits status for port 0 - and 1 according to the following address map: addr 0 - attn_bit_0; addr 1 - - attn_ack_bit_0; addr 2 - attn_bit_1; addr 3 - attn_ack_bit_1; */ #define HC_REG_ATTN_BIT 0x108120 -/* [RW 16] attn bits status index for attn bit msg; addr 0 - function 0; - addr 1 - functin 1 */ #define HC_REG_ATTN_IDX 0x108100 -/* [RW 32] port 0 lower 32 bits address field for attn messag. */ #define HC_REG_ATTN_MSG0_ADDR_L 0x108018 -/* [RW 32] port 1 lower 32 bits address field for attn messag. */ #define HC_REG_ATTN_MSG1_ADDR_L 0x108020 -/* [RW 8] status block number for attn bit msg - function 0; */ #define HC_REG_ATTN_NUM_P0 0x108038 -/* [RW 8] status block number for attn bit msg - function 1 */ #define HC_REG_ATTN_NUM_P1 0x10803c #define HC_REG_CONFIG_0 0x108000 #define HC_REG_CONFIG_1 0x108004 +#define HC_REG_FUNC_NUM_P0 0x1080ac +#define HC_REG_FUNC_NUM_P1 0x1080b0 /* [RW 3] Parity mask register #0 read/write */ #define HC_REG_HC_PRTY_MASK 0x1080a0 /* [R 3] Parity register #0 read */ #define HC_REG_HC_PRTY_STS 0x108094 -/* [RW 17] status block interrupt mask; one in each bit means unmask; zerow - in each bit means mask; bit 0 - default SB; bit 1 - SB_0; bit 2 - SB_1... - bit 16- SB_15; addr 0 - port 0; addr 1 - port 1 */ #define HC_REG_INT_MASK 0x108108 -/* [RW 16] port 0 attn bit condition monitoring; each bit that is set will - lock a change fron 0 to 1 in the corresponding attention signals that - comes from the AEU */ #define HC_REG_LEADING_EDGE_0 0x108040 #define HC_REG_LEADING_EDGE_1 0x108048 -/* [RW 16] all producer and consumer of port 0 according to the following - addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63; - Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons: - U/C/X/T/Attn-69/70/71/72/73 */ #define HC_REG_P0_PROD_CONS 0x108200 -/* [RW 16] all producer and consumer of port 1according to the following - addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63; - Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons: - U/C/X/T/Attn-69/70/71/72/73 */ #define HC_REG_P1_PROD_CONS 0x108400 -/* [W 1] This register is write only and has 4 addresses as follow: 0 = - clear all PBA bits port 0; 1 = clear all pending interrupts request - port0; 2 = clear all PBA bits port 1; 3 = clear all pending interrupts - request port1; here is no meaning for the data in this register */ #define HC_REG_PBA_COMMAND 0x108140 #define HC_REG_PCI_CONFIG_0 0x108010 #define HC_REG_PCI_CONFIG_1 0x108014 -/* [RW 24] all counters acording to the following address: LSB: 0=read; 1= - read_clear; 0-71 = HW counters (the inside order is the same as the - interrupt table in the spec); 72-219 = SW counters 1 (stops after first - consumer upd) the inside order is: 72-103 - U_non_default_p0; 104-135 - C_non_defaul_p0; 36-145 U/C/X/T/Attn_default_p0; 146-177 - U_non_default_p1; 178-209 C_non_defaul_p1; 10-219 U/C/X/T/Attn_default_p1 - ; 220-367 = SW counters 2 (stops when prod=cons) the inside order is: - 220-251 - U_non_default_p0; 252-283 C_non_defaul_p0; 84-293 - U/C/X/T/Attn_default_p0; 294-325 U_non_default_p1; 326-357 - C_non_defaul_p1; 58-367 U/C/X/T/Attn_default_p1 ; 368-515 = mailbox - counters; (the inside order of the mailbox counter is 368-431 U and C - non_default_p0; 432-441 U/C/X/T/Attn_default_p0; 442-505 U and C - non_default_p1; 506-515 U/C/X/T/Attn_default_p1) */ #define HC_REG_STATISTIC_COUNTERS 0x109000 -/* [RW 16] port 0 attn bit condition monitoring; each bit that is set will - lock a change fron 1 to 0 in the corresponding attention signals that - comes from the AEU */ #define HC_REG_TRAILING_EDGE_0 0x108044 #define HC_REG_TRAILING_EDGE_1 0x10804c #define HC_REG_UC_RAM_ADDR_0 0x108028 #define HC_REG_UC_RAM_ADDR_1 0x108030 -/* [RW 16] ustorm address for coalesc now message */ #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068 #define HC_REG_VQID_0 0x108008 #define HC_REG_VQID_1 0x10800c @@ -883,14 +885,16 @@ rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458 -/* [W 11] write to this register results with the clear of the latched +/* [W 14] write to this register results with the clear of the latched signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP latch; one in d5 clears GRC Latched timeout attention; one in d6 clears GRC Latched reserved access attention; one in d7 clears Latched rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears - Latched ump_tx_parity; one in d10 clears Latched scpad_parity; read from - this register return zero */ + Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both + ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears + pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read + from this register return zero */ #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c /* [RW 32] first 32b for enabling the output for function 0 output0. mapped as follows: [0] NIG attention for function0; [1] NIG attention for @@ -907,7 +911,11 @@ TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c +#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c +#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc +#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc +#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc /* [RW 32] first 32b for enabling the output for function 1 output0. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function @@ -923,9 +931,13 @@ TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c +#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c -/* [RW 32] first 32b for enabling the output for close the gate nig 0. - mapped as follows: [0] NIG attention for function0; [1] NIG attention for +#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c +#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c +#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c +/* [RW 32] first 32b for enabling the output for close the gate nig. mapped + as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event @@ -939,8 +951,8 @@ TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c -/* [RW 32] first 32b for enabling the output for close the gate pxp 0. - mapped as follows: [0] NIG attention for function0; [1] NIG attention for +/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped + as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event @@ -984,34 +996,34 @@ interrupt; */ #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120 -/* [RW 32] second 32b for enabling the output for close the gate nig 0. - mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; - [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] - Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] - XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] - XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw - interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI - core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity - error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw - interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI - Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw - interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM - Parity error; [31] CCM Hw interrupt; */ +/* [RW 32] second 32b for enabling the output for close the gate nig. mapped + as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM + Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw + interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity + error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw + interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] + NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; + [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw + interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM + Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI + Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM + Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw + interrupt; */ #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190 -/* [RW 32] second 32b for enabling the output for close the gate pxp 0. - mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; - [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] - Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] - XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] - XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw - interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI - core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity - error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw - interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI - Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw - interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM - Parity error; [31] CCM Hw interrupt; */ +/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped + as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM + Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw + interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity + error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw + interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] + NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; + [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw + interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM + Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI + Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM + Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw + interrupt; */ #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped @@ -1044,34 +1056,34 @@ attn1; */ #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124 -/* [RW 32] third 32b for enabling the output for close the gate nig 0. - mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] - PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity - error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC - Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE - Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] - IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; - [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; - [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; - [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; - [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers - attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] - General attn1; */ +/* [RW 32] third 32b for enabling the output for close the gate nig. mapped + as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP + Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; + [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw + interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity + error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) + Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] + pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] + MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] + SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW + timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 + func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General + attn1; */ #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194 -/* [RW 32] third 32b for enabling the output for close the gate pxp 0. - mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] - PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity - error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC - Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE - Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] - IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; - [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; - [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; - [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; - [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers - attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] - General attn1; */ +/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped + as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP + Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; + [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw + interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity + error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) + Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] + pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] + MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] + SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW + timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 + func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General + attn1; */ #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped @@ -1088,6 +1100,10 @@ Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098 +#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8 +#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8 +#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8 +#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; @@ -1102,34 +1118,36 @@ Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138 -/* [RW 32] fourth 32b for enabling the output for close the gate nig - 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General - attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] - General attn8; [7] General attn9; [8] General attn10; [9] General attn11; - [10] General attn12; [11] General attn13; [12] General attn14; [13] - General attn15; [14] General attn16; [15] General attn17; [16] General - attn18; [17] General attn19; [18] General attn20; [19] General attn21; - [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched - attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched - attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved - access attention; [28] MCP Latched rom_parity; [29] MCP Latched - ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched - scpad_parity; */ +#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158 +#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168 +#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178 +#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188 +/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped + as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] + General attn5; [4] General attn6; [5] General attn7; [6] General attn8; + [7] General attn9; [8] General attn10; [9] General attn11; [10] General + attn12; [11] General attn13; [12] General attn14; [13] General attn15; + [14] General attn16; [15] General attn17; [16] General attn18; [17] + General attn19; [18] General attn20; [19] General attn21; [20] Main power + interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN + Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC + Latched timeout attention; [27] GRC Latched reserved access attention; + [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP + Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198 -/* [RW 32] fourth 32b for enabling the output for close the gate pxp - 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General - attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] - General attn8; [7] General attn9; [8] General attn10; [9] General attn11; - [10] General attn12; [11] General attn13; [12] General attn14; [13] - General attn15; [14] General attn16; [15] General attn17; [16] General - attn18; [17] General attn19; [18] General attn20; [19] General attn21; - [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched - attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched - attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved - access attention; [28] MCP Latched rom_parity; [29] MCP Latched - ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched - scpad_parity; */ +/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped + as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] + General attn5; [4] General attn6; [5] General attn7; [6] General attn8; + [7] General attn9; [8] General attn10; [9] General attn11; [10] General + attn12; [11] General attn13; [12] General attn14; [13] General attn15; + [14] General attn16; [15] General attn17; [16] General attn18; [17] + General attn19; [18] General attn20; [19] General attn21; [20] Main power + interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN + Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC + Latched timeout attention; [27] GRC Latched reserved access attention; + [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP + Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu @@ -1148,6 +1166,7 @@ #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c +#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050 #define MISC_REG_AEU_GENERAL_ATTN_21 0xa054 @@ -1158,6 +1177,7 @@ #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 +#define MISC_REG_AEU_GENERAL_MASK 0xa61c /* [RW 32] first 32b for inverting the input for function 0; for each bit: 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; @@ -1189,10 +1209,29 @@ #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; - [9:8] = mask close the gates signals of function 0 toward PXP [8] and NIG - [9]. Zero = mask; one = unmask */ + [9:8] = raserved. Zero = mask; one = unmask */ #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064 +/* [RW 1] If set a system kill occurred */ +#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610 +/* [RW 32] Represent the status of the input vector to the AEU when a system + kill occurred. The register is reset in por reset. Mapped as follows: [0] + NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 + mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; + [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] + PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event + function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP + Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for + mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] + BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC + Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw + interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI + Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw + interrupt; */ +#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600 +#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604 +#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608 +#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 Port. */ #define MISC_REG_BOND_ID 0xa400 @@ -1206,8 +1245,80 @@ starts at 0x0 for the A0 tape-out and increments by one for each all-layer tape-out. */ #define MISC_REG_CHIP_REV 0xa40c -/* [RW 32] The following driver registers(1..6) represent 6 drivers and 32 - clients. Each client can be controlled by one driver only. One in each +/* [RW 32] The following driver registers(1...16) represent 16 drivers and + 32 clients. Each client can be controlled by one driver only. One in each + bit represent that this driver control the appropriate client (Ex: bit 5 + is set means this driver control client number 5). addr1 = set; addr0 = + clear; read from both addresses will give the same result = status. write + to address 1 will set a request to control all the clients that their + appropriate bit (in the write command) is set. if the client is free (the + appropriate bit in all the other drivers is clear) one will be written to + that driver register; if the client isn't free the bit will remain zero. + if the appropriate bit is set (the driver request to gain control on a + client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW + interrupt will be asserted). write to address 0 will set a request to + free all the clients that their appropriate bit (in the write command) is + set. if the appropriate bit is clear (the driver request to free a client + it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will + be asserted). */ +#define MISC_REG_DRIVER_CONTROL_10 0xa3e0 +#define MISC_REG_DRIVER_CONTROL_10_SIZE 2 +/* [RW 32] The following driver registers(1...16) represent 16 drivers and + 32 clients. Each client can be controlled by one driver only. One in each + bit represent that this driver control the appropriate client (Ex: bit 5 + is set means this driver control client number 5). addr1 = set; addr0 = + clear; read from both addresses will give the same result = status. write + to address 1 will set a request to control all the clients that their + appropriate bit (in the write command) is set. if the client is free (the + appropriate bit in all the other drivers is clear) one will be written to + that driver register; if the client isn't free the bit will remain zero. + if the appropriate bit is set (the driver request to gain control on a + client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW + interrupt will be asserted). write to address 0 will set a request to + free all the clients that their appropriate bit (in the write command) is + set. if the appropriate bit is clear (the driver request to free a client + it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will + be asserted). */ +#define MISC_REG_DRIVER_CONTROL_11 0xa3e8 +#define MISC_REG_DRIVER_CONTROL_11_SIZE 2 +/* [RW 32] The following driver registers(1...16) represent 16 drivers and + 32 clients. Each client can be controlled by one driver only. One in each + bit represent that this driver control the appropriate client (Ex: bit 5 + is set means this driver control client number 5). addr1 = set; addr0 = + clear; read from both addresses will give the same result = status. write + to address 1 will set a request to control all the clients that their + appropriate bit (in the write command) is set. if the client is free (the + appropriate bit in all the other drivers is clear) one will be written to + that driver register; if the client isn't free the bit will remain zero. + if the appropriate bit is set (the driver request to gain control on a + client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW + interrupt will be asserted). write to address 0 will set a request to + free all the clients that their appropriate bit (in the write command) is + set. if the appropriate bit is clear (the driver request to free a client + it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will + be asserted). */ +#define MISC_REG_DRIVER_CONTROL_12 0xa3f0 +#define MISC_REG_DRIVER_CONTROL_12_SIZE 2 +/* [RW 32] The following driver registers(1...16) represent 16 drivers and + 32 clients. Each client can be controlled by one driver only. One in each + bit represent that this driver control the appropriate client (Ex: bit 5 + is set means this driver control client number 5). addr1 = set; addr0 = + clear; read from both addresses will give the same result = status. write + to address 1 will set a request to control all the clients that their + appropriate bit (in the write command) is set. if the client is free (the + appropriate bit in all the other drivers is clear) one will be written to + that driver register; if the client isn't free the bit will remain zero. + if the appropriate bit is set (the driver request to gain control on a + client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW + interrupt will be asserted). write to address 0 will set a request to + free all the clients that their appropriate bit (in the write command) is + set. if the appropriate bit is clear (the driver request to free a client + it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will + be asserted). */ +#define MISC_REG_DRIVER_CONTROL_13 0xa3f8 +#define MISC_REG_DRIVER_CONTROL_13_SIZE 2 +/* [RW 32] The following driver registers(1...16) represent 16 drivers and + 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write @@ -1223,6 +1334,47 @@ it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). */ #define MISC_REG_DRIVER_CONTROL_1 0xa510 +#define MISC_REG_DRIVER_CONTROL_14 0xa5e0 +#define MISC_REG_DRIVER_CONTROL_14_SIZE 2 +/* [RW 32] The following driver registers(1...16) represent 16 drivers and + 32 clients. Each client can be controlled by one driver only. One in each + bit represent that this driver control the appropriate client (Ex: bit 5 + is set means this driver control client number 5). addr1 = set; addr0 = + clear; read from both addresses will give the same result = status. write + to address 1 will set a request to control all the clients that their + appropriate bit (in the write command) is set. if the client is free (the + appropriate bit in all the other drivers is clear) one will be written to + that driver register; if the client isn't free the bit will remain zero. + if the appropriate bit is set (the driver request to gain control on a + client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW + interrupt will be asserted). write to address 0 will set a request to + free all the clients that their appropriate bit (in the write command) is + set. if the appropriate bit is clear (the driver request to free a client + it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will + be asserted). */ +#define MISC_REG_DRIVER_CONTROL_15 0xa5e8 +#define MISC_REG_DRIVER_CONTROL_15_SIZE 2 +/* [RW 32] The following driver registers(1...16) represent 16 drivers and + 32 clients. Each client can be controlled by one driver only. One in each + bit represent that this driver control the appropriate client (Ex: bit 5 + is set means this driver control client number 5). addr1 = set; addr0 = + clear; read from both addresses will give the same result = status. write + to address 1 will set a request to control all the clients that their + appropriate bit (in the write command) is set. if the client is free (the + appropriate bit in all the other drivers is clear) one will be written to + that driver register; if the client isn't free the bit will remain zero. + if the appropriate bit is set (the driver request to gain control on a + client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW + interrupt will be asserted). write to address 0 will set a request to + free all the clients that their appropriate bit (in the write command) is + set. if the appropriate bit is clear (the driver request to free a client + it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will + be asserted). */ +#define MISC_REG_DRIVER_CONTROL_16 0xa5f0 +#define MISC_REG_DRIVER_CONTROL_16_SIZE 2 +/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 + only. */ +#define MISC_REG_E1HMF_MODE 0xa5f8 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of these bits is written as a '1'; the corresponding SPIO bit will turn off it's drivers and become an input. This is the reset state of all GPIO @@ -1240,6 +1392,18 @@ This is the result value of the pin; not the drive value. Writing these bits will have not effect. */ #define MISC_REG_GPIO 0xa490 +/* [R 28] this field hold the last information that caused reserved + attention. bits [19:0] - address; [22:20] function; [23] reserved; + [27:24] the master thatcaused the attention - according to the following + encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = + dbu; 8 = dmae */ +#define MISC_REG_GRC_RSV_ATTN 0xa3c0 +/* [R 28] this field hold the last information that caused timeout + attention. bits [19:0] - address; [22:20] function; [23] reserved; + [27:24] the master thatcaused the attention - according to the following + encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = + dbu; 8 = dmae */ +#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any access that does not finish within ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is @@ -1282,6 +1446,11 @@ #define MISC_REG_MISC_PRTY_MASK 0xa398 /* [R 1] Parity register #0 read */ #define MISC_REG_MISC_PRTY_STS 0xa38c +#define MISC_REG_NIG_WOL_P0 0xa270 +#define MISC_REG_NIG_WOL_P1 0xa274 +/* [R 1] If set indicate that the pcie_rst_b was asserted without perst + assertion */ +#define MISC_REG_PCIE_HOT_RESET 0xa618 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 @@ -1303,7 +1472,7 @@ #define MISC_REG_PLL_STORM_CTRL_2 0xa298 |