diff options
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_reg.h')
| -rw-r--r-- | drivers/net/bnx2x/bnx2x_reg.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h index 86bba25d2d3..949e8bd7318 100644 --- a/drivers/net/bnx2x/bnx2x_reg.h +++ b/drivers/net/bnx2x/bnx2x_reg.h @@ -5184,6 +5184,7 @@ #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11) #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13) #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12) +#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (1<<2) #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5) #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9) #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12) @@ -6037,6 +6038,7 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_PMA_REG_BCM_CTRL 0x0096 #define MDIO_PMA_REG_FEC_CTRL 0x00ab #define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000 +#define MDIO_PMA_REG_TX_ALARM_CTRL 0x9001 #define MDIO_PMA_REG_LASI_CTRL 0x9002 #define MDIO_PMA_REG_RX_ALARM 0x9003 #define MDIO_PMA_REG_TX_ALARM 0x9004 @@ -6201,6 +6203,29 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 +/* BCM84833 only */ +#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a +#define MDIO_84833_SUPER_ISOLATE 0x8000 +/* These are mailbox register set used by 84833. */ +#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 +#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 +#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 +#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 +#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 + +/* Mailbox command set used by 84833. */ +#define PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE 0x2 +/* Mailbox status set used by 84833. */ +#define PHY84833_CMD_RECEIVED 0x0001 +#define PHY84833_CMD_IN_PROGRESS 0x0002 +#define PHY84833_CMD_COMPLETE_PASS 0x0004 +#define PHY84833_CMD_COMPLETE_ERROR 0x0008 +#define PHY84833_CMD_OPEN_FOR_CMDS 0x0010 +#define PHY84833_CMD_SYSTEM_BOOT 0x0020 +#define PHY84833_CMD_NOT_OPEN_FOR_CMDS 0x0040 +#define PHY84833_CMD_CLEAR_COMPLETE 0x0080 +#define PHY84833_CMD_OPEN_OVERRIDE 0xa5a5 + #define IGU_FUNC_BASE 0x0400 #define IGU_ADDR_MSIX 0x0000 |