diff options
Diffstat (limited to 'drivers/net/bnx2x.c')
| -rw-r--r-- | drivers/net/bnx2x.c | 9065 |
1 files changed, 9065 insertions, 0 deletions
diff --git a/drivers/net/bnx2x.c b/drivers/net/bnx2x.c new file mode 100644 index 00000000000..e8c5754798e --- /dev/null +++ b/drivers/net/bnx2x.c @@ -0,0 +1,9065 @@ +/* bnx2x.c: Broadcom Everest network driver. + * + * Copyright (c) 2007 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + * + * Written by: Eliezer Tamir <eliezert@broadcom.com> + * Based on code from Michael Chan's bnx2 driver + * UDP CSUM errata workaround by Arik Gendelman + * Slowpath rework by Vladislav Zolotarov + * Statistics and Link managment by Yitchak Gertner + * + */ + +/* define this to make the driver freeze on error + * to allow getting debug info + * (you will need to reboot afterwords) + */ +/*#define BNX2X_STOP_ON_ERROR*/ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/kernel.h> +#include <linux/device.h> /* for dev_info() */ +#include <linux/timer.h> +#include <linux/errno.h> +#include <linux/ioport.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include <linux/interrupt.h> +#include <linux/pci.h> +#include <linux/init.h> +#include <linux/netdevice.h> +#include <linux/etherdevice.h> +#include <linux/skbuff.h> +#include <linux/dma-mapping.h> +#include <linux/bitops.h> +#include <linux/irq.h> +#include <linux/delay.h> +#include <asm/byteorder.h> +#include <linux/time.h> +#include <linux/ethtool.h> +#include <linux/mii.h> +#ifdef NETIF_F_HW_VLAN_TX + #include <linux/if_vlan.h> + #define BCM_VLAN 1 +#endif +#include <net/ip.h> +#include <net/tcp.h> +#include <net/checksum.h> +#include <linux/workqueue.h> +#include <linux/crc32.h> +#include <linux/prefetch.h> +#include <linux/zlib.h> +#include <linux/version.h> +#include <linux/io.h> + +#include "bnx2x_reg.h" +#include "bnx2x_fw_defs.h" +#include "bnx2x_hsi.h" +#include "bnx2x.h" +#include "bnx2x_init.h" + +#define DRV_MODULE_VERSION "0.40.15" +#define DRV_MODULE_RELDATE "$DateTime: 2007/11/15 07:28:37 $" +#define BNX2X_BC_VER 0x040009 + +/* Time in jiffies before concluding the transmitter is hung. */ +#define TX_TIMEOUT (5*HZ) + +static const char version[] __devinitdata = + "Broadcom NetXtreme II 577xx 10Gigabit Ethernet Driver " + DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; + +MODULE_AUTHOR("Eliezer Tamir <eliezert@broadcom.com>"); +MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_MODULE_VERSION); +MODULE_INFO(cvs_version, "$Revision: #356 $"); + +static int use_inta; +static int poll; +static int onefunc; +static int nomcp; +static int debug; +static int use_multi; + +module_param(use_inta, int, 0); +module_param(poll, int, 0); +module_param(onefunc, int, 0); +module_param(debug, int, 0); +MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X"); +MODULE_PARM_DESC(poll, "use polling (for debug)"); +MODULE_PARM_DESC(onefunc, "enable only first function"); +MODULE_PARM_DESC(nomcp, "ignore managment CPU (Implies onefunc)"); +MODULE_PARM_DESC(debug, "defualt debug msglevel"); + +#ifdef BNX2X_MULTI +module_param(use_multi, int, 0); +MODULE_PARM_DESC(use_multi, "use per-CPU queues"); +#endif + +enum bnx2x_board_type { + BCM57710 = 0, +}; + +/* indexed by board_t, above */ +static const struct { + char *name; +} board_info[] __devinitdata = { + { "Broadcom NetXtreme II BCM57710 XGb" } +}; + +static const struct pci_device_id bnx2x_pci_tbl[] = { + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 }, + { 0 } +}; + +MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); + +/**************************************************************************** +* General service functions +****************************************************************************/ + +/* used only at init + * locking is done by mcp + */ +static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) +{ + pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); + pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); + pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, + PCICFG_VENDOR_ID_OFFSET); +} + +#ifdef BNX2X_IND_RD +static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) +{ + u32 val; + + pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); + pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); + pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, + PCICFG_VENDOR_ID_OFFSET); + + return val; +} +#endif + +static const u32 dmae_reg_go_c[] = { + DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, + DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, + DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, + DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 +}; + +/* copy command into DMAE command memory and set DMAE command go */ +static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, + int idx) +{ + u32 cmd_offset; + int i; + + cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); + for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { + REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); + +/* DP(NETIF_MSG_DMAE, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", + idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); */ + } + REG_WR(bp, dmae_reg_go_c[idx], 1); +} + +static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, + u32 dst_addr, u32 len32) +{ + struct dmae_command *dmae = &bp->dmae; + int port = bp->port; + u32 *wb_comp = bnx2x_sp(bp, wb_comp); + int timeout = 200; + + memset(dmae, 0, sizeof(struct dmae_command)); + + dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC | + DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | + DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | +#ifdef __BIG_ENDIAN + DMAE_CMD_ENDIANITY_B_DW_SWAP | +#else + DMAE_CMD_ENDIANITY_DW_SWAP | +#endif + (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0)); + dmae->src_addr_lo = U64_LO(dma_addr); + dmae->src_addr_hi = U64_HI(dma_addr); + dmae->dst_addr_lo = dst_addr >> 2; + dmae->dst_addr_hi = 0; + dmae->len = len32; + dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); + dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); + dmae->comp_val = BNX2X_WB_COMP_VAL; + +/* + DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n" + DP_LEVEL "src_addr [%x:%08x] len [%d *4] " + "dst_addr [%x:%08x (%08x)]\n" + DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n", + dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, + dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr, + dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val); +*/ +/* + DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n", + bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], + bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); +*/ + + *wb_comp = 0; + + bnx2x_post_dmae(bp, dmae, port * 8); + + udelay(5); + /* adjust timeout for emulation/FPGA */ + if (CHIP_REV_IS_SLOW(bp)) + timeout *= 100; + while (*wb_comp != BNX2X_WB_COMP_VAL) { +/* DP(NETIF_MSG_DMAE, "wb_comp 0x%08x\n", *wb_comp); */ + udelay(5); + if (!timeout) { + BNX2X_ERR("dmae timeout!\n"); + break; + } + timeout--; + } +} + +#ifdef BNX2X_DMAE_RD +static void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) +{ + struct dmae_command *dmae = &bp->dmae; + int port = bp->port; + u32 *wb_comp = bnx2x_sp(bp, wb_comp); + int timeout = 200; + + memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4); + memset(dmae, 0, sizeof(struct dmae_command)); + + dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI | + DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | + DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | +#ifdef __BIG_ENDIAN + DMAE_CMD_ENDIANITY_B_DW_SWAP | +#else + DMAE_CMD_ENDIANITY_DW_SWAP | +#endif + (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0)); + dmae->src_addr_lo = src_addr >> 2; + dmae->src_addr_hi = 0; + dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); + dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); + dmae->len = len32; + dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); + dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); + dmae->comp_val = BNX2X_WB_COMP_VAL; + +/* + DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n" + DP_LEVEL "src_addr [%x:%08x] len [%d *4] " + "dst_addr [%x:%08x (%08x)]\n" + DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n", + dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, + dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr, + dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val); +*/ + + *wb_comp = 0; + + bnx2x_post_dmae(bp, dmae, port * 8); + + udelay(5); + while (*wb_comp != BNX2X_WB_COMP_VAL) { + udelay(5); + if (!timeout) { + BNX2X_ERR("dmae timeout!\n"); + break; + } + timeout--; + } +/* + DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n", + bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], + bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); +*/ +} +#endif + +static int bnx2x_mc_assert(struct bnx2x *bp) +{ + int i, j; + int rc = 0; + char last_idx; + const char storm[] = {"XTCU"}; + const u32 intmem_base[] = { + BAR_XSTRORM_INTMEM, + BAR_TSTRORM_INTMEM, + BAR_CSTRORM_INTMEM, + BAR_USTRORM_INTMEM + }; + + /* Go through all instances of all SEMIs */ + for (i = 0; i < 4; i++) { + last_idx = REG_RD8(bp, XSTORM_ASSERT_LIST_INDEX_OFFSET + + intmem_base[i]); + BNX2X_ERR("DATA %cSTORM_ASSERT_LIST_INDEX 0x%x\n", + storm[i], last_idx); + + /* print the asserts */ + for (j = 0; j < STROM_ASSERT_ARRAY_SIZE; j++) { + u32 row0, row1, row2, row3; + + row0 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + + intmem_base[i]); + row1 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 4 + + intmem_base[i]); + row2 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 8 + + intmem_base[i]); + row3 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 12 + + intmem_base[i]); + + if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { + BNX2X_ERR("DATA %cSTORM_ASSERT_INDEX 0x%x =" + " 0x%08x 0x%08x 0x%08x 0x%08x\n", + storm[i], j, row3, row2, row1, row0); + rc++; + } else { + break; + } + } + } + return rc; +} +static void bnx2x_fw_dump(struct bnx2x *bp) +{ + u32 mark, offset; + u32 data[9]; + int word; + + mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104); + printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n", mark); + + for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) { + for (word = 0; word < 8; word++) + data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH + + offset + 4*word)); + data[8] = 0x0; + printk(KERN_ERR PFX "%s", (char *)data); + } + for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) { + for (word = 0; word < 8; word++) + data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH + + offset + 4*word)); + data[8] = 0x0; + printk(KERN_ERR PFX "%s", (char *)data); + } + printk("\n" KERN_ERR PFX "end of fw dump\n"); +} + +static void bnx2x_panic_dump(struct bnx2x *bp) +{ + int i; + u16 j, start, end; + + BNX2X_ERR("begin crash dump -----------------\n"); + + for_each_queue(bp, i) { + struct bnx2x_fastpath *fp = &bp->fp[i]; + struct eth_tx_db_data *hw_prods = fp->hw_tx_prods; + + BNX2X_ERR("queue[%d]: tx_pkt_prod(%x) tx_pkt_cons(%x)" + " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)" + " *rx_cons_sb(%x) rx_comp_prod(%x)" + " rx_comp_cons(%x) fp_c_idx(%x) fp_u_idx(%x)" + " bd data(%x,%x)\n", + i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod, + fp->tx_bd_cons, *fp->tx_cons_sb, *fp->rx_cons_sb, + fp->rx_comp_prod, fp->rx_comp_cons, fp->fp_c_idx, + fp->fp_u_idx, hw_prods->packets_prod, + hw_prods->bds_prod); + + start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10); + end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245); + for (j = start; j < end; j++) { + struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j]; + + BNX2X_ERR("packet[%x]=[%p,%x]\n", j, + sw_bd->skb, sw_bd->first_bd); + } + + start = TX_BD(fp->tx_bd_cons - 10); + end = TX_BD(fp->tx_bd_cons + 254); + for (j = start; j < end; j++) { + u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j]; + + BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n", + j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]); + } + + start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); + end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); + for (j = start; j < end; j++) { + u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; + struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; + + BNX2X_ERR("rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", + j, rx_bd[0], rx_bd[1], sw_bd->skb); + } + + start = RCQ_BD(fp->rx_comp_cons - 10); + end = RCQ_BD(fp->rx_comp_cons + 503); + for (j = start; j < end; j++) { + u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; + + BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n", + j, cqe[0], cqe[1], cqe[2], cqe[3]); + } + } + + BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_t_idx(%u)" + " def_x_idx(%u) def_att_idx(%u) attn_state(%u)" + " spq_prod_idx(%u)\n", + bp->def_c_idx, bp->def_u_idx, bp->def_t_idx, bp->def_x_idx, + bp->def_att_idx, bp->attn_state, bp->spq_prod_idx); + + + bnx2x_mc_assert(bp); + BNX2X_ERR("end crash dump -----------------\n"); + + bp->stats_state = STATS_STATE_DISABLE; + DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n"); +} + +static void bnx2x_enable_int(struct bnx2x *bp) +{ + int port = bp->port; + u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; + u32 val = REG_RD(bp, addr); + int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; + + if (msix) { + val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0; + val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | + HC_CONFIG_0_REG_ATTN_BIT_EN_0); + } else { + val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | + HC_CONFIG_0_REG_INT_LINE_EN_0 | + HC_CONFIG_0_REG_ATTN_BIT_EN_0); + val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; + } + + DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) msi %d\n", + val, port, addr, msix); + + REG_WR(bp, addr, val); +} + +static void bnx2x_disable_int(struct bnx2x *bp) +{ + int port = bp->port; + u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; + u32 val = REG_RD(bp, addr); + + val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | + HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | + HC_CONFIG_0_REG_INT_LINE_EN_0 | + HC_CONFIG_0_REG_ATTN_BIT_EN_0); + + DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", + val, port, addr); + + REG_WR(bp, addr, val); + if (REG_RD(bp, addr) != val) + BNX2X_ERR("BUG! proper val not read from IGU!\n"); +} + +static void bnx2x_disable_int_sync(struct bnx2x *bp) +{ + + int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; + int i; + + atomic_inc(&bp->intr_sem); + /* prevent the HW from sending interrupts*/ + bnx2x_disable_int(bp); + + /* make sure all ISRs are done */ + if (msix) { + for_each_queue(bp, i) + synchronize_irq(bp->msix_table[i].vector); + + /* one more for the Slow Path IRQ */ + synchronize_irq(bp->msix_table[i].vector); + } else + synchronize_irq(bp->pdev->irq); + + /* make sure sp_task is not running */ + cancel_work_sync(&bp->sp_task); + +} + +/* fast path code */ + +/* + * general service functions + */ + +static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 id, + u8 storm, u16 index, u8 op, u8 update) +{ + u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_PORT_BASE * bp->port) * 8; + struct igu_ack_register igu_ack; + + igu_ack.status_block_index = index; + igu_ack.sb_id_and_flags = + ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | + (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | + (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | + (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); + +/* DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", + (*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr); */ + REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack)); +} + +static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) +{ + struct host_status_block *fpsb = fp->status_blk; + u16 rc = 0; + + barrier(); /* status block is written to by the chip */ + if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) { + fp->fp_c_idx = fpsb->c_status_block.status_block_index; + rc |= 1; + } + if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) { + fp->fp_u_idx = fpsb->u_status_block.status_block_index; + rc |= 2; + } + return rc; +} + +static inline int bnx2x_has_work(struct bnx2x_fastpath *fp) +{ + u16 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); + + if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) + rx_cons_sb++; + + if ((rx_cons_sb != fp->rx_comp_cons) || + (le16_to_cpu(*fp->tx_cons_sb) != fp->tx_pkt_cons)) + return 1; + + return 0; +} + +static u16 bnx2x_ack_int(struct bnx2x *bp) +{ + u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_PORT_BASE * bp->port) * 8; + u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr); + +/* DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", + result, BAR_IGU_INTMEM + igu_addr); */ + +#ifdef IGU_DEBUG +#warning IGU_DEBUG active + if (result == 0) { + BNX2X_ERR("read %x from IGU\n", result); + REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0); + } +#endif + return result; +} + + +/* + * fast path service functions + */ + +/* free skb in the packet ring at pos idx + * return idx of last bd freed + */ +static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp, + u16 idx) +{ + struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx]; + struct eth_tx_bd *tx_bd; + struct sk_buff *skb = tx_buf->skb; + u16 bd_idx = tx_buf->first_bd; + int nbd; + + DP(BNX2X_MSG_OFF, "pkt_idx %d buff @(%p)->skb %p\n", + idx, tx_buf, skb); + + /* unmap first bd */ + DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx); + tx_bd = &fp->tx_desc_ring[bd_idx]; + pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd), + BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE); + + nbd = le16_to_cpu(tx_bd->nbd) - 1; +#ifdef BNX2X_STOP_ON_ERROR + if (nbd > (MAX_SKB_FRAGS + 2)) { + BNX2X_ERR("bad nbd!\n"); + bnx2x_panic(); + } +#endif + + /* Skip a parse bd and the TSO split header bd + since they have no mapping */ + if (nbd) + bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); + + if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM | + ETH_TX_BD_FLAGS_TCP_CSUM | + ETH_TX_BD_FLAGS_SW_LSO)) { + if (--nbd) + bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); + tx_bd = &fp->tx_desc_ring[bd_idx]; + /* is this a TSO split header bd? */ + if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) { + if (--nbd) + bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); + } + } + + /* now free frags */ + while (nbd > 0) { + + DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx); + tx_bd = &fp->tx_desc_ring[bd_idx]; + pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd), + BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE); + if (--nbd) + bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); + } + + /* release skb */ + BUG_TRAP(skb); + dev_kfree_skb(skb); + tx_buf->first_bd = 0; + tx_buf->skb = NULL; + + return bd_idx; +} + +static inline u32 bnx2x_tx_avail(struct bnx2x_fastpath *fp) +{ + u16 used; + u32 prod; + u32 cons; + + /* Tell compiler that prod and cons can change */ + barrier(); + prod = fp->tx_bd_prod; + cons = fp->tx_bd_cons; + + used = (NUM_TX_BD - NUM_TX_RINGS + prod - cons + + (cons / TX_DESC_CNT) - (prod / TX_DESC_CNT)); + + if (prod >= cons) { + /* used = prod - cons - prod/size + cons/size */ + used -= NUM_TX_BD - NUM_TX_RINGS; + } + + BUG_TRAP(used <= fp->bp->tx_ring_size); + BUG_TRAP((fp->bp->tx_ring_size - used) <= MAX_TX_AVAIL); + + return (fp->bp->tx_ring_size - used); +} + +static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work) +{ + struct bnx2x *bp = fp->bp; + u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons; + int done = 0; + +#ifdef BNX2X_STOP_ON_ERROR + if (unlikely(bp->panic)) + return; +#endif + + hw_cons = le16_to_cpu(*fp->tx_cons_sb); + sw_cons = fp->tx_pkt_cons; + + while (sw_cons != hw_cons) { + u16 pkt_cons; + + pkt_cons = TX_BD(sw_cons); + + /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */ + + DP(NETIF_MSG_TX_DONE, "hw_cons %u sw_cons %u pkt_cons %d\n", + hw_cons, sw_cons, pkt_cons); + +/* if (NEXT_TX_IDX(sw_cons) != hw_cons) { + rmb(); + prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb); + } +*/ + bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons); + sw_cons++; + done++; + + if (done == work) + break; + } + + fp->tx_pkt_cons = sw_cons; + fp->tx_bd_cons = bd_cons; + + /* Need to make the tx_cons update visible to start_xmit() + * before checking for netif_queue_stopped(). Without the + * memory barrier, there is a small possibility that start_xmit() + * will miss it and cause the queue to be stopped forever. + */ + smp_mb(); + + /* TBD need a thresh? */ + if (unlikely(netif_queue_stopped(bp->dev))) { + + netif_tx_lock(bp->dev); + + if (netif_queue_stopped(bp->dev) && + (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)) + netif_wake_queue(bp->dev); + + netif_tx_unlock(bp->dev); + + } +} + +static void bnx2x_sp_event(struct bnx2x_fastpath *fp, + union eth_rx_cqe *rr_cqe) +{ + struct bnx2x *bp = fp->bp; + int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); + int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); + + DP(NETIF_MSG_RX_STATUS, + "fp %d cid %d got ramrod #%d state is %x type is %d\n", + fp->index, cid, command, bp->state, rr_cqe->ramrod_cqe.type); + + bp->spq_left++; + + if (fp->index) { + switch (command | fp->state) { + case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | + BNX2X_FP_STATE_OPENING): + DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", + cid); + fp->state = BNX2X_FP_STATE_OPEN; + break; + + case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING): + DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", + cid); + fp->state = BNX2X_FP_STATE_HALTED; + break; + + default: + BNX2X_ERR("unexpected MC reply(%d) state is %x\n", + command, fp->state); + } + mb(); /* force bnx2x_wait_ramrod to see the change */ + return; + } + switch (command | bp->state) { + case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT): + DP(NETIF_MSG_IFUP, "got setup ramrod\n"); + bp->state = BNX2X_STATE_OPEN; + break; + + case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT): + DP(NETIF_MSG_IFDOWN, "got halt ramrod\n"); + bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE; + fp->state = BNX2X_FP_STATE_HALTED; + break; + + case (RAMROD_CMD_ID_ETH_PORT_DEL | BNX2X_STATE_CLOSING_WAIT4_DELETE): + DP(NETIF_MSG_IFDOWN, "got delete ramrod\n"); + bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD; + break; + + case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT): + DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid); + bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_DELETED; + break; + + case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN): + DP(NETIF_MSG_IFUP, "got set mac ramrod\n"); + break; + + default: + BNX2X_ERR("unexpected ramrod (%d) state is %x\n", + command, bp->state); + } + + mb(); /* force bnx2x_wait_ramrod to see the change */ +} + +static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp, + struct bnx2x_fastpath *fp, u16 index) +{ + struct sk_buff *skb; + struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index]; + struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index]; + dma_addr_t mapping; + + skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size); + if (unlikely(skb == NULL)) + return -ENOMEM; + + mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size, + PCI_DMA_FROMDEVICE); + if (unlikely(dma_mapping_error(mapping))) { + + dev_kfree_skb(skb); + return -ENOMEM; + } + + rx_buf->skb = skb; + pci_unmap_addr_set(rx_buf, mapping, mapping); + + rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); + rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); + + return 0; +} + +/* note that we are not allocating a new skb, + * we are just moving one from cons to prod + * we are not creating a new mapping, + * so there is no need to check for dma_mapping_error(). + */ +static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp, + struct sk_buff *skb, u16 cons, u16 prod) +{ + struct bnx2x *bp = fp->bp; + struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; + struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; + struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; + struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; + + pci_dma_sync_single_for_device(bp->pdev, + pci_unmap_addr(cons_rx_buf, mapping), + bp->rx_offset + RX_COPY_THRESH, + PCI_DMA_FROMDEVICE); + + prod_rx_buf->skb = cons_rx_buf->skb; + pci_unmap_addr_set(prod_rx_buf, mapping, + pci_unmap_addr(cons_rx_buf, mapping)); + *prod_bd = *cons_bd; +} + +static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget) +{ + struct bnx2x *bp = fp->bp; + u16 bd_cons, bd_prod, comp_ring_cons; + u16 hw_comp_cons, sw_comp_cons, sw_comp_prod; + int rx_pkt = 0; + +#ifdef BNX2X_STOP_ON_ERROR + if (unlikely(bp->panic)) + return 0; +#endif + + hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb); + if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) + hw_comp_cons++; + + bd_cons = fp->rx_bd_cons; + bd_prod = fp->rx_bd_prod; + sw_comp_cons = fp->rx_comp_cons; + sw_comp_prod = fp->rx_comp_prod; + + /* Memory barrier necessary as speculative reads of the rx + * buffer can be ahead of the index in the status block + */ + rmb(); + + DP(NETIF_MSG_RX_STATUS, + "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n", + fp->index, hw_comp_cons, sw_comp_cons); + + while (sw_comp_cons != hw_comp_cons) { + unsigned int len, pad; + struct sw_rx_bd *rx_buf; + struct sk_buff *skb; + union eth_rx_cqe *cqe; + + comp_ring_cons = RCQ_BD(sw_comp_cons); + bd_prod = RX_BD(bd_prod); + bd_cons = RX_BD(bd_cons); + + cqe = &fp->rx_comp_ring[comp_ring_cons]; + + DP(NETIF_MSG_RX_STATUS, "hw_comp_cons %u sw_comp_cons %u" + " comp_ring (%u) bd_ring (%u,%u)\n", + hw_comp_cons, sw_comp_cons, + comp_ring_cons, bd_prod, bd_cons); + DP(NETIF_MSG_RX_STATUS, "CQE type %x err %x status %x" + " queue %x vlan %x len %x\n", + cqe->fast_path_cqe.type, + cqe->fast_path_cqe.error_type_flags, + cqe->fast_path_cqe.status_flags, + cqe->fast_path_cqe.rss_hash_result, + cqe->fast_path_cqe.vlan_tag, cqe->fast_path_cqe.pkt_len); + + /* is this a slowpath msg? */ + if (unlikely(cqe->fast_path_cqe.type)) { + bnx2x_sp_event(fp, cqe); + goto next_cqe; + + /* this is an rx packet */ + } else { + rx_buf = &fp->rx_buf_ring[bd_cons]; + skb = rx_buf->skb; + + len = le16_to_cpu(cqe->fast_path_cqe.pkt_len); + pad = cqe->fast_path_cqe.placement_offset; + + pci_dma_sync_single_for_device(bp->pdev, + pci_unmap_addr(rx_buf, mapping), + pad + RX_COPY_THRESH, + PCI_DMA_FROMDEVICE); + prefetch(skb); + prefetch(((char *)(skb)) + 128); + + /* is this an error packet? */ + if (unlikely(cqe->fast_path_cqe.error_type_flags & + ETH_RX_ERROR_FALGS)) { + /* do we sometimes forward error packets anyway? */ + DP(NETIF_MSG_RX_ERR, + "ERROR flags(%u) Rx packet(%u)\n", + cqe->fast_path_cqe.error_type_flags, + sw_comp_cons); + /* TBD make sure MC counts this as a drop */ + goto reuse_rx; + } + + /* Since we don't have a jumbo ring + * copy small packets if mtu > 1500 + */ + if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) && + (len <= RX_COPY_THRESH)) { + struct sk_buff *new_skb; + + new_skb = netdev_alloc_skb(bp->dev, + len + pad); + if (new_skb == NULL) { + DP(NETIF_MSG_RX_ERR, + "ERROR packet dropped " + "because of alloc failure\n"); + /* TBD count this as a drop? */ + goto reuse_rx; + } + + /* aligned copy */ + skb_copy_from_linear_data_offset(skb, pad, + new_skb->data + pad, len); + skb_reserve(new_skb, pad); + skb_put(new_skb, len); + + bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod); + + skb = new_skb; + + } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) { + pci_unmap_single(bp->pdev, + pci_unmap_addr(rx_buf, mapping), + bp->rx_buf_use_size, + PCI_DMA_FROMDEVICE); + skb_reserve(skb, pad); + skb_put(skb, len); + + } else { + DP(NETIF_MSG_RX_ERR, + "ERROR packet dropped because " + "of alloc failure\n"); +reuse_rx: + bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod); + goto next_rx; + } + + skb->protocol = eth_type_trans(skb, bp->dev); + + skb->ip_summed = CHECKSUM_NONE; + if (bp->rx_csum && BNX2X_RX_SUM_OK(cqe)) + skb->ip_summed = CHECKSUM_UNNECESSARY; + + /* TBD do we pass bad csum packets in promisc */ + } + +#ifdef BCM_VLAN + if ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) + & PARSING_FLAGS_NUMBER_OF_NESTED_VLANS) + && (bp->vlgrp != NULL)) + vlan_hwaccel_receive_skb(skb, bp->vlgrp, + le16_to_cpu(cqe->fast_path_cqe.vlan_tag)); + else +#endif + netif_receive_skb(skb); + + bp->dev->last_rx = jiffies; + +next_rx: + rx_buf->skb = NULL; + + bd_cons = NEXT_RX_IDX(bd_cons); + bd_prod = NEXT_RX_IDX(bd_prod); +next_cqe: + sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod); + sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons); + rx_pkt++; + + if ((rx_pkt == budget)) + break; + } /* while */ + + fp->rx_bd_cons = bd_cons; + fp->rx_bd_prod = bd_prod; + fp->rx_comp_cons = sw_comp_cons; + fp->rx_comp_prod = sw_comp_prod; + + REG_WR(bp, BAR_TSTRORM_INTMEM + + TSTORM_RCQ_PROD_OFFSET(bp->port, fp->index), sw_comp_prod); + + mmiowb(); /* keep prod updates ordered */ + + fp->rx_pkt += rx_pkt; + fp->rx_calls++; + + return rx_pkt; +} + +static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie) +{ + struct bnx2x_fastpath *fp = fp_cookie; + struct bnx2x *bp = fp->bp; + struct net_device *dev = bp->dev; + int index = fp->index; + + DP(NETIF_MSG_INTR, "got an msix interrupt on [%d]\n", index); + bnx2x_ack_sb(bp, index, USTORM_ID, 0, IGU_INT_DISABLE, 0); + +#ifdef BNX2X_STOP_ON_ERROR + if (unlikely(bp->panic)) + return IRQ_HANDLED; +#endif + + prefetch(fp->rx_cons_sb); + prefetch(fp->tx_cons_sb); + prefetch(&fp->status_blk->c_status_block.status_block_index); + prefetch(&fp->status_blk->u_status_block.status_block_index); + + netif_rx_schedule(dev, &bnx2x_fp(bp, index, napi)); + return IRQ_HANDLED; +} + +static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) +{ + struct net_device *dev = dev_instance; + struct bnx2x *bp = netdev_priv(dev); + u16 status = bnx2x_ack_int(bp); + + if (unlikely(status == 0)) { + DP(NETIF_MSG_INTR, "not our interrupt!\n"); + return IRQ_NONE; + } + + DP(NETIF_MSG_INTR, "got an interrupt status is %u\n", status); + +#ifdef BNX2X_STOP_ON_ERROR + if (unlikely(bp->panic)) + return IRQ_HANDLED; +#endif + + /* Return here if interrupt is shared and is disabled */ + if (unlikely(atomic_read(&bp->intr_sem) != 0)) { + DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n"); + return IRQ_HANDLED; + } + + if (status & 0x2) { + struct bnx2x_fastpath *fp = &bp->fp[0]; + + prefetch(fp->rx_cons_sb); + prefetch(fp->tx_cons_sb); + prefetch(&fp->status_blk->c_status_block.status_block_index); + prefetch(&fp->status_blk->u_status_block.status_block_index); + + netif_rx_schedule(dev, &bnx2x_fp(bp, 0, napi)); + + status &= ~0x2; + if (!status) + return IRQ_HANDLED; + } + + if (unlikely(status & 0x1)) { + + schedule_work(&bp->sp_task); + + status &= ~0x1; + if (!status) + return IRQ_HANDLED; + } + + DP(NETIF_MSG_INTR, "got an unknown interrupt! (status is %u)\n", + status); + + return IRQ_HANDLED; +} + +/* end of fast path */ + +/* PHY/MAC */ + +/* + * General service functions + */ + +static void bnx2x_leds_set(struct bnx2x *bp, unsigned int speed) +{ + int port = bp->port; + + NIG_WR(NIG_REG_LED_MODE_P0 + port*4, + ((bp->hw_config & SHARED_HW_CFG_LED_MODE_MASK) >> + SHARED_HW_CFG_LED_MODE_SHIFT)); + NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); + + /* Set blinking rate to ~15.9Hz */ + NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, + LED_BLINK_RATE_VAL); + NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port*4, 1); + + /* On Ax chip versions for speeds less than 10G + LED scheme is different */ + if ((CHIP_REV(bp) == CHIP_REV_Ax) && (speed < SPEED_10000)) { + NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 1); + NIG_WR(NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4, 0); + NIG_WR(NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + port*4, 1); + } +} + +static void bnx2x_leds_unset(struct bnx2x *bp) +{ + int port = bp->port; + + NIG_WR(NIG_REG_LED_10G_P0 + port*4, 0); + NIG_WR(NIG_REG_LED_MODE_P0 + port*4, SHARED_HW_CFG_LED_MAC1); +} + +static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) +{ + u32 val = REG_RD(bp, reg); + + val |= bits; + REG_WR(bp, reg, val); + return val; +} + +static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) +{ + u32 val = REG_RD(bp, reg); + + val &= ~bits; + REG_WR(bp, reg, val); + return val; +} + +static int bnx2x_ |