diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/atombios.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios.h | 4785 |
1 files changed, 4785 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h new file mode 100644 index 00000000000..cf67928abbc --- /dev/null +++ b/drivers/gpu/drm/radeon/atombios.h @@ -0,0 +1,4785 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************/ +/*Portion I: Definitions shared between VBIOS and Driver */ +/****************************************************************************/ + +#ifndef _ATOMBIOS_H +#define _ATOMBIOS_H + +#define ATOM_VERSION_MAJOR 0x00020000 +#define ATOM_VERSION_MINOR 0x00000002 + +#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) + +/* Endianness should be specified before inclusion, + * default to little endian + */ +#ifndef ATOM_BIG_ENDIAN +#error Endian not specified +#endif + +#ifdef _H2INC +#ifndef ULONG +typedef unsigned long ULONG; +#endif + +#ifndef UCHAR +typedef unsigned char UCHAR; +#endif + +#ifndef USHORT +typedef unsigned short USHORT; +#endif +#endif + +#define ATOM_DAC_A 0 +#define ATOM_DAC_B 1 +#define ATOM_EXT_DAC 2 + +#define ATOM_CRTC1 0 +#define ATOM_CRTC2 1 + +#define ATOM_DIGA 0 +#define ATOM_DIGB 1 + +#define ATOM_PPLL1 0 +#define ATOM_PPLL2 1 + +#define ATOM_SCALER1 0 +#define ATOM_SCALER2 1 + +#define ATOM_SCALER_DISABLE 0 +#define ATOM_SCALER_CENTER 1 +#define ATOM_SCALER_EXPANSION 2 +#define ATOM_SCALER_MULTI_EX 3 + +#define ATOM_DISABLE 0 +#define ATOM_ENABLE 1 +#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) +#define ATOM_LCD_BLON (ATOM_ENABLE+2) +#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) +#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) +#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) +#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) + +#define ATOM_BLANKING 1 +#define ATOM_BLANKING_OFF 0 + +#define ATOM_CURSOR1 0 +#define ATOM_CURSOR2 1 + +#define ATOM_ICON1 0 +#define ATOM_ICON2 1 + +#define ATOM_CRT1 0 +#define ATOM_CRT2 1 + +#define ATOM_TV_NTSC 1 +#define ATOM_TV_NTSCJ 2 +#define ATOM_TV_PAL 3 +#define ATOM_TV_PALM 4 +#define ATOM_TV_PALCN 5 +#define ATOM_TV_PALN 6 +#define ATOM_TV_PAL60 7 +#define ATOM_TV_SECAM 8 +#define ATOM_TV_CV 16 + +#define ATOM_DAC1_PS2 1 +#define ATOM_DAC1_CV 2 +#define ATOM_DAC1_NTSC 3 +#define ATOM_DAC1_PAL 4 + +#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 +#define ATOM_DAC2_CV ATOM_DAC1_CV +#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC +#define ATOM_DAC2_PAL ATOM_DAC1_PAL + +#define ATOM_PM_ON 0 +#define ATOM_PM_STANDBY 1 +#define ATOM_PM_SUSPEND 2 +#define ATOM_PM_OFF 3 + +/* Bit0:{=0:single, =1:dual}, + Bit1 {=0:666RGB, =1:888RGB}, + Bit2:3:{Grey level} + Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ + +#define ATOM_PANEL_MISC_DUAL 0x00000001 +#define ATOM_PANEL_MISC_888RGB 0x00000002 +#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C +#define ATOM_PANEL_MISC_FPDI 0x00000010 +#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 +#define ATOM_PANEL_MISC_SPATIAL 0x00000020 +#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 +#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 + +#define MEMTYPE_DDR1 "DDR1" +#define MEMTYPE_DDR2 "DDR2" +#define MEMTYPE_DDR3 "DDR3" +#define MEMTYPE_DDR4 "DDR4" + +#define ASIC_BUS_TYPE_PCI "PCI" +#define ASIC_BUS_TYPE_AGP "AGP" +#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" + +/* Maximum size of that FireGL flag string */ + +#define ATOM_FIREGL_FLAG_STRING "FGL" /* Flag used to enable FireGL Support */ +#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 /* sizeof( ATOM_FIREGL_FLAG_STRING ) */ + +#define ATOM_FAKE_DESKTOP_STRING "DSK" /* Flag used to enable mobile ASIC on Desktop */ +#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING + +#define ATOM_M54T_FLAG_STRING "M54T" /* Flag used to enable M54T Support */ +#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 /* sizeof( ATOM_M54T_FLAG_STRING ) */ + +#define HW_ASSISTED_I2C_STATUS_FAILURE 2 +#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 + +#pragma pack(1) /* BIOS data must use byte aligment */ + +/* Define offset to location of ROM header. */ + +#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L +#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L + +#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 +#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ +#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f +#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e + +/* Common header for all ROM Data tables. + Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. + And the pointer actually points to this header. */ + +typedef struct _ATOM_COMMON_TABLE_HEADER { + USHORT usStructureSize; + UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ + UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ + /*Image can't be updated, while Driver needs to carry the new table! */ +} ATOM_COMMON_TABLE_HEADER; + +typedef struct _ATOM_ROM_HEADER { + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, + atombios should init it as "ATOM", don't change the position */ + USHORT usBiosRuntimeSegmentAddress; + USHORT usProtectedModeInfoOffset; + USHORT usConfigFilenameOffset; + USHORT usCRC_BlockOffset; + USHORT usBIOS_BootupMessageOffset; + USHORT usInt10Offset; + USHORT usPciBusDevInitCode; + USHORT usIoBaseAddress; + USHORT usSubsystemVendorID; + USHORT usSubsystemID; + USHORT usPCI_InfoOffset; + USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ + USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ + UCHAR ucExtendedFunctionCode; + UCHAR ucReserved; +} ATOM_ROM_HEADER; + +/*==============================Command Table Portion==================================== */ + +#ifdef UEFI_BUILD +#define UTEMP USHORT +#define USHORT void* +#endif + +typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES { + USHORT ASIC_Init; /* Function Table, used by various SW components,latest version 1.1 */ + USHORT GetDisplaySurfaceSize; /* Atomic Table, Used by Bios when enabling HW ICON */ + USHORT ASIC_RegistersInit; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ + USHORT VRAM_BlockVenderDetection; /* Atomic Table, used only by Bios */ + USHORT DIGxEncoderControl; /* Only used by Bios */ + USHORT MemoryControllerInit; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ + USHORT EnableCRTCMemReq; /* Function Table,directly used by various SW components,latest version 2.1 */ + USHORT MemoryParamAdjust; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed */ + USHORT DVOEncoderControl; /* Function Table,directly used by various SW components,latest version 1.2 */ + USHORT GPIOPinControl; /* Atomic Table, only used by Bios */ + USHORT SetEngineClock; /*Function Table,directly used by various SW components,latest version 1.1 */ + USHORT SetMemoryClock; /* Function Table,directly used by various SW components,latest version 1.1 */ + USHORT SetPixelClock; /*Function Table,directly used by various SW components,latest version 1.2 */ + USHORT DynamicClockGating; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ + USHORT ResetMemoryDLL; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ + USHORT ResetMemoryDevice; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ + USHORT MemoryPLLInit; + USHORT AdjustDisplayPll; /* only used by Bios */ + USHORT AdjustMemoryController; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ + USHORT EnableASIC_StaticPwrMgt; /* Atomic Table, only used by Bios */ + USHORT ASIC_StaticPwrMgtStatusChange; /* Obsolete, only used by Bios */ + USHORT DAC_LoadDetection; /* Atomic Table, directly used by various SW components,latest version 1.2 */ + USHORT LVTMAEncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.3 */ + USHORT LCD1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT DAC1EncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT DAC2EncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT DVOOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT CV1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT GetConditionalGoldenSetting; /* only used by Bios */ + USHORT TVEncoderControl; /* Function Table,directly used by various SW components,latest version 1.1 */ + USHORT TMDSAEncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.3 */ + USHORT LVDSEncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.3 */ + USHORT TV1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT EnableScaler; /* Atomic Table, used only by Bios */ + USHORT BlankCRTC; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT EnableCRTC; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT GetPixelClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT EnableVGA_Render; /* Function Table,directly used by various SW components,latest version 1.1 */ + USHORT EnableVGA_Access; /* Obsolete , only used by Bios */ + USHORT SetCRTC_Timing; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT SetCRTC_OverScan; /* Atomic Table, used by various SW components,latest version 1.1 */ + USHORT SetCRTC_Replication; /* Atomic Table, used only by Bios */ + USHORT SelectCRTC_Source; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT EnableGraphSurfaces; /* Atomic Table, used only by Bios */ + USHORT UpdateCRTC_DoubleBufferRegisters; + USHORT LUT_AutoFill; /* Atomic Table, only used by Bios */ + USHORT EnableHW_IconCursor; /* Atomic Table, only used by Bios */ + USHORT GetMemoryClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT GetEngineClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT SetCRTC_UsingDTDTiming; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT ExternalEncoderControl; /* Atomic Table, directly used by various SW components,latest version 2.1 */ + USHORT LVTMAOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT VRAM_BlockDetectionByStrap; /* Atomic Table, used only by Bios */ + USHORT MemoryCleanUp; /* Atomic Table, only used by Bios */ + USHORT ProcessI2cChannelTransaction; /* Function Table,only used by Bios */ + USHORT WriteOneByteToHWAssistedI2C; /* Function Table,indirectly used by various SW components */ + USHORT ReadHWAssistedI2CStatus; /* Atomic Table, indirectly used by various SW components */ + USHORT SpeedFanControl; /* Function Table,indirectly used by various SW components,called from ASIC_Init */ + USHORT PowerConnectorDetection; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT MC_Synchronization; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ + USHORT ComputeMemoryEnginePLL; /* Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock */ + USHORT MemoryRefreshConversion; /* Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock */ + USHORT VRAM_GetCurrentInfoBlock; /* Atomic Table, used only by Bios */ + USHORT DynamicMemorySettings; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ + USHORT MemoryTraining; /* Atomic Table, used only by Bios */ + USHORT EnableSpreadSpectrumOnPPLL; /* Atomic Table, directly used by various SW components,latest version 1.2 */ + USHORT TMDSAOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT SetVoltage; /* Function Table,directly and/or indirectly used by various SW components,latest version 1.1 */ + USHORT DAC1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT DAC2OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ + USHORT SetupHWAssistedI2CStatus; /* Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" */ + USHORT ClockSource; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ + USHORT MemoryDeviceInit; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ + USHORT EnableYUV; /* Atomic Table, indirectly used by various SW components,called from EnableVGARender */ + USHORT DIG1EncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ + USHORT DIG2EncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ + USHORT DIG1TransmitterControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ + USHORT DIG2TransmitterControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ + USHORT ProcessAuxChannelTransaction; /* Function Table,only used by Bios */ + USHORT DPEncoderService; /* Function Table,only used by Bios */ +} ATOM_MASTER_LIST_OF_COMMAND_TABLES; + +/* For backward compatible */ +#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction +#define UNIPHYTransmitterControl DIG1TransmitterControl +#define LVTMATransmitterControl DIG2TransmitterControl +#define SetCRTC_DPM_State GetConditionalGoldenSetting +#define SetUniphyInstance ASIC_StaticPwrMgtStatusChange + +typedef struct _ATOM_MASTER_COMMAND_TABLE { + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; +} ATOM_MASTER_COMMAND_TABLE; + +/****************************************************************************/ +/* Structures used in every command table */ +/****************************************************************************/ +typedef struct _ATOM_TABLE_ATTRIBUTE { +#if ATOM_BIG_ENDIAN + USHORT UpdatedByUtility:1; /* [15]=Table updated by utility flag */ + USHORT PS_SizeInBytes:7; /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */ + USHORT WS_SizeInBytes:8; /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */ +#else + USHORT WS_SizeInBytes:8; /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */ + USHORT PS_SizeInBytes:7; /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */ + USHORT UpdatedByUtility:1; /* [15]=Table updated by utility flag */ +#endif +} ATOM_TABLE_ATTRIBUTE; + +typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS { + ATOM_TABLE_ATTRIBUTE sbfAccess; + USHORT susAccess; +} ATOM_TABLE_ATTRIBUTE_ACCESS; + +/****************************************************************************/ +/* Common header for all command tables. */ +/* Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. */ +/* And the pointer actually points to this header. */ +/****************************************************************************/ +typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER { + ATOM_COMMON_TABLE_HEADER CommonHeader; + ATOM_TABLE_ATTRIBUTE TableAttribute; +} ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; + +/****************************************************************************/ +/* Structures used by ComputeMemoryEnginePLLTable */ +/****************************************************************************/ +#define COMPUTE_MEMORY_PLL_PARAM 1 +#define COMPUTE_ENGINE_PLL_PARAM 2 + +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS { + ULONG ulClock; /* When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div */ + UCHAR ucAction; /* 0:reserved //1:Memory //2:Engine */ + UCHAR ucReserved; /* may expand to return larger Fbdiv later */ + UCHAR ucFbDiv; /* return value */ + UCHAR ucPostDiv; /* return value */ +} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; + +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 { + ULONG ulClock; /* When return, [23:0] return real clock */ + UCHAR ucAction; /* 0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register */ + USHORT usFbDiv; /* return Feedback value to be written to register */ + UCHAR ucPostDiv; /* return post div to be written to register */ +} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; +#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS + +#define SET_CLOCK_FREQ_MASK 0x00FFFFFF /* Clock change tables only take bit [23:0] as the requested clock value */ +#define USE_NON_BUS_CLOCK_MASK 0x01000000 /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */ +#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */ +#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */ +#define FIRST_TIME_CHANGE_CLOCK 0x08000000 /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */ +#define SKIP_SW_PROGRAM_PLL 0x10000000 /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */ +#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK + +#define b3USE_NON_BUS_CLOCK_MASK 0x01 /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */ +#define b3USE_MEMORY_SELF_REFRESH 0x02 /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */ +#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */ +#define b3FIRST_TIME_CHANGE_CLOCK 0x08 /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */ +#define b3SKIP_SW_PROGRAM_PLL 0x10 /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */ + +typedef struct _ATOM_COMPUTE_CLOCK_FREQ { +#if ATOM_BIG_ENDIAN + ULONG ulComputeClockFlag:8; /* =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */ + ULONG ulClockFreq:24; /* in unit of 10kHz */ +#else + ULONG ulClockFreq:24; /* in unit of 10kHz */ + ULONG ulComputeClockFlag:8; /* =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */ +#endif +} ATOM_COMPUTE_CLOCK_FREQ; + +typedef struct _ATOM_S_MPLL_FB_DIVIDER { + USHORT usFbDivFrac; + USHORT usFbDiv; +} ATOM_S_MPLL_FB_DIVIDER; + +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 { + union { + ATOM_COMPUTE_CLOCK_FREQ ulClock; /* Input Parameter */ + ATOM_S_MPLL_FB_DIVIDER ulFbDiv; /* Output Parameter */ + }; + UCHAR ucRefDiv; /* Output Parameter */ + UCHAR ucPostDiv; /* Output Parameter */ + UCHAR ucCntlFlag; /* Output Parameter */ + UCHAR ucReserved; +} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; + +/* ucCntlFlag */ +#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 +#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 +#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 + +typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER { + ATOM_COMPUTE_CLOCK_FREQ ulClock; + ULONG ulReserved[2]; +} DYNAMICE_MEMORY_SETTINGS_PARAMETER; + +typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER { + ATOM_COMPUTE_CLOCK_FREQ ulClock; + ULONG ulMemoryClock; + ULONG ulReserved; +} DYNAMICE_ENGINE_SETTINGS_PARAMETER; + +/****************************************************************************/ +/* Structures used by SetEngineClockTable */ +/****************************************************************************/ +typedef struct _SET_ENGINE_CLOCK_PARAMETERS { + ULONG ulTargetEngineClock; /* In 10Khz unit */ +} SET_ENGINE_CLOCK_PARAMETERS; + +typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION { + ULONG ulTargetEngineClock; /* In 10Khz unit */ + COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; +} SET_ENGINE_CLOCK_PS_ALLOCATION; + +/****************************************************************************/ +/* Structures used by SetMemoryClockTable */ +/****************************************************************************/ +typedef struct _SET_MEMORY_CLOCK_PARAMETERS { + ULONG ulTargetMemoryClock; /* In 10Khz unit */ +} SET_MEMORY_CLOCK_PARAMETERS; + +typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION { + ULONG ulTargetMemoryClock; /* In 10Khz unit */ + COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; +} SET_MEMORY_CLOCK_PS_ALLOCATION; + +/****************************************************************************/ +/* Structures used by ASIC_Init.ctb */ +/****************************************************************************/ +typedef struct _ASIC_INIT_PARAMETERS { + ULONG ulDefaultEngineClock; /* In 10Khz unit */ + ULONG ulDefaultMemoryClock; /* In 10Khz unit */ +} ASIC_INIT_PARAMETERS; + +typedef struct _ASIC_INIT_PS_ALLOCATION { + ASIC_INIT_PARAMETERS sASICInitClocks; + SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; /* Caller doesn't need to init this structure */ +} ASIC_INIT_PS_ALLOCATION; + +/****************************************************************************/ +/* Structure used by DynamicClockGatingTable.ctb */ +/****************************************************************************/ +typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS { + UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ + UCHAR ucPadding[3]; +} DYNAMIC_CLOCK_GATING_PARAMETERS; +#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS + +/****************************************************************************/ +/* Structure used by EnableASIC_StaticPwrMgtTable.ctb */ +/****************************************************************************/ +typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS { + UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ + UCHAR ucPadding[3]; +} ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; +#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS + +/****************************************************************************/ +/* Structures used by DAC_LoadDetectionTable.ctb */ +/****************************************************************************/ +typedef struct _DAC_LOAD_DETECTION_PARAMETERS { + USHORT usDeviceID; /* {ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} */ + UCHAR ucDacType; /* {ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} */ + UCHAR ucMisc; /* Valid only when table revision =1.3 and above */ +} DAC_LOAD_DETECTION_PARAMETERS; + +/* DAC_LOAD_DETECTION_PARAMETERS.ucMisc */ +#define DAC_LOAD_MISC_YPrPb 0x01 + +typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION { + DAC_LOAD_DETECTION_PARAMETERS sDacload; + ULONG Reserved[2]; /* Don't set this one, allocation for EXT DAC */ +} DAC_LOAD_DETECTION_PS_ALLOCATION; + +/****************************************************************************/ +/* Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb */ +/****************************************************************************/ +typedef struct _DAC_ENCODER_CONTROL_PARAMETERS { + USHORT usPixelClock; /* in 10KHz; for bios convenient */ + UCHAR ucDacStandard; /* See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) */ + UCHAR ucAction; /* 0: turn off encoder */ + /* 1: setup and turn on encoder */ + /* 7: ATOM_ENCODER_INIT Initialize DAC */ +} DAC_ENCODER_CONTROL_PARAMETERS; + +#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS + +/****************************************************************************/ +/* Structures used by DIG1EncoderControlTable */ +/* DIG2EncoderControlTable */ +/* ExternalEncoderControlTable */ +/****************************************************************************/ +typedef struct _DIG_ENCODER_CONTROL_PARAMETERS { + USHORT usPixelClock; /* in 10KHz; for bios convenient */ + UCHAR ucConfig; + /* [2] Link Select: */ + /* =0: PHY linkA if bfLane<3 */ + /* =1: PHY linkB if bfLanes<3 */ + /* =0: PHY linkA+B if bfLanes=3 */ + /* [3] Transmitter Sel */ + /* =0: UNIPHY or PCIEPHY */ + /* =1: LVTMA */ + UCHAR ucAction; /* =0: turn off encoder */ + /* =1: turn on encoder */ + UCHAR ucEncoderMode; + /* =0: DP encoder */ + /* =1: LVDS encoder */ + /* =2: DVI encoder */ + /* =3: HDMI encoder */ + /* =4: SDVO encoder */ + UCHAR ucLaneNum; /* how many lanes to enable */ + UCHAR ucReserved[2]; +} DIG_ENCODER_CONTROL_PARAMETERS; +#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS +#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS + +/* ucConfig */ +#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 +#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 +#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 +#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 +#define ATOM_ENCODER_CONFIG_LINKA 0x00 +#define ATOM_ENCODER_CONFIG_LINKB 0x04 +#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA +#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB +#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 +#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 +#define ATOM_ENCODER_CONFIG_LVTMA 0x08 +#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 +#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 +#define ATOM_ENCODER_CONFIG_DIGB 0x80 /* VBIOS Internal use, outside SW should set this bit=0 */ +/* ucAction */ +/* ATOM_ENABLE: Enable Encoder */ +/* ATOM_DISABLE: Disable Encoder */ + +/* ucEncoderMode */ +#define ATOM_ENCODER_MODE_DP 0 +#define ATOM_ENCODER_MODE_LVDS 1 +#define ATOM_ENCODER_MODE_DVI 2 +#define ATOM_ENCODER_MODE_HDMI 3 +#define ATOM_ENCODER_MODE_SDVO 4 +#define ATOM_ENCODER_MODE_TV 13 +#define ATOM_ENCODER_MODE_CV 14 +#define ATOM_ENCODER_MODE_CRT 15 + +typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 { +#if ATOM_BIG_ENDIAN + UCHAR ucReserved1:2; + UCHAR ucTransmitterSel:2; /* =0: UniphyAB, =1: UniphyCD =2: UniphyEF */ + UCHAR ucLinkSel:1; /* =0: linkA/C/E =1: linkB/D/F */ + UCHAR ucReserved:1; + UCHAR ucDPLinkRate:1; /* =0: 1.62Ghz, =1: 2.7Ghz */ +#else + UCHAR ucDPLinkRate:1; /* =0: 1.62Ghz, =1: 2.7Ghz */ + UCHAR ucReserved:1; + UCHAR ucLinkSel:1; /* =0: linkA/C/E =1: linkB/D/F */ + UCHAR ucTransmitterSel:2; /* =0: UniphyAB, =1: UniphyCD =2: UniphyEF */ + UCHAR ucReserved1:2; +#endif +} ATOM_DIG_ENCODER_CONFIG_V2; + +typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 { + USHORT usPixelClock; /* in 10KHz; for bios convenient */ + ATOM_DIG_ENCODER_CONFIG_V2 acConfig; + UCHAR ucAction; + UCHAR ucEncoderMode; + /* =0: DP encoder */ + /* =1: LVDS encoder */ + /* =2: DVI encoder */ + /* =3: HDMI encoder */ + /* =4: SDVO encoder */ + UCHAR ucLaneNum; /* how many lanes to enable */ + UCHAR ucReserved[2]; +} DIG_ENCODER_CONTROL_PARAMETERS_V2; + +/* ucConfig */ +#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 +#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 +#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 +#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 +#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 +#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 + +/****************************************************************************/ +/* Structures used by UNIPHYTransmitterControlTable */ +/* LVTMATransmitterControlTable */ +/* DVOOutputControlTable */ +/****************************************************************************/ +typedef struct _ATOM_DP_VS_MODE { + UCHAR ucLaneSel; + UCHAR ucLaneSet; +} ATOM_DP_VS_MODE; + +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS { + union { + USHORT usPixelClock; /* in 10KHz; for bios convenient */ + USHORT usInitInfo; /* when init uniphy,lower 8bit is used for connector type defined in objectid.h */ + ATOM_DP_VS_MODE asMode; /* DP Voltage swing mode */ + }; + UCHAR ucConfig; + /* [0]=0: 4 lane Link, */ + /* =1: 8 lane Link ( Dual Links TMDS ) */ + /* [1]=0: InCoherent mode */ + /* =1: Coherent Mode */ + /* [2] Link Select: */ + /* =0: PHY linkA if bfLane<3 */ + /* =1: PHY linkB if bfLanes<3 */ + /* =0: PHY linkA+B if bfLanes=3 */ + /* [5:4]PCIE lane Sel */ + /* =0: lane 0~3 or 0~7 */ + /* =1: lane 4~7 */ + /* =2: lane 8~11 or 8~15 */ + /* =3: lane 12~15 */ + UCHAR ucAction; /* =0: turn off encoder */ + /* =1: turn on encoder */ + UCHAR ucReserved[4]; +} DIG_TRANSMITTER_CONTROL_PARAMETERS; + +#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS + +/* ucInitInfo */ +#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff + +/* ucConfig */ +#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 +#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 +#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 +#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 +#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 +#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 + +#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ +#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ +#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ + +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 +#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 +#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 +#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 +#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 +#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 +#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 +#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 + +/* ucAction */ +#define ATOM_TRANSMITTER_ACTION_DISABLE 0 +#define ATOM_TRANSMITTER_ACTION_ENABLE 1 +#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 +#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 +#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 +#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 +#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 +#define ATOM_TRANSMITTER_ACTION_INIT 7 +#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 +#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 +#define ATOM_TRANSMITTER_ACTION_SETUP 10 +#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 + +/* Following are used for DigTransmitterControlTable ver1.2 */ +typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 { +#if ATOM_BIG_ENDIAN + UCHAR ucTransmitterSel:2; /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */ + /* =1 Dig Transmitter 2 ( Uniphy CD ) */ + /* =2 Dig Transmitter 3 ( Uniphy EF ) */ + UCHAR ucReserved:1; + UCHAR fDPConnector:1; /* bit4=0: DP connector =1: None DP connector */ + UCHAR ucEncoderSel:1; /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */ + UCHAR ucLinkSel:1; /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */ + /* =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */ + + UCHAR fCoherentMode:1; /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */ + UCHAR fDualLinkConnector:1; /* bit0=1: Dual Link DVI connector */ +#else + UCHAR fDualLinkConnector:1; /* bit0=1: Dual Link DVI connector */ + UCHAR fCoherentMode:1; /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */ + UCHAR ucLinkSel:1; /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */ + /* =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */ + UCHAR ucEncoderSel:1; /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */ + UCHAR fDPConnector:1; /* bit4=0: DP connector =1: None DP connector */ + UCHAR ucReserved:1; + UCHAR ucTransmitterSel:2; /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */ + /* =1 Dig Transmitter 2 ( Uniphy CD ) */ + /* =2 Dig Transmitter 3 ( Uniphy EF ) */ +#endif +} ATOM_DIG_TRANSMITTER_CONFIG_V2; + +/* ucConfig */ +/* Bit0 */ +#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 + +/* Bit1 */ +#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 + +/* Bit2 */ +#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 +#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 + +/* Bit3 */ +#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 +#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 /* only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */ +#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 /* only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */ + +/* Bit4 */ +#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 + +/* Bit7:6 */ +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 /* AB */ +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 /* CD */ +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 /* EF */ + +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 { + union { + USHORT usPixelClock; /* in 10KHz; for bios convenient */ + USHORT usInitInfo; /* when init uniphy,lower 8bit is used for connector type defined in objectid.h */ + ATOM_DP_VS_MODE asMode; /* DP Voltage swing mode */ + }; + ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; + UCHAR ucAction; /* define as ATOM_TRANSMITER_ACTION_XXX */ + UCHAR ucReserved[4]; +} DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; + +/****************************************************************************/ +/* Structures used by DAC1OuputControlTable */ +/* DAC2OuputControlTable */ +/* LVTMAOutputControlTable (Before DEC30) */ +/* TMDSAOutputControlTable (Before DEC30) */ +/****************************************************************************/ +typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS { + UCHAR ucAction; /* Possible input:ATOM_ENABLE||ATOMDISABLE */ + /* When the display is LCD, in addition to above: */ + /* ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| */ + /* ATOM_LCD_SELFTEST_STOP */ + + UCHAR aucPadding[3]; /* padding to DWORD aligned */ +} DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; + +#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS + +#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION +#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS + +/****************************************************************************/ +/* Structures used by BlankCRTCTable */ +/****************************************************************************/ +typedef struct _BLANK_CRTC_PARAMETERS { + UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ + UCHAR ucBlanking; /* ATOM_BLANKING or ATOM_BLANKINGOFF */ + USHORT usBlackColorRCr; + USHORT usBlackColorGY; + USHORT usBlackColorBCb; +} BLANK_CRTC_PARAMETERS; +#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS + +/****************************************************************************/ +/* Structures used by EnableCRTCTable */ +/* EnableCRTCMemReqTable */ +/* UpdateCRTC_DoubleBufferRegistersTable */ +/****************************************************************************/ +typedef struct _ENABLE_CRTC_PARAMETERS { + UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ + UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ + UCHAR ucPadding[2]; +} ENABLE_CRTC_PARAMETERS; +#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS + +/****************************************************************************/ +/* Structures used by SetCRTC_OverScanTable */ +/****************************************************************************/ +typedef struct _SET_CRTC_OVERSCAN_PARAMETERS { + USHORT usOverscanRight; /* right */ + USHORT usOverscanLeft; /* left */ + USHORT usOverscanBottom; /* bottom */ + USHORT usOverscanTop; /* top */ + UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ + UCHAR ucPadding[3]; +} SET_CRTC_OVERSCAN_PARAMETERS; +#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS + +/****************************************************************************/ +/* Structures used by SetCRTC_ReplicationTable */ +/****************************************************************************/ +type |