diff options
Diffstat (limited to 'drivers/edac/i5100_edac.c')
| -rw-r--r-- | drivers/edac/i5100_edac.c | 551 |
1 files changed, 410 insertions, 141 deletions
diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c index 22db05a67bf..6247d186177 100644 --- a/drivers/edac/i5100_edac.c +++ b/drivers/edac/i5100_edac.c @@ -9,15 +9,25 @@ * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet * http://download.intel.com/design/chipsets/datashts/318378.pdf * + * The intel 5100 has two independent channels. EDAC core currently + * can not reflect this configuration so instead the chip-select + * rows for each respective channel are laid out one after another, + * the first half belonging to channel 0, the second half belonging + * to channel 1. + * + * This driver is for DDR2 DIMMs, and it uses chip select to select among the + * several ranks. However, instead of showing memories as ranks, it outputs + * them as DIMM's. An internal table creates the association between ranks + * and DIMM's. */ #include <linux/module.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/pci_ids.h> -#include <linux/slab.h> #include <linux/edac.h> #include <linux/delay.h> #include <linux/mmzone.h> +#include <linux/debugfs.h> #include "edac_core.h" @@ -25,6 +35,8 @@ /* device 16, func 1 */ #define I5100_MC 0x40 /* Memory Control Register */ +#define I5100_MC_SCRBEN_MASK (1 << 7) +#define I5100_MC_SCRBDONE_MASK (1 << 4) #define I5100_MS 0x44 /* Memory Status Register */ #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */ #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */ @@ -43,7 +55,7 @@ #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6) #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5) #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4) -#define I5100_FERR_NF_MEM_M1ERR_MASK 1 +#define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1) #define I5100_FERR_NF_MEM_ANY_MASK \ (I5100_FERR_NF_MEM_M16ERR_MASK | \ I5100_FERR_NF_MEM_M15ERR_MASK | \ @@ -57,6 +69,14 @@ I5100_FERR_NF_MEM_M1ERR_MASK) #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */ #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */ +#define I5100_MEM0EINJMSK0 0x200 /* Injection Mask0 Register Channel 0 */ +#define I5100_MEM1EINJMSK0 0x208 /* Injection Mask0 Register Channel 1 */ +#define I5100_MEMXEINJMSK0_EINJEN (1 << 27) +#define I5100_MEM0EINJMSK1 0x204 /* Injection Mask1 Register Channel 0 */ +#define I5100_MEM1EINJMSK1 0x206 /* Injection Mask1 Register Channel 1 */ + +/* Device 19, Function 0 */ +#define I5100_DINJ0 0x9a /* device 21 and 22, func 0 */ #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */ @@ -72,11 +92,21 @@ /* bit field accessors */ +static inline u32 i5100_mc_scrben(u32 mc) +{ + return mc >> 7 & 1; +} + static inline u32 i5100_mc_errdeten(u32 mc) { return mc >> 5 & 1; } +static inline u32 i5100_mc_scrbdone(u32 mc) +{ + return mc >> 4 & 1; +} + static inline u16 i5100_spddata_rdo(u16 a) { return a >> 15 & 1; @@ -265,42 +295,43 @@ static inline u32 i5100_recmemb_ras(u32 a) } /* some generic limits */ -#define I5100_MAX_RANKS_PER_CTLR 6 -#define I5100_MAX_CTLRS 2 +#define I5100_MAX_RANKS_PER_CHAN 6 +#define I5100_CHANNELS 2 #define I5100_MAX_RANKS_PER_DIMM 4 #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */ -#define I5100_MAX_DIMM_SLOTS_PER_CTLR 4 +#define I5100_MAX_DIMM_SLOTS_PER_CHAN 4 #define I5100_MAX_RANK_INTERLEAVE 4 #define I5100_MAX_DMIRS 5 +#define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ) struct i5100_priv { /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */ - int dimm_numrank[I5100_MAX_CTLRS][I5100_MAX_DIMM_SLOTS_PER_CTLR]; + int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN]; /* * mainboard chip select map -- maps i5100 chip selects to * DIMM slot chip selects. In the case of only 4 ranks per - * controller, the mapping is fairly obvious but not unique. - * we map -1 -> NC and assume both controllers use the same + * channel, the mapping is fairly obvious but not unique. + * we map -1 -> NC and assume both channels use the same * map... * */ - int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CTLR][I5100_MAX_RANKS_PER_DIMM]; + int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM]; /* memory interleave range */ struct { u64 limit; unsigned way[2]; - } mir[I5100_MAX_CTLRS]; + } mir[I5100_CHANNELS]; /* adjusted memory interleave range register */ - unsigned amir[I5100_MAX_CTLRS]; + unsigned amir[I5100_CHANNELS]; /* dimm interleave range */ struct { unsigned rank[I5100_MAX_RANK_INTERLEAVE]; u64 limit; - } dmir[I5100_MAX_CTLRS][I5100_MAX_DMIRS]; + } dmir[I5100_CHANNELS][I5100_MAX_DMIRS]; /* memory technology registers... */ struct { @@ -310,30 +341,46 @@ struct i5100_priv { unsigned numbank; /* 2 or 3 lines */ unsigned numrow; /* 13 .. 16 lines */ unsigned numcol; /* 11 .. 12 lines */ - } mtr[I5100_MAX_CTLRS][I5100_MAX_RANKS_PER_CTLR]; + } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; u64 tolm; /* top of low memory in bytes */ - unsigned ranksperctlr; /* number of ranks per controller */ + unsigned ranksperchan; /* number of ranks per channel */ struct pci_dev *mc; /* device 16 func 1 */ + struct pci_dev *einj; /* device 19 func 0 */ struct pci_dev *ch0mm; /* device 21 func 0 */ struct pci_dev *ch1mm; /* device 22 func 0 */ + + struct delayed_work i5100_scrubbing; + int scrub_enable; + + /* Error injection */ + u8 inject_channel; + u8 inject_hlinesel; + u8 inject_deviceptr1; + u8 inject_deviceptr2; + u16 inject_eccmask1; + u16 inject_eccmask2; + + struct dentry *debugfs; }; -/* map a rank/ctlr to a slot number on the mainboard */ +static struct dentry *i5100_debugfs; + +/* map a rank/chan to a slot number on the mainboard */ static int i5100_rank_to_slot(const struct mem_ctl_info *mci, - int ctlr, int rank) + int chan, int rank) { const struct i5100_priv *priv = mci->pvt_info; int i; - for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CTLR; i++) { + for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { int j; - const int numrank = priv->dimm_numrank[ctlr][i]; + const int numrank = priv->dimm_numrank[chan][i]; for (j = 0; j < numrank; j++) if (priv->dimm_csmap[i][j] == rank) - return i * 2 + ctlr; + return i * 2 + chan; } return -1; @@ -374,32 +421,24 @@ static const char *i5100_err_msg(unsigned err) return "none"; } -/* convert csrow index into a rank (per controller -- 0..5) */ +/* convert csrow index into a rank (per channel -- 0..5) */ static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow) { const struct i5100_priv *priv = mci->pvt_info; - return csrow % priv->ranksperctlr; + return csrow % priv->ranksperchan; } -/* convert csrow index into a controller (0..1) */ -static int i5100_csrow_to_cntlr(const struct mem_ctl_info *mci, int csrow) +/* convert csrow index into a channel (0..1) */ +static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow) { const struct i5100_priv *priv = mci->pvt_info; - return csrow / priv->ranksperctlr; -} - -static unsigned i5100_rank_to_csrow(const struct mem_ctl_info *mci, - int ctlr, int rank) -{ - const struct i5100_priv *priv = mci->pvt_info; - - return ctlr * priv->ranksperctlr + rank; + return csrow / priv->ranksperchan; } static void i5100_handle_ce(struct mem_ctl_info *mci, - int ctlr, + int chan, unsigned bank, unsigned rank, unsigned long syndrome, @@ -407,21 +446,21 @@ static void i5100_handle_ce(struct mem_ctl_info *mci, unsigned ras, const char *msg) { - const int csrow = i5100_rank_to_csrow(mci, ctlr, rank); + char detail[80]; - printk(KERN_ERR - "CE ctlr %d, bank %u, rank %u, syndrome 0x%lx, " - "cas %u, ras %u, csrow %u, label \"%s\": %s\n", - ctlr, bank, rank, syndrome, cas, ras, - csrow, mci->csrows[csrow].channels[0].label, msg); + /* Form out message */ + snprintf(detail, sizeof(detail), + "bank %u, cas %u, ras %u\n", + bank, cas, ras); - mci->ce_count++; - mci->csrows[csrow].ce_count++; - mci->csrows[csrow].channels[0].ce_count++; + edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, + 0, 0, syndrome, + chan, rank, -1, + msg, detail); } static void i5100_handle_ue(struct mem_ctl_info *mci, - int ctlr, + int chan, unsigned bank, unsigned rank, unsigned long syndrome, @@ -429,23 +468,24 @@ static void i5100_handle_ue(struct mem_ctl_info *mci, unsigned ras, const char *msg) { - const int csrow = i5100_rank_to_csrow(mci, ctlr, rank); + char detail[80]; - printk(KERN_ERR - "UE ctlr %d, bank %u, rank %u, syndrome 0x%lx, " - "cas %u, ras %u, csrow %u, label \"%s\": %s\n", - ctlr, bank, rank, syndrome, cas, ras, - csrow, mci->csrows[csrow].channels[0].label, msg); + /* Form out message */ + snprintf(detail, sizeof(detail), + "bank %u, cas %u, ras %u\n", + bank, cas, ras); - mci->ue_count++; - mci->csrows[csrow].ue_count++; + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, + 0, 0, syndrome, + chan, rank, -1, + msg, detail); } -static void i5100_read_log(struct mem_ctl_info *mci, int ctlr, +static void i5100_read_log(struct mem_ctl_info *mci, int chan, u32 ferr, u32 nerr) { struct i5100_priv *priv = mci->pvt_info; - struct pci_dev *pdev = (ctlr) ? priv->ch1mm : priv->ch0mm; + struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm; u32 dw; u32 dw2; unsigned syndrome = 0; @@ -484,7 +524,7 @@ static void i5100_read_log(struct mem_ctl_info *mci, int ctlr, else msg = i5100_err_msg(nerr); - i5100_handle_ce(mci, ctlr, bank, rank, syndrome, cas, ras, msg); + i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); } if (i5100_validlog_nrecmemvalid(dw)) { @@ -506,7 +546,7 @@ static void i5100_read_log(struct mem_ctl_info *mci, int ctlr, else msg = i5100_err_msg(nerr); - i5100_handle_ue(mci, ctlr, bank, rank, syndrome, cas, ras, msg); + i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); } pci_write_config_dword(pdev, I5100_VALIDLOG, dw); @@ -515,23 +555,90 @@ static void i5100_read_log(struct mem_ctl_info *mci, int ctlr, static void i5100_check_error(struct mem_ctl_info *mci) { struct i5100_priv *priv = mci->pvt_info; - u32 dw; - + u32 dw, dw2; pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw); if (i5100_ferr_nf_mem_any(dw)) { - u32 dw2; pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2); - if (dw2) - pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, - dw2); - pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw), i5100_ferr_nf_mem_any(dw), i5100_nerr_nf_mem_any(dw2)); + + pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2); } + pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); +} + +/* The i5100 chipset will scrub the entire memory once, then + * set a done bit. Continuous scrubbing is achieved by enqueing + * delayed work to a workqueue, checking every few minutes if + * the scrubbing has completed and if so reinitiating it. + */ + +static void i5100_refresh_scrubbing(struct work_struct *work) +{ + struct delayed_work *i5100_scrubbing = container_of(work, + struct delayed_work, + work); + struct i5100_priv *priv = container_of(i5100_scrubbing, + struct i5100_priv, + i5100_scrubbing); + u32 dw; + + pci_read_config_dword(priv->mc, I5100_MC, &dw); + + if (priv->scrub_enable) { + + pci_read_config_dword(priv->mc, I5100_MC, &dw); + + if (i5100_mc_scrbdone(dw)) { + dw |= I5100_MC_SCRBEN_MASK; + pci_write_config_dword(priv->mc, I5100_MC, dw); + pci_read_config_dword(priv->mc, I5100_MC, &dw); + } + + schedule_delayed_work(&(priv->i5100_scrubbing), + I5100_SCRUB_REFRESH_RATE); + } +} +/* + * The bandwidth is based on experimentation, feel free to refine it. + */ +static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth) +{ + struct i5100_priv *priv = mci->pvt_info; + u32 dw; + + pci_read_config_dword(priv->mc, I5100_MC, &dw); + if (bandwidth) { + priv->scrub_enable = 1; + dw |= I5100_MC_SCRBEN_MASK; + schedule_delayed_work(&(priv->i5100_scrubbing), + I5100_SCRUB_REFRESH_RATE); + } else { + priv->scrub_enable = 0; + dw &= ~I5100_MC_SCRBEN_MASK; + cancel_delayed_work(&(priv->i5100_scrubbing)); + } + pci_write_config_dword(priv->mc, I5100_MC, dw); + + pci_read_config_dword(priv->mc, I5100_MC, &dw); + + bandwidth = 5900000 * i5100_mc_scrben(dw); + + return bandwidth; +} + +static int i5100_get_scrub_rate(struct mem_ctl_info *mci) +{ + struct i5100_priv *priv = mci->pvt_info; + u32 dw; + + pci_read_config_dword(priv->mc, I5100_MC, &dw); + + return 5900000 * i5100_mc_scrben(dw); } static struct pci_dev *pci_get_device_func(unsigned vendor, @@ -553,39 +660,38 @@ static struct pci_dev *pci_get_device_func(unsigned vendor, return ret; } -static unsigned long __devinit i5100_npages(struct mem_ctl_info *mci, - int csrow) +static unsigned long i5100_npages(struct mem_ctl_info *mci, int csrow) { struct i5100_priv *priv = mci->pvt_info; - const unsigned ctlr_rank = i5100_csrow_to_rank(mci, csrow); - const unsigned ctlr = i5100_csrow_to_cntlr(mci, csrow); + const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow); + const unsigned chan = i5100_csrow_to_chan(mci, csrow); unsigned addr_lines; /* dimm present? */ - if (!priv->mtr[ctlr][ctlr_rank].present) + if (!priv->mtr[chan][chan_rank].present) return 0ULL; addr_lines = I5100_DIMM_ADDR_LINES + - priv->mtr[ctlr][ctlr_rank].numcol + - priv->mtr[ctlr][ctlr_rank].numrow + - priv->mtr[ctlr][ctlr_rank].numbank; + priv->mtr[chan][chan_rank].numcol + + priv->mtr[chan][chan_rank].numrow + + priv->mtr[chan][chan_rank].numbank; return (unsigned long) ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE); } -static void __devinit i5100_init_mtr(struct mem_ctl_info *mci) +static void i5100_init_mtr(struct mem_ctl_info *mci) { struct i5100_priv *priv = mci->pvt_info; struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; int i; - for (i = 0; i < I5100_MAX_CTLRS; i++) { + for (i = 0; i < I5100_CHANNELS; i++) { int j; struct pci_dev *pdev = mms[i]; - for (j = 0; j < I5100_MAX_RANKS_PER_CTLR; j++) { + for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) { const unsigned addr = (j < 4) ? I5100_MTR_0 + j * 2 : I5100_MTR_4 + (j - 4) * 2; @@ -644,18 +750,15 @@ static int i5100_read_spd_byte(const struct mem_ctl_info *mci, * fill dimm chip select map * * FIXME: - * o only valid for 4 ranks per controller * o not the only way to may chip selects to dimm slots * o investigate if there is some way to obtain this map from the bios */ -static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci) +static void i5100_init_dimm_csmap(struct mem_ctl_info *mci) { struct i5100_priv *priv = mci->pvt_info; int i; - WARN_ON(priv->ranksperctlr != 4); - - for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CTLR; i++) { + for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { int j; for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++) @@ -663,24 +766,33 @@ static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci) } /* only 2 chip selects per slot... */ - priv->dimm_csmap[0][0] = 0; - priv->dimm_csmap[0][1] = 3; - priv->dimm_csmap[1][0] = 1; - priv->dimm_csmap[1][1] = 2; - priv->dimm_csmap[2][0] = 2; - priv->dimm_csmap[3][0] = 3; + if (priv->ranksperchan == 4) { + priv->dimm_csmap[0][0] = 0; + priv->dimm_csmap[0][1] = 3; + priv->dimm_csmap[1][0] = 1; + priv->dimm_csmap[1][1] = 2; + priv->dimm_csmap[2][0] = 2; + priv->dimm_csmap[3][0] = 3; + } else { + priv->dimm_csmap[0][0] = 0; + priv->dimm_csmap[0][1] = 1; + priv->dimm_csmap[1][0] = 2; + priv->dimm_csmap[1][1] = 3; + priv->dimm_csmap[2][0] = 4; + priv->dimm_csmap[2][1] = 5; + } } -static void __devinit i5100_init_dimm_layout(struct pci_dev *pdev, - struct mem_ctl_info *mci) +static void i5100_init_dimm_layout(struct pci_dev *pdev, + struct mem_ctl_info *mci) { struct i5100_priv *priv = mci->pvt_info; int i; - for (i = 0; i < I5100_MAX_CTLRS; i++) { + for (i = 0; i < I5100_CHANNELS; i++) { int j; - for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CTLR; j++) { + for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) { u8 rank; if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0) @@ -693,8 +805,8 @@ static void __devinit i5100_init_dimm_layout(struct pci_dev *pdev, i5100_init_dimm_csmap(mci); } -static void __devinit i5100_init_interleaving(struct pci_dev *pdev, - struct mem_ctl_info *mci) +static void i5100_init_interleaving(struct pci_dev *pdev, + struct mem_ctl_info *mci) { u16 w; u32 dw; @@ -720,7 +832,7 @@ static void __devinit i5100_init_interleaving(struct pci_dev *pdev, pci_read_config_word(pdev, I5100_AMIR_1, &w); priv->amir[1] = w; - for (i = 0; i < I5100_MAX_CTLRS; i++) { + for (i = 0; i < I5100_CHANNELS; i++) { int j; for (j = 0; j < 5; j++) { @@ -739,57 +851,157 @@ static void __devinit i5100_init_interleaving(struct pci_dev *pdev, i5100_init_mtr(mci); } -static void __devinit i5100_init_csrows(struct mem_ctl_info *mci) +static void i5100_init_csrows(struct mem_ctl_info *mci) { int i; - unsigned long total_pages = 0UL; struct i5100_priv *priv = mci->pvt_info; - for (i = 0; i < mci->nr_csrows; i++) { + for (i = 0; i < mci->tot_dimms; i++) { + struct dimm_info *dimm; const unsigned long npages = i5100_npages(mci, i); - const unsigned cntlr = i5100_csrow_to_cntlr(mci, i); + const unsigned chan = i5100_csrow_to_chan(mci, i); const unsigned rank = i5100_csrow_to_rank(mci, i); if (!npages) continue; - /* - * FIXME: these two are totally bogus -- I don't see how to - * map them correctly to this structure... - */ - mci->csrows[i].first_page = total_pages; - mci->csrows[i].last_page = total_pages + npages - 1; - mci->csrows[i].page_mask = 0UL; - - mci->csrows[i].nr_pages = npages; - mci->csrows[i].grain = 32; - mci->csrows[i].csrow_idx = i; - mci->csrows[i].dtype = - (priv->mtr[cntlr][rank].width == 4) ? DEV_X4 : DEV_X8; - mci->csrows[i].ue_count = 0; - mci->csrows[i].ce_count = 0; - mci->csrows[i].mtype = MEM_RDDR2; - mci->csrows[i].edac_mode = EDAC_SECDED; - mci->csrows[i].mci = mci; - mci->csrows[i].nr_channels = 1; - mci->csrows[i].channels[0].chan_idx = 0; - mci->csrows[i].channels[0].ce_count = 0; - mci->csrows[i].channels[0].csrow = mci->csrows + i; - snprintf(mci->csrows[i].channels[0].label, - sizeof(mci->csrows[i].channels[0].label), - "DIMM%u", i5100_rank_to_slot(mci, cntlr, rank)); - - total_pages += npages; + dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, + chan, rank, 0); + + dimm->nr_pages = npages; + dimm->grain = 32; + dimm->dtype = (priv->mtr[chan][rank].width == 4) ? + DEV_X4 : DEV_X8; + dimm->mtype = MEM_RDDR2; + dimm->edac_mode = EDAC_SECDED; + snprintf(dimm->label, sizeof(dimm->label), "DIMM%u", + i5100_rank_to_slot(mci, chan, rank)); + + edac_dbg(2, "dimm channel %d, rank %d, size %ld\n", + chan, rank, (long)PAGES_TO_MiB(npages)); } } -static int __devinit i5100_init_one(struct pci_dev *pdev, - const struct pci_device_id *id) +/**************************************************************************** + * Error injection routines + ****************************************************************************/ + +static void i5100_do_inject(struct mem_ctl_info *mci) +{ + struct i5100_priv *priv = mci->pvt_info; + u32 mask0; + u16 mask1; + + /* MEM[1:0]EINJMSK0 + * 31 - ADDRMATCHEN + * 29:28 - HLINESEL + * 00 Reserved + * 01 Lower half of cache line + * 10 Upper half of cache line + * 11 Both upper and lower parts of cache line + * 27 - EINJEN + * 25:19 - XORMASK1 for deviceptr1 + * 9:5 - SEC2RAM for deviceptr2 + * 4:0 - FIR2RAM for deviceptr1 + */ + mask0 = ((priv->inject_hlinesel & 0x3) << 28) | + I5100_MEMXEINJMSK0_EINJEN | + ((priv->inject_eccmask1 & 0xffff) << 10) | + ((priv->inject_deviceptr2 & 0x1f) << 5) | + (priv->inject_deviceptr1 & 0x1f); + + /* MEM[1:0]EINJMSK1 + * 15:0 - XORMASK2 for deviceptr2 + */ + mask1 = priv->inject_eccmask2; + + if (priv->inject_channel == 0) { + pci_write_config_dword(priv->mc, I5100_MEM0EINJMSK0, mask0); + pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1); + } else { + pci_write_config_dword(priv->mc, I5100_MEM1EINJMSK0, mask0); + pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1); + } + + /* Error Injection Response Function + * Intel 5100 Memory Controller Hub Chipset (318378) datasheet + * hints about this register but carry no data about them. All + * data regarding device 19 is based on experimentation and the + * Intel 7300 Chipset Memory Controller Hub (318082) datasheet + * which appears to be accurate for the i5100 in this area. + * + * The injection code don't work without setting this register. + * The register needs to be flipped off then on else the hardware + * will only preform the first injection. + * + * Stop condition bits 7:4 + * 1010 - Stop after one injection + * 1011 - Never stop injecting faults + * + * Start condition bits 3:0 + * 1010 - Never start + * 1011 - Start immediately + */ + pci_write_config_byte(priv->einj, I5100_DINJ0, 0xaa); + pci_write_config_byte(priv->einj, I5100_DINJ0, 0xab); +} + +#define to_mci(k) container_of(k, struct mem_ctl_info, dev) +static ssize_t inject_enable_write(struct file *file, const char __user *data, + size_t count, loff_t *ppos) +{ + struct device *dev = file->private_data; + struct mem_ctl_info *mci = to_mci(dev); + + i5100_do_inject(mci); + + return count; +} + +static const struct file_operations i5100_inject_enable_fops = { + .open = simple_open, + .write = inject_enable_write, + .llseek = generic_file_llseek, +}; + +static int i5100_setup_debugfs(struct mem_ctl_info *mci) +{ + struct i5100_priv *priv = mci->pvt_info; + + if (!i5100_debugfs) + return -ENODEV; + + priv->debugfs = debugfs_create_dir(mci->bus->name, i5100_debugfs); + + if (!priv->debugfs) + return -ENOMEM; + + debugfs_create_x8("inject_channel", S_IRUGO | S_IWUSR, priv->debugfs, + &priv->inject_channel); + debugfs_create_x8("inject_hlinesel", S_IRUGO | S_IWUSR, priv->debugfs, + &priv->inject_hlinesel); + debugfs_create_x8("inject_deviceptr1", S_IRUGO | S_IWUSR, priv->debugfs, + &priv->inject_deviceptr1); + debugfs_create_x8("inject_deviceptr2", S_IRUGO | S_IWUSR, priv->debugfs, + &priv->inject_deviceptr2); + debugfs_create_x16("inject_eccmask1", S_IRUGO | S_IWUSR, priv->debugfs, + &priv->inject_eccmask1); + debugfs_create_x16("inject_eccmask2", S_IRUGO | S_IWUSR, priv->debugfs, + &priv->inject_eccmask2); + debugfs_create_file("inject_enable", S_IWUSR, priv->debugfs, + &mci->dev, &i5100_inject_enable_fops); + + return 0; + +} + +static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id) { int rc; struct mem_ctl_info *mci; + struct edac_mc_layer layers[2]; struct i5100_priv *priv; - struct pci_dev *ch0mm, *ch1mm; + struct pci_dev *ch0mm, *ch1mm, *einj; int ret = 0; u32 dw; int ranksperch; @@ -815,13 +1027,6 @@ static int __devinit i5100_init_one(struct pci_dev *pdev, pci_read_config_dword(pdev, I5100_MS, &dw); ranksperch = !!(dw & (1 << 8)) * 2 + 4; - if (ranksperch != 4) { - /* FIXME: get 6 ranks / controller to work - need hw... */ - printk(KERN_INFO "i5100_edac: unsupported configuration.\n"); - ret = -ENODEV; - goto bail_pdev; - } - /* enable error reporting... */ pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw); dw &= ~I5100_FERR_NF_MEM_ANY_MASK; @@ -855,19 +1060,53 @@ static int __devinit i5100_init_one(struct pci_dev *pdev, goto bail_ch1; } - mci = edac_mc_alloc(sizeof(*priv), ranksperch * 2, 1, 0); + layers[0].type = EDAC_MC_LAYER_CHANNEL; + layers[0].size = 2; + layers[0].is_virt_csrow = false; + layers[1].type = EDAC_MC_LAYER_SLOT; + layers[1].size = ranksperch; + layers[1].is_virt_csrow = true; + mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, + sizeof(*priv)); if (!mci) { ret = -ENOMEM; goto bail_disable_ch1; } - mci->dev = &pdev->dev; + + /* device 19, func 0, Error injection */ + einj = pci_get_device_func(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_5100_19, 0); + if (!einj) { + ret = -ENODEV; + goto bail_einj; + } + + rc = pci_enable_device(einj); + if (rc < 0) { + ret = rc; + goto bail_disable_einj; + } + + + mci->pdev = &pdev->dev; priv = mci->pvt_info; - priv->ranksperctlr = ranksperch; + priv->ranksperchan = ranksperch; priv->mc = pdev; priv->ch0mm = ch0mm; priv->ch1mm = ch1mm; + priv->einj = einj; + + INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing); + + /* If scrubbing was already enabled by the bios, start maintaining it */ + pci_read_config_dword(pdev, I5100_MC, &dw); + if (i5100_mc_scrben(dw)) { + priv->scrub_enable = 1; + schedule_delayed_work(&(priv->i5100_scrubbing), + I5100_SCRUB_REFRESH_RATE); + } i5100_init_dimm_layout(pdev, mci); i5100_init_interleaving(pdev, mci); @@ -882,6 +1121,15 @@ static int __devinit i5100_init_one(struct pci_dev *pdev, mci->ctl_page_to_phys = NULL; mci->edac_check = i5100_check_error; + mci->set_sdram_scrub_rate = i5100_set_scrub_rate; + mci->get_sdram_scrub_rate = i5100_get_scrub_rate; + + priv->inject_channel = 0; + priv->inject_hlinesel = 0; + priv->inject_deviceptr1 = 0; + priv->inject_deviceptr2 = 0; + priv->inject_eccmask1 = 0; + priv->inject_eccmask2 = 0; i5100_init_csrows(mci); @@ -897,14 +1145,24 @@ static int __devinit i5100_init_one(struct pci_dev *pdev, if (edac_mc_add_mc(mci)) { ret = -ENODEV; - goto bail_mc; + goto bail_scrub; } + i5100_setup_debugfs(mci); + return ret; -bail_mc: +bail_scrub: + priv->scrub_enable = 0; + cancel_delayed_work_sync(&(priv->i5100_scrubbing)); edac_mc_free(mci); +bail_disable_einj: + pci_disable_device(einj); + +bail_einj: + pci_dev_put(einj); + bail_disable_ch1: pci_disable_device(ch1mm); @@ -924,7 +1182,7 @@ bail: return ret; } -static void __devexit i5100_remove_one(struct pci_dev *pdev) +static void i5100_remove_one(struct pci_dev *pdev) { struct mem_ctl_info *mci; struct i5100_priv *priv; @@ -935,16 +1193,24 @@ static void __devexit i5100_remove_one(struct pci_dev *pdev) return; priv = mci->pvt_info; + + debugfs_remove_recursive(priv->debugfs); + + priv->scrub_enable = 0; + cancel_delayed_work_sync(&(priv->i5100_scrubbing)); + pci_disable_device(pdev); pci_disable_device(priv->ch0mm); pci_disable_device(priv->ch1mm); + pci_disable_device(priv->einj); pci_dev_put(priv->ch0mm); pci_dev_put(priv->ch1mm); + pci_dev_put(priv->einj); edac_mc_free(mci); } -static const struct pci_device_id i5100_pci_tbl[] __devinitdata = { +static const struct pci_device_id i5100_pci_tbl[] = { /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) }, { 0, } @@ -954,7 +1220,7 @@ MODULE_DEVICE_TABLE(pci, i5100_pci_tbl); static struct pci_driver i5100_driver = { .name = KBUILD_BASENAME, .probe = i5100_init_one, - .remove = __devexit_p(i5100_remove_one), + .remove = i5100_remove_one, .id_table = i5100_pci_tbl, }; @@ -962,13 +1228,16 @@ static int __init i5100_init(void) { int pci_rc; - pci_rc = pci_register_driver(&i5100_driver); + i5100_debugfs = debugfs_create_dir("i5100_edac", NULL); + pci_rc = pci_register_driver(&i5100_driver); return (pci_rc < 0) ? pci_rc : 0; } static void __exit i5100_exit(void) { + debugfs_remove(i5100_debugfs); + pci_unregister_driver(&i5100_driver); } |