diff options
Diffstat (limited to 'arch/sh64')
| -rw-r--r-- | arch/sh64/kernel/Makefile | 36 | ||||
| -rw-r--r-- | arch/sh64/kernel/alphanum.c | 43 | ||||
| -rw-r--r-- | arch/sh64/kernel/dma.c | 297 | ||||
| -rw-r--r-- | arch/sh64/kernel/early_printk.c | 99 | ||||
| -rw-r--r-- | arch/sh64/kernel/led.c | 40 | ||||
| -rw-r--r-- | arch/sh64/kernel/pci_sh5.c | 536 | ||||
| -rw-r--r-- | arch/sh64/kernel/pci_sh5.h | 107 | ||||
| -rw-r--r-- | arch/sh64/kernel/pcibios.c | 168 | ||||
| -rw-r--r-- | arch/sh64/kernel/setup.c | 379 | ||||
| -rw-r--r-- | arch/sh64/kernel/time.c | 531 |
10 files changed, 0 insertions, 2236 deletions
diff --git a/arch/sh64/kernel/Makefile b/arch/sh64/kernel/Makefile deleted file mode 100644 index e3467bda616..00000000000 --- a/arch/sh64/kernel/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# -# Copyright (C) 2000, 2001 Paolo Alberelli -# Copyright (C) 2003 Paul Mundt -# -# Makefile for the Linux sh64 kernel. -# -# Note! Dependencies are done automagically by 'make dep', which also -# removes any old dependencies. DON'T put your own dependencies here -# unless it's something special (ie not a .c file). -# - -extra-y := head.o init_task.o vmlinux.lds - -obj-y := process.o signal.o entry.o traps.o irq.o irq_intc.o \ - ptrace.o setup.o time.o sys_sh64.o semaphore.o sh_ksyms.o \ - switchto.o syscalls.o - -obj-$(CONFIG_HEARTBEAT) += led.o -obj-$(CONFIG_SH_ALPHANUMERIC) += alphanum.o -obj-$(CONFIG_SH_DMA) += dma.o -obj-$(CONFIG_SH_FPU) += fpu.o -obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -obj-$(CONFIG_KALLSYMS) += unwind.o -obj-$(CONFIG_PCI) += pcibios.o -obj-$(CONFIG_MODULES) += module.o - -ifeq ($(CONFIG_PCI),y) -obj-$(CONFIG_CPU_SH5) += pci_sh5.o -endif - -USE_STANDARD_AS_RULE := true - diff --git a/arch/sh64/kernel/alphanum.c b/arch/sh64/kernel/alphanum.c deleted file mode 100644 index d1619d95fba..00000000000 --- a/arch/sh64/kernel/alphanum.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * arch/sh64/kernel/alphanum.c - * - * Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com> - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * Machine-independent functions for handling 8-digit alphanumeric display - * (e.g. Agilent HDSP-253x) - */ -#include <linux/stddef.h> -#include <linux/sched.h> - -void mach_alphanum(int pos, unsigned char val); - -void print_seg(char *file, int line) -{ - int i; - unsigned int nibble; - - for (i = 0; i < 5; i++) { - mach_alphanum(i, file[i]); - } - - for (i = 0; i < 3; i++) { - nibble = ((line >> (i * 4)) & 0xf); - mach_alphanum(7 - i, nibble + ((nibble > 9) ? 55 : 48)); - } -} - -void print_seg_num(unsigned num) -{ - int i; - unsigned int nibble; - - for (i = 0; i < 8; i++) { - nibble = ((num >> (i * 4)) & 0xf); - - mach_alphanum(7 - i, nibble + ((nibble > 9) ? 55 : 48)); - } -} - diff --git a/arch/sh64/kernel/dma.c b/arch/sh64/kernel/dma.c deleted file mode 100644 index 32c6f0549bf..00000000000 --- a/arch/sh64/kernel/dma.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * arch/sh64/kernel/dma.c - * - * DMA routines for the SH-5 DMAC. - * - * Copyright (C) 2003 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/types.h> -#include <linux/irq.h> -#include <linux/spinlock.h> -#include <linux/mm.h> -#include <asm/hardware.h> -#include <asm/dma.h> -#include <asm/signal.h> -#include <asm/errno.h> -#include <asm/io.h> - -typedef struct { - unsigned long dev_addr; - unsigned long mem_addr; - - unsigned int mode; - unsigned int count; -} dma_info_t; - -static dma_info_t dma_info[MAX_DMA_CHANNELS]; -static DEFINE_SPINLOCK(dma_spin_lock); - -/* arch/sh64/kernel/irq_intc.c */ -extern void make_intc_irq(unsigned int irq); - -/* DMAC Interrupts */ -#define DMA_IRQ_DMTE0 18 -#define DMA_IRQ_DERR 22 - -#define DMAC_COMMON_BASE (dmac_base + 0x08) -#define DMAC_SAR_BASE (dmac_base + 0x10) -#define DMAC_DAR_BASE (dmac_base + 0x18) -#define DMAC_COUNT_BASE (dmac_base + 0x20) -#define DMAC_CTRL_BASE (dmac_base + 0x28) -#define DMAC_STATUS_BASE (dmac_base + 0x30) - -#define DMAC_SAR(n) (DMAC_SAR_BASE + ((n) * 0x28)) -#define DMAC_DAR(n) (DMAC_DAR_BASE + ((n) * 0x28)) -#define DMAC_COUNT(n) (DMAC_COUNT_BASE + ((n) * 0x28)) -#define DMAC_CTRL(n) (DMAC_CTRL_BASE + ((n) * 0x28)) -#define DMAC_STATUS(n) (DMAC_STATUS_BASE + ((n) * 0x28)) - -/* DMAC.COMMON Bit Definitions */ -#define DMAC_COMMON_PR 0x00000001 /* Priority */ - /* Bits 1-2 Reserved */ -#define DMAC_COMMON_ME 0x00000008 /* Master Enable */ -#define DMAC_COMMON_NMI 0x00000010 /* NMI Flag */ - /* Bits 5-6 Reserved */ -#define DMAC_COMMON_ER 0x00000780 /* Error Response */ -#define DMAC_COMMON_AAE 0x00007800 /* Address Alignment Error */ - /* Bits 15-63 Reserved */ - -/* DMAC.SAR Bit Definitions */ -#define DMAC_SAR_ADDR 0xffffffff /* Source Address */ - -/* DMAC.DAR Bit Definitions */ -#define DMAC_DAR_ADDR 0xffffffff /* Destination Address */ - -/* DMAC.COUNT Bit Definitions */ -#define DMAC_COUNT_CNT 0xffffffff /* Transfer Count */ - -/* DMAC.CTRL Bit Definitions */ -#define DMAC_CTRL_TS 0x00000007 /* Transfer Size */ -#define DMAC_CTRL_SI 0x00000018 /* Source Increment */ -#define DMAC_CTRL_DI 0x00000060 /* Destination Increment */ -#define DMAC_CTRL_RS 0x00000780 /* Resource Select */ -#define DMAC_CTRL_IE 0x00000800 /* Interrupt Enable */ -#define DMAC_CTRL_TE 0x00001000 /* Transfer Enable */ - /* Bits 15-63 Reserved */ - -/* DMAC.STATUS Bit Definitions */ -#define DMAC_STATUS_TE 0x00000001 /* Transfer End */ -#define DMAC_STATUS_AAE 0x00000002 /* Address Alignment Error */ - /* Bits 2-63 Reserved */ - -static unsigned long dmac_base; - -void set_dma_count(unsigned int chan, unsigned int count); -void set_dma_addr(unsigned int chan, unsigned int addr); - -static irqreturn_t dma_mte(int irq, void *dev_id, struct pt_regs *regs) -{ - unsigned int chan = irq - DMA_IRQ_DMTE0; - dma_info_t *info = dma_info + chan; - u64 status; - - if (info->mode & DMA_MODE_WRITE) { - sh64_out64(info->mem_addr & DMAC_SAR_ADDR, DMAC_SAR(chan)); - } else { - sh64_out64(info->mem_addr & DMAC_DAR_ADDR, DMAC_DAR(chan)); - } - - set_dma_count(chan, info->count); - - /* Clear the TE bit */ - status = sh64_in64(DMAC_STATUS(chan)); - status &= ~DMAC_STATUS_TE; - sh64_out64(status, DMAC_STATUS(chan)); - - return IRQ_HANDLED; -} - -static struct irqaction irq_dmte = { - .handler = dma_mte, - .flags = IRQF_DISABLED, - .name = "DMA MTE", -}; - -static irqreturn_t dma_err(int irq, void *dev_id, struct pt_regs *regs) -{ - u64 tmp; - u8 chan; - - printk(KERN_NOTICE "DMAC: Got a DMA Error!\n"); - - tmp = sh64_in64(DMAC_COMMON_BASE); - - /* Check for the type of error */ - if ((chan = tmp & DMAC_COMMON_AAE)) { - /* It's an address alignment error.. */ - printk(KERN_NOTICE "DMAC: Alignment error on channel %d, ", chan); - - printk(KERN_NOTICE "SAR: 0x%08llx, DAR: 0x%08llx, COUNT: %lld\n", - (sh64_in64(DMAC_SAR(chan)) & DMAC_SAR_ADDR), - (sh64_in64(DMAC_DAR(chan)) & DMAC_DAR_ADDR), - (sh64_in64(DMAC_COUNT(chan)) & DMAC_COUNT_CNT)); - - } else if ((chan = tmp & DMAC_COMMON_ER)) { - /* Something else went wrong.. */ - printk(KERN_NOTICE "DMAC: Error on channel %d\n", chan); - } - - /* Reset the ME bit to clear the interrupt */ - tmp |= DMAC_COMMON_ME; - sh64_out64(tmp, DMAC_COMMON_BASE); - - return IRQ_HANDLED; -} - -static struct irqaction irq_derr = { - .handler = dma_err, - .flags = IRQF_DISABLED, - .name = "DMA Error", -}; - -static inline unsigned long calc_xmit_shift(unsigned int chan) -{ - return sh64_in64(DMAC_CTRL(chan)) & 0x03; -} - -void setup_dma(unsigned int chan, dma_info_t *info) -{ - unsigned int irq = DMA_IRQ_DMTE0 + chan; - dma_info_t *dma = dma_info + chan; - - make_intc_irq(irq); - setup_irq(irq, &irq_dmte); - dma = info; -} - -void enable_dma(unsigned int chan) -{ - u64 ctrl; - - ctrl = sh64_in64(DMAC_CTRL(chan)); - ctrl |= DMAC_CTRL_TE; - sh64_out64(ctrl, DMAC_CTRL(chan)); -} - -void disable_dma(unsigned int chan) -{ - u64 ctrl; - - ctrl = sh64_in64(DMAC_CTRL(chan)); - ctrl &= ~DMAC_CTRL_TE; - sh64_out64(ctrl, DMAC_CTRL(chan)); -} - -void set_dma_mode(unsigned int chan, char mode) -{ - dma_info_t *info = dma_info + chan; - - info->mode = mode; - - set_dma_addr(chan, info->mem_addr); - set_dma_count(chan, info->count); -} - -void set_dma_addr(unsigned int chan, unsigned int addr) -{ - dma_info_t *info = dma_info + chan; - unsigned long sar, dar; - - info->mem_addr = addr; - sar = (info->mode & DMA_MODE_WRITE) ? info->mem_addr : info->dev_addr; - dar = (info->mode & DMA_MODE_WRITE) ? info->dev_addr : info->mem_addr; - - sh64_out64(sar & DMAC_SAR_ADDR, DMAC_SAR(chan)); - sh64_out64(dar & DMAC_SAR_ADDR, DMAC_DAR(chan)); -} - -void set_dma_count(unsigned int chan, unsigned int count) -{ - dma_info_t *info = dma_info + chan; - u64 tmp; - - info->count = count; - - tmp = (info->count >> calc_xmit_shift(chan)) & DMAC_COUNT_CNT; - - sh64_out64(tmp, DMAC_COUNT(chan)); -} - -unsigned long claim_dma_lock(void) -{ - unsigned long flags; - - spin_lock_irqsave(&dma_spin_lock, flags); - - return flags; -} - -void release_dma_lock(unsigned long flags) -{ - spin_unlock_irqrestore(&dma_spin_lock, flags); -} - -int get_dma_residue(unsigned int chan) -{ - return sh64_in64(DMAC_COUNT(chan) << calc_xmit_shift(chan)); -} - -int __init init_dma(void) -{ - struct vcr_info vcr; - u64 tmp; - - /* Remap the DMAC */ - dmac_base = onchip_remap(PHYS_DMAC_BLOCK, 1024, "DMAC"); - if (!dmac_base) { - printk(KERN_ERR "Unable to remap DMAC\n"); - return -ENOMEM; - } - - /* Report DMAC.VCR Info */ - vcr = sh64_get_vcr_info(dmac_base); - printk("DMAC: Module ID: 0x%04x, Module version: 0x%04x\n", - vcr.mod_id, vcr.mod_vers); - - /* Set the ME bit */ - tmp = sh64_in64(DMAC_COMMON_BASE); - tmp |= DMAC_COMMON_ME; - sh64_out64(tmp, DMAC_COMMON_BASE); - - /* Enable the DMAC Error Interrupt */ - make_intc_irq(DMA_IRQ_DERR); - setup_irq(DMA_IRQ_DERR, &irq_derr); - - return 0; -} - -static void __exit exit_dma(void) -{ - onchip_unmap(dmac_base); - free_irq(DMA_IRQ_DERR, 0); -} - -module_init(init_dma); -module_exit(exit_dma); - -MODULE_AUTHOR("Paul Mundt"); -MODULE_DESCRIPTION("DMA API for SH-5 DMAC"); -MODULE_LICENSE("GPL"); - -EXPORT_SYMBOL(setup_dma); -EXPORT_SYMBOL(claim_dma_lock); -EXPORT_SYMBOL(release_dma_lock); -EXPORT_SYMBOL(enable_dma); -EXPORT_SYMBOL(disable_dma); -EXPORT_SYMBOL(set_dma_mode); -EXPORT_SYMBOL(set_dma_addr); -EXPORT_SYMBOL(set_dma_count); -EXPORT_SYMBOL(get_dma_residue); - diff --git a/arch/sh64/kernel/early_printk.c b/arch/sh64/kernel/early_printk.c deleted file mode 100644 index 4f913112367..00000000000 --- a/arch/sh64/kernel/early_printk.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * arch/sh64/kernel/early_printk.c - * - * SH-5 Early SCIF console (cloned and hacked from sh implementation) - * - * Copyright (C) 2003, 2004 Paul Mundt <lethal@linux-sh.org> - * Copyright (C) 2002 M. R. Brown <mrbrown@0xd6.org> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/console.h> -#include <linux/tty.h> -#include <linux/init.h> -#include <asm/io.h> -#include <asm/hardware.h> - -#define SCIF_BASE_ADDR 0x01030000 -#define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR - -/* - * Fixed virtual address where SCIF is mapped (should already be done - * in arch/sh64/kernel/head.S!). - */ -#define SCIF_REG 0xfa030000 - -enum { - SCIF_SCSMR2 = SCIF_REG + 0x00, - SCIF_SCBRR2 = SCIF_REG + 0x04, - SCIF_SCSCR2 = SCIF_REG + 0x08, - SCIF_SCFTDR2 = SCIF_REG + 0x0c, - SCIF_SCFSR2 = SCIF_REG + 0x10, - SCIF_SCFRDR2 = SCIF_REG + 0x14, - SCIF_SCFCR2 = SCIF_REG + 0x18, - SCIF_SCFDR2 = SCIF_REG + 0x1c, - SCIF_SCSPTR2 = SCIF_REG + 0x20, - SCIF_SCLSR2 = SCIF_REG + 0x24, -}; - -static void sh_console_putc(int c) -{ - while (!(ctrl_inw(SCIF_SCFSR2) & 0x20)) - cpu_relax(); - - ctrl_outb(c, SCIF_SCFTDR2); - ctrl_outw((ctrl_inw(SCIF_SCFSR2) & 0x9f), SCIF_SCFSR2); - - if (c == '\n') - sh_console_putc('\r'); -} - -static void sh_console_flush(void) -{ - ctrl_outw((ctrl_inw(SCIF_SCFSR2) & 0xbf), SCIF_SCFSR2); - - while (!(ctrl_inw(SCIF_SCFSR2) & 0x40)) - cpu_relax(); - - ctrl_outw((ctrl_inw(SCIF_SCFSR2) & 0xbf), SCIF_SCFSR2); -} - -static void sh_console_write(struct console *con, const char *s, unsigned count) -{ - while (count-- > 0) - sh_console_putc(*s++); - - sh_console_flush(); -} - -static int __init sh_console_setup(struct console *con, char *options) -{ - con->cflag = CREAD | HUPCL | CLOCAL | B19200 | CS8; - - return 0; -} - -static struct console sh_console = { - .name = "scifcon", - .write = sh_console_write, - .setup = sh_console_setup, - .flags = CON_PRINTBUFFER | CON_BOOT, - .index = -1, -}; - -void __init enable_early_printk(void) -{ - ctrl_outb(0x2a, SCIF_SCBRR2); /* 19200bps */ - - ctrl_outw(0x04, SCIF_SCFCR2); /* Reset TFRST */ - ctrl_outw(0x10, SCIF_SCFCR2); /* TTRG0=1 */ - - ctrl_outw(0, SCIF_SCSPTR2); - ctrl_outw(0x60, SCIF_SCFSR2); - ctrl_outw(0, SCIF_SCLSR2); - ctrl_outw(0x30, SCIF_SCSCR2); - - register_console(&sh_console); -} diff --git a/arch/sh64/kernel/led.c b/arch/sh64/kernel/led.c deleted file mode 100644 index e35d3f667fb..00000000000 --- a/arch/sh64/kernel/led.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/sh64/kernel/led.c - * - * Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com> - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * Flash the LEDs - */ -#include <linux/stddef.h> -#include <linux/sched.h> - -void mach_led(int pos, int val); - -/* acts like an actual heart beat -- ie thump-thump-pause... */ -void heartbeat(void) -{ - static unsigned int cnt = 0, period = 0, dist = 0; - - if (cnt == 0 || cnt == dist) { - mach_led(-1, 1); - } else if (cnt == 7 || cnt == dist + 7) { - mach_led(-1, 0); - } - - if (++cnt > period) { - cnt = 0; - - /* - * The hyperbolic function below modifies the heartbeat period - * length in dependency of the current (5min) load. It goes - * through the points f(0)=126, f(1)=86, f(5)=51, f(inf)->30. - */ - period = ((672 << FSHIFT) / (5 * avenrun[0] + - (7 << FSHIFT))) + 30; - dist = period / 4; - } -} - diff --git a/arch/sh64/kernel/pci_sh5.c b/arch/sh64/kernel/pci_sh5.c deleted file mode 100644 index b4d9534d2b0..00000000000 --- a/arch/sh64/kernel/pci_sh5.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) - * Copyright (C) 2003, 2004 Paul Mundt - * Copyright (C) 2004 Richard Curnow - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * Support functions for the SH5 PCI hardware. - */ - -#include <linux/kernel.h> -#include <linux/rwsem.h> -#include <linux/smp.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/pci.h> -#include <linux/delay.h> -#include <linux/types.h> -#include <asm/pci.h> -#include <linux/irq.h> - -#include <asm/io.h> -#include <asm/hardware.h> -#include "pci_sh5.h" - -static unsigned long pcicr_virt; -unsigned long pciio_virt; - -static void __init pci_fixup_ide_bases(struct pci_dev *d) -{ - int i; - - /* - * PCI IDE controllers use non-standard I/O port decoding, respect it. - */ - if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) - return; - printk("PCI: IDE base address fixup for %s\n", pci_name(d)); - for(i=0; i<4; i++) { - struct resource *r = &d->resource[i]; - if ((r->start & ~0x80) == 0x374) { - r->start |= 2; - r->end = r->start; - } - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); - -char * __devinit pcibios_setup(char *str) -{ - return str; -} - -/* Rounds a number UP to the nearest power of two. Used for - * sizing the PCI window. - */ -static u32 __init r2p2(u32 num) -{ - int i = 31; - u32 tmp = num; - - if (num == 0) - return 0; - - do { - if (tmp & (1 << 31)) - break; - i--; - tmp <<= 1; - } while (i >= 0); - - tmp = 1 << i; - /* If the original number isn't a power of 2, round it up */ - if (tmp != num) - tmp <<= 1; - - return tmp; -} - -extern unsigned long long memory_start, memory_end; - -int __init sh5pci_init(unsigned memStart, unsigned memSize) -{ - u32 lsr0; - u32 uval; - - pcicr_virt = onchip_remap(SH5PCI_ICR_BASE, 1024, "PCICR"); - if (!pcicr_virt) { - panic("Unable to remap PCICR\n"); - } - - pciio_virt = onchip_remap(SH5PCI_IO_BASE, 0x10000, "PCIIO"); - if (!pciio_virt) { - panic("Unable to remap PCIIO\n"); - } - - pr_debug("Register base addres is 0x%08lx\n", pcicr_virt); - - /* Clear snoop registers */ - SH5PCI_WRITE(CSCR0, 0); - SH5PCI_WRITE(CSCR1, 0); - - pr_debug("Wrote to reg\n"); - - /* Switch off interrupts */ - SH5PCI_WRITE(INTM, 0); - SH5PCI_WRITE(AINTM, 0); - SH5PCI_WRITE(PINTM, 0); - - /* Set bus active, take it out of reset */ - uval = SH5PCI_READ(CR); - - /* Set command Register */ - SH5PCI_WRITE(CR, uval | CR_LOCK_MASK | CR_CFINT| CR_FTO | CR_PFE | CR_PFCS | CR_BMAM); - - uval=SH5PCI_READ(CR); - pr_debug("CR is actually 0x%08x\n",uval); - - /* Allow it to be a master */ - /* NB - WE DISABLE I/O ACCESS to stop overlap */ - /* set WAIT bit to enable stepping, an attempt to improve stability */ - SH5PCI_WRITE_SHORT(CSR_CMD, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_WAIT); - - /* - ** Set translation mapping memory in order to convert the address - ** used for the main bus, to the PCI internal address. - */ - SH5PCI_WRITE(MBR,0x40000000); - - /* Always set the max size 512M */ - SH5PCI_WRITE(MBMR, PCISH5_MEM_SIZCONV(512*1024*1024)); - - /* - ** I/O addresses are mapped at internal PCI specific address - ** as is described into the configuration bridge table. - ** These are changed to 0, to allow cards that have legacy - ** io such as vga to function correctly. We set the SH5 IOBAR to - ** 256K, which is a bit big as we can only have 64K of address space - */ - - SH5PCI_WRITE(IOBR,0x0); - - pr_debug("PCI:Writing 0x%08x to IOBR\n",0); - - /* Set up a 256K window. Totally pointless waste of address space */ - SH5PCI_WRITE(IOBMR,0); - pr_debug("PCI:Writing 0x%08x to IOBMR\n",0); - - /* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec. Ideally, - * we would want to map the I/O region somewhere, but it is so big this is not - * that easy! - */ - SH5PCI_WRITE(CSR_IBAR0,~0); - /* Set memory size value */ - memSize = memory_end - memory_start; - - /* Now we set up the mbars so the PCI bus can see the memory of the machine */ - if (memSize < (1024 * 1024)) { - printk(KERN_ERR "PCISH5: Ridiculous memory size of 0x%x?\n", memSize); - return -EINVAL; - } - - /* Set LSR 0 */ - lsr0 = (memSize > (512 * 1024 * 1024)) ? 0x1ff00001 : ((r2p2(memSize) - 0x100000) | 0x1); - SH5PCI_WRITE(LSR0, lsr0); - - pr_debug("PCI:Writing 0x%08x to LSR0\n",lsr0); - - /* Set MBAR 0 */ - SH5PCI_WRITE(CSR_MBAR0, memory_start); - SH5PCI_WRITE(LAR0, memory_start); - - SH5PCI_WRITE(CSR_MBAR1,0); - SH5PCI_WRITE(LAR1,0); - SH5PCI_WRITE(LSR1,0); - - pr_debug("PCI:Writing 0x%08llx to CSR_MBAR0\n",memory_start); - pr_debug("PCI:Writing 0x%08llx to LAR0\n",memory_start); - - /* Enable the PCI interrupts on the device */ - SH5PCI_WRITE(INTM, ~0); - SH5PCI_WRITE(AINTM, ~0); - SH5PCI_WRITE(PINTM, ~0); - - pr_debug("Switching on all error interrupts\n"); - - return(0); -} - -static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *val) -{ - SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where)); - - switch (size) { - case 1: - *val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3)); - break; - case 2: - *val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2)); - break; - case 4: - *val = SH5PCI_READ(PDR); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int sh5pci_write(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) -{ - SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where)); - - switch (size) { - case 1: - SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val); - break; - case 2: - SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val); - break; - case 4: - SH5PCI_WRITE(PDR, val); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops pci_config_ops = { - .read = sh5pci_read, - .write = sh5pci_write, -}; - -/* Everything hangs off this */ -static struct pci_bus *pci_root_bus; - - -static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin) -{ - pr_debug("swizzle for dev %d on bus %d slot %d pin is %d\n", - dev->devfn,dev->bus->number, PCI_SLOT(dev->devfn),*pin); - return PCI_SLOT(dev->devfn); -} - -static inline u8 bridge_swizzle(u8 pin, u8 slot) -{ - return (((pin-1) + slot) % 4) + 1; -} - -u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp) -{ - if (dev->bus->number != 0) { - u8 pin = *pinp; - do { - pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); - /* Move up the chain of bridges. */ - dev = dev->bus->self; - } while (dev->bus->self); - *pinp = pin; - - /* The slot is the slot of the last bridge. */ - } - - return PCI_SLOT(dev->devfn); -} - -/* This needs to be shunted out of here into the board specific bit */ - -static int __init map_cayman_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int result = -1; - - /* The complication here is that the PCI IRQ lines from the Cayman's 2 - 5V slots get into the CPU via a different path from the IRQ lines - from the 3 3.3V slots. Thus, we have to detect whether the card's - interrupts go via the 5V or 3.3V path, i.e. the 'bridge swizzling' - at the point where we cross from 5V to 3.3V is not the normal case. - - The added complication is that we don't know that the 5V slots are - always bus 2, because a card containing a PCI-PCI bridge may be - plugged into a 3.3V slot, and this changes the bus numbering. - - Also, the Cayman has an intermediate PCI bus that goes a custom - expansion board header (and to the secondary bridge). This bus has - never been used in practice. - - The 1ary onboard PCI-PCI bridge is device 3 on bus 0 - The 2ary onboard PCI-PCI bridge is device 0 on the 2ary bus of the 1ary bridge. - */ - - struct slot_pin { - int slot; - int pin; - } path[4]; - int i=0; - - while (dev->bus->number > 0) { - - slot = path[i].slot = PCI_SLOT(dev->devfn); - pin = path[i].pin = bridge_swizzle(pin, slot); - dev = dev->bus->self; - i++; - if (i > 3) panic("PCI path to root bus too long!\n"); - } - - slot = PCI_SLOT(dev->devfn); - /* This is the slot on bus 0 through which the device is eventually - reachable. */ - - /* Now work back up. */ - if ((slot < 3) || (i == 0)) { - /* Bus 0 (incl. PCI-PCI bridge itself) : perform the final - swizzle now. */ - result = IRQ_INTA + bridge_swizzle(pin, slot) - 1; - } else { - i--; - slot = path[i].slot; - pin = path[i].pin; - if (slot > 0) { - panic("PCI expansion bus device found - not handled!\n"); - } else { - if (i > 0) { - /* 5V slots */ - i--; - slot = path[i].slot; - pin = path[i].pin; - /* 'pin' was swizzled earlier wrt slot, don't do it again. */ - result = IRQ_P2INTA + (pin - 1); - } else { - /* IRQ for 2ary PCI-PCI bridge : unused */ - result = -1; - } - } - } - - return result; -} - -static irqreturn_t pcish5_err_irq(int irq, void *dev_id) -{ - struct pt_regs *regs = get_irq_regs(); - unsigned pci_int, pci_air, pci_cir, pci_aint; - - pci_int = SH5PCI_READ(INT); - pci_cir = SH5PCI_READ(CIR); - pci_air = SH5PCI_READ(AIR); - - if (pci_int) { - printk("PCI INTERRUPT (at %08llx)!\n", regs->pc); - printk("PCI INT -> 0x%x\n", pci_int & 0xffff); - printk("PCI AIR -> 0x%x\n", pci_air); - printk("PCI CIR -> 0x%x\n", pci_cir); - SH5PCI_WRITE(INT, ~0); - } - - pci_aint = SH5PCI_READ(AINT); - if (pci_aint) { - printk("PCI ARB INTERRUPT!\n"); - printk("PCI AINT -> 0x%x\n", pci_aint); - printk("PCI AIR -> 0x%x\n", pci_air); - printk("PCI CIR -> 0x%x\n", pci_cir); - SH5PCI_WRITE(AINT, ~0); - } - - return IRQ_HANDLED; -} - -static irqreturn_t pcish5_serr_irq(int irq, void *dev_id) -{ - printk("SERR IRQ\n"); - - return IRQ_NONE; -} - -static void __init -pcibios_size_bridge(struct pci_bus *bus, struct resource *ior, - struct resource *memr) -{ - struct resource io_res, mem_res; - struct pci_dev *dev; - struct pci_dev *bridge = bus->self; - struct list_head *ln; - - if (!bridge) - return; /* host bridge, nothing to do */ - - /* set reasonable default locations for pcibios_align_resource */ - io_res.start = PCIBIOS_MIN_IO; - mem_res.start = PCIBIOS_MIN_MEM; - - io_res.end = io_res.start; - mem_res.end = mem_res.start; - - /* Collect information about how our direct children are layed out. */ - for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) { - int i; - dev = pci_dev_b(ln); - - /* Skip bridges for now */ - if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) - continue; - - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - struct resource res; - unsigned long size; - - memcpy(&res, &dev->resource[i], sizeof(res)); - size = res.end - res.start + 1; - - if (res.flags & IORESOURCE_IO) { - res.start = io_res.end; - pcibios_align_resource(dev, &res, size, 0); - io_res.end = res.start + size; - } else if (res.flags & IORESOURCE_MEM) { - res.start = mem_res.end; - pcibios_align_resource(dev, &res, size, 0); - mem_res.end = res.start + size; - } - } - } - - /* And for all of the subordinate busses. */ - for (ln=bus->children.next; ln != &bus->children; ln=ln->next) - pcibios_size_bridge(pci_bus_b(ln), &io_res, &mem_res); - - /* turn the ending locations into sizes (subtract start) */ - io_res.end -= io_res.start; - mem_res.end -= mem_res.start; - - /* Align the sizes up by bridge rules */ - io_res.end = ALIGN(io_res.end, 4*1024) - 1; - mem_res.end = ALIGN(mem_res.end, 1*1024*1024) - 1; - - /* Adjust the bridge's allocation requirements */ - bridge->resource[0].end = bridge->resource[0].start + io_res.end; - bridge->resource[1].end = bridge->resource[1].start + mem_res.end; - - bridge->resource[PCI_BRIDGE_RESOURCES].end = - bridge->resource[PCI_BRIDGE_RESOURCES].start + io_res.end; - bridge->resource[PCI_BRIDGE_RESOURCES+1].end = - bridge->resource[PCI_BRIDGE_RESOURCES+1].start + mem_res.end; - - /* adjust parent's resource requirements */ - if (ior) { - ior->end = ALIGN(ior->end, 4*1024); - ior->end += io_res.end; - } - - if (memr) { - memr->end = ALIGN(memr->end, 1*1024*1024); - memr->end += mem_res.end; - } -} - -static void __init pcibios_size_bridges(void) -{ - struct resource io_res, mem_res; - - memset(&io_res, 0, sizeof(io_res)); - memset(&mem_res, 0, sizeof(mem_res)); - - pcibios_size_bridge(pci_root_bus, &io_res, &mem_res); -} - -static int __init pcibios_init(void) -{ - if (request_irq(IRQ_ERR, pcish5_err_irq, - IRQF_DISABLED, "PCI Error",NULL) < 0) { - printk(KERN_ERR "PCISH5: Cannot hook PCI_PERR interrupt\n"); - return -EINVAL; - } - - if (request_irq(IRQ_SERR, pcish5_serr_irq, - IRQF_DISABLED, "PCI SERR interrupt", NULL) < 0) { - printk(KERN_ERR "PCISH5: Cannot hook PCI_SERR interrupt\n"); - return -EINVAL; - } - - /* The pci subsystem needs to know where memory is and how much - * of it there is. I've simply made these globals. A better mechanism - * is probably needed. - */ - sh5pci_init(__pa(memory_start), - __pa(memory_end) - __pa(memory_start)); - - pci_root_bus = pci_scan_bus(0, &pci_config_ops, NULL); - pcibios_size_bridges(); - pci_assign_unassigned_resources(); - pci_fixup_irqs(no_swizzle, map_cayman_irq); - - return 0; -} - -subsys_initcall(pcibios_init); - -void __devinit pcibios_fixup_bus(struct pci_bus *bus) -{ - struct pci_dev *dev = bus->self; - int i; - -#if 1 - if(dev) { - for(i=0; i<3; i++) { - bus->resource[i] = - &dev->resource[PCI_BRIDGE_RESOURCES+i]; - bus->resource[i]->name = bus->name; - } - bus->resource[0]->flags |= IORESOURCE_IO; - bus->resource[1]->flags |= IORESOURCE_MEM; - - /* For now, propagate host limits to the bus; - * we'll adjust them later. */ - -#if 1 - bus->resource[0]->end = 64*1024 - 1 ; - bus->resource[1]->end = PCIBIOS_MIN_MEM+(256*1024*1024)-1; - bus->resource[0]->start = PCIBIOS_MIN_IO; - bus->resource[1]->start = PCIBIOS_MIN_MEM; -#else - bus->resource[0]->end = 0; - bus->resource[1]->end = 0; - bus->resource[0]->start =0; - bus->resource[1]->start = 0; -#endif - /* Turn off downstream PF memory address range by default */ - bus->resource[2]->start = 1024*1024; - bus->resource[2]->end = bus->resource[2]->start - 1; - } -#endif - -} - diff --git a/arch/sh64/kernel/pci_sh5.h b/arch/sh64/kernel/pci_sh5.h deleted file mode 100644 index c71159dd04b..00000000000 --- a/arch/sh64/kernel/pci_sh5.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * Definitions for the SH5 PCI hardware. - */ - -/* Product ID */ -#define PCISH5_PID 0x350d - -/* vendor ID */ -#define PCISH5_VID 0x1054 - -/* Configuration types */ -#define ST_TYPE0 0x00 /* Configuration cycle type 0 */ -#define ST_TYPE1 0x01 /* Configuration cycle type 1 */ - -/* VCR data */ -#define PCISH5_VCR_STATUS 0x00 -#define PCISH5_VCR_VERSION 0x08 - -/* -** ICR register offsets and bits -*/ -#define PCISH5_ICR_CR 0x100 /* PCI control register values */ -#define CR_PBAM (1<<12) -#define CR_PFCS (1<<11) -#define CR_FTO (1<<10) -#define CR_PFE (1<<9) -#define CR_TBS (1<<8) -#define CR_SPUE (1<<7) -#define CR_BMAM (1<<6) -#define CR_HOST (1<<5) -#define CR_CLKEN (1<<4) -#define CR_SOCS (1<<3) -#define CR_IOCS (1<<2) -#define CR_RSTCTL (1<<1) -#define CR_CFINT (1<<0) -#define CR_LOCK_MASK 0xa5000000 - -#define PCISH5_ICR_INT 0x114 /* Interrupt registert values */ -#define INT_MADIM (1<<2) - |