diff options
Diffstat (limited to 'arch/ppc/boot/simple')
33 files changed, 7191 insertions, 0 deletions
diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile new file mode 100644 index 00000000000..d8d801fcee1 --- /dev/null +++ b/arch/ppc/boot/simple/Makefile @@ -0,0 +1,252 @@ +# This is far from simple, but I couldn't think of a good name. This is +# for making the 'zImage' or 'zImage.initrd' on a number of targets. +# +# Author: Tom Rini <trini@mvista.com> +# +# Notes: +# (1) For machines that do not want to use the ELF image directly (including +# stripping just the ELF header off), they must set the variables +# zimage-$(CONFIG_MACHINE) and zimagerd-$(CONFIG_MACHINE) to the target +# that produces the desired image and they must set end-$(CONFIG_MACHINE) +# to what will be suffixed to the image filename. +# (2) Regardless of (1), to have the resulting image be something other +# than 'zImage.elf', set end-$(CONFIG_MACHINE) to be the suffix used for +# the zImage, znetboot, and znetbootrd targets. +# (3) For machine targets which use the mktree program, you can optionally +# set entrypoint-$(CONFIG_MACHINE) to the location which the image should be +# loaded at. The optimal setting for entrypoint-$(CONFIG_MACHINE) is the link +# address. +# (4) It is advisable to pass in the memory size using BI_MEMSIZE and +# get_mem_size(), which is memory controller dependent. Add in the correct +# XXX_memory.o file for this to work, as well as editing the +# misc-$(CONFIG_MACHINE) variable. + +boot := arch/ppc/boot +common := $(boot)/common +utils := $(boot)/utils +bootlib := $(boot)/lib +images := $(boot)/images +of1275 := $(boot)/of1275 +tftpboot := /tftpboot + +# Normally, we use the 'misc.c' file for decompress_kernel and +# whatnot. Sometimes we need to override this however. +misc-y := misc.o + +# Normally, we have our images end in .elf, but something we want to +# change this. +end-y := elf + +# Additionally, we normally don't need to mess with the L2 / L3 caches +# if present on 'classic' PPC. +cacheflag-y := -DCLEAR_CACHES="" +# This file will flush / disable the L2, and L3 if present. +clear_L2_L3 := $(srctree)/$(boot)/simple/clear.S + +# +# See arch/ppc/kconfig and arch/ppc/platforms/Kconfig +# for definition of what platform each config option refer to. +#---------------------------------------------------------------------------- + zimage-$(CONFIG_CPCI690) := zImage-STRIPELF +zimageinitrd-$(CONFIG_CPCI690) := zImage.initrd-STRIPELF + extra.o-$(CONFIG_CPCI690) := misc-cpci690.o + end-$(CONFIG_CPCI690) := cpci690 + cacheflag-$(CONFIG_CPCI690) := -include $(clear_L2_L3) + + zimage-$(CONFIG_IBM_OPENBIOS) := zImage-TREE +zimageinitrd-$(CONFIG_IBM_OPENBIOS) := zImage.initrd-TREE + end-$(CONFIG_IBM_OPENBIOS) := treeboot + misc-$(CONFIG_IBM_OPENBIOS) := misc-embedded.o + + end-$(CONFIG_EMBEDDEDBOOT) := embedded + misc-$(CONFIG_EMBEDDEDBOOT) := misc-embedded.o + + zimage-$(CONFIG_EBONY) := zImage-TREE +zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE + end-$(CONFIG_EBONY) := ebony + entrypoint-$(CONFIG_EBONY) := 0x01000000 + extra.o-$(CONFIG_EBONY) := openbios.o + + zimage-$(CONFIG_LUAN) := zImage-TREE +zimageinitrd-$(CONFIG_LUAN) := zImage.initrd-TREE + end-$(CONFIG_LUAN) := luan + entrypoint-$(CONFIG_LUAN) := 0x01000000 + extra.o-$(CONFIG_LUAN) := pibs.o + + zimage-$(CONFIG_OCOTEA) := zImage-TREE +zimageinitrd-$(CONFIG_OCOTEA) := zImage.initrd-TREE + end-$(CONFIG_OCOTEA) := ocotea + entrypoint-$(CONFIG_OCOTEA) := 0x01000000 + extra.o-$(CONFIG_OCOTEA) := pibs.o + + extra.o-$(CONFIG_EV64260) := misc-ev64260.o + end-$(CONFIG_EV64260) := ev64260 + cacheflag-$(CONFIG_EV64260) := -include $(clear_L2_L3) + + extra.o-$(CONFIG_CHESTNUT) := misc-chestnut.o + end-$(CONFIG_CHESTNUT) := chestnut + + zimage-$(CONFIG_GEMINI) := zImage-STRIPELF +zimageinitrd-$(CONFIG_GEMINI) := zImage.initrd-STRIPELF + end-$(CONFIG_GEMINI) := gemini + + extra.o-$(CONFIG_K2) := prepmap.o + end-$(CONFIG_K2) := k2 + cacheflag-$(CONFIG_K2) := -include $(clear_L2_L3) + + extra.o-$(CONFIG_KATANA) := misc-katana.o + end-$(CONFIG_KATANA) := katana + cacheflag-$(CONFIG_KATANA) := -include $(clear_L2_L3) + + extra.o-$(CONFIG_RADSTONE_PPC7D) := misc-radstone_ppc7d.o + end-$(CONFIG_RADSTONE_PPC7D) := radstone_ppc7d + cacheflag-$(CONFIG_RADSTONE_PPC7D) := -include $(clear_L2_L3) + +# kconfig 'feature', only one of these will ever be 'y' at a time. +# The rest will be unset. +motorola := $(CONFIG_MCPN765)$(CONFIG_MVME5100)$(CONFIG_PRPMC750) \ +$(CONFIG_PRPMC800)$(CONFIG_LOPEC)$(CONFIG_PPLUS) +motorola := $(strip $(motorola)) +pcore := $(CONFIG_PCORE)$(CONFIG_POWERPMC250) + + zimage-$(motorola) := zImage-PPLUS +zimageinitrd-$(motorola) := zImage.initrd-PPLUS + end-$(motorola) := pplus + +# Overrides previous assingment + extra.o-$(CONFIG_PPLUS) := prepmap.o + extra.o-$(CONFIG_LOPEC) := mpc10x_memory.o + + zimage-$(pcore) := zImage-STRIPELF +zimageinitrd-$(pcore) := zImage.initrd-STRIPELF + extra.o-$(pcore) := chrpmap.o + end-$(pcore) := pcore + cacheflag-$(pcore) := -include $(clear_L2_L3) + + zimage-$(CONFIG_PPC_PREP) := zImage-PPLUS +zimageinitrd-$(CONFIG_PPC_PREP) := zImage.initrd-PPLUS + extra.o-$(CONFIG_PPC_PREP) := prepmap.o + misc-$(CONFIG_PPC_PREP) += misc-prep.o mpc10x_memory.o + end-$(CONFIG_PPC_PREP) := prep + + end-$(CONFIG_SANDPOINT) := sandpoint + cacheflag-$(CONFIG_SANDPOINT) := -include $(clear_L2_L3) + + zimage-$(CONFIG_SPRUCE) := zImage-TREE +zimageinitrd-$(CONFIG_SPRUCE) := zImage.initrd-TREE + end-$(CONFIG_SPRUCE) := spruce + entrypoint-$(CONFIG_SPRUCE) := 0x00800000 + misc-$(CONFIG_SPRUCE) += misc-spruce.o + + zimage-$(CONFIG_LITE5200) := zImage-STRIPELF +zimageinitrd-$(CONFIG_LITE5200) := zImage.initrd-STRIPELF + end-$(CONFIG_LITE5200) := lite5200 + cacheflag-$(CONFIG_LITE5200) := -include $(clear_L2_L3) + + +# SMP images should have a '.smp' suffix. + end-$(CONFIG_SMP) := $(end-y).smp + +# This is a treeboot that needs init functions until the +# boot rom is sorted out (i.e. this is short lived) +extra-aflags-$(CONFIG_REDWOOD_4) := -Wa,-m405 +extra.o-$(CONFIG_REDWOOD_4) := rw4/rw4_init.o rw4/rw4_init_brd.o +EXTRA_AFLAGS := $(extra-aflags-y) +# head.o needs to get the cacheflags defined. +AFLAGS_head.o += $(cacheflag-y) + +# Linker args. This specifies where the image will be run at. +LD_ARGS := -T $(srctree)/$(boot)/ld.script \ + -Ttext $(CONFIG_BOOT_LOAD) -Bstatic +OBJCOPY_ARGS := -O elf32-powerpc + +# head.o and relocate.o must be at the start. +boot-y := head.o relocate.o $(extra.o-y) $(misc-y) +boot-$(CONFIG_40x) += embed_config.o +boot-$(CONFIG_8xx) += embed_config.o +boot-$(CONFIG_8260) += embed_config.o +boot-$(CONFIG_BSEIP) += iic.o +boot-$(CONFIG_MBX) += iic.o pci.o qspan_pci.o +boot-$(CONFIG_MV64X60) += misc-mv64x60.o +boot-$(CONFIG_RPXCLASSIC) += iic.o pci.o qspan_pci.o +boot-$(CONFIG_RPXLITE) += iic.o +# Different boards need different serial implementations. +ifeq ($(CONFIG_SERIAL_CPM_CONSOLE),y) +boot-$(CONFIG_8xx) += m8xx_tty.o +boot-$(CONFIG_8260) += m8260_tty.o +endif +boot-$(CONFIG_SERIAL_MPC52xx_CONSOLE) += mpc52xx_tty.o +boot-$(CONFIG_SERIAL_MPSC_CONSOLE) += mv64x60_tty.o + +LIBS := $(common)/lib.a $(bootlib)/lib.a +ifeq ($(CONFIG_PPC_PREP),y) +LIBS += $(of1275)/lib.a +endif + +OBJS := $(addprefix $(obj)/,$(boot-y)) + +# Tools +MKBUGBOOT := $(utils)/mkbugboot +MKPREP := $(utils)/mkprep +MKTREE := $(utils)/mktree + +targets := dummy.o + +$(obj)/zvmlinux: $(OBJS) $(LIBS) $(srctree)/$(boot)/ld.script \ + $(images)/vmlinux.gz $(obj)/dummy.o + $(OBJCOPY) $(OBJCOPY_ARGS) \ + --add-section=.image=$(images)/vmlinux.gz \ + --set-section-flags=.image=contents,alloc,load,readonly,data \ + $(obj)/dummy.o $(obj)/image.o + $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/image.o $(LIBS) + $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab \ + -R .stabstr -R .ramdisk -R .sysmap + +$(obj)/zvmlinux.initrd: $(OBJS) $(LIBS) $(srctree)/$(boot)/ld.script \ + $(images)/vmlinux.gz $(obj)/dummy.o + $(OBJCOPY) $(OBJCOPY_ARGS) \ + --add-section=.ramdisk=$(images)/ramdisk.image.gz \ + --set-section-flags=.ramdisk=contents,alloc,load,readonly,data \ + --add-section=.image=$(images)/vmlinux.gz \ + --set-section-flags=.image=contents,alloc,load,readonly,data \ + $(obj)/dummy.o $(obj)/image.o + $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/image.o $(LIBS) + $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab \ + -R .stabstr -R .sysmap + +# Sort-of dummy rules, that let us format the image we want. +zImage: $(images)/$(zimage-y) $(obj)/zvmlinux + cp -f $(obj)/zvmlinux $(images)/zImage.elf + rm -f $(obj)/zvmlinux + +zImage.initrd: $(images)/$(zimageinitrd-y) $(obj)/zvmlinux.initrd + cp -f $(obj)/zvmlinux.initrd $(images)/zImage.initrd.elf + rm -f $(obj)/zvmlinux.initrd + +znetboot: zImage + cp $(images)/zImage.$(end-y) $(tftpboot)/zImage.$(end-y) + +znetboot.initrd: zImage.initrd + cp $(images)/zImage.initrd.$(end-y) $(tftpboot)/zImage.initrd.$(end-y) + +$(images)/zImage-STRIPELF: $(obj)/zvmlinux + dd if=$(obj)/zvmlinux of=$(images)/zImage.$(end-y) skip=64 bs=1k + +$(images)/zImage.initrd-STRIPELF: $(obj)/zvmlinux.initrd + dd if=$(obj)/zvmlinux.initrd of=$(images)/zImage.initrd.$(end-y) \ + skip=64 bs=1k + +$(images)/zImage-TREE: $(obj)/zvmlinux $(MKTREE) + $(MKTREE) $(obj)/zvmlinux $(images)/zImage.$(end-y) $(ENTRYPOINT) + +$(images)/zImage.initrd-TREE: $(obj)/zvmlinux.initrd $(MKTREE) + $(MKTREE) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y) \ + $(ENTRYPOINT) + +$(images)/zImage-PPLUS: $(obj)/zvmlinux $(MKPREP) $(MKBUGBOOT) + $(MKPREP) -pbp $(obj)/zvmlinux $(images)/zImage.$(end-y) + $(MKBUGBOOT) $(obj)/zvmlinux $(images)/zImage.bugboot + +$(images)/zImage.initrd-PPLUS: $(obj)/zvmlinux.initrd $(MKPREP) $(MKBUGBOOT) + $(MKPREP) -pbp $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y) + $(MKBUGBOOT) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.bugboot diff --git a/arch/ppc/boot/simple/chrpmap.c b/arch/ppc/boot/simple/chrpmap.c new file mode 100644 index 00000000000..14d9e05d98b --- /dev/null +++ b/arch/ppc/boot/simple/chrpmap.c @@ -0,0 +1,12 @@ +/* + * 2004 (C) IBM. This file is licensed under the terms of the GNU General + * Public License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <nonstdio.h> + +void board_isa_init(void) +{ + ISA_init(0xFE000000); +} diff --git a/arch/ppc/boot/simple/clear.S b/arch/ppc/boot/simple/clear.S new file mode 100644 index 00000000000..95c5647a0f5 --- /dev/null +++ b/arch/ppc/boot/simple/clear.S @@ -0,0 +1,19 @@ +/* + * Code to call _setup_L2CR to flus, invalidate and disable the L2, + * and if present, do the same to the L3. + */ + +#define CLEAR_CACHES \ + bl _setup_L2CR; \ + \ + /* If 745x, turn off L3CR as well */ \ + mfspr r8,SPRN_PVR; \ + srwi r8,r8,16; \ + \ + cmpli cr0,r8,0x8000; /* 7450 */ \ + cmpli cr1,r8,0x8001; /* 7455 */ \ + cmpli cr2,r8,0x8002; /* 7457 */ \ + /* Now test if any are true. */ \ + cror 4*cr0+eq,4*cr0+eq,4*cr1+eq; \ + cror 4*cr0+eq,4*cr0+eq,4*cr2+eq; \ + beql _setup_L3CR diff --git a/arch/ppc/boot/simple/cpc700_memory.c b/arch/ppc/boot/simple/cpc700_memory.c new file mode 100644 index 00000000000..8c75cf6c238 --- /dev/null +++ b/arch/ppc/boot/simple/cpc700_memory.c @@ -0,0 +1,36 @@ +/* + * arch/ppc/boot/common/cpc700_memory.c + * + * Find memory based upon settings in the CPC700 bridge + * + * Author: Dan Cox + * + * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#include <asm/types.h> +#include <asm/io.h> +#include "cpc700.h" + +unsigned long +cpc700_get_mem_size(void) +{ + int i; + unsigned long len, amt; + + /* Start at MB1EA, since MB0EA will most likely be the ending address + for ROM space. */ + for(len = 0, i = CPC700_MB1EA; i <= CPC700_MB4EA; i+=4) { + amt = cpc700_read_memreg(i); + if (amt == 0) + break; + len = amt; + } + + return len; +} + + diff --git a/arch/ppc/boot/simple/dummy.c b/arch/ppc/boot/simple/dummy.c new file mode 100644 index 00000000000..31dbf45bf99 --- /dev/null +++ b/arch/ppc/boot/simple/dummy.c @@ -0,0 +1,4 @@ +int main(void) +{ + return 0; +} diff --git a/arch/ppc/boot/simple/embed_config.c b/arch/ppc/boot/simple/embed_config.c new file mode 100644 index 00000000000..c342b47e763 --- /dev/null +++ b/arch/ppc/boot/simple/embed_config.c @@ -0,0 +1,981 @@ +/* Board specific functions for those embedded 8xx boards that do + * not have boot monitor support for board information. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/types.h> +#include <linux/config.h> +#include <linux/string.h> +#include <asm/reg.h> +#ifdef CONFIG_8xx +#include <asm/mpc8xx.h> +#endif +#ifdef CONFIG_8260 +#include <asm/mpc8260.h> +#include <asm/immap_cpm2.h> +#endif +#ifdef CONFIG_40x +#include <asm/io.h> +#endif +extern unsigned long timebase_period_ns; + +/* For those boards that don't provide one. +*/ +#if !defined(CONFIG_MBX) +static bd_t bdinfo; +#endif + +/* IIC functions. + * These are just the basic master read/write operations so we can + * examine serial EEPROM. + */ +extern void iic_read(uint devaddr, u_char *buf, uint offset, uint count); + +/* Supply a default Ethernet address for those eval boards that don't + * ship with one. This is an address from the MBX board I have, so + * it is unlikely you will find it on your network. + */ +static ushort def_enet_addr[] = { 0x0800, 0x3e26, 0x1559 }; + +#if defined(CONFIG_MBX) + +/* The MBX hands us a pretty much ready to go board descriptor. This + * is where the idea started in the first place. + */ +void +embed_config(bd_t **bdp) +{ + u_char *mp; + u_char eebuf[128]; + int i = 8; + bd_t *bd; + + bd = *bdp; + + /* Read the first 128 bytes of the EEPROM. There is more, + * but this is all we need. + */ + iic_read(0xa4, eebuf, 0, 128); + + /* All we are looking for is the Ethernet MAC address. The + * first 8 bytes are 'MOTOROLA', so check for part of that. + * Next, the VPD describes a MAC 'packet' as being of type 08 + * and size 06. So we look for that and the MAC must follow. + * If there are more than one, we still only care about the first. + * If it's there, assume we have a valid MAC address. If not, + * grab our default one. + */ + if ((*(uint *)eebuf) == 0x4d4f544f) { + while (i < 127 && !(eebuf[i] == 0x08 && eebuf[i + 1] == 0x06)) + i += eebuf[i + 1] + 2; /* skip this packet */ + + if (i == 127) /* Couldn't find. */ + mp = (u_char *)def_enet_addr; + else + mp = &eebuf[i + 2]; + } + else + mp = (u_char *)def_enet_addr; + + for (i=0; i<6; i++) + bd->bi_enetaddr[i] = *mp++; + + /* The boot rom passes these to us in MHz. Linux now expects + * them to be in Hz. + */ + bd->bi_intfreq *= 1000000; + bd->bi_busfreq *= 1000000; + + /* Stuff a baud rate here as well. + */ + bd->bi_baudrate = 9600; +} +#endif /* CONFIG_MBX */ + +#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || \ + defined(CONFIG_RPX8260) || defined(CONFIG_EP405) +/* Helper functions for Embedded Planet boards. +*/ +/* Because I didn't find anything that would do this....... +*/ +u_char +aschex_to_byte(u_char *cp) +{ + u_char byte, c; + + c = *cp++; + + if ((c >= 'A') && (c <= 'F')) { + c -= 'A'; + c += 10; + } else if ((c >= 'a') && (c <= 'f')) { + c -= 'a'; + c += 10; + } else + c -= '0'; + + byte = c * 16; + + c = *cp; + + if ((c >= 'A') && (c <= 'F')) { + c -= 'A'; + c += 10; + } else if ((c >= 'a') && (c <= 'f')) { + c -= 'a'; + c += 10; + } else + c -= '0'; + + byte += c; + + return(byte); +} + +static void +rpx_eth(bd_t *bd, u_char *cp) +{ + int i; + + for (i=0; i<6; i++) { + bd->bi_enetaddr[i] = aschex_to_byte(cp); + cp += 2; + } +} + +#ifdef CONFIG_RPX8260 +static uint +rpx_baseten(u_char *cp) +{ + uint retval; + + retval = 0; + + while (*cp != '\n') { + retval *= 10; + retval += (*cp) - '0'; + cp++; + } + return(retval); +} +#endif + +#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) +static void +rpx_brate(bd_t *bd, u_char *cp) +{ + uint rate; + + rate = 0; + + while (*cp != '\n') { + rate *= 10; + rate += (*cp) - '0'; + cp++; + } + + bd->bi_baudrate = rate * 100; +} + +static void +rpx_cpuspeed(bd_t *bd, u_char *cp) +{ + uint num, den; + + num = den = 0; + + while (*cp != '\n') { + num *= 10; + num += (*cp) - '0'; + cp++; + if (*cp == '/') { + cp++; + den = (*cp) - '0'; + break; + } + } + + /* I don't know why the RPX just can't state the actual + * CPU speed..... + */ + if (den) { + num /= den; + num *= den; + } + bd->bi_intfreq = bd->bi_busfreq = num * 1000000; + + /* The 8xx can only run a maximum 50 MHz bus speed (until + * Motorola changes this :-). Greater than 50 MHz parts + * run internal/2 for bus speed. + */ + if (num > 50) + bd->bi_busfreq /= 2; +} +#endif + +#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || defined(CONFIG_EP405) +static void +rpx_memsize(bd_t *bd, u_char *cp) +{ + uint size; + + size = 0; + + while (*cp != '\n') { + size *= 10; + size += (*cp) - '0'; + cp++; + } + + bd->bi_memsize = size * 1024 * 1024; +} +#endif /* LITE || CLASSIC || EP405 */ +#if defined(CONFIG_EP405) +static void +rpx_nvramsize(bd_t *bd, u_char *cp) +{ + uint size; + + size = 0; + + while (*cp != '\n') { + size *= 10; + size += (*cp) - '0'; + cp++; + } + + bd->bi_nvramsize = size * 1024; +} +#endif /* CONFIG_EP405 */ + +#endif /* Embedded Planet boards */ + +#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) + +/* Read the EEPROM on the RPX-Lite board. +*/ +void +embed_config(bd_t **bdp) +{ + u_char eebuf[256], *cp; + bd_t *bd; + + /* Read the first 256 bytes of the EEPROM. I think this + * is really all there is, and I hope if it gets bigger the + * info we want is still up front. + */ + bd = &bdinfo; + *bdp = bd; + +#if 1 + iic_read(0xa8, eebuf, 0, 128); + iic_read(0xa8, &eebuf[128], 128, 128); + + /* We look for two things, the Ethernet address and the + * serial baud rate. The records are separated by + * newlines. + */ + cp = eebuf; + for (;;) { + if (*cp == 'E') { + cp++; + if (*cp == 'A') { + cp += 2; + rpx_eth(bd, cp); + } + } + if (*cp == 'S') { + cp++; + if (*cp == 'B') { + cp += 2; + rpx_brate(bd, cp); + } + } + if (*cp == 'D') { + cp++; + if (*cp == '1') { + cp += 2; + rpx_memsize(bd, cp); + } + } + if (*cp == 'H') { + cp++; + if (*cp == 'Z') { + cp += 2; + rpx_cpuspeed(bd, cp); + } + } + + /* Scan to the end of the record. + */ + while ((*cp != '\n') && (*cp != 0xff)) + cp++; + + /* If the next character is a 0 or ff, we are done. + */ + cp++; + if ((*cp == 0) || (*cp == 0xff)) + break; + } + bd->bi_memstart = 0; +#else + /* For boards without initialized EEPROM. + */ + bd->bi_memstart = 0; + bd->bi_memsize = (8 * 1024 * 1024); + bd->bi_intfreq = 48000000; + bd->bi_busfreq = 48000000; + bd->bi_baudrate = 9600; +#endif +} +#endif /* RPXLITE || RPXCLASSIC */ + +#ifdef CONFIG_BSEIP +/* Build a board information structure for the BSE ip-Engine. + * There is more to come since we will add some environment + * variables and a function to read them. + */ +void +embed_config(bd_t **bdp) +{ + u_char *cp; + int i; + bd_t *bd; + + bd = &bdinfo; + *bdp = bd; + + /* Baud rate and processor speed will eventually come + * from the environment variables. + */ + bd->bi_baudrate = 9600; + + /* Get the Ethernet station address from the Flash ROM. + */ + cp = (u_char *)0xfe003ffa; + for (i=0; i<6; i++) { + bd->bi_enetaddr[i] = *cp++; + } + + /* The rest of this should come from the environment as well. + */ + bd->bi_memstart = 0; + bd->bi_memsize = (16 * 1024 * 1024); + bd->bi_intfreq = 48000000; + bd->bi_busfreq = 48000000; +} +#endif /* BSEIP */ + +#ifdef CONFIG_FADS +/* Build a board information structure for the FADS. + */ +void +embed_config(bd_t **bdp) +{ + u_char *cp; + int i; + bd_t *bd; + + bd = &bdinfo; + *bdp = bd; + + /* Just fill in some known values. + */ + bd->bi_baudrate = 9600; + + /* Use default enet. + */ + cp = (u_char *)def_enet_addr; + for (i=0; i<6; i++) { + bd->bi_enetaddr[i] = *cp++; + } + + bd->bi_memstart = 0; + bd->bi_memsize = (8 * 1024 * 1024); + bd->bi_intfreq = 40000000; + bd->bi_busfreq = 40000000; +} +#endif /* FADS */ + +#ifdef CONFIG_8260 +/* Compute 8260 clock values if the rom doesn't provide them. + */ +static unsigned char bus2core_8260[] = { +/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, 2, + 6, 5, 13, 2, 14, 4, 15, 2, 3, 11, 8, 10, 16, 12, 7, 2, +}; + +static void +clk_8260(bd_t *bd) +{ + uint scmr, vco_out, clkin; + uint plldf, pllmf, corecnf; + volatile cpm2_map_t *ip; + + ip = (cpm2_map_t *)CPM_MAP_ADDR; + scmr = ip->im_clkrst.car_scmr; + + /* The clkin is always bus frequency. + */ + clkin = bd->bi_busfreq; + + /* Collect the bits from the scmr. + */ + plldf = (scmr >> 12) & 1; + pllmf = scmr & 0xfff; + corecnf = (scmr >> 24) &0x1f; + + /* This is arithmetic from the 8260 manual. + */ + vco_out = clkin / (plldf + 1); + vco_out *= 2 * (pllmf + 1); + bd->bi_vco = vco_out; /* Save for later */ + + bd->bi_cpmfreq = vco_out / 2; /* CPM Freq, in MHz */ + bd->bi_intfreq = bd->bi_busfreq * bus2core_8260[corecnf] / 2; + + /* Set Baud rate divisor. The power up default is divide by 16, + * but we set it again here in case it was changed. + */ + ip->im_clkrst.car_sccr = 1; /* DIV 16 BRG */ + bd->bi_brgfreq = vco_out / 16; +} + +static unsigned char bus2core_8280[] = { +/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, 2, + 6, 5, 13, 2, 14, 2, 15, 2, 3, 2, 2, 2, 16, 2, 2, 2, +}; + +static void +clk_8280(bd_t *bd) +{ + uint scmr, main_clk, clkin; + uint pllmf, corecnf; + volatile cpm2_map_t *ip; + + ip = (cpm2_map_t *)CPM_MAP_ADDR; + scmr = ip->im_clkrst.car_scmr; + + /* The clkin is always bus frequency. + */ + clkin = bd->bi_busfreq; + + /* Collect the bits from the scmr. + */ + pllmf = scmr & 0xf; + corecnf = (scmr >> 24) & 0x1f; + + /* This is arithmetic from the 8280 manual. + */ + main_clk = clkin * (pllmf + 1); + + bd->bi_cpmfreq = main_clk / 2; /* CPM Freq, in MHz */ + bd->bi_intfreq = bd->bi_busfreq * bus2core_8280[corecnf] / 2; + + /* Set Baud rate divisor. The power up default is divide by 16, + * but we set it again here in case it was changed. + */ + ip->im_clkrst.car_sccr = (ip->im_clkrst.car_sccr & 0x3) | 0x1; + bd->bi_brgfreq = main_clk / 16; +} +#endif + +#ifdef CONFIG_SBC82xx +void +embed_config(bd_t **bdp) +{ + u_char *cp; + int i; + bd_t *bd; + unsigned long pvr; + + bd = *bdp; + + bd = &bdinfo; + *bdp = bd; + bd->bi_baudrate = 9600; + bd->bi_memsize = 256 * 1024 * 1024; /* just a guess */ + + cp = (void*)SBC82xx_MACADDR_NVRAM_SCC1; + memcpy(bd->bi_enetaddr, cp, 6); + + /* can busfreq be calculated? */ + pvr = mfspr(SPRN_PVR); + if ((pvr & 0xffff0000) == 0x80820000) { + bd->bi_busfreq = 100000000; + clk_8280(bd); + } else { + bd->bi_busfreq = 66000000; + clk_8260(bd); + } + +} +#endif /* SBC82xx */ + +#if defined(CONFIG_EST8260) || defined(CONFIG_TQM8260) +void +embed_config(bd_t **bdp) +{ + u_char *cp; + int i; + bd_t *bd; + + bd = *bdp; +#if 0 + /* This is actually provided by my boot rom. I have it + * here for those people that may load the kernel with + * a JTAG/COP tool and not the rom monitor. + */ + bd->bi_baudrate = 115200; + bd->bi_intfreq = 200000000; + bd->bi_busfreq = 66666666; + bd->bi_cpmfreq = 66666666; + bd->bi_brgfreq = 33333333; + bd->bi_memsize = 16 * 1024 * 1024; +#else + /* The boot rom passes these to us in MHz. Linux now expects + * them to be in Hz. + */ + bd->bi_intfreq *= 1000000; + bd->bi_busfreq *= 1000000; + bd->bi_cpmfreq *= 1000000; + bd->bi_brgfreq *= 1000000; +#endif + + cp = (u_char *)def_enet_addr; + for (i=0; i<6; i++) { + bd->bi_enetaddr[i] = *cp++; + } +} +#endif /* EST8260 */ + +#ifdef CONFIG_SBS8260 +void +embed_config(bd_t **bdp) +{ + u_char *cp; + int i; + bd_t *bd; + + /* This should provided by the boot rom. + */ + bd = &bdinfo; + *bdp = bd; + bd->bi_baudrate = 9600; + bd->bi_memsize = 64 * 1024 * 1024; + + /* Set all of the clocks. We have to k |