diff options
Diffstat (limited to 'arch/powerpc')
103 files changed, 6144 insertions, 1855 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 10a0a5488a4..2ba14e77296 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -414,6 +414,10 @@ config ARCH_SPARSEMEM_DEFAULT config ARCH_POPULATES_NODE_MAP def_bool y +config SYS_SUPPORTS_HUGETLBFS + def_bool y + depends on PPC_BOOK3S_64 + source "mm/Kconfig" config ARCH_MEMORY_PROBE diff --git a/arch/powerpc/boot/addRamDisk.c b/arch/powerpc/boot/addRamDisk.c index c02a99952be..893f446cbd2 100644 --- a/arch/powerpc/boot/addRamDisk.c +++ b/arch/powerpc/boot/addRamDisk.c @@ -58,7 +58,7 @@ static int check_elf64(void *p, int size, struct addr_range *r) return 64; } -void get4k(FILE *file, char *buf ) +static void get4k(FILE *file, char *buf ) { unsigned j; unsigned num = fread(buf, 1, 4096, file); @@ -66,12 +66,12 @@ void get4k(FILE *file, char *buf ) buf[j] = 0; } -void put4k(FILE *file, char *buf ) +static void put4k(FILE *file, char *buf ) { fwrite(buf, 1, 4096, file); } -void death(const char *msg, FILE *fdesc, const char *fname) +static void death(const char *msg, FILE *fdesc, const char *fname) { fprintf(stderr, msg); fclose(fdesc); diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts index cee8080aa24..dd3860846f1 100644 --- a/arch/powerpc/boot/dts/cm5200.dts +++ b/arch/powerpc/boot/dts/cm5200.dts @@ -210,7 +210,6 @@ compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d40 0x40>; interrupts = <2 16 0>; - fsl5200-clocking; }; sram@8000 { diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts index 4c36186ef94..8e9be6bfe23 100644 --- a/arch/powerpc/boot/dts/digsy_mtc.dts +++ b/arch/powerpc/boot/dts/digsy_mtc.dts @@ -199,7 +199,6 @@ compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d00 0x40>; interrupts = <2 15 0>; - fsl5200-clocking; rtc@50 { compatible = "at,24c08"; diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts index de30b3f9eb2..82ff2b13bc3 100644 --- a/arch/powerpc/boot/dts/lite5200.dts +++ b/arch/powerpc/boot/dts/lite5200.dts @@ -247,7 +247,6 @@ compatible = "fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d00 0x40>; interrupts = <2 15 0>; - fsl5200-clocking; }; i2c@3d40 { @@ -256,7 +255,6 @@ compatible = "fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d40 0x40>; interrupts = <2 16 0>; - fsl5200-clocking; }; sram@8000 { compatible = "fsl,mpc5200-sram"; diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts index d13cb11ce62..e45a63be3a8 100644 --- a/arch/powerpc/boot/dts/lite5200b.dts +++ b/arch/powerpc/boot/dts/lite5200b.dts @@ -251,7 +251,6 @@ compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d00 0x40>; interrupts = <2 15 0>; - fsl5200-clocking; }; i2c@3d40 { @@ -260,7 +259,6 @@ compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d40 0x40>; interrupts = <2 16 0>; - fsl5200-clocking; }; sram@8000 { diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts index e297d8b4187..0c3902bc5b6 100644 --- a/arch/powerpc/boot/dts/media5200.dts +++ b/arch/powerpc/boot/dts/media5200.dts @@ -223,7 +223,6 @@ compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d00 0x40>; interrupts = <2 15 0>; - fsl5200-clocking; }; i2c@3d40 { @@ -232,7 +231,6 @@ compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d40 0x40>; interrupts = <2 16 0>; - fsl5200-clocking; }; sram@8000 { diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts index 7be8ca03867..6ca4fc144a3 100644 --- a/arch/powerpc/boot/dts/motionpro.dts +++ b/arch/powerpc/boot/dts/motionpro.dts @@ -222,7 +222,6 @@ compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d40 0x40>; interrupts = <2 16 0>; - fsl5200-clocking; rtc@68 { compatible = "dallas,ds1339"; diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts index c2b8dbfab79..c353dac3341 100644 --- a/arch/powerpc/boot/dts/mpc5121ads.dts +++ b/arch/powerpc/boot/dts/mpc5121ads.dts @@ -209,7 +209,6 @@ reg = <0x1700 0x20>; interrupts = <9 0x8>; interrupt-parent = < &ipic >; - fsl5200-clocking; }; i2c@1720 { @@ -220,7 +219,6 @@ reg = <0x1720 0x20>; interrupts = <10 0x8>; interrupt-parent = < &ipic >; - fsl5200-clocking; }; i2c@1740 { @@ -231,7 +229,6 @@ reg = <0x1740 0x20>; interrupts = <11 0x8>; interrupt-parent = < &ipic >; - fsl5200-clocking; }; i2ccontrol@1760 { diff --git a/arch/powerpc/boot/dts/mpc8377_wlan.dts b/arch/powerpc/boot/dts/mpc8377_wlan.dts index 9a603695723..9ea78305696 100644 --- a/arch/powerpc/boot/dts/mpc8377_wlan.dts +++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts @@ -67,7 +67,7 @@ device-width = <1>; partition@0 { - reg = <0 0x8000>; + reg = <0 0x80000>; label = "u-boot"; read-only; }; diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts index 06332d61830..1e3ec8f059b 100644 --- a/arch/powerpc/boot/dts/mpc8569mds.dts +++ b/arch/powerpc/boot/dts/mpc8569mds.dts @@ -487,8 +487,8 @@ &qe_pio_f 5 0 /* USBTN */ &qe_pio_f 6 0 /* USBRP */ &qe_pio_f 8 0 /* USBRN */ - &bcsr17 6 0 /* SPEED */ - &bcsr17 5 1>; /* POWER */ + &bcsr17 1 0 /* SPEED */ + &bcsr17 2 0>; /* POWER */ }; enet0: ucc@2000 { diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts new file mode 100644 index 00000000000..b72a7581d79 --- /dev/null +++ b/arch/powerpc/boot/dts/mucmc52.dts @@ -0,0 +1,332 @@ +/* + * Manroland mucmc52 board Device Tree Source + * + * Copyright (C) 2009 DENX Software Engineering GmbH + * Heiko Schocher <hs@denx.de> + * Copyright 2006-2007 Secret Lab Technologies Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "manroland,mucmc52"; + compatible = "manroland,mucmc52"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&mpc5200_pic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,5200@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x4000>; // L1, 16K + i-cache-size = <0x4000>; // L1, 16K + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x04000000>; // 64MB + }; + + soc5200@f0000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc5200b-immr"; + ranges = <0 0xf0000000 0x0000c000>; + reg = <0xf0000000 0x00000100>; + bus-frequency = <0>; // from bootloader + system-frequency = <0>; // from bootloader + + cdm@200 { + compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; + reg = <0x200 0x38>; + }; + + mpc5200_pic: interrupt-controller@500 { + // 5200 interrupts are encoded into two levels; + interrupt-controller; + #interrupt-cells = <3>; + compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; + reg = <0x500 0x80>; + }; + + gpt0: timer@600 { // GPT 0 in GPIO mode + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + reg = <0x600 0x10>; + interrupts = <1 9 0>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpt1: timer@610 { // General Purpose Timer in GPIO mode + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + reg = <0x610 0x10>; + interrupts = < |