diff options
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/apm82181-adma.h | 309 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/async_tx.h | 88 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/dcr-regs.h | 237 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/mmio-regs.h | 61 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/ppc460ex_adma.h | 186 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/ppc460ex_dma.h | 262 | ||||
| -rwxr-xr-x | arch/powerpc/include/asm/ppc460ex_plb_adma.h | 575 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/ppc460ex_xor.h | 147 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/ppc4xx_cpm.h | 82 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/ppc4xx_ocm.h | 48 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 2 |
11 files changed, 1996 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/apm82181-adma.h b/arch/powerpc/include/asm/apm82181-adma.h new file mode 100644 index 00000000000..b16014b8c07 --- /dev/null +++ b/arch/powerpc/include/asm/apm82181-adma.h @@ -0,0 +1,309 @@ +/* + * 2009-2010 (C) Applied Micro Circuits Corporation. + * + * Author: Tai Tri Nguyen<ttnguyen@appliedmicro.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of + * any kind, whether express or implied. + */ + +#ifndef APM82181_ADMA_H +#define APM82181_ADMA_H + + +#include <linux/types.h> + + +#define to_apm82181_adma_chan(chan) container_of(chan,apm82181_ch_t,common) +#define to_apm82181_adma_device(dev) container_of(dev,apm82181_dev_t,common) +#define tx_to_apm82181_adma_slot(tx) container_of(tx,apm82181_desc_t,async_tx) + +#define APM82181_DMA_PROC_ROOT "driver/apm82181_adma" + +/* Number of operands supported in the h/w */ +#define XOR_MAX_OPS 16 +/* this is the XOR_CBBCR width */ +#define APM82181_ADMA_XOR_MAX_BYTE_COUNT (1 << 31) +#define APM82181_ADMA_DMA_MAX_BYTE_COUNT 1024 * 1024 +#define MAX_APM82181_DMA_CHANNELS 5 +#define APM82181_ADMA_THRESHOLD 1 + +#define APM82181_PDMA0_ID 0 +#define APM82181_PDMA1_ID 1 +#define APM82181_PDMA2_ID 2 +#define APM82181_PDMA3_ID 3 +#define APM82181_XOR_ID 4 + +/* DMA 0/1/2/3 registers */ +#define DCR_DMAx_BASE(x) (0x200 + x*0x8) /* DMA DCR base */ +#define DCR_DMA2P40_CRx(x) (DCR_DMAx_BASE(x) + 0x0) /* DMA Channel Control */ +#define DMA_CR_CE (1 << 31) +#define DMA_CR_CIE (1 << 30) +#define DMA_CR_PL (1 << 28) +#define DMA_CR_PW_128 0x08000000 +#define DMA_CR_DAI 0x01000000 +#define DMA_CR_SAI 0x00800000 +#define DMA_CR_BEN 0x00400000 +#define DMA_CR_TM_S_MM 0x00300000 +#define DMA_CR_ETD 0x00000100 +#define DMA_CR_TCE 0x00000080 +#define DMA_CR_CP(x) (x<<5)& 0x00000060 +#define DMA_CR_DEC (1 << 2) +#define DMA_CR_SL (1 << 1) +#define DCR_DMA2P40_CTCx(x) (DCR_DMAx_BASE(x) + 0x1) /* DMA Count 0 */ +#define DMA_CTC_ETIE (1 << 28) +#define DMA_CTC_EIE (1 << 27) +#define DMA_CTC_PCE (1 << 20) +#define DMA_CTC_TC_MASK 0x000fffff +#define DCR_DMA2P40_SAHx(x) (DCR_DMAx_BASE(x) + 0x2) /* DMA Src Addr High 0 */ +#define DCR_DMA2P40_SALx(x) (DCR_DMAx_BASE(x) + 0x3) /* DMA Src Addr Low 0 */ +#define DCR_DMA2P40_DAHx(x) (DCR_DMAx_BASE(x) + 0x4) /* DMA Dest Addr High 0 */ +#define DCR_DMA2P40_DALx(x) (DCR_DMAx_BASE(x) + 0x5) /* DMA Dest Addr Low 0 */ +#define DCR_DMA2P40_SGHx(x) (DCR_DMAx_BASE(x) + 0x6) /* DMA SG Desc Addr High 0 */ +#define DCR_DMA2P40_SGLx(x) (DCR_DMAx_BASE(x) + 0x7) /* DMA SG Desc Addr Low 0 */ +/* DMA Status Register */ +#define DCR_DMA2P40_SR 0x220 +#define DMA_SR_CS(x) (1 << (31 -x)) +#define DMA_SR_TS(x) (1 << (27 -x)) +#define DMA_SR_RI(x) (1 << (23 -x)) +#define DMA_SR_IR(x) (1 << (19 -x)) +#define DMA_SR_ER(x) (1 << (15 -x)) +#define DMA_SR_CB(x) (1 << (11 -x)) +#define DMA_SR_SG(x) (1 << (7 -x)) +/* S/G registers */ +#define DCR_DMA2P40_SGC 0x223 +#define DMA_SGC_SSG(x) ( 1 << (31 - x)) +#define DMA_SGC_SGL(x,y) ( y << (27 - x)) /* x: channel; y: 0 PLB, 1 OPB*/ +#define DMA_SGC_EM(x) ( 1 << (15 - x)) +#define DMA_SGC_EM_ALL 0x0000F000 + +/* + * XOR Command Block Control Register bits + */ +#define XOR_CBCR_LNK_BIT (1<<31) /* link present */ +#define XOR_CBCR_TGT_BIT (1<<30) /* target present */ +#define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */ +#define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */ +#define XOR_CBCR_XNOR_BIT (1<<15) /* XOR/XNOR */ +#define XOR_CDCR_OAC_MSK (0x7F) /* operand address count */ + +/* + * XORCore Status Register bits + */ +#define XOR_SR_XCP_BIT (1<<31) /* core processing */ +#define XOR_SR_ICB_BIT (1<<17) /* invalid CB */ +#define XOR_SR_IC_BIT (1<<16) /* invalid command */ +#define XOR_SR_IPE_BIT (1<<15) /* internal parity error */ +#define XOR_SR_RNZ_BIT (1<<2) /* result not Zero */ +#define XOR_SR_CBC_BIT (1<<1) /* CB complete */ +#define XOR_SR_CBLC_BIT (1<<0) /* CB list complete */ + +/* + * XORCore Control Set and Reset Register bits + */ +#define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */ +#define XOR_CRSR_XAE_BIT (1<<30) /* enable */ +#define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */ +#define XOR_CRSR_PAUS_BIT (1<<28) /* pause */ +#define XOR_CRSR_64BA_BIT (1<<27) /* 64/32 CB format */ +#define XOR_CRSR_CLP_BIT (1<<25) /* continue list processing */ + +/* + * XORCore Interrupt Enable Register + */ +#define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block Interrupt Enable */ +#define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command Interrupt Enable */ +#define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error Interrupt Enable */ +#define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */ +#define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */ + +typedef struct apm82181_plb_dma4_device { + struct resource reg; /* Resource for register */ + void __iomem *reg_base; + struct of_device *ofdev; + struct device *dev; +} apm82181_plb_dma_t; + +/** + * struct apm82181_dma_device - internal representation of an DMA device + * @id: HW DMA Device selector + * @ofdev: OF device + * @dcr_base: dcr base of HW PLB DMA channels + * @reg_base: base of ADMA XOR channel + * @dma_desc_pool: base of DMA descriptor region (DMA address) + * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) + * @pool_size: memory pool size for the channel device + * @common: embedded struct dma_device + * @cap_mask: capabilities of ADMA channels + */ +typedef struct apm82181_plb_dma_device { + int id; + struct of_device *ofdev; + u32 dcr_base; + void __iomem *xor_base; + struct device *dev; + struct dma_device common; + struct apm82181_plb_dma4_device *pdma; + void *dma_desc_pool_virt; + u32 pool_size; + dma_addr_t dma_desc_pool; + dma_cap_mask_t cap_mask; +} apm82181_dev_t; + +/** + * struct apm82181_dma_chan - internal representation of an ADMA channel + * @lock: serializes enqueue/dequeue operations to the slot pool + * @device: parent device + * @chain: device chain view of the descriptors + * @common: common dmaengine channel object members + * @all_slots: complete domain of slots usable by the channel + * @reg: Resource for register + * @pending: allows batching of hardware operations + * @completed_cookie: identifier for the most recently completed operation + * @slots_allocated: records the actual size of the descriptor slot pool + * @hw_chain_inited: h/w descriptor chain initialization flag + * @irq_tasklet: bottom half where apm82181_adma_slot_cleanup runs + * @needs_unmap: if buffers should not be unmapped upon final processing + */ +typedef struct apm82181_plb_dma_chan { + spinlock_t lock; + struct apm82181_plb_dma_device *device; + struct timer_list cleanup_watchdog; + struct list_head chain; + struct dma_chan common; + struct list_head all_slots; + struct apm82181_adma_plb_desc_slot *last_used; + int pending; + dma_cookie_t completed_cookie; + int slots_allocated; + int hw_chain_inited; + struct tasklet_struct irq_tasklet; + u8 needs_unmap; + phys_addr_t current_cdb_addr; +} apm82181_ch_t; + +typedef struct apm82181_adma_plb_desc_slot { + dma_addr_t phys; + struct apm82181_adma_plb_desc_slot *group_head; + struct apm82181_adma_plb_desc_slot *hw_next; + struct dma_async_tx_descriptor async_tx; + struct list_head slot_node; + struct list_head chain_node; + struct list_head group_list; + unsigned int unmap_len; + void *hw_desc; + u16 stride; + u16 idx; + u16 slot_cnt; + u8 src_cnt; + u8 dst_cnt; + u8 slots_per_op; + u8 descs_per_op; + unsigned long flags; + unsigned long reverse_flags[8]; +#define APM82181_DESC_INT 0 /* generate interrupt on complete */ + +}apm82181_desc_t; + +typedef struct { + u32 ce:1; + u32 cie:1; + u32 td:1; + u32 pl:1; + u32 pw:3; + u32 dai:1; + u32 sai:1; + u32 ben:1; + u32 tm:2; + u32 psc:2; + u32 pwc:6; + u32 phc:3; + u32 etd:1; + u32 tce:1; + u32 cp:2; + u32 pf:2; + u32 dec:1; + u32 sl:1; + u32 reserved:1; +} __attribute__((packed)) dma_cdb_ctrl_t; + +typedef struct { + u32 link:1; + u32 sgl:1; + u32 tcie:1; + u32 etie:1; + u32 eie:1; + u32 sid:3; + u32 bten:1; + u32 bsiz:2; + u32 pce:1; + u32 tc:20; +} __attribute__((packed)) dma_cdb_count_t; +/* scatter/gather descriptor struct */ +typedef struct dma_cdb { + dma_cdb_ctrl_t ctrl; + dma_cdb_count_t cnt; + u32 src_hi; + u32 src_lo; + u32 dest_hi; + u32 dest_lo; + u32 sg_hi; + u32 sg_lo; +}dma_cdb_t; + +typedef struct { + uint32_t control; + phys_addr_t src_addr; + phys_addr_t dst_addr; + uint32_t control_count; + uint32_t next; +} ppc_sgl_t; + +/* + * XOR Accelerator engine Command Block Type + */ +typedef struct { + /* + * Basic 64-bit format XOR CB + */ + u32 cbc; /* control */ + u32 cbbc; /* byte count */ + u32 cbs; /* status */ + u8 pad0[4]; /* reserved */ + u32 cbtah; /* target address high */ + u32 cbtal; /* target address low */ + u32 cblah; /* link address high */ + u32 cblal; /* link address low */ + struct { + u32 h; + u32 l; + } __attribute__ ((packed)) ops [16]; +} __attribute__ ((packed)) xor_cb_t; + +/* + * XOR hardware registers + */ +typedef struct { + u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */ + u8 pad0[352]; /* reserved */ + u32 cbcr; /* CB control register */ + u32 cbbcr; /* CB byte count register */ + u32 cbsr; /* CB status register */ + u8 pad1[4]; /* reserved */ + u32 cbtahr; /* operand target address high register */ + u32 cbtalr; /* operand target address low register */ + u32 cblahr; /* CB link address high register */ + u32 cblalr; /* CB link address low register */ + u32 crsr; /* control set register */ + u32 crrr; /* control reset register */ + u32 ccbahr; /* current CB address high register */ + u32 ccbalr; /* current CB address low register */ + u32 plbr; /* PLB configuration register */ + u32 ier; /* interrupt enable register */ + u32 pecr; /* parity error count register */ + u32 sr; /* status register */ + u32 revidr; /* revision ID register */ +} xor_regs_t; + +#endif diff --git a/arch/powerpc/include/asm/async_tx.h b/arch/powerpc/include/asm/async_tx.h new file mode 100644 index 00000000000..6b49cf1f702 --- /dev/null +++ b/arch/powerpc/include/asm/async_tx.h @@ -0,0 +1,88 @@ +/* + * Copyright(c) 2008 DENX Engineering. All rights reserved. + * + * Author: Yuri Tikhonov <yur@emcraft.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * The full GNU General Public License is included in this distribution in the + * file called COPYING. + */ +#ifndef _PPC_ASYNC_TX_H_ +#define _PPC_ASYNC_TX_H_ + +#if defined(CONFIG_440SPe) || defined(CONFIG_440SP) +extern int ppc440spe_adma_estimate (struct dma_chan *chan, + enum dma_transaction_type cap, struct page **src_lst, + int src_cnt, size_t src_sz); +#define ppc_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) \ + ppc440spe_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +extern int ppc460ex_adma_estimate (struct dma_chan *chan, + enum dma_transaction_type cap, struct page **src_lst, + int src_cnt, size_t src_sz); +#define ppc_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) \ + ppc460ex_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) +#elif defined(CONFIG_APM82181) +extern int apm82181_adma_estimate (struct dma_chan *chan, + enum dma_transaction_type cap, struct page **src_lst, + int src_cnt, size_t src_sz); +#define ppc_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) \ + apm82181_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) +#endif + +struct ppc_dma_chan_ref { + struct dma_chan *chan; + struct list_head node; +}; + +extern struct list_head ppc_adma_chan_list; + +/** + * ppc_async_tx_find_best_channel - find a channel with the maximum rank for the + * transaction type given (the rank of the operation is the value + * returned by the device_estimate method). + * @cap: transaction type + * @src_lst: array of pointers to sources for the transaction + * @src_cnt: number of arguments (size of the srcs array) + * @src_sz: length of the each argument pointed by srcs + */ +static inline struct dma_chan * +ppc_async_tx_find_best_channel (enum dma_transaction_type cap, + struct page **src_lst, int src_cnt, size_t src_sz) +{ + struct dma_chan *best_chan = NULL; + struct ppc_dma_chan_ref *ref; + int best_rank = -1; + + list_for_each_entry(ref, &ppc_adma_chan_list, node) + if (dma_has_cap(cap, ref->chan->device->cap_mask)) { + int rank; + + rank = ppc_adma_estimate (ref->chan, + cap, src_lst, src_cnt, src_sz); + if (rank > best_rank) { + best_rank = rank; + best_chan = ref->chan; + } + } + + return best_chan; +} + +#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \ + ppc_async_tx_find_best_channel(type, src, src_count, len) + +#endif diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h index 828e3aa1f2f..7e15ef98b69 100644 --- a/arch/powerpc/include/asm/dcr-regs.h +++ b/arch/powerpc/include/asm/dcr-regs.h @@ -28,10 +28,53 @@ #define DCRN_CPR0_CONFIG_ADDR 0xc #define DCRN_CPR0_CONFIG_DATA 0xd -/* SDRs (440GX and 440SP/440SPe) */ +#define CPR0_CLKUPD 0x0020 +#define CPR0_CLKUPD_CUD 0x80000000 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLC_ENG 0x40000000 +#define CPR0_PLLD 0x0060 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CPR0_PLBED 0x0080 +#define CPR0_PLBED_DIV1 0x01000000 +#define CPR0_PLBED_DIV2 0x02000000 +#define CPR0_PLBED_DIV3 0x03000000 +#define CPR0_PLBED_DIV4 0x04000000 +#define CPR0_PLBED_DIV5 0x05000000 +#define CPR0_PLBED_DIV6 0x06000000 +#define CPR0_PLBED_DIV7 0x07000000 +#endif +#if defined(CONFIG_APM82181) || defined(CONFIG_APM82161) +#define CPR0_DDR2D 0x0100 +#define CPR0_DDR2D_DIV1 0x02000000 +#endif +#define CPR0_PLB2D 0x00a0 +#define CPR0_PLB2D_DIV1 0x02000000 + +#define CPR0_OPBD 0x00c0 +#define CPR0_OPBD_DIV1 0x01000000 +#define CPR0_OPBD_DIV2 0x02000000 +#define CPR0_OPBD_DIV3 0x03000000 +#define CPR0_PERD 0x00e0 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CPR0_AHBD 0x0100 +#define CPR0_AHBD_DIV1 0x01000000 +#endif +#define CPR0_ICFG 0x0140 + +/* SDRs (440GX, 440SP, 440SPe 460EX and 460GT) */ #define DCRN_SDR0_CONFIG_ADDR 0xe #define DCRN_SDR0_CONFIG_DATA 0xf +#define SDR0_SRST0 0x0200 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || defined(CONFIG_APM82181)\ + || defined(CONFIG_APM82161) + +#define SDR0_SRST_I2ODMA (0x80000000 >> 15) /* Reset I2O/DMA */ +#define SDR0_SRST0_DMC 0x00200000 +#define SDR0_SRST0_L2C 0x00000004 +#define SDR0_SRST0_UART0 0x80000000 +#endif +#define SDR0_SRST1 0x0201 #define SDR0_PFC0 0x4100 #define SDR0_PFC1 0x4101 #define SDR0_PFC1_EPS 0x1c00000 @@ -75,6 +118,77 @@ #define ICINTSTAT_ICTX1 0x20000000 #define ICINTSTAT_ICTX 0x60000000 +/* SDR read/write helper macros */ +#define SDR_READ(offset) ({\ + mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \ + mfdcr(DCRN_SDR0_CONFIG_DATA);}) +#define SDR_WRITE(offset, data) ({\ + mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \ + mtdcr(DCRN_SDR0_CONFIG_DATA,data);}) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + /* I2O DMA registers*/ + #define DCRN_I2O0_IBAL 0x066 + #define DCRN_I2O0_IBAH 0x067 + + /* 460EX/GT XOR DCRs */ + #define DCRN_MQ0_XORBA 0x44 + #define DCRN_MQ0_CF1H 0x45 + #define DCRN_MQ0_CF2H 0x46 + #define DCRN_MQ0_BAUL 0x4a + #define DCRN_MQ0_CF1L 0x4b + #define DCRN_MQ0_CFBHL 0x4f + #define DCRN_MQ0_BAUH 0x50 + + /* RXOR BlockSize Register */ + #define MQ0_CF2H_RXOR_BS_MASK 0xfffffe00 + + /* HB/LL Paths Configuration Register */ + #define MQ0_CFBHL_TPLM 28 + #define MQ0_CFBHL_HBCL 23 + #define MQ0_CFBHL_POLY 15 + + + + #define MQ_CF1_AAFR 31 + #define MQ_CF1_RPLM 12 + #define MQ_CF1_RPEN 11 + #define MQ_CF1_RFTE 10 + #define MQ_CF1_WRCL 7 + /* MQ HB/LL Configuration masks & shifts */ + #define MQ_CF1_RPLM_MSK 0xF + #define MQ_CF1_WRCL_MSK 0x7 + /* HB/LL Paths Configuration Register */ + #define MQ0_CFBHL_TPLM 28 + #define MQ0_CFBHL_HBCL 23 + #define MQ0_CFBHL_POLY 15 + + /* 460EX/460GT PLB Arbiter DCRs */ + #define DCRN_PLB_REVID 0x080 /* PLB Revision ID */ + #define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */ + + #define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */ + #define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */ + #define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */ + #define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */ + #define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */ + + #define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */ + #define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */ + #define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */ + #define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */ + #define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */ + + /* PLB0/1 ACR masks & shifts */ + #define PLB_ACR_RDP_MSK 0x3 + + #define PLB_ACR_PPM0 31 + #define PLB_ACR_PPM1 30 + #define PLB_ACR_PPM3 28 + #define PLB_ACR_HBU 27 + #define PLB_ACR_RDP 25 + #define PLB_ACR_WRP 24 + #endif + /* SDRs (460EX/460GT) */ #define SDR0_ETH_CFG 0x4103 #define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */ @@ -130,6 +244,7 @@ #define L2C_CFG_NAM 0x00000100 #define L2C_CFG_SMCM 0x00000080 #define L2C_CFG_NBRM 0x00000040 +#define L2C_CFG_SNP440 0x00000010 #define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */ #define DCRN_L2C0_CMD 0x01 #define L2C_CMD_CLR 0x80000000 @@ -157,4 +272,124 @@ #define L2C_SNP_SSR_32G 0x0000f000 #define L2C_SNP_ESR 0x00000800 +/* MQ registers (460EX/460GT) */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define MQ0_B0BASE 0x0040 +#define MQ0_B1BASE 0x0041 +#define MQ0_B2BASE 0x0042 +#define MQ0_B3BASE 0x0043 +#define MQ0_CF1H 0x0045 +#define MQ0_BAUL 0x004A +#define MQ0_CF1L 0x004B +#define MQ0_CFBHL 0x004F +#define MQ0_BAUH 0x0050 +#endif /*defined(CONFIG_460EX) || defined(CONFIG_460GT)*/ + +/* DDR registers to (460EX/460GT) */ +#if defined(CONFIG_APM82181) || defined(CONFIG_APM82161) +#define DCRN_SDRAM0_CONFIG_ADDR 0x10 +#define DCRN_SDRAM0_CONFIG_DATA 0x11 + +#define SDRAM0_BESR 0x0000 +#define SDRAM0_BEARL 0x0002 +#define SDRAM0_BEARH 0x0003 +#define SDRAM0_WMIRQ 0x0006 +#define SDRAM0_PLBOPT 0x0008 +#define SDRAM0_PUABA 0x0009 +#define SDRAM0_MCSTAT 0x001F +#define SDRAM0_MCSTAT_MIC 0x80000000 +#define SDRAM0_MCSTAT_SRMS 0x40000000 +#define SDRAM0_MCOPT1 0x0020 +#define SDRAM0_MCOPT2 0x0021 +#define SDRAM0_MCOPT2_SREN 0x80000000 +#define SDRAM0_MCOPT2_IPTR 0x20000000 +#define SDRAM0_MCOPT2_DCEN 0x08000000 +#define SDRAM0_MODT0 0x0022 +#define SDRAM0_MODT1 0x0023 +#define SDRAM0_CODT 0x0026 +#define SDRAM0_RTR 0x0030 +#define SDRAM0_MB0CF 0x0040 +#define SDRAM0_MB1CF 0x0044 +#define SDRAM0_INITPLR0 0x0050 +#define SDRAM0_INITPLR1 0x0051 +#define SDRAM0_INITPLR2 0x0052 +#define SDRAM0_INITPLR3 0x0053 +#define SDRAM0_INITPLR4 0x0054 +#define SDRAM0_INITPLR5 0x0055 +#define SDRAM0_INITPLR6 0x0056 +#define SDRAM0_INITPLR7 0x0057 +#define SDRAM0_INITPLR8 0x0058 +#define SDRAM0_INITPLR9 0x0059 +#define SDRAM0_INITPLR10 0x005A +#define SDRAM0_INITPLR11 0x005B +#define SDRAM0_INITPLR12 0x005C +#define SDRAM0_INITPLR13 0x005D +#define SDRAM0_INITPLR14 0x005E +#define SDRAM0_INITPLR15 0x005F +#define SDRAM0_RQDC 0x0070 +#define SDRAM0_RFDC 0x0074 +#define SDRAM0_RDCC 0x0078 +#define SDRAM0_DLCR 0x007A +#define SDRAM0_CLKTR 0x0080 +#define SDRAM0_WRDTR 0x0081 +#define SDRAM0_SDTR1 0x0085 +#define SDRAM0_SDTR2 0x0086 +#define SDRAM0_SDTR3 0x0087 +#define SDRAM0_MMODE 0x0088 +#define SDRAM0_MEMODE 0x0089 +#define SDRAM0_ECCES 0x0098 +#else + +#define DCRN_MCIF0_CONFIG_ADDR 0x10 +#define DCRN_MCIF0_CONFIG_DATA 0x11 + +#define MCIF0_MCSTAT 0x0014 +#define MCIF0_MCSTAT_MIC 0x80000000 +#define MCIF0_MCSTAT_SRMS 0x40000000 +#define MCIF0_MCOPT1 0x0020 +#define MCIF0_MCOPT2 0x0021 +#define MCIF0_MCOPT2_SREN 0x80000000 +#define MCIF0_MCOPT2_IPTR 0x20000000 +#define MCIF0_MCOPT2_DCEN 0x08000000 +#define MCIF0_MODT0 0x0022 +#define MCIF0_MODT1 0x0023 +#define MCIF0_MODT2 0x0024 +#define MCIF0_MODT3 0x0025 +#define MCIF0_CODT 0x0026 +#define MCIF0_RTR 0x0030 +#define MCIF0_MB0CF 0x0040 +#define MCIF0_MB1CF 0x0044 +#define MCIF0_MB2CF 0x0048 +#define MCIF0_MB3CF 0x004C +#define MCIF0_INITPLR0 0x0050 +#define MCIF0_INITPLR1 0x0051 +#define MCIF0_INITPLR2 0x0052 +#define MCIF0_INITPLR3 0x0053 +#define MCIF0_INITPLR4 0x0054 +#define MCIF0_INITPLR5 0x0055 +#define MCIF0_INITPLR6 0x0056 +#define MCIF0_INITPLR7 0x0057 +#define MCIF0_INITPLR8 0x0058 +#define MCIF0_INITPLR9 0x0059 +#define MCIF0_INITPLR10 0x005A +#define MCIF0_INITPLR11 0x005B +#define MCIF0_INITPLR12 0x005C +#define MCIF0_INITPLR13 0x005D +#define MCIF0_INITPLR14 0x005E +#define MCIF0_INITPLR15 0x005F +#define MCIF0_RQDC 0x0070 +#define MCIF0_RFDC 0x0074 +#define MCIF0_RCDC 0x0078 +#define MCIF0_DLCR 0x007A +#define MCIF0_CLKTR 0x0080 +#define MCIF0_WRDTR 0x0081 +#define MCIF0_SDTR1 0x0085 +#define MCIF0_SDTR2 0x0086 +#define MCIF0_SDTR3 0x0087 +#define MCIF0_MMODE 0x0088 +#define MCIF0_MEMODE 0x0089 +#define MCIF0_ECCES 0x0098 + +#endif /* defined(APM82181) || defined(APM82161) */ + #endif /* __DCR_REGS_H__ */ diff --git a/arch/powerpc/include/asm/mmio-regs.h b/arch/powerpc/include/asm/mmio-regs.h new file mode 100644 index 00000000000..d97f22e67e7 --- /dev/null +++ b/arch/powerpc/include/asm/mmio-regs.h @@ -0,0 +1,61 @@ +/* + * MMIO register definitions used on various IBM/AMCC * 4xx processors + * + * (C) Copyright 2008, Applied Micro Circuits Corporation + * Victor Gallardo (vgallardo@amcc.com) + * + * based on dcr-regs.h + * + * Copyright 2007 Benjamin Herrenschmidt, IBM Corp + * <benh@kernel.crashing.org> + */ + +#ifndef __MMIO_REGS_H__ +#define __MMIO_REGS_H__ + +/* IIC Register offset */ +#define IIC_MDBUF 0x00 +#define IIC_SDBUF 0x02 +#define IIC_LMADR 0x04 +#define IIC_HMADR 0x05 +#define IIC_CNTL 0x06 +#define IIC_MDCNTL 0x07 +#define IIC_STS 0x08 +#define IIC_EXTSTS 0x09 +#define IIC_LSADR 0x0A +#define IIC_HSADR 0x0B +#define IIC_CLKDIV 0x0C +#define IIC_INTRMSK 0x0D +#define IIC_XFRCNT 0x0E +#define IIC_XTCNTLSS 0x0F +#define IIC_DIRECTCNTL 0x10 + +/* STS Register Bit definition */ +#define IIC_STS_PT 0x01 +#define IIC_STS_IRQA 0x02 +#define IIC_STS_ERR 0x04 +#define IIC_STS_SCMP 0x08 +#define IIC_STS_MDBF 0x10 +#define IIC_STS_MDBS 0x20 +#define IIC_STS_SLPR 0x40 +#define IIC_STS_SSS 0x80 + +/* MDCNTL Register Bit definition */ +#define IIC_MDCNTL_HSCL 0x01 +#define IIC_MDCNTL_EUBS 0x02 +#define IIC_MDCNTL_EINT 0x04 +#define IIC_MDCNTL_ESM 0x08 +#define IIC_MDCNTL_FSM 0x10 +#define IIC_MDCNTL_EGC 0x20 +#define IIC_MDCNTL_FMDB 0x40 +#define IIC_MDCNTL_FSDB 0x80 + +/* CNTL Register Bit definition */ +#define IIC_CNTL_PT 0x01 +#define IIC_CNTL_READ 0x02 +#define IIC_CNTL_CHT 0x04 +#define IIC_CNTL_RPST 0x08 +#define IIC_CNTL_AMD 0x40 +#define IIC_CNTL_HMT 0x80 + +#endif /* __MMIO_REGS_H__ */ diff --git a/arch/powerpc/include/asm/ppc460ex_adma.h b/arch/powerpc/include/asm/ppc460ex_adma.h new file mode 100644 index 00000000000..828a62fbe68 --- /dev/null +++ b/arch/powerpc/include/asm/ppc460ex_adma.h @@ -0,0 +1,186 @@ +/* + * 2006-2007 (C) DENX Software Engineering. + * + * Author: Yuri Tikhonov <yur@emcraft.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of + * any kind, whether express or implied. + */ + +#ifndef PPC460EX_ADMA_H +#define PPC460EX_ADMA_H + +#include <linux/types.h> +#include <asm/ppc460ex_dma.h> + +#define to_ppc460ex_adma_chan(chan) container_of(chan,ppc460ex_ch_t,common) +#define to_ppc460ex_adma_device(dev) container_of(dev,ppc460ex_dev_t,common) +#define tx_to_ppc460ex_adma_slot(tx) container_of(tx,ppc460ex_desc_t,async_tx) + +#define PPC460EX_R6_PROC_ROOT "driver/460ex_raid6" +#define PPC460EX_R5_PROC_ROOT "driver/460ex_raid5" +/* Default polynomial (for 440SP is only available) */ +#define PPC460EX_DEFAULT_POLY 0x4d + +#define PPC460EX_ADMA_WATCHDOG_MSEC 3 +#define PPC460EX_ADMA_THRESHOLD 1 +#define ADMA_DESC_MEM_OCM 0x1 + +#define PPC460EX_DMA0_ID 0 +#define PPC460EX_DMA1_ID 1 +#define PPC460EX_XOR_ID 2 + +#define PPC460EX_ADMA_DMA_MAX_BYTE_COUNT 0xFFFFFFUL +/* this is the XOR_CBBCR width */ +#define PPC460EX_ADMA_XOR_MAX_BYTE_COUNT (1 << 31) +#define PPC460EX_ADMA_ZERO_SUM_MAX_BYTE_COUNT PPC460EX_ADMA_XOR_MAX_BYTE_COUNT + +#define PPC460EX_RXOR_RUN 0 + +#undef ADMA_LL_DEBUG + +/** + * struct ppc460ex_adma_device - internal representation of an ADMA device + * @pdev: Platform device + * @id: HW ADMA Device selector + * @dma_desc_pool: base of DMA descriptor region (DMA address) + * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) + * @common: embedded struct dma_device + */ +typedef struct ppc460ex_adma_device { + //struct platform_device *pdev; + struct of_device *odev; + struct resource res[3]; /* Resource for register */ + void *dma_desc_pool_virt; + struct device *dev; + + int id; + dma_addr_t dma_desc_pool; + struct dma_device common; + + int eot_irq; + int err_irq; + int desc_memory; + +} ppc460ex_dev_t; + +/** + * struct ppc460ex_adma_chan - internal representation of an ADMA channel + * @lock: serializes enqueue/dequeue operations to the slot pool + * @device: parent device + * @chain: device chain view of the descriptors + * @common: common dmaengine channel object members + * @all_slots: complete domain of slots usable by the channel + * @pending: allows batching of hardware operations + * @completed_cookie: identifier for the most recently completed operation + * @slots_allocated: records the actual size of the descriptor slot pool + * @hw_chain_inited: h/w descriptor chain initialization flag + * @irq_tasklet: bottom half where ppc460ex_adma_slot_cleanup runs + * @needs_unmap: if buffers should not be unmapped upon final processing + */ +typedef struct ppc460ex_adma_chan { + spinlock_t lock; + struct ppc460ex_adma_device *device; + struct timer_list cleanup_watchdog; + struct list_head chain; + struct dma_chan common; + struct list_head all_slots; + struct ppc460ex_adma_desc_slot *last_used; + int pending; + dma_cookie_t completed_cookie; + int slots_allocated; + int hw_chain_inited; + struct tasklet_struct irq_tasklet; + u8 needs_unmap; +} ppc460ex_ch_t; + +typedef struct ppc460ex_rxor { + u32 addrl; + u32 addrh; + int len; + int xor_count; + int addr_count; + int desc_count; + int state; +} ppc460ex_rxor_cursor_t; + +/** + * struct ppc460ex_adma_desc_slot - PPC460EX-ADMA software descriptor + * @phys: hardware address of the hardware descriptor chain + * @group_head: first operation in a transaction + * @hw_next: pointer to the next descriptor in chain + * @async_tx: support for the async_tx api + * @slot_node: node on the iop_adma_chan.all_slots list + * @chain_node: node on the op_adma_chan.chain list + * @group_list: list of slots that make up a multi-descriptor transaction + * for example transfer lengths larger than the supported hw max + * @unmap_len: transaction bytecount + * @hw_desc: virtual address of the hardware descriptor chain + * @stride: currently chained or not + * @idx: pool index + * @slot_cnt: total slots used in an transaction (group of operations) + * @src_cnt: number of sources set in this descriptor + * @dst_cnt: number of destinations set in the descriptor + * @slots_per_op: number of slots per operation + * @descs_per_op: number of slot per P/Q operation see comment + * for ppc460ex_prep_dma_pqxor function + * @flags: desc state/type + * @reverse_flags: 1 if a corresponding rxor address uses reversed address order + * @xor_check_result: result of zero sum + * @crc32_result: result crc calculation + */ +typedef struct ppc460ex_adma_desc_slot { + dma_addr_t phys; + struct ppc460ex_adma_desc_slot *group_head; + struct ppc460ex_adma_desc_slot *hw_next; + struct dma_async_tx_descriptor async_tx; + struct list_head slot_node; + struct list_head chain_node; /* node in channel ops list */ + struct list_head group_list; /* list */ + unsigned int unmap_len; + void *hw_desc; + u16 stride; + u16 idx; + u16 slot_cnt; + u8 src_cnt; + u8 dst_cnt; + u8 slots_per_op; + u8 descs_per_op; + unsigned long flags; + unsigned long reverse_flags[8]; + +#define PPC460EX_DESC_INT 0 /* generate interrupt on complete */ +#define PPC460EX_ZERO_P 1 /* clear P destionaion */ +#define PPC460EX_ZERO_Q 2 /* clear Q destination */ +#define PPC460EX_COHERENT 3 /* src/dst are coherent */ + +#define PPC460EX_DESC_WXOR 4 /* WXORs are in chain */ +#define PPC460EX_DESC_RXOR 5 /* RXOR is in chain */ + +#define PPC460EX_DESC_RXOR123 8 /* CDB for RXOR123 operation */ +#define PPC460EX_DESC_RXOR124 9 /* CDB for RXOR124 operation */ +#define PPC460EX_DESC_RXOR125 10 /* CDB for RXOR125 operation */ +#define PPC460EX_DESC_RXOR12 11 /* CDB for RXOR12 operation */ +#define PPC460EX_DESC_RXOR_REV 12 /* CDB contains srcs in reversed order */ + +#define PPC460EX_DESC_PCHECK 13 +#define PPC460EX_DESC_QCHECK 14 + +#define PPC460EX_DESC_RXOR_MSK 0x3 + + ppc460ex_rxor_cursor_t rxor_cursor; + + union { + u32 *xor_check_result; + u32 *crc32_result; + }; +} ppc460ex_desc_t; + +typedef struct ppc460ex_adma_platform_data { + int hw_id; + dma_cap_mask_t cap_mask; + size_t pool_size; +} ppc460ex_aplat_t; + +#endif /* PPC460EX_ADMA_H */ diff --git a/arch/powerpc/include/asm/ppc460ex_dma.h b/arch/powerpc/include/asm/ppc460ex_dma.h new file mode 100644 index 00000000000..a758ca4a5f9 --- /dev/null +++ b/arch/powerpc/include/asm/ppc460ex_dma.h @@ -0,0 +1,262 @@ +/* + * include/asm-ppc/ppc440spe_dma.h + * + * 440SPe's DMA engines support header file + * + * 2006 (c) DENX Software Engineering + * + * Author: Yuri Tikhonov <yur@emcraft.com> + * + * This file is licensed under the term of the GNU General Public License + * version 2. The program licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef PPC440SPE_DMA_H +#define PPC440SPE_DMA_H + +#include <asm/types.h> + +/* Number of elements in the array with statical CDBs */ +#define MAX_STAT_DMA_CDBS 16 +/* Number of DMA engines available on the contoller */ +#define DMA_ENGINES_NUM 1 + +/* Maximum h/w supported number of destinations */ +#define DMA_DEST_MAX_NUM 2 + +/* FIFO's params */ +#define DMA1_FIFO_SIZE 0x1000 +#define DMA_FIFO_ENABLE (1<<12) + +/* DMA Configuration Register. Prefetch disable */ +#define DMA_CFG_DXEPD (1 << 31) +/* DMA Configuration Register. Prefetch disable */ +#define DMA_CFG_DXERO (1 << 30) +/* DMA Configuration Register. Data Transfer Engine PLB Priority: */ +#define DMA_CFG_DXEPR_LP (0<<26) +#define DMA_CFG_DXEPR_HP (3<<26) +#define DMA_CFG_DXEPR_HHP (2<<26) +#define DMA_CFG_DXEPR_HHHP (1<<26) + +/* DMA Configuration Register. DMA FIFO Manager PLB Priority: */ +#define DMA_CFG_DFMPP_LP (0<<23) +#define DMA_CFG_DFMPP_HP (3<<23) +#define DMA_CFG_DFMPP_HHP (2<<23) +#define DMA_CFG_DFMPP_HHHP (1<<23) + +/* DMA Configuration Register. Force 64-byte Alignment */ +#define DMA_CFG_FALGN (1 << 19) + +/* I2O Memory Mapped Registers base address */ +#define I2O_MMAP_BASE 0x400100000ULL +#define I2O_REG_ENABLE 0x1 +#define I2O_MMAP_SIZE 0xF4ULL + +/* DMA Memory Mapped Registers base address */ +#define DMA0_MMAP_BASE 0x400100100ULL +#define DMA1_MMAP_BASE 0x400100200ULL +#define DMA_MMAP_SIZE 0x80 + +/* DMA Interrupt Sources, UIC0[20],[22] */ +//#define DMA0_CP_FIFO_FULL_IRQ 19 +//#define DMA0_CS_FIFO_NEED_SERVICE_IRQ 20 +#define DMA1_CP_FIFO_FULL_IRQ 21 +#define DMA1_CS_FIFO_NEED_SERVICE_IRQ 22 +#define DMA_ERROR_IRQ 54 + +/*UIC0:*/ +#define D0CPF_INT (1<<12) +#define D0CSF_INT (1<<11) +#define D1CPF_INT (1<<10) +#define D1CSF_INT (1<<9) +/*UIC1:*/ +#define DMAE_INT (1<<9) + +/* I2O IOP Interrupt Mask Register */ +#define I2O_IOPIM_P0SNE (1<<3) +#define I2O_IOPIM_P0EM (1<<5) +#define I2O_IOPIM_P1SNE (1<<6) +#define I2O_IOPIM_P1EM (1<<8) + +/* DMA CDB fields */ +#define DMA_CDB_MSK (0xF) +#define DMA_CDB_64B_ADDR (1<<2) +#define DMA_CDB_NO_INT (1<<3) +#define DMA_CDB_STATUS_MSK (0x3) +#define DMA_CDB_ADDR_MSK (0xFFFFFFF0) + +/* DMA CDB OpCodes */ +#define DMA_CDB_OPC_NO_OP (0x00) +#define DMA_CDB_OPC_MV_SG1_SG2 (0x01) +#define DMA_CDB_OPC_MULTICAST (0x05) +#define DMA_CDB_OPC_DFILL128 (0x24) +#define DMA_CDB_OPC_DCHECK128 (0x23) + +#define DMA_CUED_XOR_BASE (0x10000000) +#define DMA_CUED_XOR_HB (0x00000008) + +#ifdef CONFIG_440SP +#define DMA_CUED_MULT1_OFF 0 +#define DMA_CUED_MULT2_OFF 8 +#define DMA_CUED_MULT3_OFF 16 +#define DMA_CUED_REGION_OFF 24 +#define DMA_CUED_XOR_WIN_MSK (0xFC000000) +#else +#define DMA_CUED_MULT1_OFF 2 +#define DMA_CUED_MULT2_OFF 10 +#define DMA_CUED_MULT3_OFF 18 +#define DMA_CUED_REGION_OFF 26 +#define DMA_CUED_XOR_WIN_MSK (0xF0000000) +#endif + +#define DMA_CUED_REGION_MSK 0x3 +#define DMA_RXOR123 0x0 +#define DMA_RXOR124 0x1 +#define DMA_RXOR125 0x2 +#define DMA_RXOR12 0x3 + +/* S/G addresses */ +#define DMA_CDB_SG_SRC 1 +#define DMA_CDB_SG_DST1 2 +#define DMA_CDB_SG_DST2 3 + +/* + * DMAx engines Command Descriptor Block Type + */ +typedef struct dma_cdb { + /* + * Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf) + */ + u8 pad0[2]; /* reserved */ + u8 attr; /* attributes */ + u8 opc; /* opcode */ + u32 sg1u; /* upper SG1 address */ + u32 sg1l; /* lower SG1 address */ + u32 cnt; /* SG count, 3B used */ + u32 sg2u; /* upper SG2 address */ + u32 sg2l; /* lower SG2 address */ + u32 sg3u; /* upper SG3 address */ + u32 sg3l; /* lower SG3 address */ +} dma_cdb_t; + +/* + * Descriptor of allocated CDB + */ +typedef struct { + dma_cdb_t *vaddr; /* virtual address of CDB */ + dma_addr_t paddr; /* physical address of CDB */ + /* + * Additional fields + */ + struct list_head link; /* link in processing list */ + u32 status; /* status of the CDB */ + /* status bits: */ + #define DMA_CDB_DONE (1<<0) /* CDB processing competed */ + #define DMA_CDB_CANCEL (1<<1) /* waiting thread was interrupted */ +} dma_cdbd_t; + +/* + * DMAx hardware registers (p.515 in 440SPe UM 1.22) + */ +typedef struct { + u32 cpfpl; + u32 cpfph; + u32 csfpl; + u32 csfph; + u32 dsts; + u32 cfg; + u8 pad0[0x8]; + u16 cpfhp; + u16 cpftp; + u16 csfhp; + u16 csftp; + u8 pad1[0x8]; + u32 acpl; + u32 acph; + u32 s1bpl; + u32 s1bph; + u32 s2bpl; + u32 s2bph; + u32 s3bpl; + u32 s3bph; + u8 pad2[0x10]; + u32 earl; + u32 earh; + u8 pad3[0x8]; + u32 seat; + u32 sead; + u32 op; + u32 fsiz; +} dma_regs_t; + +/* + * I2O hardware registers (p.528 in 440SPe UM 1.22) + */ +typedef struct { + u32 ists; + u32 iseat; + u32 isead; + u8 pad0[0x14]; + u32 idbel; + u8 pad1[0xc]; + u32 ihis; + u32 ihim; + u8 pad2[0x8]; + u32 ihiq; + u32 ihoq; + u8 pad3[0x8]; + u32 iopis; + u32 iopim; + u32 iopiq; + u8 iopoq; + u8 pad4[3]; + u16 iiflh; + u16 iiflt; + u16 iiplh; + u16 iiplt; + u16 ioflh; + u16 ioflt; + u16 ioplh; + u16 ioplt; + u32 iidc; + u32 ictl; + u32 ifcpp; + u8 pad5[0x4]; + u16 mfac0; + u16 mfac1; + u16 mfac2; + u16 mfac3; + u16 mfac4; + u16 mfac5; + u16 mfac6; + u16 mfac7; + u16 ifcfh; + u16 ifcht; + u8 pad6[0x4]; + u32 iifmc; + u32 iodb; + u32 iodbc; + u32 ifbal; + u32 ifbah; + u32 ifsiz; + u32 ispd0; + u32 ispd1; + u32 ispd2; + u32 ispd3; + u32 ihipl; + u32 ihiph; + u32 ihopl; + u32 ihoph; + u32 iiipl; + u32 iiiph; + u32 iiopl; + u32 iioph; + u32 ifcpl; + u32 ifcph; + u8 pad7[0x8]; + u32 iopt; +} i2o_regs_t; + +#endif /* PPC440SPE_DMA_H */ + diff --git a/arch/powerpc/include/asm/ppc460ex_plb_adma.h b/arch/powerpc/include/asm/ppc460ex_plb_adma.h new file mode 100755 index 00000000000..965786e1d4b --- /dev/null +++ b/arch/powerpc/include/asm/ppc460ex_plb_adma.h @@ -0,0 +1,575 @@ + + +#include <linux/types.h> + + +#define to_ppc460ex_adma_chan(chan) container_of(chan,ppc460ex_p_ch_t,common) +#define to_ppc460ex_adma_device(dev) container_of(dev,ppc460ex_p_dev_t,common) +#define tx_to_ppc460ex_adma_slot(tx) container_of(tx,ppc460ex_p_desc_t,async_tx) + + +#define DMA_HEXDUMP(b, l) \ + print_hex_dump(KERN_CONT, "", DUMP_PREFIX_OFFSET, \ + 16, 1, (b), (l), false); + +#define PPC460EX_DMA_PROC_ROOT "driver/460ex_plb_dma" + +#define MAX_PPC460EX_DMA_CHANNELS 4 + +#define PPC460EX_ADMA_DMA_MAX_BYTE_COUNT 1024 * 1024 + +#define PPC460EX_ADMA_THRESHOLD 1 + +#define DCR_DMA0_BASE 0x200 +#define DCR_DMA1_BASE 0x208 +#define DCR_DMA2_BASE 0x210 +#define DCR_DMA3_BASE 0x218 +#define DCR_DMASR_BASE 0x220 + +#define PPC460EX_PDMA0_ID 0 +#define PPC460EX_PDMA1_ID 1 +#define PPC460EX_PDMA2_ID 2 +#define PPC460EX_PDMA3_ID 3 + + +#define DMA_FIFO_SIZE 0x1000 + +#define DMA_CDB_SIZE 64 + + +/* DMA Registers */ +#define DCR_DMA2P40_CR0 (DCR_DMA0_BASE + 0x0) /* DMA Channel Control 0 */ +#define DCR_DMA2P40_CTC0 (DCR_DMA0_BASE + 0x1) /* DMA Count 0 */ +#define DCR_DMA2P40_SAH0 (DCR_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */ +#define DCR_DMA2P40_SAL0 (DCR_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */ +#define DCR_DMA2P40_DAH0 (DCR_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */ +#define DCR_DMA2P40_DAL0 (DCR_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */ +#define DCR_DMA2P40_SGH0 (DCR_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */ +#define DCR_DMA2P40_SGL0 (DCR_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */ + +#define DCR_DMA2P40_CR1 (DCR_DMA1_BASE + 0x0) /* DMA Channel Control 1 */ +#define DCR_DMA2P40_CTC1 (DCR_DMA1_BASE + 0x1) /* DMA Count 1 */ +#define DCR_DMA2P40_SAH1 (DCR_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */ +#define DCR_DMA2P40_SAL1 (DCR_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */ +#define DCR_DMA2P40_DAH1 (DCR_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */ +#define DCR_DMA2P40_DAL1 (DCR_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */ +#define DCR_DMA2P40_SGH1 (DCR_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */ +#define DCR_DMA2P40_SGL1 (DCR_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */ + +#define DCR_DMA2P40_CR2 (DCR_DMA2_BASE + 0x0) /* DMA Channel Control 2 */ +#define DCR_DMA2P40_CTC2 (DCR_DMA2_BASE + 0x1) /* DMA Count 2 */ +#define DCR_DMA2P40_SAH2 (DCR_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */ +#define DCR_DMA2P40_SAL2 (DCR_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */ +#define DCR_DMA2P40_DAH2 (DCR_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */ +#define DCR_DMA2P40_DAL2 (DCR_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */ +#define DCR_DMA2P40_SGH2 (DCR_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */ +#define DCR_DMA2P40_SGL2 (DCR_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */ + +#define DCR_DMA2P40_CR3 (DCR_DMA3_BASE + 0x0) /* DMA Channel Control 3 */ +#define DCR_DMA2P40_CTC3 (DCR_DMA3_BASE + 0x1) /* DMA Count 3 */ +#define DCR_DMA2P40_SAH3 (DCR_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */ +#define DCR_DMA2P40_SAL3 (DCR_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */ +#define DCR_DMA2P40_DAH3 (DCR_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */ +#define DCR_DMA2P40_DAL3 (DCR_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */ +#define DCR_DMA2P40_SGH3 (DCR_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */ +#define DCR_DMA2P40_SGL3 (DCR_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */ + +#define DCR_DMA2P40_SR (DCR_DMASR_BASE + 0x0) /* DMA Status Register */ +#define DCR_DMA2P40_SGC (DCR_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ +#define DCR_DMA2P40_SLP (DCR_DMASR_BASE + 0x5) /* DMA Sleep Register */ +#define DCR_DMA2P40_POL (DCR_DMASR_BASE + 0x6) /* DMA Polarity Register */ + + + +/* + * Function return status codes + * These values are used to indicate whether or not the function + * call was successful, or a bad/invalid parameter was passed. + */ +#define DMA_STATUS_GOOD 0 +#define DMA_STATUS_BAD_CHANNEL 1 +#define DMA_STATUS_BAD_HANDLE 2 +#define DMA_STATUS_BAD_MODE 3 +#define DMA_STATUS_NULL_POINTER 4 +#define DMA_STATUS_OUT_OF_MEMORY 5 +#define DMA_STATUS_SGL_LIST_EMPTY 6 +#define DMA_STATUS_GENERAL_ERROR 7 +#define DMA_STATUS_CHANNEL_NOTFREE 8 + +#define DMA_CHANNEL_BUSY 0x80000000 + +/* + * These indicate status as returned from the DMA Status Register. + */ +#define DMA_STATUS_NO_ERROR 0 +#define DMA_STATUS_CS 1 /* Count Status */ +#define DMA_STATUS_TS 2 /* Transfer Status */ +#define DMA_STATUS_DMA_ERROR 3 /* DMA Error Occurred */ +#define DMA_STATUS_DMA_BUSY 4 /* The channel is busy */ + +/* + * DMA Channel Control Registers + */ +#ifdef CONFIG_44x +#define PPC4xx_DMA_64BIT +#define DMA_CR_OFFSET 1 +#else +#define DMA_CR_OFFSET 0 +#endif + +#define DMA_CE_ENABLE (1<<31) /* DMA Channel Enable */ +#define SET_DMA_CE_ENABLE(x) (((x)&0x1)<<31) +#define GET_DMA_CE_ENABLE(x) (((x)&DMA_CE_ENABLE)>>31) + +#define DMA_CIE_ENABLE (1<<30) /* DMA Channel Interrupt Enable */ +#define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30) +#define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30) + +#define DMA_TD (1<<29) +#define SET_DMA_TD(x) (((x)&0x1)<<29) +#define GET_DMA_TD(x) (((x)&DMA_TD)>>29) + +#define DMA_PL (1<<28) /* Peripheral Location */ +#define SET_DMA_PL(x) (((x)&0x1)<<28) +#define GET_DMA_PL(x) (((x)&DMA_PL)>>28) + +#define EXTERNAL_PERIPHERAL 0 +#define INTERNAL_PERIPHERAL 1 + +#define SET_DMA_PW(x) (((x)&0x7)<<(26-DMA_CR_OFFSET)) /* Peripheral Width */ +#define DMA_PW_MASK SET_DMA_PW(7) +#define PW_8 0 +#define PW_16 1 +#define PW_32 2 +#define PW_64 3 +#define PW_128 4 + + +#define GET_DMA_PW(x) (((x)&DMA_PW_MASK)>>(26-DMA_CR_OFFSET)) + +#define DMA_DAI (1<<(25-DMA_CR_OFFSET)) /* Destination Address Increment */ +#define SET_DMA_DAI(x) (((x)&0x1)<<(25-DMA_CR_OFFSET)) + +#define DMA_SAI (1<<(24-DMA_CR_OFFSET)) /* Source Address Increment */ +#define SET_DMA_SAI(x) (((x)&0x1)<<(24-DMA_CR_OFFSET)) + +#define DMA_BEN (1<<(23-DMA_CR_OFFSET)) /* Buffer Enable */ +#define SET_DMA_BEN(x) (((x)&0x1)<<(23-DMA_CR_OFFSET)) + +#define SET_DMA_TM(x) (((x)&0x3)<<(21-DMA_CR_OFFSET)) /* Transfer Mode */ +#define DMA_TM_MASK SET_DMA_TM(3) +#define TM_PERIPHERAL 0 /* Peripheral */ +#define TM_RESERVED 1 /* Reserved */ +#define TM_S_MM 2 /* Memory to Memory */ +#define TM_D_MM 3 /* Device Paced Memory to Memory */ +#define GET_DMA_TM(x) (((x)&DMA_TM_MASK)>>(21-DMA_CR_OFFSET)) + +#define SET_DMA_PSC(x) (((x)&0x3)<<(19-DMA_CR_OFFSET)) /* Peripheral Setup Cycles */ +#define DMA_PSC_MASK SET_DMA_PSC(3) +#define GET_DMA_PSC(x) (((x)&DMA_PSC_MASK)>>(19-DMA_CR_OFFSET)) + +#define SET_DMA_PWC(x) (((x)&0x3F)<<(13-DMA_CR_OFFSET)) /* Peripheral Wait Cycles */ +#define DMA_PWC_MASK SET_DMA_PWC(0x3F) +#define GET_DMA_PWC(x) (((x)&DMA_PWC_MASK)>>(13-DMA_CR_OFFSET)) + +#define SET_DMA_PHC(x) (((x)&0x7)<<(10-DMA_CR_OFFSET)) /* Peripheral Hold Cycles */ +#define DMA_PHC_MASK SET_DMA_PHC(0x7) +#define GET_DMA_PHC(x) (((x)&DMA_PHC_MASK)>>(10-DMA_CR_OFFSET)) + +#define DMA_ETD_OUTPUT (1<<(9-DMA_CR_OFFSET)) /* EOT pin is a TC output */ +#define SET_DMA_ETD(x) (((x)&0x1)<<(9-DMA_CR_OFFSET)) + +#define DMA_TCE_ENABLE (1<<(8-DMA_CR_OFFSET)) +#define SET_DMA_TCE(x) (((x)&0x1)<<(8-DMA_CR_OFFSET)) + +#define DMA_DEC (1<<(2)) /* Address Decrement */ +#define SET_DMA_DEC(x) (((x)&0x1)<<2) +#define GET_DMA_DEC(x) (((x)&DMA_DEC)>>2) + + +/* + * Transfer Modes + * These modes are defined in a way that makes it possible to + * simply "or" in the value in the control register. + */ + +#define DMA_MODE_MM (SET_DMA_TM(TM_S_MM)) /* memory to memory */ + + /* Device-paced memory to memory, */ + /* device is at source address */ +#define DMA_MODE_MM_DEVATSRC (DMA_TD | SET_DMA_TM(TM_D_MM)) + + /* Device-paced memory to memory, */ + /* device is at destination address */ +#define DMA_MODE_MM_DEVATDST (SET_DMA_TM(TM_D_MM)) + +#define SGL_LIST_SIZE 16384 +#define DMA_PPC4xx_SIZE SGL_LIST_SIZE + +#define SET_DMA_PRIORITY(x) (((x)&0x3)<<(6-DMA_CR_OFFSET)) /* DMA Channel Priority */ +#define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3) +#define PRIORITY_LOW 0 +#define PRIORITY_MID_LOW 1 +#define PRIORITY_MID_HIGH 2 +#define PRIORITY_HIGH 3 +#define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>(6-DMA_CR_OFFSET)) + + +#define SET_DMA_PREFETCH(x) (((x)&0x3)<<(4-DMA_CR_OFFSET)) /* Memory Read Prefetch */ +#define DMA_PREFETCH_MASK SET_DMA_PREFETCH(3) +#define PREFETCH_1 0 /* Prefetch 1 Double Word */ +#define PREFETCH_2 1 +#define PREFETCH_4 2 +#define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>(4-DMA_CR_OFFSET)) + +#define DMA_PCE (1<<(3-DMA_CR_OFFSET)) /* Parity Check Enable */ +#define SET_DMA_PCE(x) (((x)&0x1)<<(3-DMA_CR_OFFSET)) +#define GET_DMA_PCE(x) (((x)&DMA_PCE)>>(3-DMA_CR_OFFSET)) + +/* + * DMA Polarity Configuration Register + */ +#define DMAReq_ActiveLow(chan) (1<<(31-(chan*3))) +#define DMAAck_ActiveLow(chan) (1<<(30-(chan*3))) +#define EOT_ActiveLow(chan) (1<<(29-(chan*3))) /* End of Transfer */ + +/* + * DMA Sleep Mode Register + */ +#define SLEEP_MODE_ENABLE (1<<21) + +/* + * DMA Status Register + */ +#define DMA_CS0 (1<<31) /* Terminal Count has been reached */ +#define DMA_CS1 (1<<30) +#define DMA_CS2 (1<<29) +#define DMA_CS3 (1<<28) + +#define DMA_TS0 (1<<27) /* End of Transfer has been requested */ +#define DMA_TS1 (1<<26) +#define DMA_TS2 (1<<25) +#define DMA_TS3 (1<<24) + +#define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ +#define DMA_CH1_ERR (1<<22) +#define DMA_CH2_ERR (1<<21) +#define DMA_CH3_ERR (1<<20) + +#define DMA_IN_DMA_REQ0 (1<<19) /* Internal DMA Request is pending */ +#define DMA_IN_DMA_REQ1 (1<<18) +#define DMA_IN_DMA_REQ2 (1<<17) +#define DMA_IN_DMA_REQ3 (1<<16) + +#define DMA_EXT_DMA_REQ0 (1<<15) /* External DMA Request is pending */ +#define DMA_EXT_DMA_REQ1 (1<<14) +#define DMA_EXT_DMA_REQ2 (1<<13) +#define DMA_EXT_DMA_REQ3 (1<<12) + +#define DMA_CH0_BUSY (1<<11) /* DMA Channel 0 Busy */ +#define DMA_CH1_BUSY (1<<10) +#define DMA_CH2_BUSY (1<<9) +#define DMA_CH3_BUSY (1<<8) + +#define DMA_SG0 (1<<7) /* DMA Channel 0 Scatter/Gather in progress */ +#define DMA_SG1 (1<<6) +#define DMA_SG2 (1<<5) +#define DMA_SG3 (1<<4) + +/* DMA Channel Count Register */ +#define DMA_CTC_TCIE (1<<29) /* Terminal Count Interrupt Enable */ +#define DMA_CTC_ETIE (1<<28) /* EOT Interupt Enable */ +#define DMA_CTC_EIE (1<<27) /* Error Interrupt Enable */ +#define DMA_CTC_BTEN (1<<23) /* Burst Enable/Disable bit */ +#define DMA_CTC_BSIZ_MSK (3<<21) /* Mask of the Burst size bits */ +#define DMA_CTC_BSIZ_2 (0) +#define DMA_CTC_BSIZ_4 (1<<21) +#define DMA_CTC_BSIZ_8 (2<<21) +#define DMA_CTC_BSIZ_16 (3<<21) +#define DMA_CTC_TC_MASK 0xFFFFF + +/* + * DMA SG Command Register + */ +#define SSG_ENABLE(chan) (1<<(31-chan)) /* Start Scatter Gather */ +#define SSG_MASK_ENABLE(chan) (1<<(15-chan)) /* Enable writing to SSG0 bit */ + + +/* + * DMA Scatter/Gather Descriptor Bit fields + */ +#define SG_LINK (1<<31) /* Link */ +#define SG_TCI_ENABLE (1<<29) /* Enable Terminal Count Interrupt */ +#define SG_ETI_ENABLE (1<<28) /* Enable End of Transfer Interrupt */ +#define SG_ERI_ENABLE (1<<27) /* Enable Error Interrupt */ +#define SG_COUNT_MASK 0xFFFF /* Count Field */ + +#define SET_DMA_CONTROL \ + (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \ + SET_DMA_BEN(p_init->buffer_enable) | /* buffer enable */\ + SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \ + SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \ + SET_DMA_PL(p_init->pl) | /* peripheral location */ \ + SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \ + SET_DMA_SAI(p_init->sai) | /* src addr increment */ \ + SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \ + SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \ + SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \ + SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \ + SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \ + SET_DMA_PREFETCH(p_init->pf) /* read prefetch */) + +#define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan)) + + +/** + * struct ppc460ex_dma_device - internal representation of an DMA device + * @pdev: Platform device + * @id: HW DMA Device selector + * @dma_desc_pool: base of DMA descriptor region (DMA address) + * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) + * @common: embedded struct dma_device + */ +typedef struct ppc460ex_plb_dma_device { + //struct platform_device *pdev; + struct of_device *odev; + void __iomem *reg_base; + struct device *dev; + struct resource reg; /* Resource for register */ + int id; + struct dma_device common; + struct ppc460ex_plb_dma_chan *chan[MAX_PPC460EX_DMA_CHANNELS]; + wait_queue_head_t queue; +} ppc460ex_p_dev_t; + +typedef uint32_t sgl_handle_t; +/** + * struct ppc460ex_dma_chan - internal representation of an ADMA channel + * @lock: serializes enqueue/dequeue operations to the slot pool + * @device: parent device + * @chain: device chain view of the descriptors + * @common: common dmaengine channel object members + * @all_slots: complete domain of slots usable by the channel + * @reg: Resource for register + * @pending: allows batching of hardware operations + * @completed_cookie: identifier for the most recently completed operation + * @slots_allocated: records the actual size of the descriptor slot pool + * @hw_chain_inited: h/w descriptor chain initialization flag + * @irq_tasklet: bottom half where ppc460ex_adma_slot_cleanup runs + * @needs_unmap: if buffers should not be unmapped upon final processing + */ +typedef struct ppc460ex_plb_dma_chan { + spinlock_t lock; + void __iomem *reg_base; + struct ppc460ex_plb_dma_device *device; + struct timer_list cleanup_watchdog; + struct list_head chain; + struct dma_chan common; + struct list_head all_slots; + struct ppc460ex_adma_desc_slot *last_used; + int pending; + dma_cookie_t completed_cookie; + int slots_allocated; + int hw_chain_inited; + void *dma_desc_pool_virt; + dma_addr_t dma_desc_pool; + + struct resource reg; /* Resource for register */ + unsigned int chan_id; + struct tasklet_struct irq_tasklet; + u8 needs_unmap; + sgl_handle_t *phandle; + unsigned short in_use; /* set when channel is being used, clr when + * available. + */ + /* + * Valid polarity settings: + * DMAReq_ActiveLow(n) + * DMAAck_ActiveLow(n) + * EOT_ActiveLow(n) + * + * n is 0 to max dma chans + */ + unsigned int polarity; + + char buffer_enable; /* Boolean: buffer enable */ + char tce_enable; /* Boolean: terminal count enable */ + char etd_output; /* Boolean: eot pin is a tc output */ + char pce; /* Boolean: parity check enable */ + + /* + * Peripheral location: + * INTERNAL_PERIPHERAL (UART0 on the 405GP) + * EXTERNAL_PERIPHERAL + */ + char pl; /* internal/external peripheral */ + + /* + * Valid pwidth settings: + * PW_8 + * PW_16 + * PW_32 + * PW_64 + */ + unsigned int pwidth; + + char dai; /* Boolean: dst address increment */ + char sai; /* Boolean: src address increment */ + + /* + * Valid psc settings: 0-3 + */ + unsigned int psc; /* Peripheral Setup Cycles */ + + /* + * Valid pwc settings: + * 0-63 + */ + unsigned int pwc; /* Peripheral Wait Cycles */ + + /* + * Valid phc settings: + * 0-7 + */ + unsigned int phc; /* Peripheral Hold Cycles */ + + /* + * Valid cp (channel priority) settings: + * PRIORITY_LOW + * PRIORITY_MID_LOW + * PRIORITY_MID_HIGH + * PRIORITY_HIGH + */ + unsigned int cp; /* channel priority */ + + /* + * Valid pf (memory read prefetch) settings: + * + * PREFETCH_1 + * PREFETCH_2 + * PREFETCH_4 + */ + unsigned int pf; /* memory read prefetch */ + + /* + * Boolean: channel interrupt enable + * NOTE: for sgl transfers, only the last descriptor will be setup to + * interrupt. + */ + char int_enable; + + char shift; /* easy access to byte_count shift, based on */ + /* the width of the channel */ + + uint32_t control; /* channel control word */ + + /* These variabled are used ONLY in single dma transfers */ + unsigned int mode; /* transfer mode */ + phys_addr_t addr; + char ce; /* channel enable */ + char int_on_final_sg;/* for scatter/gather - only interrupt on last sg */ + +} ppc460ex_p_ch_t; +typedef struct ppc460ex_adma_plb_desc_slot { + dma_addr_t phys; + struct ppc460ex_adma_plb_desc_slot *group_head; + struct ppc460ex_adma_plb_desc_slot *hw_next; + struct dma_async_tx_descriptor async_tx; + struct list_head slot_node; + struct list_head chain_node; + struct list_head group_list; + unsigned int unmap_len; + void *hw_desc; + u16 stride; + u16 idx; + u16 slot_cnt; + u8 src_cnt; + u8 dst_cnt; + u8 slots_per_op; + u8 descs_per_op; + unsigned long flags; + unsigned long reverse_flags[8]; +#define PPC460EX_DESC_INT 0 /* generate interrupt on complete */ + +}ppc460ex_p_desc_t; + +typedef struct ppc460ex_adma_plb_platform_data { + int hw_id; + dma_cap_mask_t cap_mask; + size_t pool_size; +} ppc460ex_p_aplat_t; + +typedef struct dma_cdb { + u32 ctrl; + u32 cnt; + u32 src_hi; + u32 src_lo; + u32 dest_hi; + u32 dest_lo; + u32 sg_hi; + u32 sg_lo; +}dma_cdb_t; +/* + * PPC44x DMA implementations have a slightly different + * descriptor layout. Probably moved about due to the + * change to 64-bit addresses and link pointer. I don't + * know why they didn't just leave control_count after + * the dst_addr. + */ +#ifdef PPC4xx_DMA_64BIT +typedef struct { + uint32_t control; + uint32_t control_count; + phys_addr_t src_addr; + phys_addr_t dst_addr; + phys_addr_t next; +} ppc_sgl_t; +#else +typedef struct { + uint32_t control; + phys_addr_t src_addr; + phys_addr_t dst_addr; + uint32_t control_count; + uint32_t next; +} ppc_sgl_t; +#endif + + + +typedef struct { + unsigned int ch_id; + uint32_t control; /* channel ctrl word; loaded from each descrptr */ + uint32_t sgl_control; /* LK, TCI, ETI, and ERI bits in sgl descriptor */ + dma_addr_t dma_addr; /* dma (physical) address of this list */ + ppc_sgl_t *phead; + dma_addr_t phead_dma; + ppc_sgl_t *ptail; + dma_addr_t ptail_dma; +} sgl_list_info_t; + +typedef struct { + phys_addr_t *src_addr; + phys_addr_t *dst_addr; + phys_addr_t dma_src_addr; + phys_addr_t dma_dst_addr; +} pci_alloc_desc_t; + +#define PPC460EX_DMA_SGXFR_COMPLETE(id) (!((1 << (11-id)) & mfdcr(DCR_DMA2P40_SR))) +#define PPC460EX_DMA_CHAN_BUSY(id) ( (1 << (11-id)) & mfdcr(DCR_DMA2P40_SR) ) +#define DMA_STATUS(id) (mfdcr(DCR_DMA2P40_SR)) +#define CLEAR_DMA_STATUS(id) (mtdcr(DCR_DMA2P40_SR, 0xFFFFFFFF)) +#define PPC460EX_DMA_SGSTAT_FREE(id) (!((1 << (7-id)) & mfdcr(DCR_DMA2P40_SR)) ) +#define PPC460EX_DMA_TC_REACHED(id) ( (1 << (31-id)) & mfdcr(DCR_DMA2P40_SR) ) +#define PPC460EX_DMA_CHAN_XFR_COMPLETE(id) ( (!PPC460EX_DMA_CHAN_BUSY(id)) && (PPC460EX_DMA_TC_REACHED(id)) ) +#define PPC460EX_DMA_CHAN_SGXFR_COMPLETE(id) ( (!PPC460EX_DMA_CHAN_BUSY(id)) && PPC460EX_DMA_SGSTAT_FREE(id) ) +#define PPC460EX_DMA_SG_IN_PROGRESS(id) ( (1 << (7-id)) | (1 << (11-id)) ) +#define PPC460EX_DMA_SG_OP_COMPLETE(id) ( (PPC460EX_DMA_SG_IN_PROGRESS(id) & DMA_STATUS(id) ) == 0) + + + +#if 0 +extern int test_dma_memcpy(void *src, void *dst, unsigned int length, unsigned int dma_ch); + +extern int test_sgdma_memcpy(void *src, void *dst, void *src1, void *dst1, + unsigned int length, unsigned int dma_ch); +#endif diff --git a/arch/powerpc/include/asm/ppc460ex_xor.h b/arch/powerpc/include/asm/ppc460ex_xor.h new file mode 100644 index 00000000000..30a0334c7eb --- /dev/null +++ b/arch/powerpc/include/asm/ppc460ex_xor.h @@ -0,0 +1,147 @@ +/* + * include/asm/ppc440spe_xor.h + * + * 440SPe's XOR engines support header file + * + * 2006 (c) DENX Software Engineering + * + * Author: Yuri Tikhonov <yur@emcraft.com> + * + * This file is licensed under the term of the GNU General Public License + * version 2. The program licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef PPC440SPE_XOR_H +#define PPC440SPE_XOR_H + +#include <asm/types.h> + +/* Number of operands supported in the h/w */ +#define XOR_MAX_OPS 16 + +/* XOR Memory Mapped Registers base address is different + * for ppc440sp and ppc440spe processors + */ +#ifdef CONFIG_440SP +#define XOR_MMAP_BASE 0x100200000ULL +#else +#define XOR_MMAP_BASE 0x400200000ULL +#endif +#define XOR_MMAP_SIZE 0x224ULL + +/* XOR Interrupt Source, UIC1[31] */ +#define XOR_IRQ 63 + +/* + * XOR Command Block Control Register bits + */ +#define XOR_CBCR_LNK_BIT (1<<31) /* link present */ +#define XOR_CBCR_TGT_BIT (1<<30) /* target present */ +#define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */ +#define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */ +#define XOR_CBCR_XNOR_BIT (1<<15) /* XOR/XNOR */ +#define XOR_CDCR_OAC_MSK (0x7F) /* operand address count */ + +/* + * XORCore Status Register bits + */ +#define XOR_SR_XCP_BIT (1<<31) /* core processing */ +#define XOR_SR_ICB_BIT (1<<17) /* invalid CB */ +#define XOR_SR_IC_BIT (1<<16) /* invalid command */ +#define XOR_SR_IPE_BIT (1<<15) /* internal parity error */ +#define XOR_SR_RNZ_BIT (1<<2) /* result not Zero */ +#define XOR_SR_CBC_BIT (1<<1) /* CB complete */ +#define XOR_SR_CBLC_BIT (1<<0) /* CB list complete */ + +/* + * XORCore Control Set and Reset Register bits + */ +#define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */ +#define XOR_CRSR_XAE_BIT (1<<30) /* enable */ +#define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */ +#define XOR_CRSR_PAUS_BIT (1<<28) /* pause */ +#define XOR_CRSR_64BA_BIT (1<<27) /* 64/32 CB format */ +#define XOR_CRSR_CLP_BIT (1<<25) /* continue list processing */ + +/* + * XORCore Interrupt Enable Register + */ +#define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block Interrupt Enable */ +#define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command Interrupt Enable */ +#define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error Interrupt Enable */ +#define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */ +#define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */ + +/* + * XOR Accelerator engine Command Block Type + */ +typedef struct { + /* + * Basic 64-bit format XOR CB (Table 19-1, p.463, 440spe_um_1_22.pdf) + */ + u32 cbc; /* control */ + u32 cbbc; /* byte count */ + u32 cbs; /* status */ + u8 pad0[4]; /* reserved */ + u32 cbtah; /* target address high */ + u32 cbtal; /* target address low */ + u32 cblah; /* link address high */ + u32 cblal; /* link address low */ + struct { + u32 h; + u32 l; + } __attribute__ ((packed)) ops [16]; +} __attribute__ ((packed)) xor_cb_t; + +typedef struct { + xor_cb_t *vaddr; + dma_addr_t paddr; + + /* + * Additional fields + */ + struct list_head link; /* link to processing CBs */ + u32 status; /* status of the CB */ + /* status bits: */ + #define XOR_CB_DONE (1<<0) /* CB processing competed */ + #define XOR_CB_CANCEL (1<<1) /* waiting thread was interrupted */ +#if 0 + #define XOR_CB_STALLOC (1<<2) /* CB allocated statically */ +#endif +} xor_cbd_t; + + +/* + * XOR hardware registers Table 19-3, UM 1.22 + */ +typedef struct { + u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */ + u8 pad0[352]; /* reserved */ + u32 cbcr; /* CB control register */ + u32 cbbcr; /* CB byte count register */ + u32 cbsr; /* CB status register */ + u8 pad1[4]; /* reserved */ + u32 cbtahr; /* operand target address high register */ + u32 cbtalr; /* operand target address low register */ + u32 cblahr; /* CB link address high register */ + u32 cblalr; /* CB link address low register */ + u32 crsr; /* control set register */ + u32 crrr; /* control reset register */ + u32 ccbahr; /* current CB address high register */ + u32 ccbalr; /* current CB address low register */ + u32 plbr; /* PLB configuration register */ + u32 ier; /* interrupt enable register */ + u32 pecr; /* parity error count register */ + u32 sr; /* status register */ + u32 revidr; /* revision ID register */ +} xor_regs_t; + +/* + * Prototypes + */ +int init_xor_eng(void); +int spe440_xor_block (unsigned int ops_count, unsigned int op_len, void **ops); + +#endif /* PPC440SPE_XOR_H */ + diff --git a/arch/powerpc/include/asm/ppc4xx_cpm.h b/arch/powerpc/include/asm/ppc4xx_cpm.h new file mode 100644 index 00000000000..56884fde4b5 --- /dev/null +++ b/arch/powerpc/include/asm/ppc4xx_cpm.h @@ -0,0 +1,82 @@ +/* + * PowerPC 4xx Clock and Power Management + * + * (C) Copyright 2008, Applied Micro Circuits Corporation + * Victor Gallardo (vgallardo@amcc.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_POWERPC_PPC4xx_CPM_H__ +#define __ASM_POWERPC_PPC4xx_CPM_H__ + +#define CPM_PM_DOZE 0 +#define CPM_PM_NAP 1 +#define CPM_PM_DEEPSLEEP 2 +#define CPM_PM_MODES_MAX 3 + + +#define CPM_PM_EMAC0_MR0_RXI 0x80000000 +#define CPM_PM_ENABLE_EMAC0_MR0_RXE 0x08000000 +#define CPM_PM_DISABLE_EMAC0_MR0_RXE 0xf7ffffff + +#if defined(CONFIG_APM82181) || defined(CONFIG_APM82161) +#define CPM_PM_ENABLE_EMAC0_MR0_WKE 0x05000000 +#define CPM_PM_DISABLE_EMAC0_MR0_WKE 0xfaffffff +#else +#define CPM_PM_ENABLE_EMAC0_MR0_WKE 0x04000000 +#define CPM_PM_DISABLE_EMAC0_MR0_WKE 0xfbffffff +#endif /* defined(CONFIG_APM82181) || defined(CONFIG_APM82161) */ + + +#define CPM_PM_DATA_IIC_PTR 255 + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + +#define CONFIG_CPM_PM_AD5243 +#define CPM_PM_AD5243_ADDR 0x5e +#define CPM_PM_AD5243_1_290V 0x80 /* 1.290 volts */ +#define CPM_PM_AD5243_1_250V 0x7A /* 1.250 volts */ +#define CPM_PM_AD5243_1_200V 0x70 /* 1.200 volts */ +#define CPM_PM_AD5243_1_150V 0x67 /* 1.150 volts */ +#define CPM_PM_AD5243_1_100V 0x5d /* 1.100 volts */ +#define CPM_PM_AD5243_1_050V 0x54 /* 1.050 volts */ +#define CPM_PM_AD5243_1_000V 0x4a /* 1.000 volts */ +#endif + +#ifndef __ASSEMBLY__ + +#if defined(CONFIG_PPC4xx_CPM) + +#include <linux/suspend.h> + +int cpm_pm_idle(int pm_mode); +int cpm_pm_suspend(suspend_state_t state, int suspend_mode); +const char *cpm_mode_name(int mode); +#else + +#define cpm_pm_idle(pm_mode) do { } while(0) +#define cpm_pm_suspend(state) 0 + +#endif /* CONFIG_PPC4xx_CPM */ + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_POWERPC_PPC4xx_CPM_H__ */ + diff --git a/arch/powerpc/include/asm/ppc4xx_ocm.h b/arch/powerpc/include/asm/ppc4xx_ocm.h new file mode 100644 index 00000000000..fe3cc648544 --- /dev/null +++ b/arch/powerpc/include/asm/ppc4xx_ocm.h @@ -0,0 +1,48 @@ +/* + * PowerPC 4xx OCM memory allocation support + * + * (C) Copyright 2009, Applied Micro Circuits Corporation + * Victor Gallardo (vgallardo@amcc.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_POWERPC_PPC4xx_OCM_H__ +#define __ASM_POWERPC_PPC4xx_OCM_H__ + +#include <linux/types.h> + +#define OCM_NON_CACHED 0 +#define OCM_CACHED 1 + +#if defined(CONFIG_PPC4xx_OCM) + +void * ocm_alloc(phys_addr_t *phys, int size, int align, + int flags, const char *owner); +void ocm_free(const void * virt); + +#else + +#define ocm_alloc(phys, size, align, flags, owner) NULL +#define ocm_free(addr) ((void)0) + +#endif /* CONFIG_PPC4xx_OCM */ + +#endif /* __ASM_POWERPC_PPC4xx_OCM_H__ */ + diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 3bf78350552..46d5f66e034 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -177,6 +177,8 @@ #endif /* Bit definitions for CCR1. */ +#define CCR0_DTB 0x00008000 /* Disable trace broadcast */ +#define CCR0_GDCBT 0x00002000 /* Guarentee data cache block touch */ #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ #define CCR1_TCS 0x00000080 /* Timer Clock Select */ |