diff options
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/apm82181-adma.h | 309 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/async_tx.h | 88 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/dcr-regs.h | 237 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/mmio-regs.h | 61 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/ppc460ex_adma.h | 186 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/ppc460ex_dma.h | 262 | ||||
| -rwxr-xr-x | arch/powerpc/include/asm/ppc460ex_plb_adma.h | 575 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/ppc460ex_xor.h | 147 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/ppc4xx_cpm.h | 82 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/ppc4xx_ocm.h | 48 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 2 |
11 files changed, 1996 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/apm82181-adma.h b/arch/powerpc/include/asm/apm82181-adma.h new file mode 100644 index 00000000000..b16014b8c07 --- /dev/null +++ b/arch/powerpc/include/asm/apm82181-adma.h @@ -0,0 +1,309 @@ +/* + * 2009-2010 (C) Applied Micro Circuits Corporation. + * + * Author: Tai Tri Nguyen<ttnguyen@appliedmicro.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of + * any kind, whether express or implied. + */ + +#ifndef APM82181_ADMA_H +#define APM82181_ADMA_H + + +#include <linux/types.h> + + +#define to_apm82181_adma_chan(chan) container_of(chan,apm82181_ch_t,common) +#define to_apm82181_adma_device(dev) container_of(dev,apm82181_dev_t,common) +#define tx_to_apm82181_adma_slot(tx) container_of(tx,apm82181_desc_t,async_tx) + +#define APM82181_DMA_PROC_ROOT "driver/apm82181_adma" + +/* Number of operands supported in the h/w */ +#define XOR_MAX_OPS 16 +/* this is the XOR_CBBCR width */ +#define APM82181_ADMA_XOR_MAX_BYTE_COUNT (1 << 31) +#define APM82181_ADMA_DMA_MAX_BYTE_COUNT 1024 * 1024 +#define MAX_APM82181_DMA_CHANNELS 5 +#define APM82181_ADMA_THRESHOLD 1 + +#define APM82181_PDMA0_ID 0 +#define APM82181_PDMA1_ID 1 +#define APM82181_PDMA2_ID 2 +#define APM82181_PDMA3_ID 3 +#define APM82181_XOR_ID 4 + +/* DMA 0/1/2/3 registers */ +#define DCR_DMAx_BASE(x) (0x200 + x*0x8) /* DMA DCR base */ +#define DCR_DMA2P40_CRx(x) (DCR_DMAx_BASE(x) + 0x0) /* DMA Channel Control */ +#define DMA_CR_CE (1 << 31) +#define DMA_CR_CIE (1 << 30) +#define DMA_CR_PL (1 << 28) +#define DMA_CR_PW_128 0x08000000 +#define DMA_CR_DAI 0x01000000 +#define DMA_CR_SAI 0x00800000 +#define DMA_CR_BEN 0x00400000 +#define DMA_CR_TM_S_MM 0x00300000 +#define DMA_CR_ETD 0x00000100 +#define DMA_CR_TCE 0x00000080 +#define DMA_CR_CP(x) (x<<5)& 0x00000060 +#define DMA_CR_DEC (1 << 2) +#define DMA_CR_SL (1 << 1) +#define DCR_DMA2P40_CTCx(x) (DCR_DMAx_BASE(x) + 0x1) /* DMA Count 0 */ +#define DMA_CTC_ETIE (1 << 28) +#define DMA_CTC_EIE (1 << 27) +#define DMA_CTC_PCE (1 << 20) +#define DMA_CTC_TC_MASK 0x000fffff +#define DCR_DMA2P40_SAHx(x) (DCR_DMAx_BASE(x) + 0x2) /* DMA Src Addr High 0 */ +#define DCR_DMA2P40_SALx(x) (DCR_DMAx_BASE(x) + 0x3) /* DMA Src Addr Low 0 */ +#define DCR_DMA2P40_DAHx(x) (DCR_DMAx_BASE(x) + 0x4) /* DMA Dest Addr High 0 */ +#define DCR_DMA2P40_DALx(x) (DCR_DMAx_BASE(x) + 0x5) /* DMA Dest Addr Low 0 */ +#define DCR_DMA2P40_SGHx(x) (DCR_DMAx_BASE(x) + 0x6) /* DMA SG Desc Addr High 0 */ +#define DCR_DMA2P40_SGLx(x) (DCR_DMAx_BASE(x) + 0x7) /* DMA SG Desc Addr Low 0 */ +/* DMA Status Register */ +#define DCR_DMA2P40_SR 0x220 +#define DMA_SR_CS(x) (1 << (31 -x)) +#define DMA_SR_TS(x) (1 << (27 -x)) +#define DMA_SR_RI(x) (1 << (23 -x)) +#define DMA_SR_IR(x) (1 << (19 -x)) +#define DMA_SR_ER(x) (1 << (15 -x)) +#define DMA_SR_CB(x) (1 << (11 -x)) +#define DMA_SR_SG(x) (1 << (7 -x)) +/* S/G registers */ +#define DCR_DMA2P40_SGC 0x223 +#define DMA_SGC_SSG(x) ( 1 << (31 - x)) +#define DMA_SGC_SGL(x,y) ( y << (27 - x)) /* x: channel; y: 0 PLB, 1 OPB*/ +#define DMA_SGC_EM(x) ( 1 << (15 - x)) +#define DMA_SGC_EM_ALL 0x0000F000 + +/* + * XOR Command Block Control Register bits + */ +#define XOR_CBCR_LNK_BIT (1<<31) /* link present */ +#define XOR_CBCR_TGT_BIT (1<<30) /* target present */ +#define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */ +#define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */ +#define XOR_CBCR_XNOR_BIT (1<<15) /* XOR/XNOR */ +#define XOR_CDCR_OAC_MSK (0x7F) /* operand address count */ + +/* + * XORCore Status Register bits + */ +#define XOR_SR_XCP_BIT (1<<31) /* core processing */ +#define XOR_SR_ICB_BIT (1<<17) /* invalid CB */ +#define XOR_SR_IC_BIT (1<<16) /* invalid command */ +#define XOR_SR_IPE_BIT (1<<15) /* internal parity error */ +#define XOR_SR_RNZ_BIT (1<<2) /* result not Zero */ +#define XOR_SR_CBC_BIT (1<<1) /* CB complete */ +#define XOR_SR_CBLC_BIT (1<<0) /* CB list complete */ + +/* + * XORCore Control Set and Reset Register bits + */ +#define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */ +#define XOR_CRSR_XAE_BIT (1<<30) /* enable */ +#define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */ +#define XOR_CRSR_PAUS_BIT (1<<28) /* pause */ +#define XOR_CRSR_64BA_BIT (1<<27) /* 64/32 CB format */ +#define XOR_CRSR_CLP_BIT (1<<25) /* continue list processing */ + +/* + * XORCore Interrupt Enable Register + */ +#define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block Interrupt Enable */ +#define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command Interrupt Enable */ +#define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error Interrupt Enable */ +#define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */ +#define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */ + +typedef struct apm82181_plb_dma4_device { + struct resource reg; /* Resource for register */ + void __iomem *reg_base; + struct of_device *ofdev; + struct device *dev; +} apm82181_plb_dma_t; + +/** + * struct apm82181_dma_device - internal representation of an DMA device + * @id: HW DMA Device selector + * @ofdev: OF device + * @dcr_base: dcr base of HW PLB DMA channels + * @reg_base: base of ADMA XOR channel + * @dma_desc_pool: base of DMA descriptor region (DMA address) + * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) + * @pool_size: memory pool size for the channel device + * @common: embedded struct dma_device + * @cap_mask: capabilities of ADMA channels + */ +typedef struct apm82181_plb_dma_device { + int id; + struct of_device *ofdev; + u32 dcr_base; + void __iomem *xor_base; + struct device *dev; + struct dma_device common; + struct apm82181_plb_dma4_device *pdma; + void *dma_desc_pool_virt; + u32 pool_size; + dma_addr_t dma_desc_pool; + dma_cap_mask_t cap_mask; +} apm82181_dev_t; + +/** + * struct apm82181_dma_chan - internal representation of an ADMA channel + * @lock: serializes enqueue/dequeue operations to the slot pool + * @device: parent device + * @chain: device chain view of the descriptors + * @common: common dmaengine channel object members + * @all_slots: complete domain of slots usable by the channel + * @reg: Resource for register + * @pending: allows batching of hardware operations + * @completed_cookie: identifier for the most recently completed operation + * @slots_allocated: records the actual size of the descriptor slot pool + * @hw_chain_inited: h/w descriptor chain initialization flag + * @irq_tasklet: bottom half where apm82181_adma_slot_cleanup runs + * @needs_unmap: if buffers should not be unmapped upon final processing + */ +typedef struct apm82181_plb_dma_chan { + spinlock_t lock; + struct apm82181_plb_dma_device *device; + struct timer_list cleanup_watchdog; + struct list_head chain; + struct dma_chan common; + struct list_head all_slots; + struct apm82181_adma_plb_desc_slot *last_used; + int pending; + dma_cookie_t completed_cookie; + int slots_allocated; + int hw_chain_inited; + struct tasklet_struct irq_tasklet; + u8 needs_unmap; + phys_addr_t current_cdb_addr; +} apm82181_ch_t; + +typedef struct apm82181_adma_plb_desc_slot { + dma_addr_t phys; + struct apm82181_adma_plb_desc_slot *group_head; + struct apm82181_adma_plb_desc_slot *hw_next; + struct dma_async_tx_descriptor async_tx; + struct list_head slot_node; + struct list_head chain_node; + struct list_head group_list; + unsigned int unmap_len; + void *hw_desc; + u16 stride; + u16 idx; + u16 slot_cnt; + u8 src_cnt; + u8 dst_cnt; + u8 slots_per_op; + u8 descs_per_op; + unsigned long flags; + unsigned long reverse_flags[8]; +#define APM82181_DESC_INT 0 /* generate interrupt on complete */ + +}apm82181_desc_t; + +typedef struct { + u32 ce:1; + u32 cie:1; + u32 td:1; + u32 pl:1; + u32 pw:3; + u32 dai:1; + u32 sai:1; + u32 ben:1; + u32 tm:2; + u32 psc:2; + u32 pwc:6; + u32 phc:3; + u32 etd:1; + u32 tce:1; + u32 cp:2; + u32 pf:2; + u32 dec:1; + u32 sl:1; + u32 reserved:1; +} __attribute__((packed)) dma_cdb_ctrl_t; + +typedef struct { + u32 link:1; + u32 sgl:1; + u32 tcie:1; + u32 etie:1; + u32 eie:1; + u32 sid:3; + u32 bten:1; + u32 bsiz:2; + u32 pce:1; + u32 tc:20; +} __attribute__((packed)) dma_cdb_count_t; +/* scatter/gather descriptor struct */ +typedef struct dma_cdb { + dma_cdb_ctrl_t ctrl; + dma_cdb_count_t cnt; + u32 src_hi; + u32 src_lo; + u32 dest_hi; + u32 dest_lo; + u32 sg_hi; + u32 sg_lo; +}dma_cdb_t; + +typedef struct { + uint32_t control; + phys_addr_t src_addr; + phys_addr_t dst_addr; + uint32_t control_count; + uint32_t next; +} ppc_sgl_t; + +/* + * XOR Accelerator engine Command Block Type + */ +typedef struct { + /* + * Basic 64-bit format XOR CB + */ + u32 cbc; /* control */ + u32 cbbc; /* byte count */ + u32 cbs; /* status */ + u8 pad0[4]; /* reserved */ + u32 cbtah; /* target address high */ + u32 cbtal; /* target address low */ + u32 cblah; /* link address high */ + u32 cblal; /* link address low */ + struct { + u32 h; + u32 l; + } __attribute__ ((packed)) ops [16]; +} __attribute__ ((packed)) xor_cb_t; + +/* + * XOR hardware registers + */ +typedef struct { + u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */ + u8 pad0[352]; /* reserved */ + u32 cbcr; /* CB control register */ + u32 cbbcr; /* CB byte count register */ + u32 cbsr; /* CB status register */ + u8 pad1[4]; /* reserved */ + u32 cbtahr; /* operand target address high register */ + u32 cbtalr; /* operand target address low register */ + u32 cblahr; /* CB link address high register */ + u32 cblalr; /* CB link address low register */ + u32 crsr; /* control set register */ + u32 crrr; /* control reset register */ + u32 ccbahr; /* current CB address high register */ + u32 ccbalr; /* current CB address low register */ + u32 plbr; /* PLB configuration register */ + u32 ier; /* interrupt enable register */ + u32 pecr; /* parity error count register */ + u32 sr; /* status register */ + u32 revidr; /* revision ID register */ +} xor_regs_t; + +#endif diff --git a/arch/powerpc/include/asm/async_tx.h b/arch/powerpc/include/asm/async_tx.h new file mode 100644 index 00000000000..6b49cf1f702 --- /dev/null +++ b/arch/powerpc/include/asm/async_tx.h @@ -0,0 +1,88 @@ +/* + * Copyright(c) 2008 DENX Engineering. All rights reserved. + * + * Author: Yuri Tikhonov <yur@emcraft.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * The full GNU General Public License is included in this distribution in the + * file called COPYING. + */ +#ifndef _PPC_ASYNC_TX_H_ +#define _PPC_ASYNC_TX_H_ + +#if defined(CONFIG_440SPe) || defined(CONFIG_440SP) +extern int ppc440spe_adma_estimate (struct dma_chan *chan, + enum dma_transaction_type cap, struct page **src_lst, + int src_cnt, size_t src_sz); +#define ppc_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) \ + ppc440spe_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +extern int ppc460ex_adma_estimate (struct dma_chan *chan, + enum dma_transaction_type cap, struct page **src_lst, + int src_cnt, size_t src_sz); +#define ppc_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) \ + ppc460ex_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) +#elif defined(CONFIG_APM82181) +extern int apm82181_adma_estimate (struct dma_chan *chan, + enum dma_transaction_type cap, struct page **src_lst, + int src_cnt, size_t src_sz); +#define ppc_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) \ + apm82181_adma_estimate(chan, cap, src_lst, src_cnt, src_sz) +#endif + +struct ppc_dma_chan_ref { + struct dma_chan *chan; + struct list_head node; +}; + +extern struct list_head ppc_adma_chan_list; + +/** + * ppc_async_tx_find_best_channel - find a channel with the maximum rank for the + * transaction type given (the rank of the operation is the value + * returned by the device_estimate method). + * @cap: transaction type + * @src_lst: array of pointers to sources for the transaction + * @src_cnt: number of arguments (size of the srcs array) + * @src_sz: length of the each argument pointed by srcs + */ +static inline struct dma_chan * +ppc_async_tx_find_best_channel (enum dma_transaction_type cap, + struct page **src_lst, int src_cnt, size_t src_sz) +{ + struct dma_chan *best_chan = NULL; + struct ppc_dma_chan_ref *ref; + int best_rank = -1; + + list_for_each_entry(ref, &ppc_adma_chan_list, node) + if (dma_has_cap(cap, ref->chan->device->cap_mask)) { + int rank; + + rank = ppc_adma_estimate (ref->chan, + cap, src_lst, src_cnt, src_sz); + if (rank > best_rank) { + best_rank = rank; + best_chan = ref->chan; + } + } + + return best_chan; +} + +#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \ + ppc_async_tx_find_best_channel(type, src, src_count, len) + +#endif diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h index 828e3aa1f2f..7e15ef98b69 100644 --- a/arch/powerpc/include/asm/dcr-regs.h +++ b/arch/powerpc/include/asm/dcr-regs.h @@ -28,10 +28,53 @@ #define DCRN_CPR0_CONFIG_ADDR 0xc #define DCRN_CPR0_CONFIG_DATA 0xd -/* SDRs (440GX and 440SP/440SPe) */ +#define CPR0_CLKUPD 0x0020 +#define CPR0_CLKUPD_CUD 0x80000000 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLC_ENG 0x40000000 +#define CPR0_PLLD 0x0060 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CPR0_PLBED 0x0080 +#define CPR0_PLBED_DIV1 0x01000000 +#define CPR0_PLBED_DIV2 0x02000000 +#define CPR0_PLBED_DIV3 0x03000000 +#define CPR0_PLBED_DIV4 0x04000000 +#define CPR0_PLBED_DIV5 0x05000000 +#define CPR0_PLBED_DIV6 0x06000000 +#define CPR0_PLBED_DIV7 0x07000000 +#endif +#if defined(CONFIG_APM82181) || defined(CONFIG_APM82161) +#define CPR0_DDR2D 0x0100 +#define CPR0_DDR2D_DIV1 0x02000000 +#endif +#define CPR0_PLB2D 0x00a0 +#define CPR0_PLB2D_DIV1 0x02000000 + +#define CPR0_OPBD 0x00c0 +#define CPR0_OPBD_DIV1 0x01000000 +#define CPR0_OPBD_DIV2 0x02000000 +#define CPR0_OPBD_DIV3 0x03000000 +#define CPR0_PERD 0x00e0 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CPR0_AHBD 0x0100 +#define CPR0_AHBD_DIV1 0x01000000 +#endif +#define CPR0_ICFG 0x0140 + +/* SDRs (440GX, 440SP, 440SPe 460EX and 460GT) */ #define DCRN_SDR0_CONFIG_ADDR 0xe #define DCRN_SDR0_CONFIG_DATA 0xf +#define SDR0_SRST0 0x0200 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || defined(CONFIG_APM82181)\ + || defined(CONFIG_APM82161) + +#define SDR0_SRST_I2ODMA (0x80000000 >> 15) /* Reset I2O/DMA */ +#define SDR0_SRST0_DMC 0x00200000 +#define SDR0_SRST0_L2C 0x00000004 +#define SDR0_SRST0_UART0 0x80000000 +#endif +#define SDR0_SRST1 0x0201 #define SDR0_PFC0 0x4100 #define SDR0_PFC1 0x4101 #define SDR0_PFC1_EPS 0x1c00000 @@ -75,6 +118,77 @@ #define ICINTSTAT_ICTX1 0x20000000 #define ICINTSTAT_ICTX 0x60000000 +/* SDR read/write helper macros */ +#define SDR_READ(offset) ({\ + mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \ + mfdcr(DCRN_SDR0_CONFIG_DATA);}) +#define SDR_WRITE(offset, data) ({\ + mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \ + mtdcr(DCRN_SDR0_CONFIG_DATA,data);}) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + /* I2O DMA registers*/ + #define DCRN_I2O0_IBAL 0x066 + #define DCRN_I2O0_IBAH 0x067 + + /* 460EX/GT XOR DCRs */ + #define DCRN_MQ0_XORBA 0x44 + #define DCRN_MQ0_CF1H 0x45 + #define DCRN_MQ0_CF2H 0x46 + #define DCRN_MQ0_BAUL 0x4a + #define DCRN_MQ0_CF1L 0x4b + #define DCRN_MQ0_CFBHL 0x4f + #define DCRN_MQ0_BAUH 0x50 + + /* RXOR BlockSize Register */ + #define MQ0_CF2H_RXOR_BS_MASK 0xfffffe00 + + /* HB/LL Paths Configuration Register */ + #define MQ0_CFBHL_TPLM 28 + #define MQ0_CFBHL_HBCL 23 + #define MQ0_CFBHL_POLY 15 + + + + #define MQ_CF1_AAFR 31 + #define MQ_CF1_RPLM 12 + #define MQ_CF1_RPEN 11 + #define MQ_CF1_RFTE 10 + #define MQ_CF1_WRCL 7 + /* MQ HB/LL Configuration masks & shifts */ + #define MQ_CF1_RPLM_MSK 0xF + #define MQ_CF1_WRCL_MSK 0x7 + /* HB/LL Paths Configuration Register */ + #define MQ0_CFBHL_TPLM 28 + #define MQ0_CFBHL_HBCL 23 + #define MQ0_CFBHL_POLY 15 + + /* 460EX/460GT PLB Arbiter DCRs */ + #define DCRN_PLB_REVID 0x080 /* PLB Revision ID */ + #define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */ + + #define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */ + #define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */ + #define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */ + #define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */ + #define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */ + + #define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */ + #define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */ + #define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */ + #define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */ + #define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */ + + /* PLB0/1 ACR masks & shifts */ + #define PLB_ACR_RDP_MSK 0x3 + + #define PLB_ACR_PPM0 31 + #define PLB_ACR_PPM1 30 + #define PLB_ACR_PPM3 28 + #define PLB_ACR_HBU 27 + #define PLB_ACR_RDP 25 + #define PLB_ACR_WRP 24 + #endif + /* SDRs (460EX/460GT) */ #define SDR0_ETH_CFG 0x4103 #define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */ @@ -130,6 +244,7 @@ #define L2C_CFG_NAM 0x00000100 #define L2C_CFG_SMCM 0x00000080 #define L2C_CFG_NBRM 0x00000040 +#define L2C_CFG_SNP440 0x00000010 #define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */ #define DCRN_L2C0_CMD 0x01 #define L2C_CMD_CLR 0x80000000 @@ -157,4 +272,124 @@ #define L2C_SNP_SSR_32G 0x0000f000 #define L2C_SNP_ESR 0x00000800 +/* MQ registers (460EX/460GT) */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define MQ0_B0BASE 0x0040 +#define MQ0_B1BASE 0x0041 +#define MQ0_B2BASE 0x0042 +#define MQ0_B3BASE 0x0043 +#define MQ0_CF1H 0x0045 +#define MQ0_BAUL 0x004A +#define MQ0_CF1L 0x004B +#define MQ0_CFBHL 0x004F +#define MQ0_BAUH 0x0050 +#endif /*defined(CONFIG_460EX) || defined(CONFIG_460GT)*/ + +/* DDR registers to (460EX/460GT) */ +#if defined(CONFIG_APM82181) || defined(CONFIG_APM82161) +#define DCRN_SDRAM0_CONFIG_ADDR 0x10 +#define DCRN_SDRAM0_CONFIG_DATA 0x11 + +#define SDRAM0_BESR 0x0000 +#define SDRAM0_BEARL 0x0002 +#define SDRAM0_BEARH 0x0003 +#define SDRAM0_WMIRQ 0x0006 +#define SDRAM0_PLBOPT 0x0008 +#define SDRAM0_PUABA 0x0009 +#define SDRAM0_MCSTAT 0x001F +#define SDRAM0_MCSTAT_MIC 0x80000000 +#define SDRAM0_MCSTAT_SRMS 0x40000000 +#define SDRAM0_MCOPT1 0x0020 +#define SDRAM0_MCOPT2 0x0021 +#define SDRAM0_MCOPT2_SREN 0x80000000 +#define SDRAM0_MCOPT2_IPTR 0x20000000 +#define SDRAM0_MCOPT2_DCEN 0x08000000 +#define SDRAM0_MODT0 0x0022 +#define SDRAM0_MODT1 0x0023 +#define SDRAM0_CODT 0x0026 +#define SDRAM0_RTR 0x0030 +#define SDRAM0_MB0CF 0x0040 +#define SDRAM0_MB1CF 0x0044 +#define SDRAM0_INITPLR0 0x0050 +#define SDRAM0_INITPLR1 0x0051 +#define SDRAM0_INITPLR2 0x0052 +#define SDRAM0_INITPLR3 0x0053 +#define SDRAM0_INITPLR4 0x0054 +#define SDRAM0_INITPLR5 0x0055 +#define SDRAM0_INITPLR6 0x0056 +#define SDRAM0_INITPLR7 0x0057 +#define SDRAM0_INITPLR8 0x0058 +#define SDRAM0_INITPLR9 0x0059 +#define SDRAM0_INITPLR10 0x005A +#define SDRAM0_INITPLR11 0x005B +#define SDRAM0_INITPLR12 0x005C +#define SDRAM0_INITPLR13 0x005D +#define SDRAM0_INITPLR14 0x005E +#define SDRAM0_INITPLR15 0x005F +#define SDRAM0_RQDC 0x0070 +#define SDRAM0_RFDC 0x0074 +#define SDRAM0_RDCC 0x0078 +#define SDRAM0_DLCR 0x007A +#define SDRAM0_CLKTR 0x0080 +#define SDRAM0_WRDTR 0x0081 +#define SDRAM0_SDTR1 0x0085 +#define SDRAM0_SDTR2 0x0086 +#define SDRAM0_SDTR3 0x0087 +#define SDRAM0_MMODE 0x0088 +#define SDRAM0_MEMODE 0x0089 +#define SDRAM0_ECCES 0x0098 +#else + +#define DCRN_MCIF0_CONFIG_ADDR 0x10 +#define DCRN_MCIF0_CONFIG_DATA 0x11 + +#define MCIF0_MCSTAT 0x0014 +#define MCIF0_MCSTAT_MIC 0x80000000 +#define MCIF0_MCSTAT_SRMS 0x40000000 +#define MCIF0_MCOPT1 0x0020 +#define MCIF0_MCOPT2 0x0021 +#define MCIF0_MCOPT2_SREN 0x80000000 +#define MCIF0_MCOPT2_IPTR 0x20000000 +#define MCIF0_MCOPT2_DCEN 0x08000000 +#define MCIF0_MODT0 0x0022 +#define MCIF0_MODT1 0x0023 +#define MCIF0_MODT2 0x0024 +#define MCIF0_MODT3 0x0025 +#define MCIF0_CODT 0x0026 +#define MCIF0_RTR 0x0030 +#define MCIF0_MB0CF 0x0040 +#define MCIF0_MB1CF 0x0044 +#define MCIF0_MB2CF 0x0048 +#define MCIF0_MB3CF 0x004C +#define MCIF0_INITPLR0 0x0050 +#define MCIF0_INITPLR1 0x0051 +#define MCIF0_INITPLR2 0x0052 +#define MCIF0_INITPLR3 0x0053 +#define MCIF0_INITPLR4 0x0054 +#define MCIF0_INITPLR5 0x0055 +#define MCIF0_INITPLR6 0x0056 +#define MCIF0_INITPLR7 0x0057 +#define MCIF0_INITPLR8 0x0058 +#define MCIF0_INITPLR9 0x0059 +#define MCIF0_INITPLR10 0x005A +#define MCIF0_INITPLR11 0x005B +#define MCIF0_INITPLR12 0x005C +#define MCIF0_INITPLR13 0x005D +#define MCIF0_INITPLR14 0x005E +#define MCIF0_INITPLR15 0x005F +#define MCIF0_RQDC 0x0070 +#define MCIF0_RFDC 0x0074 +#define MCIF0_RCDC 0x0078 +#define MCIF0_DLCR 0x007A +#define MCIF0_CLKTR 0x0080 +#define MCIF0_WRDTR 0x0081 +#define MCIF0_SDTR1 0x0085 +#define MCIF0_SDTR2 0x0086 +#define MCIF0_SDTR3 0x0087 +#define MCIF0_MMODE 0x0088 +#define MCIF0_MEMODE 0x0089 +#define MCIF0_ECCES 0x0098 + +#endif /* defined(APM82181) || defined(APM82161) */ + #endif /* __DCR_REGS_H__ */ diff --git a/arch/powerpc/include/asm/mmio-regs.h b/arch/powerpc/include/asm/mmio-regs.h new file mode 100644 index 00000000000..d97f22e67e7 --- /dev/null +++ b/arch/powerpc/include/asm/mmio-regs.h @@ -0,0 +1,61 @@ +/* + * MMIO register definitions used on various IBM/AMCC * 4xx processors + * + * (C) Copyright 2008, Applied Micro Circuits Corporation + * Victor Gallardo (vgallardo@amcc.com) + * + * based on dcr-regs.h + * + * Copyright 2007 Benjamin Herrenschmidt, IBM Corp + * <benh@kernel.crashing.org> + */ + +#ifndef __MMIO_REGS_H__ +#define __MMIO_REGS_H__ + +/* IIC Register offset */ +#define IIC_MDBUF 0x00 +#define IIC_SDBUF 0x02 +#define IIC_LMADR 0x04 +#define IIC_HMADR 0x05 +#define IIC_CNTL 0x06 +#define IIC_MDCNTL 0x07 +#define IIC_STS 0x08 +#define IIC_EXTSTS 0x09 +#define IIC_LSADR 0x0A +#define IIC_HSADR 0x0B +#define IIC_CLKDIV 0x0C +#define IIC_INTRMSK 0x0D +#define IIC_XFRCNT 0x0E +#define IIC_XTCNTLSS 0x0F +#define IIC_DIRECTCNTL 0x10 + +/* STS Register Bit definition */ +#define IIC_STS_PT 0x01 +#define IIC_STS_IRQA 0x02 +#define IIC_STS_ERR 0x04 +#define IIC_STS_SCMP 0x08 +#define IIC_STS_MDBF 0x10 +#define IIC_STS_MDBS 0x20 +#define IIC_STS_SLPR 0x40 +#define IIC_STS_SSS 0x80 + +/* MDCNTL Register Bit definition */ +#define IIC_MDCNTL_HSCL 0x01 +#define IIC_MDCNTL_EUBS 0x02 +#define IIC_MDCNTL_EINT 0x04 +#define IIC_MDCNTL_ESM 0x08 +#define IIC_MDCNTL_FSM 0x10 +#define IIC_MDCNTL_EGC 0x20 +#define IIC_MDCNTL_FMDB 0x40 +#define IIC_MDCNTL_FSDB 0x80 + +/* CNTL Register Bit definition */ +#define IIC_CNTL_PT 0x01 +#define IIC_CNTL_READ 0x02 +#define IIC_CNTL_CHT 0x04 +#define IIC_CNTL_RPST 0x08 +#define IIC_CNTL_AMD 0x40 +#define IIC_CNTL_HMT 0x80 + +#endif /* __MMIO_REGS_H__ */ diff --git a/arch/powerpc/include/asm/ppc460ex_adma.h b/arch/powerpc/include/asm/ppc460ex_adma.h new file mode 100644 index 00000000000..828a62fbe68 --- /dev/null +++ b/arch/powerpc/include/asm/ppc460ex_adma.h @@ -0,0 +1,186 @@ +/* + * 2006-2007 (C) DENX Software Engineering. + * + * Author: Yuri Tikhonov <yur@emcraft.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of + * any kind, whether express or implied. + */ + +#ifndef PPC460EX_ADMA_H +#define PPC460EX_ADMA_H + +#include <linux/types.h> +#include <asm/ppc460ex_dma.h> + +#define to_ppc460ex_adma_chan(chan) container_of(chan,ppc460ex_ch_t,common) +#define to_ppc460ex_adma_device(dev) container_of(dev,ppc460ex_dev_t,common) +#define tx_to_ppc460ex_adma_slot(tx) container_of(tx,ppc460ex_desc_t,async_tx) + +#define PPC460EX_R6_PROC_ROOT "driver/460ex_raid6" +#define PPC460EX_R5_PROC_ROOT "driver/460ex_raid5" +/* Default polynomial (for 440SP is only available) */ +#define PPC460EX_DEFAULT_POLY 0x4d + +#define PPC460EX_ADMA_WATCHDOG_MSEC 3 +#define PPC460EX_ADMA_THRESHOLD 1 +#define ADMA_DESC_MEM_OCM 0x1 + +#define PPC460EX_DMA0_ID 0 +#define PPC460EX_DMA1_ID 1 +#define PPC460EX_XOR_ID 2 + +#define PPC460EX_ADMA_DMA_MAX_BYTE_COUNT 0xFFFFFFUL +/* this is the XOR_CBBCR width */ +#define PPC460EX_ADMA_XOR_MAX_BYTE_COUNT (1 << 31) +#define PPC460EX_ADMA_ZERO_SUM_MAX_BYTE_COUNT PPC460EX_ADMA_XOR_MAX_BYTE_COUNT + +#define PPC460EX_RXOR_RUN 0 + +#undef ADMA_LL_DEBUG + +/** + * struct ppc460ex_adma_device - internal representation of an ADMA device + * @pdev: Platform device + * @id: HW ADMA Device selector + * @dma_desc_pool: base of DMA descriptor region (DMA address) + * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) + * @common: embedded struct dma_device + */ +typedef struct ppc460ex_adma_device { + //struct platform_device *pdev; + struct of_device *odev; + struct resource res[3]; /* Resource for register */ + void *dma_desc_pool_virt; + struct device *dev; + + int id; + dma_addr_t dma_desc_pool; + struct dma_device common; + + int eot_irq; + int err_irq; + int desc_memory; + +} ppc460ex_dev_t; + +/** + * struct ppc460ex_adma_chan - internal representation of an ADMA channel + * @lock: serializes enqueue/dequeue operations to the slot pool + * @device: parent device + * @chain: device chain view of the descriptors + * @common: common dmaengine channel object members + * @all_slots: complete domain of slots usable by the channel + * @pending: allows batching of hardware operations + * @completed_cookie: identifier for the most recently completed operation + * @slots_allocated: records the actual size of the descriptor slot pool + * @hw_chain_inited: h/w descriptor chain initialization flag + * @irq_tasklet: bottom half where ppc460ex_adma_slot_cleanup runs + * @needs_unmap: if buffers should not be unmapped upon final processing + */ +typedef struct ppc460ex_adma_chan { + spinlock_t lock; + struct ppc460ex_adma_device *device; + struct timer_list cleanup_watchdog; + struct list_head chain; + struct dma_chan common; + struct list_head all_slots; + struct ppc460ex_adma_desc_slot *last_used; + int pending; + dma_cookie_t completed_cookie; + int slots_allocated; + int hw_chain_inited; + struct tasklet_struct irq_tasklet; + u8 needs_unmap; +} ppc460ex_ch_t; + +typedef struct ppc460ex_rxor { + u32 addrl; + u32 addrh; + int len; + int xor_count; + int addr_count; + int desc_count; + int state; +} ppc460ex_rxor_cursor_t; + +/** + * struct ppc460ex_adma_desc_slot - PPC460EX-ADMA software descriptor + * @phys: hardware address of the hardware descriptor chain + * @group_head: first operation in a transaction + * @hw_next: pointer to the next descriptor in chain + * @async_tx: support for the async_tx api + * @slot_node: node on the iop_adma_chan.all_slots list + * @chain_node: node on the op_adma_chan.chain list + * @group_list: list of slots that make up a multi-descriptor transaction + * for example transfer lengths larger than the supported hw max + * @unmap_len: transaction bytecount + * @hw_desc: virtual address of the hardware descriptor chain + * @stride: currently chained or not + * @idx: pool index + * @slot_cnt: total slots used in an transaction (group of operations) + * @src_cnt: number of sources set in this descriptor + * @dst_cnt: number of destinations set in the descriptor + * @slots_per_op: number of slots per operation + * @descs_per_op: number of slot per P/Q operation see comment + * for ppc460ex_prep_dma_pqxor function + * @flags: desc state/type + * @reverse_flags: 1 if a corresponding rxor address uses reversed address order + * @xor_check_result: result of zero sum + * @crc32_result: result crc calculation + */ +typedef struct ppc460ex_adma_desc_slot { + dma_addr_t phys; + struct ppc460ex_adma_desc_slot *group_head; + struct ppc460ex_adma_desc_slot *hw_next; + struct dma_async_tx_descriptor async_tx; + struct list_head slot_node; + struct list_head chain_node; /* node in channel ops list */ + struct list_head group_list; /* list */ + unsigned int unmap_len; + void *hw_desc; + u16 stride; + u16 idx; + u16 slot_cnt; + u8 src_cnt; + u8 dst_cnt; + u8 slots_per_op; + u8 descs_per_op; + unsigned long flags; + unsigned long reverse_flags[8]; + +#define PPC460EX_DESC_INT 0 /* generate interrupt on complete */ +#define PPC460EX_ZERO_P 1 /* clear P destionaion */ +#define PPC460EX_ZERO_Q 2 /* clear Q destination */ +#define PPC460EX_COHERENT 3 /* src/dst are coherent */ + +#define PPC460EX_DESC_WXOR 4 /* WXORs are in chain */ +#define PPC460EX_DESC_RXOR 5 /* RXOR is in chain */ + +#define PPC460EX_DESC_RXOR123 8 /* CDB for RXOR123 operation */ +#define PPC460EX_DESC_RXOR124 9 /* CDB for RXOR124 operation */ +#define PPC460EX_DESC_RXOR125 10 /* CDB for RXOR125 operation */ +#define PPC460EX_DESC_RXOR12 11 /* CDB for RXOR12 operation */ +#define PPC460EX_DESC_RXOR_REV 12 /* CDB contains srcs in reversed order */ + +#define PPC460EX_DESC_PCHECK 13 +#define PPC460EX_DESC_QCHECK 14 + +#define PPC460EX_DESC_RXOR_MSK 0x3 + + ppc460ex_rxor_cursor_t rxor_cursor; + + union { + u32 *xor_check_result; + u32 *crc32_result; + }; +} ppc460ex_desc_t; + +typedef struct ppc460ex_adma_platform_data { + int hw_id; + dma_cap_mask_t cap_mask; + size_t pool_size; +} ppc460ex_aplat_t; + +#endif /* PPC460EX_ADMA_H */ diff --git a/arch/powerpc/include/asm/ppc460ex_dma.h b/arch/powerpc/include/asm/ppc460ex_dma.h new file mode 100644 index 00000000000..a758ca4a5f9 --- /dev/null +++ b/arch/powerpc/include/asm/ppc460ex_dma.h @@ -0,0 +1,262 @@ +/* + * include/asm-ppc/ppc440spe_dma.h + * + * 440SPe's DMA engines support header file + * + * 2006 (c) DENX Software Engineering + * + * Author: Yuri Tikhonov <yur@emcraft.com> + * + * This file is licensed under the term of the GNU General Public License + * version 2. The program licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef PPC440SPE_DMA_H +#define PPC440SPE_DMA_H + +#include <asm/types.h> + +/* Number of elements in the array with statical CDBs */ +#define MAX_STAT_DMA_CDBS 16 +/* Number of DMA engines available on the contoller */ +#define DMA_ENGINES_NUM 1 |