diff options
Diffstat (limited to 'arch/openrisc')
81 files changed, 10906 insertions, 0 deletions
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig new file mode 100644 index 00000000000..4558bafbd1a --- /dev/null +++ b/arch/openrisc/Kconfig @@ -0,0 +1,207 @@ +# +# For a description of the syntax of this configuration file, +# see Documentation/kbuild/config-language.txt. +# + +config OPENRISC + def_bool y + select OF + select OF_EARLY_FLATTREE + select HAVE_MEMBLOCK + select ARCH_WANT_OPTIONAL_GPIOLIB + select HAVE_ARCH_TRACEHOOK + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW + select GENERIC_IOMAP + +config MMU + def_bool y + +config WISHBONE_BUS_BIG_ENDIAN + def_bool y + +config SYMBOL_PREFIX + string + default "" + +config HAVE_DMA_ATTRS + def_bool y + +config UID16 + def_bool y + +config RWSEM_GENERIC_SPINLOCK + def_bool y + +config RWSEM_XCHGADD_ALGORITHM + def_bool n + +config GENERIC_HWEIGHT + def_bool y + +config GENERIC_IOMAP + def_bool y + +config NO_IOPORT + def_bool y + +config GENERIC_GPIO + def_bool y + +config GENERIC_CLOCKEVENTS + def_bool y + +config TRACE_IRQFLAGS_SUPPORT + def_bool y + +# For now, use generic checksum functions +#These can be reimplemented in assembly later if so inclined +config GENERIC_CSUM + def_bool y + +config GENERIC_FIND_NEXT_BIT + def_bool y + +source "init/Kconfig" + + +menu "Processor type and features" + +choice + prompt "Subarchitecture" + default OR1K_1200 + +config OR1K_1200 + bool "OR1200" + help + Generic OpenRISC 1200 architecture + +endchoice + +config OPENRISC_BUILTIN_DTB + string "Builtin DTB" + default "" + +menu "Class II Instructions" + +config OPENRISC_HAVE_INST_FF1 + bool "Have instruction l.ff1" + default y + help + Select this if your implementation has the Class II instruction l.ff1 + +config OPENRISC_HAVE_INST_FL1 + bool "Have instruction l.fl1" + default y + help + Select this if your implementation has the Class II instruction l.fl1 + +config OPENRISC_HAVE_INST_MUL + bool "Have instruction l.mul for hardware multiply" + default y + help + Select this if your implementation has a hardware multiply instruction + +config OPENRISC_HAVE_INST_DIV + bool "Have instruction l.div for hardware divide" + default y + help + Select this if your implementation has a hardware divide instruction +endmenu + + +source "kernel/time/Kconfig" +source kernel/Kconfig.hz +source kernel/Kconfig.preempt +source "mm/Kconfig" + +config OPENRISC_NO_SPR_SR_DSX + bool "use SPR_SR_DSX software emulation" if OR1K_1200 + default y + help + SPR_SR_DSX bit is status register bit indicating whether + the last exception has happened in delay slot. + + OpenRISC architecture makes it optional to have it implemented + in hardware and the OR1200 does not have it. + + Say N here if you know that your OpenRISC processor has + SPR_SR_DSX bit implemented. Say Y if you are unsure. + +config CMDLINE + string "Default kernel command string" + default "" + help + On some architectures there is currently no way for the boot loader + to pass arguments to the kernel. For these architectures, you should + supply some command-line options at build time by entering them + here. + +menu "Debugging options" + +config DEBUG_STACKOVERFLOW + bool "Check for kernel stack overflow" + default y + help + Make extra checks for space avaliable on stack in some + critical functions. This will cause kernel to run a bit slower, + but will catch most of kernel stack overruns and exit gracefuly. + + Say Y if you are unsure. + +config JUMP_UPON_UNHANDLED_EXCEPTION + bool "Try to die gracefully" + default y + help + Now this puts kernel into infinite loop after first oops. Till + your kernel crashes this doesn't have any influence. + + Say Y if you are unsure. + +config OPENRISC_EXCEPTION_DEBUG + bool "Print processor state at each exception" + default n + help + This option will make your kernel unusable for all but kernel + debugging. + + Say N if you are unsure. + +config OPENRISC_ESR_EXCEPTION_BUG_CHECK + bool "Check for possible ESR exception bug" + default n + help + This option enables some checks that might expose some problems + in kernel. + + Say N if you are unsure. + +endmenu + +endmenu + +menu "Executable file formats" + +source "fs/Kconfig.binfmt" + +endmenu + +source "net/Kconfig" + +source "drivers/Kconfig" + +source "fs/Kconfig" + +source "security/Kconfig" + +source "crypto/Kconfig" + +source "lib/Kconfig" + +menu "Kernel hacking" + +source "lib/Kconfig.debug" + +endmenu diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile new file mode 100644 index 00000000000..158ae4c0dc6 --- /dev/null +++ b/arch/openrisc/Makefile @@ -0,0 +1,55 @@ +# BK Id: %F% %I% %G% %U% %#% +# +# This file is included by the global makefile so that you can add your own +# architecture-specific flags and dependencies. Remember to do have actions +# for "archclean" and "archdep" for cleaning up and making dependencies for +# this architecture +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 1994 by Linus Torvalds +# Modifications for the OpenRISC architecture: +# Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> +# Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> +# +# Based on: +# arch/i386/Makefile + +KBUILD_DEFCONFIG := or1ksim_defconfig + +LDFLAGS := +OBJCOPYFLAGS := -O binary -R .note -R .comment -S +LDFLAGS_vmlinux := +LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) + +KBUILD_CFLAGS += -pipe -ffixed-r10 + +ifeq ($(CONFIG_OPENRISC_HAVE_INST_MUL),y) + KBUILD_CFLAGS += $(call cc-option,-mhard-mul) +else + KBUILD_CFLAGS += $(call cc-option,-msoft-mul) +endif + +ifeq ($(CONFIG_OPENRISC_HAVE_INST_DIV),y) + KBUILD_CFLAGS += $(call cc-option,-mhard-div) +else + KBUILD_CFLAGS += $(call cc-option,-msoft-div) +endif + +head-y := arch/openrisc/kernel/head.o arch/openrisc/kernel/init_task.o + +core-y += arch/openrisc/lib/ \ + arch/openrisc/kernel/ \ + arch/openrisc/mm/ +libs-y += $(LIBGCC) + +ifneq '$(CONFIG_OPENRISC_BUILTIN_DTB)' '""' +BUILTIN_DTB := y +else +BUILTIN_DTB := n +endif +core-$(BUILTIN_DTB) += arch/openrisc/boot/ + +all: vmlinux diff --git a/arch/openrisc/README.openrisc b/arch/openrisc/README.openrisc new file mode 100644 index 00000000000..c9f7edf2b9a --- /dev/null +++ b/arch/openrisc/README.openrisc @@ -0,0 +1,99 @@ +OpenRISC Linux +============== + +This is a port of Linux to the OpenRISC class of microprocessors; the initial +target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k). + +For information about OpenRISC processors and ongoing development: + + website http://openrisc.net + +For more information about Linux on OpenRISC, please contact South Pole AB. + + email: info@southpole.se + + website: http://southpole.se + http://southpoleconsulting.com + +--------------------------------------------------------------------- + +Build instructions for OpenRISC toolchain and Linux +=================================================== + +In order to build and run Linux for OpenRISC, you'll need at least a basic +toolchain and, perhaps, the architectural simulator. Steps to get these bits +in place are outlined here. + +1) The toolchain can be obtained from openrisc.net. Instructions for building +a toolchain can be found at: + +http://openrisc.net/toolchain-build.html + +2) or1ksim (optional) + +or1ksim is the architectural simulator which will allow you to actually run +your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand. + + git clone git://openrisc.net/jonas/or1ksim-svn + + cd or1ksim + ./configure --prefix=$OPENRISC_PREFIX + make + make install + +3) Linux kernel + +Build the kernel as usual + + make ARCH=openrisc defconfig + make ARCH=openrisc + +4) Run in architectural simulator + +Grab the or1ksim platform configuration file (from the or1ksim source) and +together with your freshly built vmlinux, run your kernel with the following +incantation: + + sim -f arch/openrisc/or1ksim.cfg vmlinux + +--------------------------------------------------------------------- + +Terminology +=========== + +In the code, the following particles are used on symbols to limit the scope +to more or less specific processor implementations: + +openrisc: the OpenRISC class of processors +or1k: the OpenRISC 1000 family of processors +or1200: the OpenRISC 1200 processor + +--------------------------------------------------------------------- + +History +======== + +18. 11. 2003 Matjaz Breskvar (phoenix@bsemi.com) + initial port of linux to OpenRISC/or32 architecture. + all the core stuff is implemented and seams usable. + +08. 12. 2003 Matjaz Breskvar (phoenix@bsemi.com) + complete change of TLB miss handling. + rewrite of exceptions handling. + fully functional sash-3.6 in default initrd. + a much improved version with changes all around. + +10. 04. 2004 Matjaz Breskvar (phoenix@bsemi.com) + alot of bugfixes all over. + ethernet support, functional http and telnet servers. + running many standard linux apps. + +26. 06. 2004 Matjaz Breskvar (phoenix@bsemi.com) + port to 2.6.x + +30. 11. 2004 Matjaz Breskvar (phoenix@bsemi.com) + lots of bugfixes and enhancments. + added opencores framebuffer driver. + +09. 10. 2010 Jonas Bonn (jonas@southpole.se) + major rewrite to bring up to par with upstream Linux 2.6.36 diff --git a/arch/openrisc/TODO.openrisc b/arch/openrisc/TODO.openrisc new file mode 100644 index 00000000000..acfeef9c58e --- /dev/null +++ b/arch/openrisc/TODO.openrisc @@ -0,0 +1,16 @@ +The OpenRISC Linux port is fully functional and has been tracking upstream +since 2.6.35. There are, however, remaining items to be completed within +the coming months. Here's a list of known-to-be-less-than-stellar items +that are due for investigation shortly, i.e. our TODO list: + +-- Implement the rest of the DMA API... dma_map_sg, etc. + +-- Consolidate usage of memblock and bootmem... move everything over to + memblock. + +-- Finish the renaming cleanup... there are references to or32 in the code + which was an older name for the architecture. The name we've settled on is + or1k and this change is slowly trickling through the stack. For the time + being, or32 is equivalent to or1k. + +-- Implement optimized version of memcpy and memset diff --git a/arch/openrisc/boot/Makefile b/arch/openrisc/boot/Makefile new file mode 100644 index 00000000000..98ca185097a --- /dev/null +++ b/arch/openrisc/boot/Makefile @@ -0,0 +1,15 @@ + + +ifneq '$(CONFIG_OPENRISC_BUILTIN_DTB)' '""' +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_OPENRISC_BUILTIN_DTB)).dtb.o +else +BUILTIN_DTB := +endif +obj-y += $(BUILTIN_DTB) + +clean-files := *.dtb.S + +#DTC_FLAGS ?= -p 1024 + +$(obj)/%.dtb: $(src)/dts/%.dts + $(call cmd,dtc) diff --git a/arch/openrisc/boot/dts/or1ksim.dts b/arch/openrisc/boot/dts/or1ksim.dts new file mode 100644 index 00000000000..5d4f9027afa --- /dev/null +++ b/arch/openrisc/boot/dts/or1ksim.dts @@ -0,0 +1,50 @@ +/dts-v1/; +/ { + compatible = "opencores,or1ksim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "console=uart,mmio,0x90000000,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + }; + + /* + * OR1K PIC is built into CPU and accessed via special purpose + * registers. It is not addressable and, hence, has no 'reg' + * property. + */ + pic: pic { + compatible = "opencores,or1k-pic"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@90000000 { + compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; + reg = <0x90000000 0x100>; + interrupts = <2>; + clock-frequency = <20000000>; + }; + + enet0: ethoc@92000000 { + compatible = "opencores,ethmac-rtlsvn338"; + reg = <0x92000000 0x100>; + interrupts = <4>; + }; +}; diff --git a/arch/openrisc/configs/or1ksim_defconfig b/arch/openrisc/configs/or1ksim_defconfig new file mode 100644 index 00000000000..ea172bdfa36 --- /dev/null +++ b/arch/openrisc/configs/or1ksim_defconfig @@ -0,0 +1,65 @@ +CONFIG_CROSS_COMPILE="or32-linux-" +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +CONFIG_EXPERT=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_EPOLL is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +CONFIG_MODULES=y +# CONFIG_BLOCK is not set +CONFIG_OPENRISC_BUILTIN_DTB="or1ksim" +CONFIG_NO_HZ=y +CONFIG_HZ_100=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +# CONFIG_TCP_CONG_CUBIC is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +CONFIG_PROC_DEVICETREE=y +CON |