diff options
Diffstat (limited to 'arch/mips/include/asm')
46 files changed, 729 insertions, 290 deletions
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 50b4ef288c5..2e1ad4c652b 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -676,9 +676,8 @@ static inline int ffs(int word) #include <asm/arch_hweight.h> #include <asm-generic/bitops/const_hweight.h> -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #include <asm-generic/bitops/ext2-atomic.h> -#include <asm-generic/bitops/minix.h> #endif /* __KERNEL__ */ diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h index b9c8203688d..c0ead631384 100644 --- a/arch/mips/include/asm/dec/prom.h +++ b/arch/mips/include/asm/dec/prom.h @@ -108,7 +108,7 @@ extern int (*__pmax_close)(int); /* * On MIPS64 we have to call PROM functions via a helper - * dispatcher to accomodate ABI incompatibilities. + * dispatcher to accommodate ABI incompatibilities. */ #define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \ __asm__(#fun " = call_o32") diff --git a/arch/mips/include/asm/errno.h b/arch/mips/include/asm/errno.h index a0efc73819e..6dcd3583ed0 100644 --- a/arch/mips/include/asm/errno.h +++ b/arch/mips/include/asm/errno.h @@ -121,6 +121,8 @@ #define ERFKILL 167 /* Operation not possible due to RF-kill */ +#define EHWPOISON 168 /* Memory page has hardware error */ + #define EDQUOT 1133 /* Quota exceeded */ #ifdef __KERNEL__ diff --git a/arch/mips/include/asm/floppy.h b/arch/mips/include/asm/floppy.h index 992d232adc8..c5c7c0e6064 100644 --- a/arch/mips/include/asm/floppy.h +++ b/arch/mips/include/asm/floppy.h @@ -24,7 +24,7 @@ static inline void fd_cacheflush(char * addr, long size) * And on Mips's the CMOS info fails also ... * * FIXME: This information should come from the ARC configuration tree - * or whereever a particular machine has stored this ... + * or wherever a particular machine has stored this ... */ #define FLOPPY0_TYPE fd_drive_type(0) #define FLOPPY1_TYPE fd_drive_type(1) diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h index b9cce90346c..6ebf1734b41 100644 --- a/arch/mips/include/asm/futex.h +++ b/arch/mips/include/asm/futex.h @@ -75,7 +75,7 @@ } static inline int -futex_atomic_op_inuser(int encoded_op, int __user *uaddr) +futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -85,7 +85,7 @@ futex_atomic_op_inuser(int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int))) + if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); @@ -132,11 +132,13 @@ futex_atomic_op_inuser(int encoded_op, int __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { - int retval; + int ret = 0; + u32 val; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; if (cpu_has_llsc && R10000_LLSC_WAR) { @@ -145,25 +147,25 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) " .set push \n" " .set noat \n" " .set mips3 \n" - "1: ll %0, %2 \n" - " bne %0, %z3, 3f \n" + "1: ll %1, %3 \n" + " bne %1, %z4, 3f \n" " .set mips0 \n" - " move $1, %z4 \n" + " move $1, %z5 \n" " .set mips3 \n" - "2: sc $1, %1 \n" + "2: sc $1, %2 \n" " beqzl $1, 1b \n" __WEAK_LLSC_MB "3: \n" " .set pop \n" " .section .fixup,\"ax\" \n" - "4: li %0, %5 \n" + "4: li %0, %6 \n" " j 3b \n" " .previous \n" " .section __ex_table,\"a\" \n" " "__UA_ADDR "\t1b, 4b \n" " "__UA_ADDR "\t2b, 4b \n" " .previous \n" - : "=&r" (retval), "=R" (*uaddr) + : "+r" (ret), "=&r" (val), "=R" (*uaddr) : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) : "memory"); } else if (cpu_has_llsc) { @@ -172,31 +174,32 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) " .set push \n" " .set noat \n" " .set mips3 \n" - "1: ll %0, %2 \n" - " bne %0, %z3, 3f \n" + "1: ll %1, %3 \n" + " bne %1, %z4, 3f \n" " .set mips0 \n" - " move $1, %z4 \n" + " move $1, %z5 \n" " .set mips3 \n" - "2: sc $1, %1 \n" + "2: sc $1, %2 \n" " beqz $1, 1b \n" __WEAK_LLSC_MB "3: \n" " .set pop \n" " .section .fixup,\"ax\" \n" - "4: li %0, %5 \n" + "4: li %0, %6 \n" " j 3b \n" " .previous \n" " .section __ex_table,\"a\" \n" " "__UA_ADDR "\t1b, 4b \n" " "__UA_ADDR "\t2b, 4b \n" " .previous \n" - : "=&r" (retval), "=R" (*uaddr) + : "+r" (ret), "=&r" (val), "=R" (*uaddr) : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) : "memory"); } else return -ENOSYS; - return retval; + *uval = val; + return ret; } #endif diff --git a/arch/mips/include/asm/hw_irq.h b/arch/mips/include/asm/hw_irq.h index aca05a43a97..77adda297ad 100644 --- a/arch/mips/include/asm/hw_irq.h +++ b/arch/mips/include/asm/hw_irq.h @@ -13,7 +13,7 @@ extern atomic_t irq_err_count; /* - * interrupt-retrigger: NOP for now. This may not be apropriate for all + * interrupt-retrigger: NOP for now. This may not be appropriate for all * machines, we'll see ... */ diff --git a/arch/mips/include/asm/i8253.h b/arch/mips/include/asm/i8253.h index 48bb8237299..9ad011366f7 100644 --- a/arch/mips/include/asm/i8253.h +++ b/arch/mips/include/asm/i8253.h @@ -12,8 +12,13 @@ #define PIT_CH0 0x40 #define PIT_CH2 0x42 +#define PIT_LATCH LATCH + extern raw_spinlock_t i8253_lock; extern void setup_pit_timer(void); +#define inb_pit inb_p +#define outb_pit outb_p + #endif /* __ASM_I8253_H */ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 5b017f23e24..b04e4de5dd2 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -242,7 +242,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, * This version of ioremap ensures that the memory is marked uncachable * on the CPU as well as honouring existing caching rules from things like * the PCI bus. Note that there are other caches and buffers on many - * busses. In paticular driver authors should read up on PCI writes + * busses. In particular driver authors should read up on PCI writes * * It's useful if some control registers are in such an area and * write combining or read caching is not desirable: diff --git a/arch/mips/include/asm/ioctls.h b/arch/mips/include/asm/ioctls.h index d967b899762..92403c3d600 100644 --- a/arch/mips/include/asm/ioctls.h +++ b/arch/mips/include/asm/ioctls.h @@ -85,6 +85,7 @@ #define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ #define TIOCGDEV _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */ #define TIOCSIG _IOW('T', 0x36, int) /* Generate signal on Pty slave */ +#define TIOCVHANGUP 0x5437 /* I hope the range from 0x5480 on is free ... */ #define TIOCSCTTY 0x5480 /* become controlling tty */ diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index b003ed52ed1..0ec01294b06 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -55,9 +55,9 @@ static inline void smtc_im_ack_irq(unsigned int irq) #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF #include <linux/cpumask.h> -extern int plat_set_irq_affinity(unsigned int irq, - const struct cpumask *affinity); -extern void smtc_forward_irq(unsigned int irq); +extern int plat_set_irq_affinity(struct irq_data *d, + const struct cpumask *affinity, bool force); +extern void smtc_forward_irq(struct irq_data *d); /* * IRQ affinity hook invoked at the beginning of interrupt dispatch @@ -70,51 +70,53 @@ extern void smtc_forward_irq(unsigned int irq); * cpumask implementations, this version is optimistically assuming * that cpumask.h macro overhead is reasonable during interrupt dispatch. */ -#define IRQ_AFFINITY_HOOK(irq) \ -do { \ - if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) {\ - smtc_forward_irq(irq); \ - irq_exit(); \ - return; \ - } \ -} while (0) +static inline int handle_on_other_cpu(unsigned int irq) +{ + struct irq_data *d = irq_get_irq_data(irq); + + if (cpumask_test_cpu(smp_processor_id(), d->affinity)) + return 0; + smtc_forward_irq(d); + return 1; +} #else /* Not doing SMTC affinity */ -#define IRQ_AFFINITY_HOOK(irq) do { } while (0) +static inline int handle_on_other_cpu(unsigned int irq) { return 0; } #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP +static inline void smtc_im_backstop(unsigned int irq) +{ + if (irq_hwmask[irq] & 0x0000ff00) + write_c0_tccontext(read_c0_tccontext() & + ~(irq_hwmask[irq] & 0x0000ff00)); +} + /* * Clear interrupt mask handling "backstop" if irq_hwmask * entry so indicates. This implies that the ack() or end() * functions will take over re-enabling the low-level mask. * Otherwise it will be done on return from exception. */ -#define __DO_IRQ_SMTC_HOOK(irq) \ -do { \ - IRQ_AFFINITY_HOOK(irq); \ - if (irq_hwmask[irq] & 0x0000ff00) \ - write_c0_tccontext(read_c0_tccontext() & \ - ~(irq_hwmask[irq] & 0x0000ff00)); \ -} while (0) - -#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \ -do { \ - if (irq_hwmask[irq] & 0x0000ff00) \ - write_c0_tccontext(read_c0_tccontext() & \ - ~(irq_hwmask[irq] & 0x0000ff00)); \ -} while (0) +static inline int smtc_handle_on_other_cpu(unsigned int irq) +{ + int ret = handle_on_other_cpu(irq); + + if (!ret) + smtc_im_backstop(irq); + return ret; +} #else -#define __DO_IRQ_SMTC_HOOK(irq) \ -do { \ - IRQ_AFFINITY_HOOK(irq); \ -} while (0) -#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0) +static inline void smtc_im_backstop(unsigned int irq) { } +static inline int smtc_handle_on_other_cpu(unsigned int irq) +{ + return handle_on_other_cpu(irq); +} #endif diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h index 9ef3b0d1789..309cbcd6909 100644 --- a/arch/mips/include/asm/irqflags.h +++ b/arch/mips/include/asm/irqflags.h @@ -174,7 +174,7 @@ __asm__( "mtc0 \\flags, $2, 1 \n" #elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) /* - * Slow, but doesn't suffer from a relativly unlikely race + * Slow, but doesn't suffer from a relatively unlikely race * condition we're having since days 1. */ " beqz \\flags, 1f \n" diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h index 5325084d5c4..32978d32561 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h @@ -4,7 +4,7 @@ #define TAGVER_LEN 4 /* Length of Tag Version */ #define TAGLAYOUT_LEN 4 /* Length of FlashLayoutVer */ #define SIG1_LEN 20 /* Company Signature 1 Length */ -#define SIG2_LEN 14 /* Company Signature 2 Lenght */ +#define SIG2_LEN 14 /* Company Signature 2 Length */ #define BOARDID_LEN 16 /* Length of BoardId */ #define ENDIANFLAG_LEN 2 /* Endian Flag Length */ #define CHIPID_LEN 6 /* Chip Id Length */ diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index 6ddab8aef64..5b05f186e39 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -11,172 +11,91 @@ #define NR_IRQS OCTEON_IRQ_LAST #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 -/* 0 - 7 represent the i8259 master */ -#define OCTEON_IRQ_I8259M0 0 -#define OCTEON_IRQ_I8259M1 1 -#define OCTEON_IRQ_I8259M2 2 -#define OCTEON_IRQ_I8259M3 3 -#define OCTEON_IRQ_I8259M4 4 -#define OCTEON_IRQ_I8259M5 5 -#define OCTEON_IRQ_I8259M6 6 -#define OCTEON_IRQ_I8259M7 7 -/* 8 - 15 represent the i8259 slave */ -#define OCTEON_IRQ_I8259S0 8 -#define OCTEON_IRQ_I8259S1 9 -#define OCTEON_IRQ_I8259S2 10 -#define OCTEON_IRQ_I8259S3 11 -#define OCTEON_IRQ_I8259S4 12 -#define OCTEON_IRQ_I8259S5 13 -#define OCTEON_IRQ_I8259S6 14 -#define OCTEON_IRQ_I8259S7 15 -/* 16 - 23 represent the 8 MIPS standard interrupt sources */ -#define OCTEON_IRQ_SW0 16 -#define OCTEON_IRQ_SW1 17 -#define OCTEON_IRQ_CIU0 18 -#define OCTEON_IRQ_CIU1 19 -#define OCTEON_IRQ_CIU4 20 -#define OCTEON_IRQ_5 21 -#define OCTEON_IRQ_PERF 22 -#define OCTEON_IRQ_TIMER 23 -/* 24 - 87 represent the sources in CIU_INTX_EN0 */ -#define OCTEON_IRQ_WORKQ0 24 -#define OCTEON_IRQ_WORKQ1 25 -#define OCTEON_IRQ_WORKQ2 26 -#define OCTEON_IRQ_WORKQ3 27 -#define OCTEON_IRQ_WORKQ4 28 -#define OCTEON_IRQ_WORKQ5 29 -#define OCTEON_IRQ_WORKQ6 30 -#define OCTEON_IRQ_WORKQ7 31 -#define OCTEON_IRQ_WORKQ8 32 -#define OCTEON_IRQ_WORKQ9 33 -#define OCTEON_IRQ_WORKQ10 34 -#define OCTEON_IRQ_WORKQ11 35 -#define OCTEON_IRQ_WORKQ12 36 -#define OCTEON_IRQ_WORKQ13 37 -#define OCTEON_IRQ_WORKQ14 38 -#define OCTEON_IRQ_WORKQ15 39 -#define OCTEON_IRQ_GPIO0 40 -#define OCTEON_IRQ_GPIO1 41 -#define OCTEON_IRQ_GPIO2 42 -#define OCTEON_IRQ_GPIO3 43 -#define OCTEON_IRQ_GPIO4 44 -#define OCTEON_IRQ_GPIO5 45 -#define OCTEON_IRQ_GPIO6 46 -#define OCTEON_IRQ_GPIO7 47 -#define OCTEON_IRQ_GPIO8 48 -#define OCTEON_IRQ_GPIO9 49 -#define OCTEON_IRQ_GPIO10 50 -#define OCTEON_IRQ_GPIO11 51 -#define OCTEON_IRQ_GPIO12 52 -#define OCTEON_IRQ_GPIO13 53 -#define OCTEON_IRQ_GPIO14 54 -#define OCTEON_IRQ_GPIO15 55 -#define OCTEON_IRQ_MBOX0 56 -#define OCTEON_IRQ_MBOX1 57 -#define OCTEON_IRQ_UART0 58 -#define OCTEON_IRQ_UART1 59 -#define OCTEON_IRQ_PCI_INT0 60 -#define OCTEON_IRQ_PCI_INT1 61 -#define OCTEON_IRQ_PCI_INT2 62 -#define OCTEON_IRQ_PCI_INT3 63 -#define OCTEON_IRQ_PCI_MSI0 64 -#define OCTEON_IRQ_PCI_MSI1 65 -#define OCTEON_IRQ_PCI_MSI2 66 -#define OCTEON_IRQ_PCI_MSI3 67 -#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */ -#define OCTEON_IRQ_TWSI 69 -#define OCTEON_IRQ_RML 70 -#define OCTEON_IRQ_TRACE 71 -#define OCTEON_IRQ_GMX_DRP0 72 -#define OCTEON_IRQ_GMX_DRP1 73 -#define OCTEON_IRQ_IPD_DRP 74 -#define OCTEON_IRQ_KEY_ZERO 75 -#define OCTEON_IRQ_TIMER0 76 -#define OCTEON_IRQ_TIMER1 77 -#define OCTEON_IRQ_TIMER2 78 -#define OCTEON_IRQ_TIMER3 79 -#define OCTEON_IRQ_USB0 80 -#define OCTEON_IRQ_PCM 81 -#define OCTEON_IRQ_MPI 82 -#define OCTEON_IRQ_TWSI2 83 -#define OCTEON_IRQ_POWIQ 84 -#define OCTEON_IRQ_IPDPPTHR 85 -#define OCTEON_IRQ_MII0 86 -#define OCTEON_IRQ_BOOTDMA 87 -/* 88 - 151 represent the sources in CIU_INTX_EN1 */ -#define OCTEON_IRQ_WDOG0 88 -#define OCTEON_IRQ_WDOG1 89 -#define OCTEON_IRQ_WDOG2 90 -#define OCTEON_IRQ_WDOG3 91 -#define OCTEON_IRQ_WDOG4 92 -#define OCTEON_IRQ_WDOG5 93 -#define OCTEON_IRQ_WDOG6 94 -#define OCTEON_IRQ_WDOG7 95 -#define OCTEON_IRQ_WDOG8 96 -#define OCTEON_IRQ_WDOG9 97 -#define OCTEON_IRQ_WDOG10 98 -#define OCTEON_IRQ_WDOG11 99 -#define OCTEON_IRQ_WDOG12 100 -#define OCTEON_IRQ_WDOG13 101 -#define OCTEON_IRQ_WDOG14 102 -#define OCTEON_IRQ_WDOG15 103 -#define OCTEON_IRQ_UART2 104 -#define OCTEON_IRQ_USB1 105 -#define OCTEON_IRQ_MII1 106 -#define OCTEON_IRQ_RESERVED107 107 -#define OCTEON_IRQ_RESERVED108 108 -#define OCTEON_IRQ_RESERVED109 109 -#define OCTEON_IRQ_RESERVED110 110 -#define OCTEON_IRQ_RESERVED111 111 -#define OCTEON_IRQ_RESERVED112 112 -#define OCTEON_IRQ_RESERVED113 113 -#define OCTEON_IRQ_RESERVED114 114 -#define OCTEON_IRQ_RESERVED115 115 -#define OCTEON_IRQ_RESERVED116 116 -#define OCTEON_IRQ_RESERVED117 117 -#define OCTEON_IRQ_RESERVED118 118 -#define OCTEON_IRQ_RESERVED119 119 -#define OCTEON_IRQ_RESERVED120 120 -#define OCTEON_IRQ_RESERVED121 121 -#define OCTEON_IRQ_RESERVED122 122 -#define OCTEON_IRQ_RESERVED123 123 -#define OCTEON_IRQ_RESERVED124 124 -#define OCTEON_IRQ_RESERVED125 125 -#define OCTEON_IRQ_RESERVED126 126 -#define OCTEON_IRQ_RESERVED127 127 -#define OCTEON_IRQ_RESERVED128 128 -#define OCTEON_IRQ_RESERVED129 129 -#define OCTEON_IRQ_RESERVED130 130 -#define OCTEON_IRQ_RESERVED131 131 -#define OCTEON_IRQ_RESERVED132 132 -#define OCTEON_IRQ_RESERVED133 133 -#define OCTEON_IRQ_RESERVED134 134 -#define OCTEON_IRQ_RESERVED135 135 -#define OCTEON_IRQ_RESERVED136 136 -#define OCTEON_IRQ_RESERVED137 137 -#define OCTEON_IRQ_RESERVED138 138 -#define OCTEON_IRQ_RESERVED139 139 -#define OCTEON_IRQ_RESERVED140 140 -#define OCTEON_IRQ_RESERVED141 141 -#define OCTEON_IRQ_RESERVED142 142 -#define OCTEON_IRQ_RESERVED143 143 -#define OCTEON_IRQ_RESERVED144 144 -#define OCTEON_IRQ_RESERVED145 145 -#define OCTEON_IRQ_RESERVED146 146 -#define OCTEON_IRQ_RESERVED147 147 -#define OCTEON_IRQ_RESERVED148 148 -#define OCTEON_IRQ_RESERVED149 149 -#define OCTEON_IRQ_RESERVED150 150 -#define OCTEON_IRQ_RESERVED151 151 +enum octeon_irq { +/* 1 - 8 represent the 8 MIPS standard interrupt sources */ + OCTEON_IRQ_SW0 = 1, + OCTEON_IRQ_SW1, +/* CIU0, CUI2, CIU4 are 3, 4, 5 */ + OCTEON_IRQ_5 = 6, + OCTEON_IRQ_PERF, + OCTEON_IRQ_TIMER, +/* sources in CIU_INTX_EN0 */ + OCTEON_IRQ_WORKQ0, + OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16, + OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16, + OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15, + OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16, + OCTEON_IRQ_MBOX1, + OCTEON_IRQ_UART0, + OCTEON_IRQ_UART1, + OCTEON_IRQ_UART2, + OCTEON_IRQ_PCI_INT0, + OCTEON_IRQ_PCI_INT1, + OCTEON_IRQ_PCI_INT2, + OCTEON_IRQ_PCI_INT3, + OCTEON_IRQ_PCI_MSI0, + OCTEON_IRQ_PCI_MSI1, + OCTEON_IRQ_PCI_MSI2, + OCTEON_IRQ_PCI_MSI3, + + OCTEON_IRQ_TWSI, + OCTEON_IRQ_TWSI2, + OCTEON_IRQ_RML, + OCTEON_IRQ_TRACE0, + OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4, + OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5, + OCTEON_IRQ_KEY_ZERO, + OCTEON_IRQ_TIMER0, + OCTEON_IRQ_TIMER1, + OCTEON_IRQ_TIMER2, + OCTEON_IRQ_TIMER3, + OCTEON_IRQ_USB0, + OCTEON_IRQ_USB1, + OCTEON_IRQ_PCM, + OCTEON_IRQ_MPI, + OCTEON_IRQ_POWIQ, + OCTEON_IRQ_IPDPPTHR, + OCTEON_IRQ_MII0, + OCTEON_IRQ_MII1, + OCTEON_IRQ_BOOTDMA, + + OCTEON_IRQ_NAND, + OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */ + OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */ + OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */ + OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */ + OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */ + OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */ + OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */ + OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */ + OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */ + OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */ + OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */ + OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */ + OCTEON_IRQ_DFA, /* Summary of DFA */ + OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */ + OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */ + OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */ + OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */ + OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5, + OCTEON_IRQ_PTP, + OCTEON_IRQ_PEM0, + OCTEON_IRQ_PEM1, + OCTEON_IRQ_SRIO0, + OCTEON_IRQ_SRIO1, + OCTEON_IRQ_LMC0, + OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */ + OCTEON_IRQ_RST, +}; #ifdef CONFIG_PCI_MSI -/* 152 - 215 represent the MSI interrupts 0-63 */ -#define OCTEON_IRQ_MSI_BIT0 152 -#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) +/* 152 - 407 represent the MSI interrupts 0-255 */ +#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1) -#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) +#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) +#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) #else -#define OCTEON_IRQ_LAST 152 +#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1) #endif #endif diff --git a/arch/mips/include/asm/mach-ip32/mc146818rtc.h b/arch/mips/include/asm/mach-ip32/mc146818rtc.h index c28ba8d8407..6b6bab43d5c 100644 --- a/arch/mips/include/asm/mach-ip32/mc146818rtc.h +++ b/arch/mips/include/asm/mach-ip32/mc146818rtc.h @@ -26,7 +26,7 @@ static inline void CMOS_WRITE(unsigned char data, unsigned long addr) } /* - * FIXME: Do it right. For now just assume that noone lives in 20th century + * FIXME: Do it right. For now just assume that no one lives in 20th century * and no O2 user in 22th century ;-) */ #define mc146818_decode_year(year) ((year) + 2000) diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h index 8987a76e967..564ab81d6cd 100644 --- a/arch/mips/include/asm/mach-jz4740/platform.h +++ b/arch/mips/include/asm/mach-jz4740/platform.h @@ -30,6 +30,7 @@ extern struct platform_device jz4740_i2s_device; extern struct platform_device jz4740_pcm_device; extern struct platform_device jz4740_codec_device; extern struct platform_device jz4740_adc_device; +extern struct platform_device jz4740_wdt_device; void jz4740_serial_device_register(void); diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h index 021f77ca59e..2a8e2bb5d53 100644 --- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h @@ -1,5 +1,5 @@ /* - * The header file of cs5536 sourth bridge. + * The header file of cs5536 south bridge. * * Copyright (C) 2007 Lemote, Inc. * Author : jlliu <liujl@lemote.com> diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h index 6d1ff9060e4..65059255dc1 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1000.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1000.h @@ -1,5 +1,5 @@ /* - * Alchemy Semi Pb1000 Referrence Board + * Alchemy Semi Pb1000 Reference Board * * Copyright 2001, 2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. <source@mvista.com> diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index 962eb55dc88..fce4332ebb7 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/< |