diff options
Diffstat (limited to 'arch/mips/alchemy/common')
-rw-r--r-- | arch/mips/alchemy/common/Makefile | 4 | ||||
-rw-r--r-- | arch/mips/alchemy/common/au1xxx_irqmap.c | 205 | ||||
-rw-r--r-- | arch/mips/alchemy/common/clocks.c | 65 | ||||
-rw-r--r-- | arch/mips/alchemy/common/cputable.c | 52 | ||||
-rw-r--r-- | arch/mips/alchemy/common/dbdma.c | 65 | ||||
-rw-r--r-- | arch/mips/alchemy/common/irq.c | 745 | ||||
-rw-r--r-- | arch/mips/alchemy/common/power.c | 406 | ||||
-rw-r--r-- | arch/mips/alchemy/common/reset.c | 2 | ||||
-rw-r--r-- | arch/mips/alchemy/common/setup.c | 71 | ||||
-rw-r--r-- | arch/mips/alchemy/common/sleeper.S | 118 | ||||
-rw-r--r-- | arch/mips/alchemy/common/time.c | 311 |
11 files changed, 755 insertions, 1289 deletions
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index df48fd65bbf..d50d4764eaf 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -6,8 +6,8 @@ # obj-y += prom.o irq.o puts.o time.o reset.o \ - au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ - sleeper.o cputable.o dma.o dbdma.o gpio.o + clocks.o platform.o power.o setup.o \ + sleeper.o dma.o dbdma.o gpio.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/alchemy/common/au1xxx_irqmap.c b/arch/mips/alchemy/common/au1xxx_irqmap.c deleted file mode 100644 index c7ca1596394..00000000000 --- a/arch/mips/alchemy/common/au1xxx_irqmap.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Au1xxx processor specific IRQ tables - * - * Copyright 2004 Embedded Edge, LLC - * dan@embeddededge.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include <linux/init.h> -#include <linux/kernel.h> - -#include <au1000.h> - -/* The IC0 interrupt table. This is processor, rather than - * board dependent, so no reason to keep this info in the board - * dependent files. - * - * Careful if you change match 2 request! - * The interrupt handler is called directly from the low level dispatch code. - */ -struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = { - -#if defined(CONFIG_SOC_AU1000) - { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, - { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, - { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, - -#elif defined(CONFIG_SOC_AU1500) - - { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, - { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, - { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, - { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, - { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, - { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, - { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, - -#elif defined(CONFIG_SOC_AU1100) - - { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, - { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, - { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, - /* { AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0 }, */ - { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, - -#elif defined(CONFIG_SOC_AU1550) - - { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, - { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, - { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, - { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, - { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 }, - { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, - { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, - { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, - -#elif defined(CONFIG_SOC_AU1200) - - { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, - { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0 }, - { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0 }, - -#else -#error "Error: Unknown Alchemy SOC" -#endif - -}; - -int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map); diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c index 043429d17c5..d8991854530 100644 --- a/arch/mips/alchemy/common/clocks.c +++ b/arch/mips/alchemy/common/clocks.c @@ -27,12 +27,21 @@ */ #include <linux/module.h> +#include <linux/spinlock.h> +#include <asm/time.h> #include <asm/mach-au1x00/au1000.h> +/* + * I haven't found anyone that doesn't use a 12 MHz source clock, + * but just in case..... + */ +#define AU1000_SRC_CLK 12000000 + static unsigned int au1x00_clock; /* Hz */ -static unsigned int lcd_clock; /* KHz */ static unsigned long uart_baud_base; +static DEFINE_SPINLOCK(time_lock); + /* * Set the au1000_clock */ @@ -63,31 +72,45 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base) } /* - * Calculate the Au1x00's LCD clock based on the current - * cpu clock and the system bus clock, and try to keep it - * below 40 MHz (the Pb1000 board can lock-up if the LCD - * clock is over 40 MHz). + * We read the real processor speed from the PLL. This is important + * because it is more accurate than computing it from the 32 KHz + * counter, if it exists. If we don't have an accurate processor + * speed, all of the peripherals that derive their clocks based on + * this advertised speed will introduce error and sometimes not work + * properly. This function is futher convoluted to still allow configurations + * to do that in case they have really, really old silicon with a + * write-only PLL register. -- Dan */ -void set_au1x00_lcd_clock(void) +unsigned long au1xxx_calc_clock(void) { - unsigned int static_cfg0; - unsigned int sys_busclk = (get_au1x00_speed() / 1000) / - ((int)(au_readl(SYS_POWERCTRL) & 0x03) + 2); + unsigned long cpu_speed; + unsigned long flags; - static_cfg0 = au_readl(MEM_STCFG0); + spin_lock_irqsave(&time_lock, flags); - if (static_cfg0 & (1 << 11)) - lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */ + /* + * On early Au1000, sys_cpupll was write-only. Since these + * silicon versions of Au1000 are not sold by AMD, we don't bend + * over backwards trying to determine the frequency. + */ + if (au1xxx_cpu_has_pll_wo()) +#ifdef CONFIG_SOC_AU1000_FREQUENCY + cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; +#else + cpu_speed = 396000000; +#endif else - lcd_clock = sys_busclk / 4; + cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; - if (lcd_clock > 50000) /* Epson MAX */ - printk(KERN_WARNING "warning: LCD clock too high (%u KHz)\n", - lcd_clock); -} + /* On Alchemy CPU:counter ratio is 1:1 */ + mips_hpt_frequency = cpu_speed; + /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */ + set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL) + & 0x03) + 2) * 16)); -unsigned int get_au1x00_lcd_clock(void) -{ - return lcd_clock; + spin_unlock_irqrestore(&time_lock, flags); + + set_au1x00_speed(cpu_speed); + + return cpu_speed; } -EXPORT_SYMBOL(get_au1x00_lcd_clock); diff --git a/arch/mips/alchemy/common/cputable.c b/arch/mips/alchemy/common/cputable.c deleted file mode 100644 index ba6430bc2d0..00000000000 --- a/arch/mips/alchemy/common/cputable.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * arch/mips/au1000/common/cputable.c - * - * Copyright (C) 2004 Dan Malek (dan@embeddededge.com) - * Copied from PowerPC and updated for Alchemy Au1xxx processors. - * - * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include <asm/mach-au1x00/au1000.h> - -struct cpu_spec *cur_cpu_spec[NR_CPUS]; - -/* With some thought, we can probably use the mask to reduce the - * size of the table. - */ -struct cpu_spec cpu_specs[] = { - { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 }, - { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 }, - { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 }, - { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 }, - { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 }, - { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 }, - { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 }, - { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 }, - { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 }, - { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 }, - { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 }, - { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 }, - { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 }, - { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 }, - { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 }, - { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 }, - { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 } -}; - -void set_cpuspec(void) -{ - struct cpu_spec *sp; - u32 prid; - - prid = read_c0_prid(); - sp = cpu_specs; - while ((prid & sp->prid_mask) != sp->prid_value) - sp++; - cur_cpu_spec[0] = sp; -} diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 601ee9180ee..3ab6d80d150 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -174,6 +174,11 @@ static dbdev_tab_t dbdev_tab[] = { #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) +#ifdef CONFIG_PM +static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][8]; +#endif + + static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; static dbdev_tab_t *find_dbdev_id(u32 id) @@ -975,4 +980,64 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) return nbytes; } +#ifdef CONFIG_PM +void au1xxx_dbdma_suspend(void) +{ + int i; + u32 addr; + + addr = DDMA_GLOBAL_BASE; + au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00); + au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04); + au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08); + au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c); + + /* save channel configurations */ + for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) { + au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00); + au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04); + au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08); + au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c); + au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10); + au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14); + au1xxx_dbdma_pm_regs[i][6] = au_readl(addr + 0x18); + + /* halt channel */ + au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00); + au_sync(); + while (!(au_readl(addr + 0x14) & 1)) + au_sync(); + + addr += 0x100; /* next channel base */ + } + /* disable channel interrupts */ + au_writel(0, DDMA_GLOBAL_BASE + 0x0c); + au_sync(); +} + +void au1xxx_dbdma_resume(void) +{ + int i; + u32 addr; + + addr = DDMA_GLOBAL_BASE; + au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00); + au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04); + au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08); + au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c); + + /* restore channel configurations */ + for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) { + au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00); + au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04); + au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08); + au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c); + au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10); + au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14); + au_writel(au1xxx_dbdma_pm_regs[i][6], addr + 0x18); + au_sync(); + addr += 0x100; /* next channel base */ + } +} +#endif /* CONFIG_PM */ #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 40c6ceceb5f..c88c821b4c3 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -24,6 +24,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ + #include <linux/bitops.h> #include <linux/init.h> #include <linux/interrupt.h> @@ -36,15 +37,172 @@ #include <asm/mach-pb1x00/pb1000.h> #endif -#define EXT_INTC0_REQ0 2 /* IP 2 */ -#define EXT_INTC0_REQ1 3 /* IP 3 */ -#define EXT_INTC1_REQ0 4 /* IP 4 */ -#define EXT_INTC1_REQ1 5 /* IP 5 */ -#define MIPS_TIMER_IP 7 /* IP 7 */ - -void (*board_init_irq)(void) __initdata = NULL; +static int au1x_ic_settype(unsigned int irq, unsigned int flow_type); + +/* per-processor fixed function irqs */ +struct au1xxx_irqmap au1xxx_ic0_map[] __initdata = { + +#if defined(CONFIG_SOC_AU1000) + { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, + +#elif defined(CONFIG_SOC_AU1500) + + { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, + +#elif defined(CONFIG_SOC_AU1100) + + { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, + +#elif defined(CONFIG_SOC_AU1550) + + { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, + { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + +#elif defined(CONFIG_SOC_AU1200) + + { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + +#else +#error "Error: Unknown Alchemy SOC" +#endif +}; -static DEFINE_SPINLOCK(irq_lock); #ifdef CONFIG_PM @@ -130,67 +288,47 @@ void restore_au1xxx_intctl(void) #endif /* CONFIG_PM */ -inline void local_enable_irq(unsigned int irq_nr) +static void au1x_ic0_unmask(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; - - if (bit >= 32) { - au_writel(1 << (bit - 32), IC1_MASKSET); - au_writel(1 << (bit - 32), IC1_WAKESET); - } else { - au_writel(1 << bit, IC0_MASKSET); - au_writel(1 << bit, IC0_WAKESET); - } + au_writel(1 << bit, IC0_MASKSET); + au_writel(1 << bit, IC0_WAKESET); au_sync(); } - -inline void local_disable_irq(unsigned int irq_nr) +static void au1x_ic1_unmask(unsigned int irq_nr) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + au_writel(1 << bit, IC1_MASKSET); + au_writel(1 << bit, IC1_WAKESET); - if (bit >= 32) { - au_writel(1 << (bit - 32), IC1_MASKCLR); - au_writel(1 << (bit - 32), IC1_WAKECLR); - } else { - au_writel(1 << bit, IC0_MASKCLR); - au_writel(1 << bit, IC0_WAKECLR); - } +/* very hacky. does the pb1000 cpld auto-disable this int? + * nowhere in the current kernel sources is it disabled. --mlau + */ +#if defined(CONFIG_MIPS_PB1000) + if (irq_nr == AU1000_GPIO_15) + au_writel(0x4000, PB1000_MDR); /* enable int */ +#endif au_sync(); } - -static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) +static void au1x_ic0_mask(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; - - if (bit >= 32) { - au_writel(1 << (bit - 32), IC1_RISINGCLR); - au_writel(1 << (bit - 32), IC1_MASKCLR); - } else { - au_writel(1 << bit, IC0_RISINGCLR); - au_writel(1 << bit, IC0_MASKCLR); - } + au_writel(1 << bit, IC0_MASKCLR); + au_writel(1 << bit, IC0_WAKECLR); au_sync(); } - -static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) +static void au1x_ic1_mask(unsigned int irq_nr) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; - - if (bit >= 32) { - au_writel(1 << (bit - 32), IC1_FALLINGCLR); - au_writel(1 << (bit - 32), IC1_MASKCLR); - } else { - au_writel(1 << bit, IC0_FALLINGCLR); - au_writel(1 << bit, IC0_MASKCLR); - } + unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + au_writel(1 << bit, IC1_MASKCLR); + au_writel(1 << bit, IC1_WAKECLR); au_sync(); } - -static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) +static void au1x_ic0_ack(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -198,349 +336,229 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) * This may assume that we don't get interrupts from * both edges at once, or if we do, that we don't care. */ - if (bit >= 32) { - au_writel(1 << (bit - 32), IC1_FALLINGCLR); - au_writel(1 << (bit - 32), IC1_RISINGCLR); - au_writel(1 << (bit - 32), IC1_MASKCLR); - } else { - au_writel(1 << bit, IC0_FALLINGCLR); - au_writel(1 << bit, IC0_RISINGCLR); - au_writel(1 << bit, IC0_MASKCLR); - } + au_writel(1 << bit, IC0_FALLINGCLR); + au_writel(1 << bit, IC0_RISINGCLR); au_sync(); } -static inline void mask_and_ack_level_irq(unsigned int irq_nr) +static void au1x_ic1_ack(unsigned int irq_nr) { - local_disable_irq(irq_nr); - au_sync(); -#if defined(CONFIG_MIPS_PB1000) - if (irq_nr == AU1000_GPIO_15) { - au_writel(0x8000, PB1000_MDR); /* ack int */ - au_sync(); - } -#endif -} - -static void end_irq(unsigned int irq_nr) -{ - if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - local_enable_irq(irq_nr); + unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; -#if defined(CONFIG_MIPS_PB1000) - if (irq_nr == AU1000_GPIO_15) { - au_writel(0x4000, PB1000_MDR); /* enable int */ - au_sync(); - } -#endif + /* + * This may assume that we don't get interrupts from + * both edges at once, or if we do, that we don't care. + */ + au_writel(1 << bit, IC1_FALLINGCLR); + au_writel(1 << bit, IC1_RISINGCLR); + au_sync(); } -unsigned long save_local_and_disable(int controller) +static int au1x_ic1_setwake(unsigned int irq, unsigned int on) { - int i; - unsigned long flags, mask; - - spin_lock_irqsave(&irq_lock, flags); - if (controller) { - mask = au_readl(IC1_MASKSET); - for (i = 32; i < 64; i++) - local_disable_irq(i); - } else { - mask = au_readl(IC0_MASKSET); - for (i = 0; i < 32; i++) - local_disable_irq(i); - } - spin_unlock_irqrestore(&irq_lock, flags); - - return mask; -} + unsigned int bit = irq - AU1000_INTC1_INT_BASE; + unsigned long wakemsk, flags; -void restore_local_and_enable(int controller, unsigned long mask) -{ - int i; - unsigned long flags, new_mask; - - spin_lock_irqsave(&irq_lock, flags); - for (i = 0; i < 32; i++) - if (mask & (1 << i)) { - if (controller) - local_enable_irq(i + 32); - else - local_enable_irq(i); - } + /* only GPIO 0-7 can act as wakeup source: */ + if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7)) + return -EINVAL; - if (controller) - new_mask = au_readl(IC1_MASKSET); + local_irq_save(flags); + wakemsk = au_readl(SYS_WAKEMSK); + if (on) + wakemsk |= 1 << bit; else - new_mask = au_readl(IC0_MASKSET); + wakemsk &= ~(1 << bit); + au_writel(wakemsk, SYS_WAKEMSK); + au_sync(); + local_irq_restore(flags); - spin_unlock_irqrestore(&irq_lock, flags); + return 0; } - -static struct irq_chip rise_edge_irq_type = { - .name = "Au1000 Rise Edge", - .ack = mask_and_ack_rise_edge_irq, - .mask = local_disable_irq, - .mask_ack = mask_and_ack_rise_edge_irq, - .unmask = local_enable_irq, - .end = end_irq, -}; - -static struct irq_chip fall_edge_irq_type = { - .name = "Au1000 Fall Edge", - .ack = mask_and_ack_fall_edge_irq, - .mask = local_disable_irq, - .mask_ack = mask_and_ack_fall_edge_irq, - .unmask = local_enable_irq, - .end = end_irq, -}; - -static struct irq_chip either_edge_irq_type = { - .name = "Au1000 Rise or Fall Edge", - .ack = mask_and_ack_either_edge_irq, - .mask = local_disable_irq, - .mask_ack = mask_and_ack_either_edge_irq, - .unmask = local_enable_irq, - .end = end_irq, +/* + * irq_chips for both ICs; this way the mask handlers can be + * as short as possible. + * + * NOTE: the ->ack() callback is used by the handle_edge_irq + * flowhandler only, the ->mask_ack() one by handle_level_irq, + * so no need for an irq_chip for each type of irq (level/edge). + */ +static struct irq_chip au1x_ic0_chip = { + .name = "Alchemy-IC0", + .ack = au1x_ic0_ack, /* edge */ + .mask = au1x_ic0_mask, + .mask_ack = au1x_ic0_mask, /* level */ + .unmask = au1x_ic0_unmask, + .set_type = au1x_ic_settype, }; -static struct irq_chip level_irq_type = { - .name = "Au1000 Level", - .ack = mask_and_ack_level_irq, - .mask = local_disable_irq, - .mask_ack = mask_and_ack_level_irq, - .unmask = local_enable_irq, - .end = end_irq, +static struct irq_chip au1x_ic1_chip = { + .name = "Alchemy-IC1", + .ack = au1x_ic1_ack, /* edge */ + .mask = au1x_ic1_mask, + .mask_ack = au1x_ic1_mask, /* level */ + .unmask = au1x_ic1_unmask, + .set_type = au1x_ic_settype, + .set_wake = au1x_ic1_setwake, }; -static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req) +static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; - - if (irq_nr > AU1000_MAX_INTR) - return; - - /* Config2[n], Config1[n], Config0[n] */ - if (bit >= 32) { - switch (type) { - case INTC_INT_RISE_EDGE: /* 0:0:1 */ - au_writel(1 << (bit - 32), IC1_CFG2CLR); - au_writel(1 << (bit - 32), IC1_CFG1CLR); - au_writel(1 << (bit - 32), IC1_CFG0SET); - set_irq_chip(irq_nr, &rise_edge_irq_type); - break; - case INTC_INT_FALL_EDGE: /* 0:1:0 */ - au_writel(1 << (bit - 32), IC1_CFG2CLR); - au_writel(1 << (bit - 32), IC1_CFG1SET); - au_writel(1 << (bit - 32), IC1_CFG0CLR); - set_irq_chip(irq_nr, &fall_edge_irq_type); - break; - case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ - au_writel(1 << (bit - 32), IC1_CFG2CLR); |