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-rw-r--r--arch/m68k/include/asm/atariints.h2
-rw-r--r--arch/m68k/include/asm/bootstd.h2
-rw-r--r--arch/m68k/include/asm/commproc.h4
-rw-r--r--arch/m68k/include/asm/delay_no.h2
-rw-r--r--arch/m68k/include/asm/gpio.h2
-rw-r--r--arch/m68k/include/asm/m520xsim.h2
-rw-r--r--arch/m68k/include/asm/m523xsim.h2
-rw-r--r--arch/m68k/include/asm/m527xsim.h2
-rw-r--r--arch/m68k/include/asm/m5307sim.h2
-rw-r--r--arch/m68k/include/asm/m5407sim.h2
-rw-r--r--arch/m68k/include/asm/m68360_quicc.h2
-rw-r--r--arch/m68k/include/asm/mac_oss.h2
-rw-r--r--arch/m68k/include/asm/mac_via.h2
-rw-r--r--arch/m68k/include/asm/macintosh.h2
-rw-r--r--arch/m68k/include/asm/mcftimer.h2
15 files changed, 16 insertions, 16 deletions
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h
index f597892e43a..656bbbf5a6f 100644
--- a/arch/m68k/include/asm/atariints.h
+++ b/arch/m68k/include/asm/atariints.h
@@ -146,7 +146,7 @@ static inline void clear_mfp_bit( unsigned irq, int type )
/*
* {en,dis}able_irq have the usual semantics of temporary blocking the
- * interrupt, but not loosing requests that happen between disabling and
+ * interrupt, but not losing requests that happen between disabling and
* enabling. This is done with the MFP mask registers.
*/
diff --git a/arch/m68k/include/asm/bootstd.h b/arch/m68k/include/asm/bootstd.h
index bdc1a4ac4fe..e518f5a575b 100644
--- a/arch/m68k/include/asm/bootstd.h
+++ b/arch/m68k/include/asm/bootstd.h
@@ -31,7 +31,7 @@
#define __BN_flash_write_range 20
/* Calling conventions compatible to (uC)linux/68k
- * We use simmilar macros to call into the bootloader as for uClinux
+ * We use similar macros to call into the bootloader as for uClinux
*/
#define __bsc_return(type, res) \
diff --git a/arch/m68k/include/asm/commproc.h b/arch/m68k/include/asm/commproc.h
index edf5eb6c08d..a73998528d2 100644
--- a/arch/m68k/include/asm/commproc.h
+++ b/arch/m68k/include/asm/commproc.h
@@ -88,7 +88,7 @@ typedef struct cpm_buf_desc {
/* rx bd status/control bits */
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
@@ -96,7 +96,7 @@ typedef struct cpm_buf_desc {
#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
-#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
+#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
diff --git a/arch/m68k/include/asm/delay_no.h b/arch/m68k/include/asm/delay_no.h
index 55cbd6294ab..c3a0edc90f2 100644
--- a/arch/m68k/include/asm/delay_no.h
+++ b/arch/m68k/include/asm/delay_no.h
@@ -16,7 +16,7 @@ static inline void __delay(unsigned long loops)
* long word alignment which is the faster version.
* The 0x4a8e is of course a 'tstl %fp' instruction. This is better
* than using a NOP (0x4e71) instruction because it executes in one
- * cycle not three and doesn't allow for an arbitary delay waiting
+ * cycle not three and doesn't allow for an arbitrary delay waiting
* for bus cycles to finish. Also fp/a6 isn't likely to cause a
* stall waiting for the register to become valid if such is added
* to the coldfire at some stage.
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index c64c7b74cf8..b2046839f4b 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -31,7 +31,7 @@
* GPIOs in a single control area, others have some GPIOs implemented in
* different modules.
*
- * This implementation attempts accomodate the differences while presenting
+ * This implementation attempts accommodate the differences while presenting
* a generic interface that will optimize to as few instructions as possible.
*/
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 55d5a4c5fe0..b6bf2c518ba 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -157,7 +157,7 @@
#define MCFFEC_SIZE 0x800 /* Register set size */
/*
- * Reset Controll Unit.
+ * Reset Control Unit.
*/
#define MCF_RCR 0xFC0A0000
#define MCF_RSR 0xFC0A0001
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 8996df62ede..6235921eca4 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -48,7 +48,7 @@
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
/*
- * Reset Controll Unit (relative to IPSBAR).
+ * Reset Control Unit (relative to IPSBAR).
*/
#define MCF_RCR 0x110000
#define MCF_RSR 0x110001
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 74855a66c05..758810ef91e 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -283,7 +283,7 @@
#endif
/*
- * Reset Controll Unit (relative to IPSBAR).
+ * Reset Control Unit (relative to IPSBAR).
*/
#define MCF_RCR 0x110000
#define MCF_RSR 0x110001
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 4c94c01f36c..8f8609fcc9b 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -29,7 +29,7 @@
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/
+#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 762c58c8905..51e00b00b8a 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -29,7 +29,7 @@
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/
+#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
diff --git a/arch/m68k/include/asm/m68360_quicc.h b/arch/m68k/include/asm/m68360_quicc.h
index 6d40f4d18e1..59414cc108d 100644
--- a/arch/m68k/include/asm/m68360_quicc.h
+++ b/arch/m68k/include/asm/m68360_quicc.h
@@ -32,7 +32,7 @@ struct user_data {
/* BASE + 0x000: user data memory */
volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/
volatile unsigned char udata_bd[0x200]; /*user data Ucode */
- volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram */
+ volatile unsigned char ucode_ext[0x100]; /*Ucode Extension ram */
volatile unsigned char RESERVED1[0x500]; /* Reserved area */
};
#else
diff --git a/arch/m68k/include/asm/mac_oss.h b/arch/m68k/include/asm/mac_oss.h
index 7221f725193..3cf2b6ed685 100644
--- a/arch/m68k/include/asm/mac_oss.h
+++ b/arch/m68k/include/asm/mac_oss.h
@@ -61,7 +61,7 @@
/*
* OSS Interrupt levels for various sub-systems
*
- * This mapping is layed out with two things in mind: first, we try to keep
+ * This mapping is laid out with two things in mind: first, we try to keep
* things on their own levels to avoid having to do double-dispatches. Second,
* the levels match as closely as possible the alternate IRQ mapping mode (aka
* "A/UX mode") available on some VIA machines.
diff --git a/arch/m68k/include/asm/mac_via.h b/arch/m68k/include/asm/mac_via.h
index 39afb438b65..a59665e1d41 100644
--- a/arch/m68k/include/asm/mac_via.h
+++ b/arch/m68k/include/asm/mac_via.h
@@ -204,7 +204,7 @@
#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
#define vSR 0x1400 /* [VIA only] Shift register. */
-#define vACR 0x1600 /* [VIA only] Auxilary control register. */
+#define vACR 0x1600 /* [VIA only] Auxiliary control register. */
#define vPCR 0x1800 /* [VIA only] Peripheral control register. */
/* CHRP sez never ever to *write* this.
* Mac family says never to *change* this.
diff --git a/arch/m68k/include/asm/macintosh.h b/arch/m68k/include/asm/macintosh.h
index 50db3591ca1..c2a1c5eac1a 100644
--- a/arch/m68k/include/asm/macintosh.h
+++ b/arch/m68k/include/asm/macintosh.h
@@ -14,7 +14,7 @@ extern void mac_init_IRQ(void);
extern int mac_irq_pending(unsigned int);
/*
- * Floppy driver magic hook - probably shouldnt be here
+ * Floppy driver magic hook - probably shouldn't be here
*/
extern void via1_set_head(int);
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 92b276fe824..351c2723787 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -27,7 +27,7 @@
/*
* Bit definitions for the Timer Mode Register (TMR).
- * Register bit flags are common accross ColdFires.
+ * Register bit flags are common across ColdFires.
*/
#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-11-27 03:49:59 +0000