diff options
Diffstat (limited to 'arch/m32r')
114 files changed, 9457 insertions, 5 deletions
diff --git a/arch/m32r/boot/compressed/Makefile b/arch/m32r/boot/compressed/Makefile index d908e1d3c07..560484ae35e 100644 --- a/arch/m32r/boot/compressed/Makefile +++ b/arch/m32r/boot/compressed/Makefile @@ -6,7 +6,6 @@ targets := vmlinux vmlinux.bin vmlinux.bin.gz head.o misc.o \ piggy.o vmlinux.lds -EXTRA_AFLAGS := -traditional OBJECTS = $(obj)/head.o $(obj)/misc.o diff --git a/arch/m32r/include/asm/Kbuild b/arch/m32r/include/asm/Kbuild new file mode 100644 index 00000000000..c68e1680da0 --- /dev/null +++ b/arch/m32r/include/asm/Kbuild @@ -0,0 +1 @@ +include include/asm-generic/Kbuild.asm diff --git a/arch/m32r/include/asm/addrspace.h b/arch/m32r/include/asm/addrspace.h new file mode 100644 index 00000000000..81782c122da --- /dev/null +++ b/arch/m32r/include/asm/addrspace.h @@ -0,0 +1,57 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001 by Hiroyuki Kondo + * + * Defitions for the address spaces of the M32R CPUs. + */ +#ifndef __ASM_M32R_ADDRSPACE_H +#define __ASM_M32R_ADDRSPACE_H + +/* + * Memory segments (32bit kernel mode addresses) + */ +#define KUSEG 0x00000000 +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 +#define KSEG2 0xc0000000 +#define KSEG3 0xe0000000 + +#define K0BASE KSEG0 + +/* + * Returns the kernel segment base of a given address + */ +#ifndef __ASSEMBLY__ +#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000) +#else +#define KSEGX(a) ((a) & 0xe0000000) +#endif + +/* + * Returns the physical address of a KSEG0/KSEG1 address + */ +#ifndef __ASSEMBLY__ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) +#else +#define PHYSADDR(a) ((a) & 0x1fffffff) +#endif + +/* + * Map an address to a certain kernel segment + */ +#ifndef __ASSEMBLY__ +#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0)) +#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) +#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2)) +#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3)) +#else +#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0) +#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1) +#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2) +#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3) +#endif + +#endif /* __ASM_M32R_ADDRSPACE_H */ diff --git a/arch/m32r/include/asm/assembler.h b/arch/m32r/include/asm/assembler.h new file mode 100644 index 00000000000..728799fc70a --- /dev/null +++ b/arch/m32r/include/asm/assembler.h @@ -0,0 +1,230 @@ +#ifndef _ASM_M32R_ASSEMBLER_H +#define _ASM_M32R_ASSEMBLER_H + +/* + * linux/asm-m32r/assembler.h + * + * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org> + * + * This file contains M32R architecture specific macro definitions. + */ + +#include <linux/stringify.h> + +#undef __STR + +#ifdef __ASSEMBLY__ +#define __STR(x) x +#else +#define __STR(x) __stringify(x) +#endif + +#ifdef CONFIG_SMP +#define M32R_LOCK __STR(lock) +#define M32R_UNLOCK __STR(unlock) +#else +#define M32R_LOCK __STR(ld) +#define M32R_UNLOCK __STR(st) +#endif + +#ifdef __ASSEMBLY__ +#undef ENTRY +#define ENTRY(name) ENTRY_M name + .macro ENTRY_M name + .global \name + ALIGN +\name: + .endm +#endif + + +/** + * LDIMM - load immediate value + * STI - enable interruption + * CLI - disable interruption + */ + +#ifdef __ASSEMBLY__ + +#define LDIMM(reg,x) LDIMM reg x + .macro LDIMM reg x + seth \reg, #high(\x) + or3 \reg, \reg, #low(\x) + .endm + +#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) +#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg + .macro ENABLE_INTERRUPTS reg + setpsw #0x40 -> nop + ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1). + .endm + +#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg + .macro DISABLE_INTERRUPTS reg + clrpsw #0x40 -> nop + ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1). + .endm +#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ +#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg + .macro ENABLE_INTERRUPTS reg + mvfc \reg, psw + or3 \reg, \reg, #0x0040 + mvtc \reg, psw + .endm + +#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg + .macro DISABLE_INTERRUPTS reg + mvfc \reg, psw + and3 \reg, \reg, #0xffbf + mvtc \reg, psw + .endm +#endif /* CONFIG_CHIP_M32102 */ + + .macro SAVE_ALL + push r0 ; orig_r0 + push sp ; spi (r15) + push lr ; r14 + push r13 + mvfc r13, cr3 ; spu + push r13 + mvfc r13, bbpc + push r13 + mvfc r13, bbpsw + push r13 + mvfc r13, bpc + push r13 + mvfc r13, psw + push r13 +#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2) + mvfaclo r13, a1 + push r13 + mvfachi r13, a1 + push r13 + mvfaclo r13, a0 + push r13 + mvfachi r13, a0 + push r13 +#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R) + mvfaclo r13 + push r13 + mvfachi r13 + push r13 + ldi r13, #0 + push r13 ; dummy push acc1h + push r13 ; dummy push acc1l +#else +#error unknown isa configuration +#endif + ldi r13, #-1 + push r13 ; syscall_nr (default: -1) + push r12 + push r11 + push r10 + push r9 + push r8 + push r7 + push r3 + push r2 + push r1 + push r0 + addi sp, #-4 ; room for implicit pt_regs parameter + push r6 + push r5 + push r4 + .endm + + .macro RESTORE_ALL + pop r4 + pop r5 + pop r6 + addi sp, #4 + pop r0 + pop r1 + pop |