diff options
Diffstat (limited to 'arch/arm')
61 files changed, 1279 insertions, 318 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 28248b5d6a7..646a5d5eb8c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -394,6 +394,7 @@ config ARCH_KIRKWOOD select CPU_FEROCEON select PCI select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION @@ -415,6 +416,7 @@ config ARCH_MV78XX0 select CPU_FEROCEON select PCI select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION @@ -428,6 +430,7 @@ config ARCH_ORION5X select CPU_FEROCEON select PCI select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index dcf8153a947..0a1abb978d7 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -182,6 +182,7 @@ CONFIG_ARCH_KIRKWOOD=y CONFIG_MACH_DB88F6281_BP=y CONFIG_MACH_RD88F6192_NAS=y CONFIG_MACH_RD88F6281=y +CONFIG_MACH_MV88F6281GTW_GE=y CONFIG_MACH_SHEEVAPLUG=y CONFIG_MACH_TS219=y CONFIG_PLAT_ORION=y @@ -270,7 +271,9 @@ CONFIG_CMDLINE="" # # CPU Power Management # -# CONFIG_CPU_IDLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y # # Floating point emulation diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index 5b98f764511..9e2385293ec 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -903,7 +903,8 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set +CONFIG_HW_RANDOM=m +CONFIG_HW_RANDOM_TIMERIOMEM=m # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 6116e4893c0..15f8a092b70 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -114,3 +114,16 @@ .align 3; \ .long 9999b,9001f; \ .previous + +/* + * SMP data memory barrier + */ + .macro smp_dmb +#ifdef CONFIG_SMP +#if __LINUX_ARM_ARCH__ >= 7 + dmb +#elif __LINUX_ARM_ARCH__ == 6 + mcr p15, 0, r0, c7, c10, 5 @ dmb +#endif +#endif + .endm diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index ee99723b3a6..16b52f39798 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -44,11 +44,29 @@ static inline void atomic_set(atomic_t *v, int i) : "cc"); } +static inline void atomic_add(int i, atomic_t *v) +{ + unsigned long tmp; + int result; + + __asm__ __volatile__("@ atomic_add\n" +"1: ldrex %0, [%2]\n" +" add %0, %0, %3\n" +" strex %1, %0, [%2]\n" +" teq %1, #0\n" +" bne 1b" + : "=&r" (result), "=&r" (tmp) + : "r" (&v->counter), "Ir" (i) + : "cc"); +} + static inline int atomic_add_return(int i, atomic_t *v) { unsigned long tmp; int result; + smp_mb(); + __asm__ __volatile__("@ atomic_add_return\n" "1: ldrex %0, [%2]\n" " add %0, %0, %3\n" @@ -59,14 +77,34 @@ static inline int atomic_add_return(int i, atomic_t *v) : "r" (&v->counter), "Ir" (i) : "cc"); + smp_mb(); + return result; } +static inline void atomic_sub(int i, atomic_t *v) +{ + unsigned long tmp; + int result; + + __asm__ __volatile__("@ atomic_sub\n" +"1: ldrex %0, [%2]\n" +" sub %0, %0, %3\n" +" strex %1, %0, [%2]\n" +" teq %1, #0\n" +" bne 1b" + : "=&r" (result), "=&r" (tmp) + : "r" (&v->counter), "Ir" (i) + : "cc"); +} + static inline int atomic_sub_return(int i, atomic_t *v) { unsigned long tmp; int result; + smp_mb(); + __asm__ __volatile__("@ atomic_sub_return\n" "1: ldrex %0, [%2]\n" " sub %0, %0, %3\n" @@ -77,6 +115,8 @@ static inline int atomic_sub_return(int i, atomic_t *v) : "r" (&v->counter), "Ir" (i) : "cc"); + smp_mb(); + return result; } @@ -84,6 +124,8 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) { unsigned long oldval, res; + smp_mb(); + do { __asm__ __volatile__("@ atomic_cmpxchg\n" "ldrex %1, [%2]\n" @@ -95,6 +137,8 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) : "cc"); } while (res); + smp_mb(); + return oldval; } @@ -135,6 +179,7 @@ static inline int atomic_add_return(int i, atomic_t *v) return val; } +#define atomic_add(i, v) (void) atomic_add_return(i, v) static inline int atomic_sub_return(int i, atomic_t *v) { @@ -148,6 +193,7 @@ static inline int atomic_sub_return(int i, atomic_t *v) return val; } +#define atomic_sub(i, v) (void) atomic_sub_return(i, v) static inline int atomic_cmpxchg(atomic_t *v, int old, int new) { @@ -187,10 +233,8 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) -#define atomic_add(i, v) (void) atomic_add_return(i, v) -#define atomic_inc(v) (void) atomic_add_return(1, v) -#define atomic_sub(i, v) (void) atomic_sub_return(i, v) -#define atomic_dec(v) (void) atomic_sub_return(1, v) +#define atomic_inc(v) atomic_add(1, v) +#define atomic_dec(v) atomic_sub(1, v) #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0) #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0) @@ -200,11 +244,10 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0) -/* Atomic operations are already serializing on ARM */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() +#define smp_mb__before_atomic_dec() smp_mb() +#define smp_mb__after_atomic_dec() smp_mb() +#define smp_mb__before_atomic_inc() smp_mb() +#define smp_mb__after_atomic_inc() smp_mb() #include <asm-generic/atomic.h> #endif diff --git a/arch/arm/include/asm/flat.h b/arch/arm/include/asm/flat.h index 1d77e51907f..59426a4595c 100644 --- a/arch/arm/include/asm/flat.h +++ b/arch/arm/include/asm/flat.h @@ -5,9 +5,6 @@ #ifndef __ARM_FLAT_H__ #define __ARM_FLAT_H__ -/* An odd number of words will be pushed after this alignment, so - deliberately misalign the value. */ -#define flat_stack_align(sp) sp = (void *)(((unsigned long)(sp) - 4) | 4) #define flat_argvp_envp_on_stack() 1 #define flat_old_ram_flag(flags) (flags) #define flat_reloc_valid(reloc, size) ((reloc) <= (size)) diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h index ada93a8fc2e..4fc1565e4f9 100644 --- a/arch/arm/include/asm/sizes.h +++ b/arch/arm/include/asm/sizes.h @@ -29,6 +29,7 @@ #define SZ_512 0x00000200 #define SZ_1K 0x00000400 +#define SZ_2K 0x00000800 #define SZ_4K 0x00001000 #define SZ_8K 0x00002000 #define SZ_16K 0x00004000 diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index bd4dc8ed53d..d65b2f5bf41 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -248,6 +248,8 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size unsigned int tmp; #endif + smp_mb(); + switch (size) { #if __LINUX_ARM_ARCH__ >= 6 case 1: @@ -307,6 +309,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size __bad_xchg(ptr, size), ret = 0; break; } + smp_mb(); return ret; } @@ -316,6 +319,12 @@ extern void enable_hlt(void); #include <asm-generic/cmpxchg-local.h> +#if __LINUX_ARM_ARCH__ < 6 + +#ifdef CONFIG_SMP +#error "SMP is not supported on this platform" +#endif + /* * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make * them available. @@ -329,6 +338,173 @@ extern void enable_hlt(void); #include <asm-generic/cmpxchg.h> #endif +#else /* __LINUX_ARM_ARCH__ >= 6 */ + +extern void __bad_cmpxchg(volatile void *ptr, int size); + +/* + * cmpxchg only support 32-bits operands on ARMv6. + */ + +static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, + unsigned long new, int size) +{ + unsigned long oldval, res; + + switch (size) { +#ifdef CONFIG_CPU_32v6K + case 1: + do { + asm volatile("@ __cmpxchg1\n" + " ldrexb %1, [%2]\n" + " mov %0, #0\n" + " teq %1, %3\n" + " strexbeq %0, %4, [%2]\n" + : "=&r" (res), "=&r" (oldval) + : "r" (ptr), "Ir" (old), "r" (new) + : "memory", "cc"); + } while (res); + break; + case 2: + do { + asm volatile("@ __cmpxchg1\n" + " ldrexh %1, [%2]\n" + " mov %0, #0\n" + " teq %1, %3\n" + " strexheq %0, %4, [%2]\n" + : "=&r" (res), "=&r" (oldval) + : "r" (ptr), "Ir" (old), "r" (new) + : "memory", "cc"); + } while (res); + break; +#endif /* CONFIG_CPU_32v6K */ + case 4: + do { + asm volatile("@ __cmpxchg4\n" + " ldrex %1, [%2]\n" + " mov %0, #0\n" + " teq %1, %3\n" + " strexeq %0, %4, [%2]\n" + : "=&r" (res), "=&r" (oldval) + : "r" (ptr), "Ir" (old), "r" (new) + : "memory", "cc"); + } while (res); + break; + default: + __bad_cmpxchg(ptr, size); + oldval = 0; + } + + return oldval; +} + +static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old, + unsigned long new, int size) +{ + unsigned long ret; + + smp_mb(); + ret = __cmpxchg(ptr, old, new, size); + smp_mb(); + + return ret; +} + +#define cmpxchg(ptr,o,n) \ + ((__typeof__(*(ptr)))__cmpxchg_mb((ptr), \ + (unsigned long)(o), \ + (unsigned long)(n), \ + sizeof(*(ptr)))) + +static inline unsigned long __cmpxchg_local(volatile void *ptr, + unsigned long old, + unsigned long new, int size) +{ + unsigned long ret; + + switch (size) { +#ifndef CONFIG_CPU_32v6K + case 1: + case 2: + ret = __cmpxchg_local_generic(ptr, old, new, size); + break; +#endif /* !CONFIG_CPU_32v6K */ + default: + ret = __cmpxchg(ptr, old, new, size); + } + + return ret; +} + +#define cmpxchg_local(ptr,o,n) \ + ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \ + (unsigned long)(o), \ + (unsigned long)(n), \ + sizeof(*(ptr)))) + +#ifdef CONFIG_CPU_32v6K + +/* + * Note : ARMv7-M (currently unsupported by Linux) does not support + * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should + * not be allowed to use __cmpxchg64. + */ +static inline unsigned long long __cmpxchg64(volatile void *ptr, + unsigned long long old, + unsigned long long new) +{ + register unsigned long long oldval asm("r0"); + register unsigned long long __old asm("r2") = old; + register unsigned long long __new asm("r4") = new; + unsigned long res; + + do { + asm volatile( + " @ __cmpxchg8\n" + " ldrexd %1, %H1, [%2]\n" + " mov %0, #0\n" + " teq %1, %3\n" + " teqeq %H1, %H3\n" + " strexdeq %0, %4, %H4, [%2]\n" + : "=&r" (res), "=&r" (oldval) + : "r" (ptr), "Ir" (__old), "r" (__new) + : "memory", "cc"); + } while (res); + + return oldval; +} + +static inline unsigned long long __cmpxchg64_mb(volatile void *ptr, + unsigned long long old, + unsigned long long new) +{ + unsigned long long ret; + + smp_mb(); + ret = __cmpxchg64(ptr, old, new); + smp_mb(); + + return ret; +} + +#define cmpxchg64(ptr,o,n) \ + ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \ + (unsigned long long)(o), \ + (unsigned long long)(n))) + +#define cmpxchg64_local(ptr,o,n) \ + ((__typeof__(*(ptr)))__cmpxchg64((ptr), \ + (unsigned long long)(o), \ + (unsigned long long)(n))) + +#else /* !CONFIG_CPU_32v6K */ + +#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) + +#endif /* CONFIG_CPU_32v6K */ + +#endif /* __LINUX_ARM_ARCH__ >= 6 */ + #endif /* __ASSEMBLY__ */ #define arch_align_stack(x) (x) diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c index d4a0da1e48f..950391f194c 100644 --- a/arch/arm/kernel/elf.c +++ b/arch/arm/kernel/elf.c @@ -78,6 +78,15 @@ int arm_elf_read_implies_exec(const struct elf32_hdr *x, int executable_stack) return 1; if (cpu_architecture() < CPU_ARCH_ARMv6) return 1; +#if !defined(CONFIG_AEABI) || defined(CONFIG_OABI_COMPAT) + /* + * If we have support for OABI programs, we can never allow NX + * support - our signal syscall restart mechanism relies upon + * being able to execute code placed on the user stack. + */ + return 1; +#else return 0; +#endif } EXPORT_SYMBOL(arm_elf_read_implies_exec); diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index d662a2f1fd8..83b1da6b7ba 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -815,10 +815,7 @@ __kuser_helper_start: */ __kuser_memory_barrier: @ 0xffff0fa0 - -#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) - mcr p15, 0, r0, c7, c10, 5 @ dmb -#endif + smp_dmb usr_ret lr .align 5 diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h index 2e787d40d59..c7f2627385e 100644 --- a/arch/arm/lib/bitops.h +++ b/arch/arm/lib/bitops.h @@ -18,12 +18,14 @@ mov r2, #1 add r1, r1, r0, lsr #3 @ Get byte offset mov r3, r2, lsl r3 @ create mask + smp_dmb 1: ldrexb r2, [r1] ands r0, r2, r3 @ save old value of bit \instr r2, r2, r3 @ toggle bit strexb ip, r2, [r1] cmp ip, #0 bne 1b + smp_dmb cmp r0, #0 movne r0, #1 2: mov pc, lr diff --git a/arch/arm/mach-gemini/include/mach/hardware.h b/arch/arm/mach-gemini/include/mach/hardware.h index de6752674c0..213a4fcfeb1 100644 --- a/arch/arm/mach-gemini/include/mach/hardware.h +++ b/arch/arm/mach-gemini/include/mach/hardware.h @@ -15,10 +15,9 @@ /* * Memory Map definitions */ -/* FIXME: Does it really swap SRAM like this? */ #ifdef CONFIG_GEMINI_MEM_SWAP # define GEMINI_DRAM_BASE 0x00000000 -# define GEMINI_SRAM_BASE 0x20000000 +# define GEMINI_SRAM_BASE 0x70000000 #else # define GEMINI_SRAM_BASE 0x00000000 # define GEMINI_DRAM_BASE 0x10000000 diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index b5421cccd7e..25100f7acf4 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -20,6 +20,12 @@ config MACH_RD88F6281 Say 'Y' here if you want your kernel to support the Marvell RD-88F6281 Reference Board. +config MACH_MV88F6281GTW_GE + bool "Marvell 88F6281 GTW GE Board" + help + Say 'Y' here if you want your kernel to support the + Marvell 88F6281 GTW GE Board. + config MACH_SHEEVAPLUG bool "Marvell SheevaPlug Reference Board" help diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 8f03c9b9bdd..9dd680e964d 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -3,5 +3,8 @@ obj-y += common.o addr-map.o irq.o pcie.o mpp.o obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o +obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o + +obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c index 5db4f0bbe5e..1da5d1c18ec 100644 --- a/arch/arm/mach-kirkwood/addr-map.c +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -20,6 +20,7 @@ */ #define TARGET_DDR 0 #define TARGET_DEV_BUS 1 +#define TARGET_SRAM 3 #define TARGET_PCIE 4 #define ATTR_DEV_SPI_ROM 0x1e #define ATTR_DEV_BOOT 0x1d @@ -30,6 +31,7 @@ #define ATTR_DEV_CS0 0x3e #define ATTR_PCIE_IO 0xe0 #define ATTR_PCIE_MEM 0xe8 +#define ATTR_SRAM 0x01 /* * Helpers to get DDR bank info @@ -48,7 +50,6 @@ struct mbus_dram_target_info kirkwood_mbus_dram_info; -static int __initdata win_alloc_count; static int __init cpu_win_can_remap(int win) { @@ -112,7 +113,11 @@ void __init kirkwood_setup_cpu_mbus(void) setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, TARGET_DEV_BUS, ATTR_DEV_NAND, -1); - win_alloc_count = 3; + /* + * Setup window for SRAM. + */ + setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, + TARGET_SRAM, ATTR_SRAM, -1); /* * Setup MBUS dram target info. @@ -140,8 +145,3 @@ void __init kirkwood_setup_cpu_mbus(void) } kirkwood_mbus_dram_info.num_cs = cs; } - -void __init kirkwood_setup_sram_win(u32 base, u32 size) -{ - setup_cpu_win(win_alloc_count++, base, size, 0x03, 0x00, -1); -} diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index eeb00240d78..0f691983801 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -16,6 +16,7 @@ #include <linux/mv643xx_eth.h> #include <linux/mv643xx_i2c.h> #include <linux/ata_platform.h> +#include <linux/mtd/nand.h> #include <linux/spi/orion_spi.h> #include <net/dsa.h> #include <asm/page.h> @@ -29,6 +30,7 @@ #include <plat/mvsdio.h> #include <plat/mv_xor.h> #include <plat/orion_nand.h> +#include <plat/orion_wdt.h> #include <plat/time.h> #include "common.h" @@ -54,6 +56,13 @@ void __init kirkwood_map_io(void) iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); } +/* + * Default clock control bits. Any bit _not_ set in this variable + * will be cleared from the hardware after platform devices have been + * registered. Some reserved bits must be set to 1. + */ +unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; + /***************************************************************************** * EHCI @@ -95,6 +104,7 @@ static struct platform_device kirkwood_ehci = { void __init kirkwood_ehci_init(void) { + kirkwood_clk_ctrl |= CGC_USB0; platform_device_register(&kirkwood_ehci); } @@ -144,10 +154,14 @@ static struct platform_device kirkwood_ge00 = { .id = 0, .num_resources = 1, .resource = kirkwood_ge00_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, }; void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) { + kirkwood_clk_ctrl |= CGC_GE0; eth_data->shared = &kirkwood_ge00_shared; kirkwood_ge00.dev.platform_data = eth_data; @@ -202,10 +216,14 @@ static struct platform_device kirkwood_ge01 = { .id = 1, .num_resources = 1, .resource = kirkwood_ge01_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, }; void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) { + kirkwood_clk_ctrl |= CGC_GE1; eth_data->shared = &kirkwood_ge01_shared; kirkwood_ge01.dev.platform_data = eth_data; @@ -252,6 +270,43 @@ void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq) /***************************************************************************** + * NAND flash + ****************************************************************************/ +static struct resource kirkwood_nand_resource = { + .flags = IORESOURCE_MEM, + .start = KIRKWOOD_NAND_MEM_PHYS_BASE, + .end = KIRKWOOD_NAND_MEM_PHYS_BASE + + KIRKWOOD_NAND_MEM_SIZE - 1, +}; + +static struct orion_nand_data kirkwood_nand_data = { + .cle = 0, + .ale = 1, + .width = 8, +}; + +static struct platform_device kirkwood_nand_flash = { + .name = "orion_nand", + .id = -1, + .dev = { + .platform_data = &kirkwood_nand_data, + }, + .resource = &kirkwood_nand_resource, + .num_resources = 1, +}; + +void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, + int chip_delay) +{ + kirkwood_clk_ctrl |= CGC_RUNIT; + kirkwood_nand_data.parts = parts; + kirkwood_nand_data.nr_parts = nr_parts; + kirkwood_nand_data.chip_delay = chip_delay; + platform_device_register(&kirkwood_nand_flash); +} + + +/***************************************************************************** * SoC RTC ****************************************************************************/ static struct resource kirkwood_rtc_resource = { @@ -295,6 +350,9 @@ static struct platform_device kirkwood_sata = { void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) { + kirkwood_clk_ctrl |= CGC_SATA0; + if (sata_data->n_ports > 1) + kirkwood_clk_ctrl |= CGC_SATA1; sata_data->dram = &kirkwood_mbus_dram_info; kirkwood_sata.dev.platform_data = sata_data; platform_device_register(&kirkwood_sata); @@ -340,6 +398,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) else mvsdio_data->clock = 200000000; mvsdio_data->dram = &kirkwood_mbus_dram_info; + kirkwood_clk_ctrl |= CGC_SDIO; kirkwood_sdio.dev.platform_data = mvsdio_data; platform_device_register(&kirkwood_sdio); } @@ -371,6 +430,7 @@ static struct platform_device kirkwood_spi = { void __init kirkwood_spi_init() { + kirkwood_clk_ctrl |= CGC_RUNIT; platform_device_register(&kirkwood_spi); } @@ -386,12 +446,10 @@ static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = { static struct resource kirkwood_i2c_resources[] = { { - .name = "i2c", .start = I2C_PHYS_BASE, .end = I2C_PHYS_BASE + 0x1f, .flags = IORESOURCE_MEM, }, { - .name = "i2c", .start = IRQ_KIRKWOOD_TWSI, .end = IRQ_KIRKWOOD_TWSI, .flags = IORESOURCE_IRQ, @@ -503,6 +561,43 @@ void __init kirkwood_uart1_init(void) /***************************************************************************** + * Cryptographic Engines and Security Accelerator (CESA) + ****************************************************************************/ + +static struct resource kirkwood_crypto_res[] = { + { + .name = "regs", + .start = CRYPTO_PHYS_BASE, + .end = CRYPTO_PHYS_BASE + 0xffff, + .flags = IORESOURCE_MEM, + }, { + .name = "sram", + .start = KIRKWOOD_SRAM_PHYS_BASE, + .end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "crypto interrupt", + .start = IRQ_KIRKWOOD_CRYPTO, + .end = IRQ_KIRKWOOD_CRYPTO, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_crypto_device = { + .name = "mv_crypto", + .id = -1, + .num_resources = ARRAY_SIZE(kirkwood_crypto_res), + .resource = kirkwood_crypto_res, +}; + +void __init kirkwood_crypto_init(void) +{ + kirkwood_clk_ctrl |= CGC_CRYPTO; + platform_device_register(&kirkwood_crypto_device); +} + + +/***************************************************************************** * XOR ****************************************************************************/ static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = { @@ -593,6 +688,7 @@ static struct platform_device kirkwood_xor01_channel = { static void __init kirkwood_xor0_init(void) { + kirkwood_clk_ctrl |= CGC_XOR0; platform_device_register(&kirkwood_xor0_shared); /* @@ -691,6 +787,7 @@ static struct platform_device kirkwood_xor11_channel = { static void __init kirkwood_xor1_init(void) { + kirkwood_clk_ctrl |= CGC_XOR1; platform_device_register(&kirkwood_xor1_shared); /* @@ -709,6 +806,29 @@ static void __init kirkwood_xor1_init(void) /***************************************************************************** + * Watchdog + ****************************************************************************/ +static struct orion_wdt_platform_data kirkwood_wdt_data = { + .tclk = 0, +}; + +static struct platform_device kirkwood_wdt_device = { + .name = "orion_wdt", + .id = -1, + .dev = { + .platform_data = &kirkwood_wdt_data, + }, + .num_resources = 0, +}; + +static void __init kirkwood_wdt_init(void) +{ + kirkwood_wdt_data.tclk = kirkwood_tclk; + platform_device_register(&kirkwood_wdt_device); +} + + +/***************************************************************************** * Time handling ****************************************************************************/ int kirkwood_tclk; @@ -800,6 +920,49 @@ void __init kirkwood_init(void) /* internal devices that every board has */ kirkwood_rtc_init(); + kirkwood_wdt_init(); kirkwood_xor0_init(); kirkwood_xor1_init(); + kirkwood_crypto_init(); +} + +static int __init kirkwood_clock_gate(void) +{ + unsigned int curr = readl(CLOCK_GATING_CTRL); + + printk(KERN_DEBUG "Gating clock of unused units\n"); + printk(KERN_DEBUG "before: 0x%08x\n", curr); + + /* Make sure those units are accessible */ + writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL); + + /* For SATA: first shutdown the phy */ + if (!(kirkwood_clk_ctrl & CGC_SATA0)) { + /* Disable PLL and IVREF */ + writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2); + /* Disable PHY */ + writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL); + } + if (!(kirkwood_clk_ctrl & CGC_SATA1)) { + /* Disable PLL and IVREF */ + writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2); + /* Disable PHY */ + writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL); + } + + /* For PCIe: first shutdown the phy */ + if (!(kirkwood_clk_ctrl & CGC_PEX0)) { + writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL); + while (1) + if (readl(PCIE_STATUS) & 0x1) + break; + writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL); + } + + /* Now gate clock the required units */ + writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL); + printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL)); + + return 0; } +late_initcall(kirkwood_clock_gate); diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 6ee88406f38..d7de4346435 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -15,6 +15,7 @@ struct dsa_platform_data; struct mv643xx_eth_platform_data; struct mv_sata_platform_data; struct mvsdio_platform_data; +struct mtd_partition; /* * Basic Kirkwood init functions used early by machine-setup. @@ -25,7 +26,6 @@ void kirkwood_init_irq(void); extern struct mbus_dram_target_info kirkwood_mbus_dram_info; void kirkwood_setup_cpu_mbus(void); -void kirkwood_setup_sram_win(u32 base, u32 size); void kirkwood_pcie_id(u32 *dev, u32 *rev); @@ -40,9 +40,11 @@ void kirkwood_spi_init(void); void kirkwood_i2c_init(void); void kirkwood_uart0_init(void); void kirkwood_uart1_init(void); +void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay); extern int kirkwood_tclk; extern struct sys_timer kirkwood_timer; +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) #endif diff --git a/arch/arm/mach-kirkwood/cpuidle.c b/arch/arm/mach-kirkwood/cpuidle.c new file mode 100644 index 00000000000..f68d33f1f39 --- /dev/null +++ b/arch/arm/mach-kirkwood/cpuidle.c @@ -0,0 +1,96 @@ +/* + * arch/arm/mach-kirkwood/cpuidle.c + * + * CPU idle Marvell Kirkwood SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * The cpu idle uses wait-for-interrupt and DDR self refresh in order + * to implement two idle states - + * #1 wait-for-interrupt + * #2 wait-for-interrupt and DDR self refresh + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/cpuidle.h> +#include <linux/io.h> +#include <asm/proc-fns.h> +#include <mach/kirkwood.h> + +#define KIRKWOOD_MAX_STATES 2 + +static struct cpuidle_driver kirkwood_idle_driver = { + .name = "kirkwood_idle", + .owner = THIS_MODULE, +}; + +static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device); + +/* Actual code that puts the SoC in different idle states */ +static int kirkwood_enter_idle(struct cpuidle_device *dev, + struct cpuidle_state *state) +{ + struct timeval before, after; + int idle_time; + + local_irq_disable(); + do_gettimeofday(&before); + if (state == &dev->states[0]) + /* Wait for interrupt state */ + cpu_do_idle(); + else if (state == &dev->states[1]) { + /* + * Following write will put DDR in self refresh. + * Note that we have 256 cycles before DDR puts it + * self in self-refresh, so the wait-for-interrupt + * call afterwards won't get the DDR from self refresh + * mode. + */ + writel(0x7, DDR_OPERATION_BASE); + cpu_do_idle(); + } + do_gettimeofday(&after); + local_irq_enable(); + idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + + (after.tv_usec - before.tv_usec); + return idle_time; +} + +/* Initialize CPU idle by registering the idle states */ +static int kirkwood_init_cpuidle(void) +{ + struct cpuidle_device *device; + + cpuidle_register_driver(&kirkwood_idle_driver); + + device = &per_cpu(kirkwood_cpuidle_device, smp_processor_id()); + device->state_count = KIRKWOOD_MAX_STATES; + + /* Wait for interrupt state */ + device->states[0].enter = kirkwood_enter_idle; + device->states[0].exit_latency = 1; + device->states[0].target_residency = 10000; + device->states[0].flags = CPUIDLE_FLAG_TIME_VALID; + strcpy(device->states[0].name, "WFI"); + strcpy(device->states[0].desc, "Wait for interrupt"); + + /* Wait for interrupt and DDR self refresh state */ + device->states[1].enter = kirkwood_enter_idle; + device->states[1].exit_latency = 10; + device->states[1].target_residency = 10000; + device->states[1].flags = CPUIDLE_FLAG_TIME_VALID; + strcpy(device->states[1].name, "DDR SR"); + strcpy(device->states[1].desc, "WFI and DDR Self Refresh"); + + if (cpuidle_register_device(device)) { + printk(KERN_ERR "kirkwood_init_cpuidle: Failed registering\n"); + return -EIO; + } + return 0; +} + +device_initcall(kirkwood_init_cpuidle); diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c index 5505d583775..39bdf4bcace 100644 --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c @@ -11,14 +11,12 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> #include <linux/ata_platform.h> #include <linux/mv643xx_eth.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/kirkwood.h> -#include <plat/orion_nand.h> #include <plat/mvsdio.h> #include "common.h" #include "mpp.h" @@ -39,32 +37,6 @@ static struct mtd_partition db88f6281_nand_parts[] = { }, }; -static struct resource db88f6281_nand_resource = { - .flags = IORESOURCE_MEM, - .start = KIRKWOOD_NAND_MEM_PHYS_BASE, - .end = KIRKWOOD_NAND_MEM_PHYS_BASE + - KIRKWOOD_NAND_MEM_SIZE - 1, -}; - -static struct orion_nand_data db88f6281_nand_data = { - .parts = db88f6281_nand_parts, - .nr_parts = ARRAY_SIZE(db88f6281_nand_parts), - .cle = 0, - .ale = 1, - .width = 8, - .chip_delay = 25, -}; - -static struct platform_device db88f6281_nand_flash = { - .name = "orion_nand", - .id = -1, - .dev = { - .platform_data = &db88f6281_nand_data, - }, - .resource = &db88f6281_nand_resource, - .num_resources = 1, -}; - static struct mv643xx_eth_platform_data db88f6281_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; @@ -92,13 +64,12 @@ static void __init db88f6281_init(void) kirkwood_init(); kirkwood_mpp_conf(db88f6281_mpp_config); + kirkwood_nand_init(ARRAY_AND_SIZE(db88f6281_nand_parts), 25); kirkwood_ehci_init(); kirkwood_ge00_init(&db88f6281_ge00_data); kirkwood_sata_init(&db88f6281_sata_data); kirkwood_uart0_init(); kirkwood_sdio_init(&db88f6281_mvsdio_data); - - platform_device_register(&db88f6281_nand_flash); } static int __init db88f6281_pci_init(void) diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index 4f7029f521c..9e80d9232c8 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -17,12 +17,15 @@ #define CPU_RESET 0x00000002 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define WDT_RESET_OUT_EN 0x00000002 #define SOFT_RESET_OUT_EN 0x00000004 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) #define SOFT_RESET 0x00000001 #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) +#define WDT_INT_REQ 0x0008 + #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) #define BRIDGE_INT_TIMER0 0x0002 #define BRIDGE_INT_TIMER1 0x0004 @@ -39,4 +42,22 @@ #define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) #define L2_WRITETHROUGH 0x00000010 +#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c) +#define CGC_GE0 (1 << 0) +#define CGC_PEX0 (1 << 2) +#define CGC_USB0 (1 << 3) +#define CGC_SDIO (1 << 4) +#define CGC_TSU (1 << 5) +#define CGC_DUNIT (1 << 6) +#define CGC_RUNIT (1 << 7) +#define CGC_XOR0 (1 << 8) +#define CGC_AUDIO (1 << 9) +#define CGC_SATA0 (1 << 14) +#define CGC_SATA1 (1 << 15) +#define CGC_XOR1 (1 << 16) +#define CGC_CRYPTO (1 << 17) +#define CGC_GE1 (1 << 19) +#define CGC_TDM (1 << 20) +#define CGC_RESERVED ((1 << 18) | (0x6 << 21)) + #endif diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h index be07be0ef52..a643a846d5f 100644 --- a/arch/arm/mach-kirkwood/include/mach/io.h +++ b/arch/arm/mach-kirkwood/include/mach/io.h @@ -19,6 +19,31 @@ static inline void __iomem *__io(unsigned long addr) + KIRKWOOD_PCIE_IO_VIRT_BASE); } +static inline void __iomem * +__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) +{ + void __iomem *retval; + unsigned long offs = paddr - KIRKWOOD_REGS_PHYS_BASE; + if (mtype == MT_DEVICE && size && offs < KIRKWOOD_REGS_SIZE && + size <= KIRKWOOD_REGS_SIZE && offs + size <= KIRKWOOD_REGS_SIZE) { + retval = (void __iomem *)KIRKWOOD_REGS_VIRT_BASE + offs; + } else { + retval = __arm_ioremap(paddr, size, mtype); + } + + return retval; +} + +static inline void +__arch_iounmap(void __iomem *addr) +{ + if (addr < (void __iomem *)KIRKWOOD_REGS_VIRT_BASE || + addr >= (void __iomem *)(KIRKWOOD_REGS_VIRT_BASE + KIRKWOOD_REGS_SIZE)) + __iounmap(addr); +} + +#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) +#define __arch_iounmap(a) __arch_iounmap(a) #define __io(a) __io(a) #define __mem_pci(a) (a) diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index b3e13958821..07af858814a 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -20,16 +20,18 @@ * f1000000 on-chip peripheral registers * f2000000 PCIe I/O space * f3000000 NAND controller address window + * f4000000 Security Accelerator SRAM * * virt phys size * fee00000 f1000000 1M on-chip peripheral registers * fef00000 f2000000 1M PCIe I/O space */ +#define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000 +#define KIRKWOOD_SRAM_SIZE SZ_2K + #define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 -#define KIRKWOOD_NAND_MEM_SIZE SZ_64K /* 1K is sufficient, but 64K - * is the minimal window size - */ +#define KIRKWOOD_NAND_MEM_SIZE SZ_1K #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 #define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 @@ -48,6 +50,7 @@ */ #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) #define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) +#define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418) #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) #define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) @@ -63,7 +66,11 @@ #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) +#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000) + #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) +#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) +#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) @@ -80,6 +87,11 @@ #define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) +#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000) +#define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050) +#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330) +#define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050) +#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330) #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 63c44934391..a5900f64e38 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -48,6 +48,9 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list) if (!variant_mask) return; + /* Initialize gpiolib. */ + orion_gpio_init(); + printk(KERN_DEBUG "initial MPP regs:"); for (i = 0; i < MPP_NR_REGS; i++) { mpp_ctrl[i] = readl(MPP_CTRL(i)); diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c new file mode 100644 index 00000000000..0358f45766c --- /dev/null +++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c @@ -0,0 +1,173 @@ +/* + * arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c + * + * Marvell 88F6281 GTW GE Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/mtd/physmap.h> +#include <linux/timer.h> +#include <linux/mv643xx_eth.h> +#include <linux/ethtool.h> +#include <linux/gpio.h> +#include <linux/leds.h> +#include <linux/input.h> +#include <linux/gpio_keys.h> +#include <linux/spi/flash.h> +#include <linux/spi/spi.h> +#include <linux/spi/orion_spi.h> +#include <net/dsa.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <mach/kirkwood.h> +#include "common.h" +#include "mpp.h" + +static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_NONE, + .speed = SPEED_1000, + .duplex = DUPLEX_FULL, +}; + +static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = { + .port_names[0] = "lan1", + .port_names[1] = "lan2", + .port_names[2] = "lan3", + .port_names[3] = "lan4", + .port_names[4] = "wan", + .port_names[5] = "cpu", +}; + +static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = { + .nr_chips = 1, + .chip = &mv88f6281gtw_ge_switch_chip_data, +}; + +static const struct flash_platform_data mv88f6281gtw_ge_spi_slave_data = { + .type = "mx25l12805d", +}; + +static struct spi_board_info __initdata mv88f6281gtw_ge_spi_slave_info[] = { + { + .modalias = "m25p80", + .platform_data = &mv88f6281gtw_ge_spi_slave_data, + .irq = -1, + .max_speed_hz = 50000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static struct gpio_keys_button mv88f6281gtw_ge_button_pins[] = { + { + .code = KEY_RESTART, + .gpio = 47, + .desc = "SWR Button", + .active_low = 1, + }, { + .code = KEY_F1, + .gpio = 46, + .desc = "WPS Button(F1)", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data mv88f6281gtw_ge_button_data = { + .buttons = mv88f6281gtw_ge_button_pins, + .nbuttons = ARRAY_SIZE(mv88f6281gtw_ge_button_pins), +}; + +static struct platform_device mv88f6281gtw_ge_buttons = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &mv88f6281gtw_ge_button_data, + }, +}; + +static struct gpio_led mv88f6281gtw_ge_led_pins[] = { + { + .name = "gtw:green:Status", + .gpio = 20, + .active_low = 0, + }, { + .name = "gtw:red:Status", + .gpio = 21, + .active_low = 0, + }, { + .name = "gtw:green:USB", + .gpio = 12, + .active_low = 0, + }, +}; + +static struct gpio_led_platform_data mv88f6281gtw_ge_led_data = { + .leds = mv88f6281gtw_ge_led_pins, + .num_leds = ARRAY_SIZE(mv88f6281gtw_ge_led_pins), +}; + +static struct platform_device mv88f6281gtw_ge_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &mv88f6281gtw_ge_led_data, + }, +}; + +static unsigned int mv88f6281gtw_ge_mpp_config[] __initdata = { + MPP12_GPO, /* Status#_USB pin */ + MPP20_GPIO, /* Status#_GLED pin */ + MPP21_GPIO, /* Status#_RLED pin */ + MPP46_GPIO, /* WPS_Switch pin */ + MPP47_GPIO, /* SW_Init pin */ + 0 +}; + +static void __init mv88f6281gtw_ge_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + kirkwood_mpp_conf(mv88f6281gtw_ge_mpp_config); + + kirkwood_ehci_init(); + kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data); + kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ); + spi_register_board_info(mv88f6281gtw_ge_spi_slave_info, + ARRAY_SIZE(mv88f6281gtw_ge_spi_slave_info)); + kirkwood_spi_init(); + kirkwood_uart0_init(); + platform_device_register(&mv88f6281gtw_ge_leds); + platform_device_register(&mv88f6281gtw_ge_buttons); +} + +static int __init mv88f6281gtw_ge_pci_init(void) +{ + if (machine_is_mv88f6281gtw_ge()) + kirkwood_pcie_init(); + + return 0; +} +subsys_initcall(mv88f6281gtw_ge_pci_init); + +MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board") + /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = mv88f6281gtw_ge_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index 73fccacd1a7..d90b9aae308 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -14,6 +14,7 @@ #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <mach/bridge-regs.h> #include "common.h" @@ -95,6 +96,7 @@ static struct pci_ops pcie_ops = { static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) { struct resource *res; + extern unsigned int kirkwood_clk_ctrl; /* * Generic PCIe unit setup. @@ -133,6 +135,8 @@ static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) sys->resource[2] = NULL; sys->io_offset = 0; + kirkwood_clk_ctrl |= CGC_PEX0; + return 1; } diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c index 2f0e4ef3db0..8bf4153d084 100644 --- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c @@ -11,8 +11,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/partitions.h> #include <linux/ata_platform.h> #include <linux/mv643xx_eth.h> #include <linux/spi/flash.h> diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c index 31e996d65fc..31708ddbc83 100644 --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -12,7 +12,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/irq.h> -#include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> #include <linux/ata_platform.h> #include <linux/mv643xx_eth.h> @@ -22,7 +21,6 @@ #include <asm/mach/arch.h> #include <mach/kirkwood.h> #include <plat/mvsdio.h> -#include <plat/orion_nand.h> #include "common.h" #include "mpp.h" @@ -42,32 +40,6 @@ static struct mtd_partition rd88f6281_nand_parts[] = { }, }; -static struct resource rd88f6281_nand_resource = { - .flags = IORESOURCE_MEM, - .start = KIRKWOOD_NAND_MEM_PHYS_BASE, - .end = KIRKWOOD_NAND_MEM_PHYS_BASE + - KIRKWOOD_NAND_MEM_SIZE - 1, -}; - -static struct orion_nand_data rd88f6281_nand_data = { - .parts = rd88f6281_nand_parts, - .nr_parts = ARRAY_SIZE(rd88f6281_nand_parts), - .cle = 0, - .ale = 1, - .width = 8, - .chip_delay = 25, -}; - -static struct platform_device rd88f6281_nand_flash = { - .name = "orion_nand", - .id = -1, - .dev = { - .platform_data = &rd88f6281_nand_data, - }, - .resource = &rd88f6281_nand_resource, - .num_resources = 1, -}; - static struct mv643xx_eth_platform_data rd88f6281_ge00_data = { .phy_addr = MV643XX_ETH_PHY_NONE, .speed = SPEED_1000, @@ -114,6 +86,7 @@ static void __init rd88f6281_init(void) kirkwood_init(); kirkwood_mpp_conf(rd88f6281_mpp_config); + kirkwood_nand_init(ARRAY_AND_SIZE(rd88f6281_nand_parts), 25); kirkwood_ehci_init(); kirkwood_ge00_init(&rd88f6281_ge00_data); @@ -129,8 +102,6 @@ static void __init rd88f6281_init(void) kirkwood_sata_init(&rd88f6281_sata_data); kirkwood_sdio_init(&rd88f6281_mvsdio_data); kirkwood_uart0_init(); - - platform_device_register(&rd88f6281_nand_flash); } static int __init rd88f6281_pci_init(void) diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c index 831e4a56cae..c7319eeac8b 100644 --- a/arch/arm/mach-kirkwood/sheevaplug-setup.c +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c @@ -11,7 +11,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> #include <linux/mv643xx_eth.h> #include <linux/gpio.h> @@ -20,7 +19,6 @@ #include <asm/mach/arch.h> #include <mach/kirkwood.h> #include <plat/mvsdio.h> -#include <plat/orion_nand.h> #include "common.h" #include "mpp.h" @@ -40,38 +38,12 @@ static struct mtd_partition sheevaplug_nand_parts[] = { }, }; -static struct resource sheevaplug_nand_resource = { - .flags = IORESOURCE_MEM, - .start = KIRKWOOD_NAND_MEM_PHYS_BASE, - .end = KIRKWOOD_NAND_MEM_PHYS_BASE + - KIRKWOOD_NAND_MEM_SIZE - 1, -}; - -static struct orion_nand_data sheevaplug_nand_data = { - .parts = sheevaplug_nand_parts, - .nr_parts = ARRAY_SIZE(sheevaplug_nand_parts), - .cle = 0, - .ale = 1, - .width = 8, - .chip_delay = 25, -}; - -static struct platform_device sheevaplug_nand_flash = { - .name = "orion_nand", - .id = -1, - .dev = { - .platform_data = &sheevaplug_nand_data, - }, - .resource = &sheevaplug_nand_resource, - .num_resources = 1, -}; - static struct mv643xx_eth_platform_data sheevaplug_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(0), }; static struct mvsdio_platform_data sheevaplug_mvsdio_data = { - // unfortunately the CD signal has not been connected */ + /* unfortunately the CD signal has not been connected */ }; static struct gpio_led sheevaplug_led_pins[] = { @@ -111,6 +83,7 @@ static void __init sheevaplug_init(void) kirkwood_mpp_conf(sheevaplug_mpp_config); kirkwood_uart0_init(); + kirkwood_nand_init(ARRAY_AND_SIZE(sheevaplug_nand_parts), 25); if (gpio_request(29, "USB Power Enable") != 0 || gpio_direction_output(29, 1) != 0) @@ -120,7 +93,6 @@ static void __init sheevaplug_init(void) kirkwood_ge00_init(&sheevaplug_ge00_data); kirkwood_sdio_init(&sheevaplug_mvsdio_data); - platform_device_register(&sheevaplug_nand_flash); platform_device_register(&sheevaplug_leds); } diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c index dda5743cf3e..01aa213c0a6 100644 --- a/arch/arm/mach-kirkwood/ts219-setup.c +++ b/arch/arm/mach-kirkwood/ts219-setup.c @@ -142,6 +142,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { MPP1_SPI_MOSI, MPP2_SPI_SCK, MPP3_SPI_MISO, + MPP4_SATA1_ACTn, + MPP5_SATA0_ACTn, MPP8_TW_SDA, MPP9_TW_SCK, MPP10_UART0_TXD, @@ -150,10 +152,6 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { MPP14_UART1_RXD, /* PIC controller */ MPP15_GPIO, /* USB Copy button */ MPP16_GPIO, /* Reset button */ - MPP20_SATA1_ACTn, - MPP21_SATA0_ACTn, - MPP22_SATA1_PRESENTn, - MPP23_SATA0_PRESENTn, 0 }; diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c index c0d2d9d12e7..818f19d7ab1 100644 --- a/arch/arm/mach-loki/common.c +++ b/arch/arm/mach-loki/common.c @@ -82,6 +82,9 @@ static struct platform_device loki_ge0 = { .id = 0, .num_resources = 1, .resource = loki_ge0_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, }; void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data) @@ -136,6 +139,9 @@ static struct platform_device loki_ge1 = { .id = 1, .num_resources = 1, .resource = loki_ge1_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, }; void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data) diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h index d0bdb6e3682..2e914649b9e 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h @@ -3,6 +3,11 @@ #include <mach/mfp.h> +#define MFP_DRIVE_VERY_SLOW (0x0 << 13) +#define MFP_DRIVE_SLOW (0x1 << 13) +#define MFP_DRIVE_MEDIUM (0x2 << 13) +#define MFP_DRIVE_FAST (0x3 << 13) + /* GPIO */ #define GPIO0_GPIO MFP_CFG(GPIO0, AF5) #define GPIO1_GPIO MFP_CFG(GPIO1, AF5) diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h index 48a1cbc7c56..d97de36c50a 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h @@ -3,6 +3,11 @@ #include <mach/mfp.h> +#define MFP_DRIVE_VERY_SLOW (0x0 << 13) +#define MFP_DRIVE_SLOW (0x2 << 13) +#define MFP_DRIVE_MEDIUM (0x4 << 13) +#define MFP_DRIVE_FAST (0x8 << 13) + /* UART2 */ #define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) #define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6) diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-mmp/include/mach/mfp.h index 277ea4cd0f9..62e510e80a5 100644 --- a/arch/arm/mach-mmp/include/mach/mfp.h +++ b/arch/arm/mach-mmp/include/mach/mfp.h @@ -12,16 +12,13 @@ * possible, we make the following compromise: * * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT) - * 2. DRIVE strength definitions redefined to include the reserved bit10 + * 2. DRIVE strength definitions redefined to include the reserved bit + * - the reserved bit differs between pxa168 and pxa910, and the + * MFP_DRIVE_* macros are individually defined in mfp-pxa{168,910}.h * 3. Override MFP_CFG() and MFP_CFG_DRV() * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X() */ -#define MFP_DRIVE_VERY_SLOW (0x0 << 13) -#define MFP_DRIVE_SLOW (0x2 << 13) -#define MFP_DRIVE_MEDIUM (0x4 << 13) -#define MFP_DRIVE_FAST (0x8 << 13) - #undef MFP_CFG #undef MFP_CFG_DRV #undef MFP_CFG_LPM diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index b03a6eda741..a8400bb891e 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -136,7 +136,7 @@ static struct clock_event_device ckevt = { .set_mode = timer_set_mode, }; -static cycle_t clksrc_read(void) +static cycle_t clksrc_read(struct clocksource *cs) { return timer_read(); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 9ba595083da..1b22e4af879 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -321,6 +321,9 @@ static struct platform_device mv78xx0_ge00 = { .id = 0, .num_resources = 1, .resource = mv78xx0_ge00_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, }; void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) @@ -375,6 +378,9 @@ static struct platform_device mv78xx0_ge01 = { .id = 1, .num_resources = 1, .resource = mv78xx0_ge01_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, }; void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) @@ -429,6 +435,9 @@ static struct platform_device mv78xx0_ge10 = { .id = 2, .num_resources = 1, .resource = mv78xx0_ge10_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, }; void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) @@ -496,6 +505,9 @@ static struct platform_device mv78xx0_ge11 = { .id = 3, .num_resources = 1, .resource = mv78xx0_ge11_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, }; void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) @@ -532,12 +544,10 @@ static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = { static struct resource mv78xx0_i2c_0_resources[] = { { - .name = "i2c 0 base", .start = I2C_0_PHYS_BASE, .end = I2C_0_PHYS_BASE + 0x1f, .flags = IORESOURCE_MEM, }, { - .name = "i2c 0 irq", .start = IRQ_MV78XX0_I2C_0, .end = IRQ_MV78XX0_I2C_0, .flags = IORESOURCE_IRQ, @@ -567,12 +577,10 @@ static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = { static struct resource mv78xx0_i2c_1_resources[] = { { - .name = "i2c 1 base", .start = I2C_1_PHYS_BASE, .end = I2C_1_PHYS_BASE + 0x1f, .flags = IORESOURCE_MEM, }, { - .name = "i2c 1 irq", .start = IRQ_MV78XX0_I2C_1, .end = IRQ_MV78XX0_I2C_1, .flags = IORESOURCE_IRQ, diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index f289b0ea7dc..22b4ff893b3 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -28,6 +28,9 @@ void __init mv78xx0_init_irq(void) { int i; + /* Initialize gpiolib. */ + orion_gpio_init(); + orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index c14d1213727..6f3f77d031d 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -14,6 +14,7 @@ #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> +#include <linux/errno.h> #include <mach/hardware.h> #include "common.h" @@ -44,6 +45,7 @@ #define TARGET_DEV_BUS 1 #define TARGET_PCI 3 #define TARGET_PCIE 4 +#define TARGET_SRAM 9 #define ATTR_PCIE_MEM 0x59 #define ATTR_PCIE_IO 0x51 #define ATTR_PCIE_WA 0x79 @@ -53,6 +55,7 @@ #define ATTR_DEV_CS1 0x1d #define ATTR_DEV_CS2 0x1b #define ATTR_DEV_BOOT 0xf +#define ATTR_SRAM 0x0 /* * Helpers to get DDR bank info @@ -87,13 +90,13 @@ static int __init orion5x_cpu_win_can_remap(int win) return 0; } -static void __init setup_cpu_win(int win, u32 base, u32 size, +static int __init setup_cpu_win(int win, u32 base, u32 size, u8 target, u8 attr, int remap) { if (win >= 8) { printk(KERN_ERR "setup_cpu_win: trying to allocate " "window %d\n", win); - return; + return -ENOSPC; } writel(base & 0xffff0000, CPU_WIN_BASE(win)); @@ -107,6 +110,7 @@ static void __init setup_cpu_win(int win, u32 base, u32 size, writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); writel(0, CPU_WIN_REMAP_HI(win)); } + return 0; } void __init orion5x_setup_cpu_mbus_bridge(void) @@ -193,3 +197,9 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) setup_cpu_win(win_alloc_count++, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); } + +int __init orion5x_setup_sram_win(void) +{ + return setup_cpu_win(win_alloc_count, ORION5X_SRAM_PHYS_BASE, + ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); +} diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 6af99ddabdf..eafcc49009e 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -31,7 +31,7 @@ #include <plat/ehci-orion.h> #include <plat/mv_xor.h> #include <plat/orion_nand.h> -#include <plat/orion5x_wdt.h> +#include <plat/orion_wdt.h> #include <plat/time.h> #include "common.h" @@ -188,6 +188,9 @@ static struct platform_device orion5x_eth = { .id = 0, .num_resources = 1, .resource = orion5x_eth_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, }; void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) @@ -248,12 +251,10 @@ static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { static struct resource orion5x_i2c_resources[] = { { - .name = "i2c base", .start = I2C_PHYS_BASE, .end = I2C_PHYS_BASE + 0x1f, .flags = IORESOURCE_MEM, }, { - .name = "i2c irq", .start = IRQ_ORION5X_I2C, .end = IRQ_ORION5X_I2C, .flags = IORESOURCE_IRQ, @@ -535,16 +536,52 @@ void __init orion5x_xor_init(void) platform_device_register(&orion5x_xor1_channel); } +static struct resource orion5x_crypto_res[] = { + { + .name = "regs", + .start = ORION5X_CRYPTO_PHYS_BASE, + .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff, + .flags = IORESOURCE_MEM, + }, { + .name = "sram", + .start = ORION5X_SRAM_PHYS_BASE, + .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "crypto interrupt", + .start = IRQ_ORION5X_CESA, + .end = IRQ_ORION5X_CESA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion5x_crypto_device = { + .name = "mv_crypto", + .id = -1, + .num_resources = ARRAY_SIZE(orion5x_crypto_res), + .resource = orion5x_crypto_res, +}; + +int __init orion5x_crypto_init(void) +{ + int ret; + + ret = orion5x_setup_sram_win(); + if (ret) + return ret; + + return platform_device_register(&orion5x_crypto_device); +} /***************************************************************************** * Watchdog ****************************************************************************/ -static struct orion5x_wdt_platform_data orion5x_wdt_data = { +static struct orion_wdt_platform_data orion5x_wdt_data = { .tclk = 0, }; static struct platform_device orion5x_wdt_device = { - .name = "orion5x_wdt", + .name = "orion_wdt", .id = -1, .dev = { .platform_data = &orion5x_wdt_data, diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index 798b9a5e3da..de483e83edd 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -26,6 +26,7 @@ void orion5x_setup_dev0_win(u32 base, u32 size); void orion5x_setup_dev1_win(u32 base, u32 size); void orion5x_setup_dev2_win(u32 base, u32 size); void orion5x_setup_pcie_wa_win(u32 base, u32 size); +int orion5x_setup_sram_win(void); void orion5x_ehci0_init(void); void orion5x_ehci1_init(void); @@ -37,6 +38,7 @@ void orion5x_spi_init(void); void orion5x_uart0_init(void); void orion5x_uart1_init(void); void orion5x_xor_init(void); +int orion5x_crypto_init(void); /* * PCIe/PCI functions. diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h index be896e59d3e..5c9744cd8ef 100644 --- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h @@ -17,8 +17,8 @@ #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104) -#define CPU_RESET_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) -#define WDT_RESET 0x0002 +#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) +#define WDT_RESET_OUT_EN 0x0002 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 377a773ae53..2d876657053 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -24,6 +24,7 @@ * f1000000 on-chip peripheral registers * f2000000 PCIe I/O space * f2100000 PCI I/O space + * f2200000 SRAM dedicated for the crypto unit * f4000000 device bus mappings (boot) * fa000000 device bus mappings (cs0) * fa800000 device bus mappings (cs2) @@ -49,6 +50,9 @@ #define ORION5X_PCI_IO_BUS_BASE 0x00100000 #define ORION5X_PCI_IO_SIZE SZ_1M +#define ORION5X_SRAM_PHYS_BASE (0xf2200000) +#define ORION5X_SRAM_SIZE SZ_8K + /* Relevant only for Orion-1/Orion-NAS */ #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 #define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 @@ -94,6 +98,8 @@ #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) +#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x90000) + #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h index e912490fff2..60e734c1045 100644 --- a/arch/arm/mach-orion5x/include/mach/system.h +++ b/arch/arm/mach-orion5x/include/mach/system.h @@ -23,7 +23,7 @@ static inline void arch_reset(char mode, const char *cmd) /* * Enable and issue soft reset */ - orion5x_setbits(CPU_RESET_MASK, (1 << 2)); + orion5x_setbits(RSTOUTn_MASK, (1 << 2)); orion5x_setbits(CPU_SOFT_RESET, 1); } diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index e23a3f91d6c..bc4c3b9aaf8 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -124,6 +124,9 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode) u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL); u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL); + /* Initialize gpiolib. */ + orion_gpio_init(); + while (mode->mpp >= 0) { u32 *reg; int num_type; diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index 41e6d5033d5..61c086b6672 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c @@ -181,9 +181,9 @@ static void mss2_power_off(void) /* * Enable and issue soft reset */ - reg = readl(CPU_RESET_MASK); + reg = readl(RSTOUTn_MASK); reg |= 1 << 2; - writel(reg, CPU_RESET_MASK); + writel(reg, RSTOUTn_MASK); reg = readl(CPU_SOFT_RESET); reg |= 1; diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h index 0f9cdf45895..37b3d487529 100644 --- a/arch/arm/mach-orion5x/ts78xx-fpga.h +++ b/arch/arm/mach-orion5x/ts78xx-fpga.h @@ -25,6 +25,7 @@ struct fpga_devices { /* Technologic Systems */ struct fpga_device ts_rtc; struct fpga_device ts_nand; + struct fpga_device ts_rng; }; struct ts78xx_fpga_data { diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index 9a6b397f972..5041d1bc26b 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -17,6 +17,7 @@ #include <linux/m48t86.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> +#include <linux/timeriomem-rng.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -270,12 +271,57 @@ static void ts78xx_ts_nand_unload(void) } /***************************************************************************** + * HW RNG + ****************************************************************************/ +#define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044) + +static struct resource ts78xx_ts_rng_resource = { + .flags = IORESOURCE_MEM, + .start = TS_RNG_DATA, + .end = TS_RNG_DATA + 4 - 1, +}; + +static struct timeriomem_rng_data ts78xx_ts_rng_data = { + .period = 1000000, /* one second */ +}; + +static struct platform_device ts78xx_ts_rng_device = { + .name = "timeriomem_rng", + .id = -1, + .dev = { + .platform_data = &ts78xx_ts_rng_data, + }, + .resource = &ts78xx_ts_rng_resource, + .num_resources = 1, +}; + +static int ts78xx_ts_rng_load(void) +{ + int rc; + + if (ts78xx_fpga.supports.ts_rng.init == 0) { + rc = platform_device_register(&ts78xx_ts_rng_device); + if (!rc) + ts78xx_fpga.supports.ts_rng.init = 1; + } else + rc = platform_device_add(&ts78xx_ts_rng_device); + + return rc; +}; + +static void ts78xx_ts_rng_unload(void) +{ + platform_device_del(&ts78xx_ts_rng_device); +} + +/***************************************************************************** * FPGA 'hotplug' support code ****************************************************************************/ static void ts78xx_fpga_devices_zero_init(void) { ts78xx_fpga.supports.ts_rtc.init = 0; ts78xx_fpga.supports.ts_nand.init = 0; + ts78xx_fpga.supports.ts_rng.init = 0; } static void ts78xx_fpga_supports(void) @@ -289,10 +335,12 @@ static void ts78xx_fpga_supports(void) case TS7800_REV_5: ts78xx_fpga.supports.ts_rtc.present = 1; ts78xx_fpga.supports.ts_nand.present = 1; + ts78xx_fpga.supports.ts_rng.present = 1; break; default: ts78xx_fpga.supports.ts_rtc.present = 0; ts78xx_fpga.supports.ts_nand.present = 0; + ts78xx_fpga.supports.ts_rng.present = 0; } } @@ -316,6 +364,14 @@ static int ts78xx_fpga_load_devices(void) } ret |= tmp; } + if (ts78xx_fpga.supports.ts_rng.present == 1) { + tmp = ts78xx_ts_rng_load(); + if (tmp) { + printk(KERN_INFO "TS-78xx: RNG not registered\n"); + ts78xx_fpga.supports.ts_rng.present = 0; + } + ret |= tmp; + } return ret; } @@ -328,6 +384,8 @@ static int ts78xx_fpga_unload_devices(void) ts78xx_ts_rtc_unload(); if (ts78xx_fpga.supports.ts_nand.present == 1) ts78xx_ts_nand_unload(); + if (ts78xx_fpga.supports.ts_rng.present == 1) + ts78xx_ts_rng_unload(); return ret; } diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 7ddc22c2bb5..69208217b22 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -15,6 +15,7 @@ #include <linux/mtd/physmap.h> #include <linux/mv643xx_eth.h> #include <linux/ethtool.h> +#include <net/dsa.h> #include <asm/mach-types.h> #include <asm/gpio.h> #include <asm/mach/arch.h> @@ -97,6 +98,20 @@ static struct mv643xx_eth_platform_data wnr854t_eth_data = { .duplex = DUPLEX_FULL, }; +static struct dsa_chip_data wnr854t_switch_chip_data = { + .port_names[0] = "lan3", + .port_names[1] = "lan4", + .port_names[2] = "wan", + .port_names[3] = "cpu", + .port_names[5] = "lan1", + .port_names[7] = "lan2", +}; + +static struct dsa_platform_data wnr854t_switch_plat_data = { + .nr_chips = 1, + .chip = &wnr854t_switch_chip_data, +}; + static void __init wnr854t_init(void) { /* @@ -110,6 +125,7 @@ static void __init wnr854t_init(void) * Configure peripherals. */ orion5x_eth_init(&wnr854t_eth_data); + orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ); orion5x_uart0_init(); orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE, diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 92ba16e1b6f..7db966dc29c 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -111,9 +111,9 @@ static unsigned long ezx_pin_config[] __initdata = { GPIO25_SSP1_TXD, GPIO26_SSP1_RXD, GPIO24_GPIO, /* pcap chip select */ - GPIO1_GPIO, /* pcap interrupt */ - GPIO4_GPIO, /* WDI_AP */ - GPIO55_GPIO, /* SYS_RESTART */ + GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, /* pcap interrupt */ + GPIO4_GPIO | MFP_LPM_DRIVE_HIGH, /* WDI_AP */ + GPIO55_GPIO | MFP_LPM_DRIVE_HIGH, /* SYS_RESTART */ /* MMC */ GPIO32_MMC_CLK, @@ -144,20 +144,20 @@ static unsigned long ezx_pin_config[] __initdata = { #if defined(CONFIG_MACH_EZX_A780) || defined(CONFIG_MACH_EZX_E680) static unsigned long gen1_pin_config[] __initdata = { /* flip / lockswitch */ - GPIO12_GPIO, + GPIO12_GPIO | WAKEUP_ON_EDGE_BOTH, /* bluetooth (bcm2035) */ - GPIO14_GPIO | WAKEUP_ON_LEVEL_HIGH, /* HOSTWAKE */ + GPIO14_GPIO | WAKEUP_ON_EDGE_RISE, /* HOSTWAKE */ GPIO48_GPIO, /* RESET */ GPIO28_GPIO, /* WAKEUP */ /* Neptune handshake */ - GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* BP_RDY */ - GPIO57_GPIO, /* AP_RDY */ - GPIO13_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI */ - GPIO3_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI2 */ - GPIO82_GPIO, /* RESET */ - GPIO99_GPIO, /* TC_MM_EN */ + GPIO0_GPIO | WAKEUP_ON_EDGE_FALL, /* BP_RDY */ + GPIO57_GPIO | MFP_LPM_DRIVE_HIGH, /* AP_RDY */ + GPIO13_GPIO | WAKEUP_ON_EDGE_BOTH, /* WDI */ + GPIO3_GPIO | WAKEUP_ON_EDGE_BOTH, /* WDI2 */ + GPIO82_GPIO | MFP_LPM_DRIVE_HIGH, /* RESET */ + GPIO99_GPIO | MFP_LPM_DRIVE_HIGH, /* TC_MM_EN */ /* sound */ GPIO52_SSP3_SCLK, @@ -199,21 +199,21 @@ static unsigned long gen1_pin_config[] __initdata = { defined(CONFIG_MACH_EZX_E2) || defined(CONFIG_MACH_EZX_E6) static unsigned long gen2_pin_config[] __initdata = { /* flip / lockswitch */ - GPIO15_GPIO, + GPIO15_GPIO | WAKEUP_ON_EDGE_BOTH, /* EOC */ - GPIO10_GPIO, + GPIO10_GPIO | WAKEUP_ON_EDGE_RISE, /* bluetooth (bcm2045) */ - GPIO13_GPIO | WAKEUP_ON_LEVEL_HIGH, /* HOSTWAKE */ + GPIO13_GPIO | WAKEUP_ON_EDGE_RISE, /* HOSTWAKE */ GPIO37_GPIO, /* RESET */ GPIO57_GPIO, /* WAKEUP */ /* Neptune handshake */ - GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* BP_RDY */ - GPIO96_GPIO, /* AP_RDY */ - GPIO3_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI */ - GPIO116_GPIO, /* RESET */ + GPIO0_GPIO | WAKEUP_ON_EDGE_FALL, /* BP_RDY */ + GPIO96_GPIO | MFP_LPM_DRIVE_HIGH, /* AP_RDY */ + GPIO3_GPIO | WAKEUP_ON_EDGE_FALL, /* WDI */ + GPIO116_GPIO | MFP_LPM_DRIVE_HIGH, /* RESET */ GPIO41_GPIO, /* BP_FLASH */ /* sound */ diff --git a/arch/arm/mach-pxa/include/mach/reset.h b/arch/arm/mach-pxa/include/mach/reset.h index 31e6a7b6ad8..b6c10556fbc 100644 --- a/arch/arm/mach-pxa/include/mach/reset.h +++ b/arch/arm/mach-pxa/include/mach/reset.h @@ -13,8 +13,9 @@ extern void clear_reset_status(unsigned int mask); /** * init_gpio_reset() - register GPIO as reset generator * @gpio: gpio nr - * @output: set gpio as out/low instead of input during normal work + * @output: set gpio as output instead of input during normal work + * @level: output level */ -extern int init_gpio_reset(int gpio, int output); +extern int init_gpio_reset(int gpio, int output, int level); #endif /* __ASM_ARCH_RESET_H */ diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 7ffb91d64c3..cf6b720c055 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -322,6 +322,7 @@ static inline void pxa27x_mfp_init(void) {} #ifdef CONFIG_PM static unsigned long saved_gafr[2][4]; static unsigned long saved_gpdr[4]; +static unsigned long saved_pgsr[4]; static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) { @@ -332,6 +333,7 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) saved_gafr[0][i] = GAFR_L(i); saved_gafr[1][i] = GAFR_U(i); saved_gpdr[i] = GPDR(i * 32); + saved_pgsr[i] = PGSR(i); GPDR(i * 32) = gpdr_lpm[i]; } @@ -346,6 +348,7 @@ static int pxa2xx_mfp_resume(struct sys_device *d) GAFR_L(i) = saved_gafr[0][i]; GAFR_U(i) = saved_gafr[1][i]; GPDR(i * 32) = saved_gpdr[i]; + PGSR(i) = saved_pgsr[i]; } PSSR = PSSR_RDH | PSSR_PH; return 0; @@ -374,6 +377,9 @@ static int __init pxa2xx_mfp_init(void) if (cpu_is_pxa27x()) pxa27x_mfp_init(); + /* clear RDH bit to enable GPIO receivers after reset/sleep exit */ + PSSR = PSSR_RDH; + /* initialize gafr_run[], pgsr_lpm[] from existing values */ for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) gpdr_lpm[i] = GPDR(i * 32); diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index 24a967e1e14..2e65f05d366 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -62,6 +62,8 @@ static unsigned long palmld_pin_config[] __initdata = { GPIO29_AC97_SDATA_IN_0, GPIO30_AC97_SDATA_OUT, GPIO31_AC97_SYNC, + GPIO89_AC97_SYSCLK, + GPIO95_AC97_nRESET, /* IrDA */ GPIO108_GPIO, /* ir disable */ diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 30662363907..05bf979b78a 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -64,6 +64,7 @@ static unsigned long palmt5_pin_config[] __initdata = { GPIO29_AC97_SDATA_IN_0, GPIO30_AC97_SDATA_OUT, GPIO31_AC97_SYNC, + GPIO89_AC97_SYSCLK, GPIO95_AC97_nRESET, /* IrDA */ diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index e2d44b1a8a9..e99a893c58a 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -65,6 +65,7 @@ static unsigned long palmtx_pin_config[] __initdata = { GPIO29_AC97_SDATA_IN_0, GPIO30_AC97_SDATA_OUT, GPIO31_AC97_SYNC, + GPIO89_AC97_SYSCLK, GPIO95_AC97_nRESET, /* IrDA */ diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c index df29d45fb4e..01e9d643394 100644 --- a/arch/arm/mach-pxa/reset.c +++ b/arch/arm/mach-pxa/reset.c @@ -20,7 +20,7 @@ static void do_hw_reset(void); static int reset_gpio = -1; -int init_gpio_reset(int gpio, int output) +int init_gpio_reset(int gpio, int output, int level) { int rc; @@ -31,7 +31,7 @@ int init_gpio_reset(int gpio, int output) } if (output) - rc = gpio_direction_output(gpio, 0); + rc = gpio_direction_output(gpio, level); else rc = gpio_direction_input(gpio); if (rc) { diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index c18e34acafc..5a45fe340a1 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -531,9 +531,15 @@ static int spitz_ohci_init(struct device *dev) return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1); } +static void spitz_ohci_exit(struct device *dev) +{ + gpio_free(SPITZ_GPIO_USB_HOST); +} + static struct pxaohci_platform_data spitz_ohci_platform_data = { .port_mode = PMM_NPS_MODE, .init = spitz_ohci_init, + .exit = spitz_ohci_exit, .flags = ENABLE_PORT_ALL | NO_OC_PROTECTION, .power_budget = 150, }; @@ -731,7 +737,7 @@ static void spitz_restart(char mode, const char *cmd) static void __init common_init(void) { - init_gpio_reset(SPITZ_GPIO_ON_RESET, 1); + init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0); pm_power_off = spitz_poweroff; arm_pm_restart = spitz_restart; diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index afac5b6d3d7..a0bd46ef5d3 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -897,7 +897,7 @@ static void __init tosa_init(void) gpio_set_wake(MFP_PIN_GPIO1, 1); /* We can't pass to gpio-keys since it will drop the Reset altfunc */ - init_gpio_reset(TOSA_GPIO_ON_RESET, 0); + init_gpio_reset(TOSA_GPIO_ON_RESET, 0, 0); pm_power_off = tosa_poweroff; arm_pm_restart = tosa_restart; diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 32eb9e33beb..e814803d474 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -15,10 +15,9 @@ #include <linux/spinlock.h> #include <linux/bitops.h> #include <linux/io.h> -#include <asm/gpio.h> +#include <linux/gpio.h> static DEFINE_SPINLOCK(gpio_lock); -static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)]; static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)]; @@ -46,82 +45,54 @@ static void __set_level(unsigned pin, int high) writel(u, GPIO_OUT(pin)); } - -/* - * GENERIC_GPIO primitives. - */ -int gpio_direction_input(unsigned pin) +static inline void __set_blinking(unsigned pin, int blink) { - unsigned long flags; - - if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_input)) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); - return -EINVAL; - } - - spin_lock_irqsave(&gpio_lock, flags); - - /* - * Some callers might not have used gpio_request(), - * so flag this pin as requested now. - */ - if (gpio_label[pin] == NULL) - gpio_label[pin] = "?"; + u32 u; - /* - * Configure GPIO direction. - */ - __set_direction(pin, 1); + u = readl(GPIO_BLINK_EN(pin)); + if (blink) + u |= 1 << (pin & 31); + else + u &= ~(1 << (pin & 31)); + writel(u, GPIO_BLINK_EN(pin)); +} - spin_unlock_irqrestore(&gpio_lock, flags); +static inline int orion_gpio_is_valid(unsigned pin, int mode) +{ + if (pin < GPIO_MAX) { + if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input)) + goto err_out; + if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output)) + goto err_out; + return true; + } - return 0; +err_out: + pr_debug("%s: invalid GPIO %d\n", __func__, pin); + return false; } -EXPORT_SYMBOL(gpio_direction_input); -int gpio_direction_output(unsigned pin, int value) +/* + * GENERIC_GPIO primitives. + */ +static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin) { unsigned long flags; - u32 u; - if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_output)) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); + if (!orion_gpio_is_valid(pin, GPIO_INPUT_OK)) return -EINVAL; - } spin_lock_irqsave(&gpio_lock, flags); - /* - * Some callers might not have used gpio_request(), - * so flag this pin as requested now. - */ - if (gpio_label[pin] == NULL) - gpio_label[pin] = "?"; - - /* - * Disable blinking. - */ - u = readl(GPIO_BLINK_EN(pin)); - u &= ~(1 << (pin & 31)); - writel(u, GPIO_BLINK_EN(pin)); - - /* - * Configure GPIO output value. - */ - __set_level(pin, value); - - /* - * Configure GPIO direction. - */ - __set_direction(pin, 0); + /* Configure GPIO direction. */ + __set_direction(pin, 1); spin_unlock_irqrestore(&gpio_lock, flags); return 0; } -EXPORT_SYMBOL(gpio_direction_output); -int gpio_get_value(unsigned pin) +static int orion_gpio_get_value(struct gpio_chip *chip, unsigned pin) { int val; @@ -132,83 +103,75 @@ int gpio_get_value(unsigned pin) return (val >> (pin & 31)) & 1; } -EXPORT_SYMBOL(gpio_get_value); -void gpio_set_value(unsigned pin, int value) +static int orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, + int value) { unsigned long flags; - u32 u; + + if (!orion_gpio_is_valid(pin, GPIO_OUTPUT_OK)) + return -EINVAL; spin_lock_irqsave(&gpio_lock, flags); - /* - * Disable blinking. - */ - u = readl(GPIO_BLINK_EN(pin)); - u &= ~(1 << (pin & 31)); - writel(u, GPIO_BLINK_EN(pin)); + /* Disable blinking. */ + __set_blinking(pin, 0); - /* - * Configure GPIO output value. - */ + /* Configure GPIO output value. */ __set_level(pin, value); + /* Configure GPIO direction. */ + __set_direction(pin, 0); + spin_unlock_irqrestore(&gpio_lock, flags); + + return 0; } -EXPORT_SYMBOL(gpio_set_value); -int gpio_request(unsigned pin, const char *label) +static void orion_gpio_set_value(struct gpio_chip *chip, unsigned pin, + int value) { unsigned long flags; - int ret; - - if (pin >= GPIO_MAX || - !(test_bit(pin, gpio_valid_input) || - test_bit(pin, gpio_valid_output))) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); - return -EINVAL; - } spin_lock_irqsave(&gpio_lock, flags); - if (gpio_label[pin] == NULL) { - gpio_label[pin] = label ? label : "?"; - ret = 0; - } else { - pr_debug("%s: GPIO %d already used as %s\n", - __func__, pin, gpio_label[pin]); - ret = -EBUSY; - } - spin_unlock_irqrestore(&gpio_lock, flags); - return ret; + /* Configure GPIO output value. */ + __set_level(pin, value); + + spin_unlock_irqrestore(&gpio_lock, flags); } -EXPORT_SYMBOL(gpio_request); -void gpio_free(unsigned pin) +static int orion_gpio_request(struct gpio_chip *chip, unsigned pin) { - if (pin >= GPIO_MAX || - !(test_bit(pin, gpio_valid_input) || - test_bit(pin, gpio_valid_output))) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); - return; - } - - if (gpio_label[pin] == NULL) - pr_warning("%s: GPIO %d already freed\n", __func__, pin); - else - gpio_label[pin] = NULL; + if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) || + orion_gpio_is_valid(pin, GPIO_OUTPUT_OK)) + return 0; + return -EINVAL; } -EXPORT_SYMBOL(gpio_free); +static struct gpio_chip orion_gpiochip = { + .label = "orion_gpio", + .direction_input = orion_gpio_direction_input, + .get = orion_gpio_get_value, + .direction_output = orion_gpio_direction_output, + .set = orion_gpio_set_value, + .request = orion_gpio_request, + .base = 0, + .ngpio = GPIO_MAX, + .can_sleep = 0, +}; + +void __init orion_gpio_init(void) +{ + gpiochip_add(&orion_gpiochip); +} /* * Orion-specific GPIO API extensions. */ void __init orion_gpio_set_unused(unsigned pin) { - /* - * Configure as output, drive low. - */ + /* Configure as output, drive low. */ __set_level(pin, 0); __set_direction(pin, 0); } @@ -230,21 +193,14 @@ void __init orion_gpio_set_valid(unsigned pin, int mode) void orion_gpio_set_blink(unsigned pin, int blink) { unsigned long flags; - u32 u; spin_lock_irqsave(&gpio_lock, flags); - /* - * Set output value to zero. - */ + /* Set output value to zero. */ __set_level(pin, 0); - u = readl(GPIO_BLINK_EN(pin)); - if (blink) - u |= 1 << (pin & 31); - else - u &= ~(1 << (pin & 31)); - writel(u, GPIO_BLINK_EN(pin)); + /* Set blinking. */ + __set_blinking(pin, blink); spin_unlock_irqrestore(&gpio_lock, flags); } @@ -368,7 +324,7 @@ static int gpio_irq_set_type(u32 irq, u32 type) } struct irq_chip orion_gpio_irq_chip = { - .name = "orion_gpio", + .name = "orion_gpio_irq", .ack = gpio_irq_ack, .mask = gpio_irq_mask, .unmask = gpio_irq_unmask, diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h index 33f6c6aec18..9646a94ed3d 100644 --- a/arch/arm/plat-orion/include/plat/gpio.h +++ b/arch/arm/plat-orion/include/plat/gpio.h @@ -14,12 +14,9 @@ /* * GENERIC_GPIO primitives. */ -int gpio_request(unsigned pin, const char *label); -void gpio_free(unsigned pin); -int gpio_direction_input(unsigned pin); -int gpio_direction_output(unsigned pin, int value); -int gpio_get_value(unsigned pin); -void gpio_set_value(unsigned pin, int value); +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep /* * Orion-specific GPIO API extensions. @@ -27,11 +24,13 @@ void gpio_set_value(unsigned pin, int value); void orion_gpio_set_unused(unsigned pin); void orion_gpio_set_blink(unsigned pin, int blink); -#define GPIO_BIDI_OK (1 << 0) -#define GPIO_INPUT_OK (1 << 1) -#define GPIO_OUTPUT_OK (1 << 2) +#define GPIO_INPUT_OK (1 << 0) +#define GPIO_OUTPUT_OK (1 << 1) void orion_gpio_set_valid(unsigned pin, int mode); +/* Initialize gpiolib. */ +void __init orion_gpio_init(void); + /* * GPIO interrupt handling. */ diff --git a/arch/arm/plat-orion/include/plat/orion5x_wdt.h b/arch/arm/plat-orion/include/plat/orion_wdt.h index 3c9cf6a305e..665c362a2fb 100644 --- a/arch/arm/plat-orion/include/plat/orion5x_wdt.h +++ b/arch/arm/plat-orion/include/plat/orion_wdt.h @@ -1,15 +1,15 @@ /* - * arch/arm/plat-orion/include/plat/orion5x_wdt.h + * arch/arm/plat-orion/include/plat/orion_wdt.h * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#ifndef __PLAT_ORION5X_WDT_H -#define __PLAT_ORION5X_WDT_H +#ifndef __PLAT_ORION_WDT_H +#define __PLAT_ORION_WDT_H -struct orion5x_wdt_platform_data { +struct orion_wdt_platform_data { u32 tclk; /* no <linux/clk.h> support yet */ }; diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index de8a001fc3a..715a30177f2 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -12,11 +12,15 @@ */ #include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/cnt32_to_63.h> +#include <linux/timer.h> #include <linux/clockchips.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <asm/mach/time.h> #include <mach/bridge-regs.h> +#include <mach/hardware.h> /* * Number of timer ticks per jiffy. @@ -39,6 +43,56 @@ static u32 ticks_per_jiffy; /* + * Orion's sched_clock implementation. It has a resolution of + * at least 7.5ns (133MHz TCLK) and a maximum value of 834 days. + * + * Because the hardware timer period is quite short (21 secs if + * 200MHz TCLK) and because cnt32_to_63() needs to be called at + * least once per half period to work properly, a kernel timer is + * set up to ensure this requirement is always met. + */ +#define TCLK2NS_SCALE_FACTOR 8 + +static unsigned long tclk2ns_scale; + +unsigned long long sched_clock(void) +{ + unsigned long long v = cnt32_to_63(0xffffffff - readl(TIMER0_VAL)); + return (v * tclk2ns_scale) >> TCLK2NS_SCALE_FACTOR; +} + +static struct timer_list cnt32_to_63_keepwarm_timer; + +static void cnt32_to_63_keepwarm(unsigned long data) +{ + mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); + (void) sched_clock(); +} + +static void __init setup_sched_clock(unsigned long tclk) +{ + unsigned long long v; + unsigned long data; + + v = NSEC_PER_SEC; + v <<= TCLK2NS_SCALE_FACTOR; + v += tclk/2; + do_div(v, tclk); + /* + * We want an even value to automatically clear the top bit + * returned by cnt32_to_63() without an additional run time + * instruction. So if the LSB is 1 then round it up. + */ + if (v & 1) + v++; + tclk2ns_scale = v; + + data = (0xffffffffUL / tclk / 2 - 2) * HZ; + setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data); + mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); +} + +/* * Clocksource handling. */ static cycle_t orion_clksrc_read(struct clocksource *cs) @@ -176,6 +230,10 @@ void __init orion_time_init(unsigned int irq, unsigned int tclk) ticks_per_jiffy = (tclk + HZ/2) / HZ; + /* + * Set scale and timer for sched_clock + */ + setup_sched_clock(tclk); /* * Setup free-running clocksource timer (interrupts @@ -190,7 +248,6 @@ void __init orion_time_init(unsigned int irq, unsigned int tclk) orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift); clocksource_register(&orion_clksrc); - /* * Setup clockevent timer (interrupt-driven.) */ diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 945e0d237a1..fec64678a63 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -12,7 +12,7 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Mon Mar 23 20:09:01 2009 +# Last update: Fri May 29 10:14:20 2009 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -916,7 +916,7 @@ nxdb500 MACH_NXDB500 NXDB500 905 apf9328 MACH_APF9328 APF9328 906 omap_wipoq MACH_OMAP_WIPOQ OMAP_WIPOQ 907 omap_twip MACH_OMAP_TWIP OMAP_TWIP 908 -palmt650 MACH_PALMT650 PALMT650 909 +treo650 MACH_TREO650 TREO650 909 acumen MACH_ACUMEN ACUMEN 910 xp100 MACH_XP100 XP100 911 fs2410 MACH_FS2410 FS2410 912 @@ -1232,7 +1232,7 @@ ql202b MACH_QL202B QL202B 1226 vpac270 MACH_VPAC270 VPAC270 1227 rd129 MACH_RD129 RD129 1228 htcwizard MACH_HTCWIZARD HTCWIZARD 1229 -xscale_treo680 MACH_XSCALE_TREO680 XSCALE_TREO680 1230 +treo680 MACH_TREO680 TREO680 1230 tecon_tmezon MACH_TECON_TMEZON TECON_TMEZON 1231 zylonite MACH_ZYLONITE ZYLONITE 1233 gene1270 MACH_GENE1270 GENE1270 1234 @@ -1418,10 +1418,10 @@ looxc550 MACH_LOOXC550 LOOXC550 1417 cnty_titan MACH_CNTY_TITAN CNTY_TITAN 1418 app3xx MACH_APP3XX APP3XX 1419 sideoatsgrama MACH_SIDEOATSGRAMA SIDEOATSGRAMA 1420 -palmtreo700p MACH_PALMTREO700P PALMTREO700P 1421 -palmtreo700w MACH_PALMTREO700W PALMTREO700W 1422 -palmtreo750 MACH_PALMTREO750 PALMTREO750 1423 -palmtreo755p MACH_PALMTREO755P PALMTREO755P 1424 +treo700p MACH_TREO700P TREO700P 1421 +treo700w MACH_TREO700W TREO700W 1422 +treo750 MACH_TREO750 TREO750 1423 +treo755p MACH_TREO755P TREO755P 1424 ezreganut9200 MACH_EZREGANUT9200 EZREGANUT9200 1425 sarge MACH_SARGE SARGE 1426 a696 MACH_A696 A696 1427 @@ -1721,7 +1721,7 @@ sapphire MACH_SAPPHIRE SAPPHIRE 1729 csb637xo MACH_CSB637XO CSB637XO 1730 evisiong MACH_EVISIONG EVISIONG 1731 stmp37xx MACH_STMP37XX STMP37XX 1732 -stmp378x MACH_STMP38XX STMP38XX 1733 +stmp378x MACH_STMP378X STMP378X 1733 tnt MACH_TNT TNT 1734 tbxt MACH_TBXT TBXT 1735 playmate MACH_PLAYMATE PLAYMATE 1736 @@ -1817,7 +1817,7 @@ smdkc100 MACH_SMDKC100 SMDKC100 1826 tavorevb MACH_TAVOREVB TAVOREVB 1827 saar MACH_SAAR SAAR 1828 deister_eyecam MACH_DEISTER_EYECAM DEISTER_EYECAM 1829 -at91sam9m10ek MACH_AT91SAM9M10EK AT91SAM9M10EK 1830 +at91sam9m10g45ek MACH_AT91SAM9M10G45EK AT91SAM9M10G45EK 1830 linkstation_produo MACH_LINKSTATION_PRODUO LINKSTATION_PRODUO 1831 hit_b0 MACH_HIT_B0 HIT_B0 1832 adx_rmu MACH_ADX_RMU ADX_RMU 1833 @@ -2132,3 +2132,116 @@ apollo MACH_APOLLO APOLLO 2141 at91cap9stk MACH_AT91CAP9STK AT91CAP9STK 2142 spc300 MACH_SPC300 SPC300 2143 eko MACH_EKO EKO 2144 +ccw9m2443 MACH_CCW9M2443 CCW9M2443 2145 +ccw9m2443js MACH_CCW9M2443JS CCW9M2443JS 2146 +m2m_router_device MACH_M2M_ROUTER_DEVICE M2M_ROUTER_DEVICE 2147 +str9104nas MACH_STAR9104NAS STAR9104NAS 2148 +pca100 MACH_PCA100 PCA100 2149 +z3_dm365_mod_01 MACH_Z3_DM365_MOD_01 Z3_DM365_MOD_01 2150 +hipox MACH_HIPOX HIPOX 2151 +omap3_piteds MACH_OMAP3_PITEDS OMAP3_PITEDS 2152 +bm150r MACH_BM150R BM150R 2153 +tbone MACH_TBONE TBONE 2154 +merlin MACH_MERLIN MERLIN 2155 +falcon MACH_FALCON FALCON 2156 +davinci_da850_evm MACH_DAVINCI_DA850_EVM DAVINCI_DA850_EVM 2157 +s5p6440 MACH_S5P6440 S5P6440 2158 +at91sam9g10ek MACH_AT91SAM9G10EK AT91SAM9G10EK 2159 +omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160 +lpc313x MACH_LPC313X LPC313X 2161 +magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162 +magx_em30 MACH_MAGX_EM30 MAGX_EM30 2163 +magx_ve66 MACH_MAGX_VE66 MAGX_VE66 2164 +meesc MACH_MEESC MEESC 2165 +otc570 MACH_OTC570 OTC570 2166 +bcu2412 MACH_BCU2412 BCU2412 2167 +beacon MACH_BEACON BEACON 2168 +actia_tgw MACH_ACTIA_TGW ACTIA_TGW 2169 +e4430 MACH_E4430 E4430 2170 +ql300 MACH_QL300 QL300 2171 +btmavb101 MACH_BTMAVB101 BTMAVB101 2172 +btmawb101 MACH_BTMAWB101 BTMAWB101 2173 +sq201 MACH_SQ201 SQ201 2174 +quatro45xx MACH_QUATRO45XX QUATRO45XX 2175 +openpad MACH_OPENPAD OPENPAD 2176 +tx25 MACH_TX25 TX25 2177 +omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178 +htcraphael_k MACH_HTCRAPHAEL_K HTCRAPHAEL_K 2179 +lal43 MACH_LAL43 LAL43 2181 +htcraphael_cdma500 MACH_HTCRAPHAEL_CDMA500 HTCRAPHAEL_CDMA500 2182 +anw6410 MACH_ANW6410 ANW6410 2183 +htcprophet MACH_HTCPROPHET HTCPROPHET 2185 +cfa_10022 MACH_CFA_10022 CFA_10022 2186 +imx27_visstrim_m10 MACH_IMX27_VISSTRIM_M10 IMX27_VISSTRIM_M10 2187 +px2imx27 MACH_PX2IMX27 PX2IMX27 2188 +stm3210e_eval MACH_STM3210E_EVAL STM3210E_EVAL 2189 +dvs10 MACH_DVS10 DVS10 2190 +portuxg20 MACH_PORTUXG20 PORTUXG20 2191 +arm_spv MACH_ARM_SPV ARM_SPV 2192 +smdkc110 MACH_SMDKC110 SMDKC110 2193 +cabespresso MACH_CABESPRESSO CABESPRESSO 2194 +hmc800 MACH_HMC800 HMC800 2195 +sholes MACH_SHOLES SHOLES 2196 +btmxc31 MACH_BTMXC31 BTMXC31 2197 +dt501 MACH_DT501 DT501 2198 +ktx MACH_KTX KTX 2199 +omap3517evm MACH_OMAP3517EVM OMAP3517EVM 2200 +netspace_v2 MACH_NETSPACE_V2 NETSPACE_V2 2201 +netspace_max_v2 MACH_NETSPACE_MAX_V2 NETSPACE_MAX_V2 2202 +d2net_v2 MACH_D2NET_V2 D2NET_V2 2203 +net2big_v2 MACH_NET2BIG_V2 NET2BIG_V2 2204 +net4big_v2 MACH_NET4BIG_V2 NET4BIG_V2 2205 +net5big_v2 MACH_NET5BIG_V2 NET5BIG_V2 2206 +endb2443 MACH_ENDB2443 ENDB2443 2207 +inetspace_v2 MACH_INETSPACE_V2 INETSPACE_V2 2208 +tros MACH_TROS TROS 2209 +pelco_homer MACH_PELCO_HOMER PELCO_HOMER 2210 +ofsp8 MACH_OFSP8 OFSP8 2211 +at91sam9g45ekes MACH_AT91SAM9G45EKES AT91SAM9G45EKES 2212 +guf_cupid MACH_GUF_CUPID GUF_CUPID 2213 +eab1r MACH_EAB1R EAB1R 2214 +desirec MACH_DESIREC DESIREC 2215 +cordoba MACH_CORDOBA CORDOBA 2216 +irvine MACH_IRVINE IRVINE 2217 +sff772 MACH_SFF772 SFF772 2218 +pelco_milano MACH_PELCO_MILANO PELCO_MILANO 2219 +pc7302 MACH_PC7302 PC7302 2220 +bip6000 MACH_BIP6000 BIP6000 2221 +silvermoon MACH_SILVERMOON SILVERMOON 2222 +vc0830 MACH_VC0830 VC0830 2223 +dt430 MACH_DT430 DT430 2224 +ji42pf MACH_JI42PF JI42PF 2225 +gnet_ksm MACH_GNET_KSM GNET_KSM 2226 +gnet_sgm MACH_GNET_SGM GNET_SGM 2227 +gnet_sgr MACH_GNET_SGR GNET_SGR 2228 +omap3_icetekevm MACH_OMAP3_ICETEKEVM OMAP3_ICETEKEVM 2229 +pnp MACH_PNP PNP 2230 +ctera_2bay_k MACH_CTERA_2BAY_K CTERA_2BAY_K 2231 +ctera_2bay_u MACH_CTERA_2BAY_U CTERA_2BAY_U 2232 +sas_c MACH_SAS_C SAS_C 2233 +vma2315 MACH_VMA2315 VMA2315 2234 +vcs MACH_VCS VCS 2235 +spear600 MACH_SPEAR600 SPEAR600 2236 +spear300 MACH_SPEAR300 SPEAR300 2237 +spear1300 MACH_SPEAR1300 SPEAR1300 2238 +lilly1131 MACH_LILLY1131 LILLY1131 2239 +arvoo_ax301 MACH_ARVOO_AX301 ARVOO_AX301 2240 +mapphone MACH_MAPPHONE MAPPHONE 2241 +legend MACH_LEGEND LEGEND 2242 +salsa MACH_SALSA SALSA 2243 +lounge MACH_LOUNGE LOUNGE 2244 +vision MACH_VISION VISION 2245 +vmb20 MACH_VMB20 VMB20 2246 +hy2410 MACH_HY2410 HY2410 2247 +hy9315 MACH_HY9315 HY9315 2248 +bullwinkle MACH_BULLWINKLE BULLWINKLE 2249 +arm_ultimator2 MACH_ARM_ULTIMATOR2 ARM_ULTIMATOR2 2250 +vs_v210 MACH_VS_V210 VS_V210 2252 +vs_v212 MACH_VS_V212 VS_V212 2253 +hmt MACH_HMT HMT 2254 +suen3 MACH_SUEN3 SUEN3 2255 +vesper MACH_VESPER VESPER 2256 +str9 MACH_STR9 STR9 2257 +omap3_wl_ff MACH_OMAP3_WL_FF OMAP3_WL_FF 2258 +simcom MACH_SIMCOM SIMCOM 2259 +mcwebio MACH_MCWEBIO MCWEBIO 2260 |