diff options
Diffstat (limited to 'arch/arm')
742 files changed, 50205 insertions, 11104 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 92622eb5cc0..2d70cece2ea 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -13,7 +13,7 @@ config ARM select RTC_LIB select SYS_SUPPORTS_APM_EMULATION select GENERIC_ATOMIC64 if (!CPU_32v6K) - select HAVE_OPROFILE + select HAVE_OPROFILE if (HAVE_PERF_EVENTS) select HAVE_ARCH_KGDB select HAVE_KPROBES if (!XIP_KERNEL) select HAVE_KRETPROBES if (HAVE_KPROBES) @@ -21,6 +21,7 @@ config ARM select HAVE_GENERIC_DMA_COHERENT select HAVE_KERNEL_GZIP select HAVE_KERNEL_LZO + select HAVE_KERNEL_LZMA select HAVE_PERF_EVENTS select PERF_USE_VMALLOC help @@ -42,6 +43,11 @@ config GENERIC_GPIO config GENERIC_TIME bool + default y + +config ARCH_USES_GETTIMEOFFSET + bool + default n config GENERIC_CLOCKEVENTS bool @@ -175,28 +181,6 @@ config ARM_L1_CACHE_SHIFT_6 help Setting ARM L1 cache line size to 64 Bytes. -if OPROFILE - -config OPROFILE_ARMV6 - def_bool y - depends on CPU_V6 && !SMP - select OPROFILE_ARM11_CORE - -config OPROFILE_MPCORE - def_bool y - depends on CPU_V6 && SMP - select OPROFILE_ARM11_CORE - -config OPROFILE_ARM11_CORE - bool - -config OPROFILE_ARMV7 - def_bool y - depends on CPU_V7 && !SMP - bool - -endif - config VECTORS_BASE hex default 0xffff0000 if MMU || CPU_HIGH_VECTOR @@ -231,6 +215,7 @@ config ARCH_AAEC2000 select CPU_ARM920T select ARM_AMBA select HAVE_CLK + select ARCH_USES_GETTIMEOFFSET help This enables support for systems based on the Agilent AAEC-2000 @@ -238,21 +223,22 @@ config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" select ARM_AMBA select ARCH_HAS_CPUFREQ - select HAVE_CLK select COMMON_CLKDEV - select ICST525 + select ICST + select GENERIC_CLOCKEVENTS + select PLAT_VERSATILE help Support for ARM's Integrator platform. config ARCH_REALVIEW bool "ARM Ltd. RealView family" select ARM_AMBA - select HAVE_CLK select COMMON_CLKDEV - select ICST307 - select GENERIC_TIME + select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB + select PLAT_VERSATILE + select ARM_TIMER_SP804 select GPIO_PL061 if GPIOLIB help This enables support for ARM Ltd RealView boards. @@ -261,20 +247,33 @@ config ARCH_VERSATILE bool "ARM Ltd. Versatile family" select ARM_AMBA select ARM_VIC - select HAVE_CLK select COMMON_CLKDEV - select ICST307 - select GENERIC_TIME + select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB + select PLAT_VERSATILE + select ARM_TIMER_SP804 help This enables support for ARM Ltd Versatile board. +config ARCH_VEXPRESS + bool "ARM Ltd. Versatile Express family" + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_AMBA + select ARM_TIMER_SP804 + select COMMON_CLKDEV + select GENERIC_CLOCKEVENTS + select HAVE_CLK + select ICST + select PLAT_VERSATILE + help + This enables support for the ARM Ltd Versatile Express boards. + config ARCH_AT91 bool "Atmel AT91" - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB select HAVE_CLK + select ARCH_USES_GETTIMEOFFSET help This enables support for systems based on the Atmel AT91RM9200, AT91SAM9 and AT91CAP9 processors. @@ -285,7 +284,6 @@ config ARCH_BCMRING select CPU_V6 select ARM_AMBA select COMMON_CLKDEV - select GENERIC_TIME select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB help @@ -294,14 +292,23 @@ config ARCH_BCMRING config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x-based" select CPU_ARM720T + select ARCH_USES_GETTIMEOFFSET help Support for Cirrus Logic 711x/721x based boards. +config ARCH_CNS3XXX + bool "Cavium Networks CNS3XXX family" + select CPU_V6 + select GENERIC_CLOCKEVENTS + select ARM_GIC + help + Support for Cavium Networks CNS3XXX platform. + config ARCH_GEMINI bool "Cortina Systems Gemini" select CPU_FA526 - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB + select ARCH_USES_GETTIMEOFFSET help Support for the Cortina Systems Gemini family SoCs @@ -310,6 +317,7 @@ config ARCH_EBSA110 select CPU_SA110 select ISA select NO_IOPORT + select ARCH_USES_GETTIMEOFFSET help This is an evaluation board for the StrongARM processor available from Digital. It has limited hardware on-board, including an @@ -321,11 +329,10 @@ config ARCH_EP93XX select CPU_ARM920T select ARM_AMBA select ARM_VIC - select GENERIC_GPIO - select HAVE_CLK select COMMON_CLKDEV select ARCH_REQUIRE_GPIOLIB select ARCH_HAS_HOLES_MEMORYMODEL + select ARCH_USES_GETTIMEOFFSET help This enables support for the Cirrus EP93xx series of CPUs. @@ -333,16 +340,15 @@ config ARCH_FOOTBRIDGE bool "FootBridge" select CPU_SA110 select FOOTBRIDGE + select ARCH_USES_GETTIMEOFFSET help Support for systems based on the DC21285 companion chip ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. config ARCH_MXC bool "Freescale MXC/iMX-based" - select GENERIC_TIME select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB - select HAVE_CLK select COMMON_CLKDEV help Support for Freescale MXC/iMX-based family of processors @@ -350,12 +356,9 @@ config ARCH_MXC config ARCH_STMP3XXX bool "Freescale STMP3xxx" select CPU_ARM926T - select HAVE_CLK select COMMON_CLKDEV select ARCH_REQUIRE_GPIOLIB - select GENERIC_TIME select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select USB_ARCH_HAS_EHCI help Support for systems based on the Freescale 3xxx CPUs. @@ -365,7 +368,6 @@ config ARCH_NETX select CPU_ARM926T select ARM_VIC select GENERIC_CLOCKEVENTS - select GENERIC_TIME help This enables support for systems based on the Hilscher NetX Soc @@ -373,6 +375,7 @@ config ARCH_H720X bool "Hynix HMS720x-based" select CPU_ARM720T select ISA_DMA_API + select ARCH_USES_GETTIMEOFFSET help This enables support for systems based on the Hynix HMS720x @@ -393,7 +396,6 @@ config ARCH_IOP32X select CPU_XSCALE select PLAT_IOP select PCI - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB help Support for Intel's 80219 and IOP32X (XScale) family of @@ -405,7 +407,6 @@ config ARCH_IOP33X select CPU_XSCALE select PLAT_IOP select PCI - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB help Support for Intel's IOP33X (XScale) family of processors. @@ -415,6 +416,7 @@ config ARCH_IXP23XX depends on MMU select CPU_XSC3 select PCI + select ARCH_USES_GETTIMEOFFSET help Support for Intel's IXP23xx (XScale) family of processors. @@ -423,6 +425,7 @@ config ARCH_IXP2000 depends on MMU select CPU_XSCALE select PCI + select ARCH_USES_GETTIMEOFFSET help Support for Intel's IXP2400/2800 (XScale) family of processors. @@ -431,7 +434,6 @@ config ARCH_IXP4XX depends on MMU select CPU_XSCALE select GENERIC_GPIO - select GENERIC_TIME select GENERIC_CLOCKEVENTS select DMABOUNCE if PCI help @@ -441,6 +443,7 @@ config ARCH_L7200 bool "LinkUp-L7200" select CPU_ARM720T select FIQ + select ARCH_USES_GETTIMEOFFSET help Say Y here if you intend to run this kernel on a LinkUp Systems L7200 Software Development Board which uses an ARM720T processor. @@ -454,9 +457,7 @@ config ARCH_L7200 config ARCH_DOVE bool "Marvell Dove" select PCI - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB - select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION help @@ -466,9 +467,7 @@ config ARCH_KIRKWOOD bool "Marvell Kirkwood" select CPU_FEROCEON select PCI - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB - select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION help @@ -478,7 +477,6 @@ config ARCH_KIRKWOOD config ARCH_LOKI bool "Marvell Loki (88RC8480)" select CPU_FEROCEON - select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION help @@ -488,9 +486,7 @@ config ARCH_MV78XX0 bool "Marvell MV78xx0" select CPU_FEROCEON select PCI - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB - select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION help @@ -502,9 +498,7 @@ config ARCH_ORION5X depends on MMU select CPU_FEROCEON select PCI - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB - select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION help @@ -515,11 +509,8 @@ config ARCH_ORION5X config ARCH_MMP bool "Marvell PXA168/910/MMP2" depends on MMU - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB - select HAVE_CLK select COMMON_CLKDEV - select GENERIC_TIME select GENERIC_CLOCKEVENTS select TICK_ONESHOT select PLAT_PXA @@ -529,8 +520,8 @@ config ARCH_MMP config ARCH_KS8695 bool "Micrel/Kendin KS8695" select CPU_ARM922T - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB + select ARCH_REQUIRE_GPIOLIB + select ARCH_USES_GETTIMEOFFSET help Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based System-on-Chip devices. @@ -539,7 +530,6 @@ config ARCH_NS9XXX bool "NetSilicon NS9xxx" select CPU_ARM926T select GENERIC_GPIO - select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_CLK help @@ -552,10 +542,7 @@ config ARCH_W90X900 bool "Nuvoton W90X900 CPU" select CPU_ARM926T select ARCH_REQUIRE_GPIOLIB - select GENERIC_GPIO - select HAVE_CLK select COMMON_CLKDEV - select GENERIC_TIME select GENERIC_CLOCKEVENTS help Support for Nuvoton (Winbond logic dept.) ARM9 processor, @@ -569,7 +556,6 @@ config ARCH_W90X900 config ARCH_NUC93X bool "Nuvoton NUC93X CPU" select CPU_ARM926T - select HAVE_CLK select COMMON_CLKDEV help Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a @@ -578,8 +564,8 @@ config ARCH_NUC93X config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" select CPU_ARM926T - select HAVE_CLK select COMMON_CLKDEV + select ARCH_USES_GETTIMEOFFSET help This enables support for Philips PNX4008 mobile platform. @@ -588,11 +574,8 @@ config ARCH_PXA depends on MMU select ARCH_MTD_XIP select ARCH_HAS_CPUFREQ - select GENERIC_GPIO - select HAVE_CLK select COMMON_CLKDEV select ARCH_REQUIRE_GPIOLIB - select GENERIC_TIME select GENERIC_CLOCKEVENTS select TICK_ONESHOT select PLAT_PXA @@ -601,14 +584,14 @@ config ARCH_PXA config ARCH_MSM bool "Qualcomm MSM" - select CPU_V6 - select GENERIC_TIME + select HAVE_CLK select GENERIC_CLOCKEVENTS help - Support for Qualcomm MSM7K based systems. This runs on the ARM11 - apps processor of the MSM7K and depends on a shared memory - interface to the ARM9 modem processor which runs the baseband stack - and controls some vital subsystems (clock and power control, etc). + Support for Qualcomm MSM/QSD based systems. This runs on the + apps processor of the MSM/QSD and depends on a shared memory + interface to the modem processor which runs the baseband + stack and controls some vital subsystems + (clock and power control, etc). config ARCH_SHMOBILE bool "Renesas SH-Mobile" @@ -625,6 +608,7 @@ config ARCH_RPC select ISA_DMA_API select NO_IOPORT select ARCH_SPARSEMEM_ENABLE + select ARCH_USES_GETTIMEOFFSET help On the Acorn Risc-PC, Linux can support the internal IDE disk and CD-ROM interface, serial and parallel port, and the floppy drive. @@ -637,8 +621,6 @@ config ARCH_SA1100 select ARCH_MTD_XIP select ARCH_HAS_CPUFREQ select CPU_FREQ - select GENERIC_GPIO - select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_CLK select TICK_ONESHOT @@ -647,23 +629,28 @@ config ARCH_SA1100 Support for StrongARM 11x0 based boards. config ARCH_S3C2410 - bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443" + bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450" select GENERIC_GPIO select ARCH_HAS_CPUFREQ select HAVE_CLK + select ARCH_USES_GETTIMEOFFSET help Samsung S3C2410X CPU based systems, such as the Simtec Electronics BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the Samsung SMDK2410 development board (and derivatives). + Note, the S3C2416 and the S3C2450 are so close that they even share + the same SoC ID code. This means that there is no seperate machine + directory (no arch/arm/mach-s3c2450) as the S3C2416 was first. + config ARCH_S3C64XX bool "Samsung S3C64XX" select PLAT_SAMSUNG select CPU_V6 - select GENERIC_GPIO select ARM_VIC select HAVE_CLK select NO_IOPORT + select ARCH_USES_GETTIMEOFFSET select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select SAMSUNG_CLKSRC @@ -720,6 +707,7 @@ config ARCH_SHARK select ISA_DMA select ZONE_DMA select PCI + select ARCH_USES_GETTIMEOFFSET help Support for the StrongARM based Digital DNARD machine, also known as "Shark" (<http://www.shark-linux.de/shark.html>). @@ -729,6 +717,7 @@ config ARCH_LH7A40X select CPU_ARM922T select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM + select ARCH_USES_GETTIMEOFFSET help Say Y here for systems based on one of the Sharp LH7A40X System on a Chip processors. These CPUs include an ARM922T @@ -742,9 +731,7 @@ config ARCH_U300 select HAVE_TCM select ARM_AMBA select ARM_VIC - select GENERIC_TIME select GENERIC_CLOCKEVENTS - select HAVE_CLK select COMMON_CLKDEV select GENERIC_GPIO help @@ -754,9 +741,9 @@ config ARCH_U8500 bool "ST-Ericsson U8500 Series" select CPU_V7 select ARM_AMBA - select GENERIC_TIME select GENERIC_CLOCKEVENTS select COMMON_CLKDEV + select ARCH_REQUIRE_GPIOLIB help Support for ST-Ericsson's Ux500 architecture @@ -765,23 +752,16 @@ config ARCH_NOMADIK select ARM_AMBA select ARM_VIC select CPU_ARM926T - select HAVE_CLK select COMMON_CLKDEV - select GENERIC_TIME select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB help Support for the Nomadik platform by ST-Ericsson config ARCH_DAVINCI bool "TI DaVinci" - select CPU_ARM926T - select GENERIC_TIME select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB - select HAVE_CLK select ZONE_DMA select HAVE_IDE select COMMON_CLKDEV @@ -792,16 +772,24 @@ config ARCH_DAVINCI config ARCH_OMAP bool "TI OMAP" - select GENERIC_GPIO select HAVE_CLK select ARCH_REQUIRE_GPIOLIB select ARCH_HAS_CPUFREQ - select GENERIC_TIME select GENERIC_CLOCKEVENTS select ARCH_HAS_HOLES_MEMORYMODEL help Support for TI's OMAP platform (OMAP1 and OMAP2). +config PLAT_SPEAR + bool "ST SPEAr" + select ARM_AMBA + select ARCH_REQUIRE_GPIOLIB + select COMMON_CLKDEV + select GENERIC_CLOCKEVENTS + select HAVE_CLK + help + Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). + endchoice # @@ -817,6 +805,8 @@ source "arch/arm/mach-bcmring/Kconfig" source "arch/arm/mach-clps711x/Kconfig" +source "arch/arm/mach-cns3xxx/Kconfig" + source "arch/arm/mach-davinci/Kconfig" source "arch/arm/mach-dove/Kconfig" @@ -887,11 +877,13 @@ source "arch/arm/plat-samsung/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s5p/Kconfig" source "arch/arm/plat-s5pc1xx/Kconfig" +source "arch/arm/plat-spear/Kconfig" if ARCH_S3C2410 source "arch/arm/mach-s3c2400/Kconfig" source "arch/arm/mach-s3c2410/Kconfig" source "arch/arm/mach-s3c2412/Kconfig" +source "arch/arm/mach-s3c2416/Kconfig" source "arch/arm/mach-s3c2440/Kconfig" source "arch/arm/mach-s3c2443/Kconfig" endif @@ -920,6 +912,8 @@ source "arch/arm/mach-ux500/Kconfig" source "arch/arm/mach-versatile/Kconfig" +source "arch/arm/mach-vexpress/Kconfig" + source "arch/arm/mach-w90x900/Kconfig" # Definitions to make life easier @@ -929,7 +923,6 @@ config ARCH_ACORN config PLAT_IOP bool select GENERIC_CLOCKEVENTS - select GENERIC_TIME config PLAT_ORION bool @@ -937,6 +930,12 @@ config PLAT_ORION config PLAT_PXA bool +config PLAT_VERSATILE + bool + +config ARM_TIMER_SP804 + bool + source arch/arm/mm/Kconfig config IWMMXT @@ -1065,6 +1064,10 @@ config PCI your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or VESA. If you have PCI, say Y, otherwise N. +config PCI_DOMAINS + bool + depends on PCI + config PCI_SYSCALL def_bool PCI @@ -1093,10 +1096,11 @@ source "kernel/time/Kconfig" config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\ - MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500) + MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\ + ARCH_U8500 || ARCH_VEXPRESS_CA9X4) depends on GENERIC_CLOCKEVENTS select USE_GENERIC_SMP_HELPERS - select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500) + select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4) help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -1277,7 +1281,7 @@ config HIGHPTE config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" - depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7) + depends on PERF_EVENTS && CPU_HAS_PMU default y help Enable hardware performance counter support for perf events. If diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ed820e737a8..4b857fbe431 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -110,6 +110,8 @@ CHECKFLAGS += -D__arm__ head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o textofs-y := 0x00008000 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 +# We don't want the htc bootloader to corrupt kernel during resume +textofs-$(CONFIG_PM_H1940) := 0x00108000 # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory ifeq ($(CONFIG_ARCH_SA1100),y) textofs-$(CONFIG_SA1111) := 0x00208000 @@ -121,6 +123,7 @@ machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 machine-$(CONFIG_ARCH_AT91) := at91 machine-$(CONFIG_ARCH_BCMRING) := bcmring machine-$(CONFIG_ARCH_CLPS711X) := clps711x +machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx machine-$(CONFIG_ARCH_DAVINCI) := davinci machine-$(CONFIG_ARCH_DOVE) := dove machine-$(CONFIG_ARCH_EBSA110) := ebsa110 @@ -160,7 +163,7 @@ machine-$(CONFIG_ARCH_PNX4008) := pnx4008 machine-$(CONFIG_ARCH_PXA) := pxa machine-$(CONFIG_ARCH_REALVIEW) := realview machine-$(CONFIG_ARCH_RPC) := rpc -machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2443 +machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx machine-$(CONFIG_ARCH_S5P6440) := s5p6440 @@ -175,9 +178,14 @@ machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx machine-$(CONFIG_ARCH_U300) := u300 machine-$(CONFIG_ARCH_U8500) := ux500 machine-$(CONFIG_ARCH_VERSATILE) := versatile +machine-$(CONFIG_ARCH_VEXPRESS) := vexpress machine-$(CONFIG_ARCH_W90X900) := w90x900 machine-$(CONFIG_ARCH_NUC93X) := nuc93x machine-$(CONFIG_FOOTBRIDGE) := footbridge +machine-$(CONFIG_MACH_SPEAR300) := spear3xx +machine-$(CONFIG_MACH_SPEAR310) := spear3xx +machine-$(CONFIG_MACH_SPEAR320) := spear3xx +machine-$(CONFIG_MACH_SPEAR600) := spear6xx # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. @@ -192,6 +200,8 @@ plat-$(CONFIG_PLAT_PXA) := pxa plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx samsung plat-$(CONFIG_PLAT_S5P) := s5p samsung +plat-$(CONFIG_PLAT_SPEAR) := spear +plat-$(CONFIG_PLAT_VERSATILE) := versatile ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 97c89e7de7d..53faa9063a0 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -65,6 +65,7 @@ SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/ suffix_$(CONFIG_KERNEL_GZIP) = gzip suffix_$(CONFIG_KERNEL_LZO) = lzo +suffix_$(CONFIG_KERNEL_LZMA) = lzma targets := vmlinux vmlinux.lds \ piggy.$(suffix_y) piggy.$(suffix_y).o \ diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c index 9c097073ce4..4c72a97bc3e 100644 --- a/arch/arm/boot/compressed/decompress.c +++ b/arch/arm/boot/compressed/decompress.c @@ -40,6 +40,10 @@ extern void error(char *); #include "../../../../lib/decompress_unlzo.c" #endif +#ifdef CONFIG_KERNEL_LZMA +#include "../../../../lib/decompress_unlzma.c" +#endif + void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)) { decompress(input, len, NULL, NULL, output, NULL, error); diff --git a/arch/arm/boot/compressed/piggy.lzma.S b/arch/arm/boot/compressed/piggy.lzma.S new file mode 100644 index 00000000000..d7e69cffbc0 --- /dev/null +++ b/arch/arm/boot/compressed/piggy.lzma.S @@ -0,0 +1,6 @@ + .section .piggydata,#alloc + .globl input_data +input_data: + .incbin "arch/arm/boot/compressed/piggy.lzma" + .globl input_data_end +input_data_end: diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 4efbb9df044..0a34c818692 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -12,10 +12,10 @@ config ARM_VIC_NR The maximum number of VICs available in the system, for power management. -config ICST525 +config ICST bool -config ICST307 +config PL330 bool config SA1111 @@ -40,3 +40,4 @@ config SHARP_SCOOP config COMMON_CLKDEV bool + select HAVE_CLK diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 76be7ff2a7c..e6e8664a941 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -4,8 +4,8 @@ obj-$(CONFIG_ARM_GIC) += gic.o obj-$(CONFIG_ARM_VIC) += vic.o -obj-$(CONFIG_ICST525) += icst525.o -obj-$(CONFIG_ICST307) += icst307.o +obj-$(CONFIG_ICST) += icst.o +obj-$(CONFIG_PL330) += pl330.o obj-$(CONFIG_SA1111) += sa1111.o obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o obj-$(CONFIG_DMABOUNCE) += dmabounce.o diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c index dba4c1da63e..e2b2bb66e09 100644 --- a/arch/arm/common/clkdev.c +++ b/arch/arm/common/clkdev.c @@ -53,12 +53,13 @@ static struct clk *clk_find(const char *dev_id, const char *con_id) continue; match += 1; } - if (match == 0) - continue; if (match > best) { clk = p->clk; - best = match; + if (match != 3) + best = match; + else + break; } } return clk; diff --git a/arch/arm/common/icst.c b/arch/arm/common/icst.c new file mode 100644 index 00000000000..9a7f09cff30 --- /dev/null +++ b/arch/arm/common/icst.c @@ -0,0 +1,100 @@ +/* + * linux/arch/arm/common/icst307.c + * + * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Support functions for calculating clocks/divisors for the ICST307 + * clock generators. See http://www.icst.com/ for more information + * on these devices. + * + * This is an almost identical implementation to the ICST525 clock generator. + * The s2div and idx2s files are different + */ +#include <linux/module.h> +#include <linux/kernel.h> + +#include <asm/hardware/icst.h> + +/* + * Divisors for each OD setting. + */ +const unsigned char icst307_s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 }; +const unsigned char icst525_s2div[8] = { 10, 2, 8, 4, 5, 7, 9, 6 }; +EXPORT_SYMBOL(icst307_s2div); +EXPORT_SYMBOL(icst525_s2div); + +unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco) +{ + return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * p->s2div[vco.s]); +} + +EXPORT_SYMBOL(icst_hz); + +/* + * Ascending divisor S values. + */ +const unsigned char icst307_idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 }; +const unsigned char icst525_idx2s[8] = { 1, 3, 4, 7, 5, 2, 6, 0 }; +EXPORT_SYMBOL(icst307_idx2s); +EXPORT_SYMBOL(icst525_idx2s); + +struct icst_vco +icst_hz_to_vco(const struct icst_params *p, unsigned long freq) +{ + struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; + unsigned long f; + unsigned int i = 0, rd, best = (unsigned int)-1; + + /* + * First, find the PLL output divisor such + * that the PLL output is within spec. + */ + do { + f = freq * p->s2div[p->idx2s[i]]; + + if (f > p->vco_min && f <= p->vco_max) + break; + } while (i < 8); + + if (i >= 8) + return vco; + + vco.s = p->idx2s[i]; + + /* + * Now find the closest divisor combination + * which gives a PLL output of 'f'. + */ + for (rd = p->rd_min; rd <= p->rd_max; rd++) { + unsigned long fref_div, f_pll; + unsigned int vd; + int f_diff; + + fref_div = (2 * p->ref) / rd; + + vd = (f + fref_div / 2) / fref_div; + if (vd < p->vd_min || vd > p->vd_max) + continue; + + f_pll = fref_div * vd; + f_diff = f_pll - f; + if (f_diff < 0) + f_diff = -f_diff; + + if ((unsigned)f_diff < best) { + vco.v = vd - 8; + vco.r = rd - 2; + if (f_diff == 0) + break; + best = f_diff; + } + } + + return vco; +} + +EXPORT_SYMBOL(icst_hz_to_vco); diff --git a/arch/arm/common/icst307.c b/arch/arm/common/icst307.c deleted file mode 100644 index 6d094c15754..00000000000 --- a/arch/arm/common/icst307.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * linux/arch/arm/common/icst307.c - * - * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Support functions for calculating clocks/divisors for the ICST307 - * clock generators. See http://www.icst.com/ for more information - * on these devices. - * - * This is an almost identical implementation to the ICST525 clock generator. - * The s2div and idx2s files are different - */ -#include <linux/module.h> -#include <linux/kernel.h> - -#include <asm/hardware/icst307.h> - -/* - * Divisors for each OD setting. - */ -static unsigned char s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 }; - -unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco) -{ - return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * s2div[vco.s]); -} - -EXPORT_SYMBOL(icst307_khz); - -/* - * Ascending divisor S values. - */ -static unsigned char idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 }; - -struct icst307_vco -icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq) -{ - struct icst307_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; - unsigned long f; - unsigned int i = 0, rd, best = (unsigned int)-1; - - /* - * First, find the PLL output divisor such - * that the PLL output is within spec. - */ - do { - f = freq * s2div[idx2s[i]]; - - /* - * f must be between 6MHz and 200MHz (3.3 or 5V) - */ - if (f > 6000 && f <= p->vco_max) - break; - } while (i < ARRAY_SIZE(idx2s)); - - if (i >= ARRAY_SIZE(idx2s)) - return vco; - - vco.s = idx2s[i]; - - /* - * Now find the closest divisor combination - * which gives a PLL output of 'f'. - */ - for (rd = p->rd_min; rd <= p->rd_max; rd++) { - unsigned long fref_div, f_pll; - unsigned int vd; - int f_diff; - - fref_div = (2 * p->ref) / rd; - - vd = (f + fref_div / 2) / fref_div; - if (vd < p->vd_min || vd > p->vd_max) - continue; - - f_pll = fref_div * vd; - f_diff = f_pll - f; - if (f_diff < 0) - f_diff = -f_diff; - - if ((unsigned)f_diff < best) { - vco.v = vd - 8; - vco.r = rd - 2; - if (f_diff == 0) - break; - best = f_diff; - } - } - - return vco; -} - -EXPORT_SYMBOL(icst307_khz_to_vco); - -struct icst307_vco -icst307_ps_to_vco(const struct icst307_params *p, unsigned long period) -{ - struct icst307_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; - unsigned long f, ps; - unsigned int i = 0, rd, best = (unsigned int)-1; - - ps = 1000000000UL / p->vco_max; - - /* - * First, find the PLL output divisor such - * that the PLL output is within spec. - */ - do { - f = period / s2div[idx2s[i]]; - - /* - * f must be between 6MHz and 200MHz (3.3 or 5V) - */ - if (f >= ps && f < 1000000000UL / 6000 + 1) - break; - } while (i < ARRAY_SIZE(idx2s)); - - if (i >= ARRAY_SIZE(idx2s)) - return vco; - - vco.s = idx2s[i]; - - ps = 500000000UL / p->ref; - - /* - * Now find the closest divisor combination - * which gives a PLL output of 'f'. - */ - for (rd = p->rd_min; rd <= p->rd_max; rd++) { - unsigned long f_in_div, f_pll; - unsigned int vd; - int f_diff; - - f_in_div = ps * rd; - - vd = (f_in_div + f / 2) / f; - if (vd < p->vd_min || vd > p->vd_max) - continue; - - f_pll = (f_in_div + vd / 2) / vd; - f_diff = f_pll - f; - if (f_diff < 0) - f_diff = -f_diff; - - if ((unsigned)f_diff < best) { - vco.v = vd - 8; - vco.r = rd - 2; - if (f_diff == 0) - break; - best = f_diff; - } - } - - return vco; -} - -EXPORT_SYMBOL(icst307_ps_to_vco); diff --git a/arch/arm/common/icst525.c b/arch/arm/common/icst525.c deleted file mode 100644 index 3d377c5bdef..00000000000 --- a/arch/arm/common/icst525.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * linux/arch/arm/common/icst525.c - * - * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Support functions for calculating clocks/divisors for the ICST525 - * clock generators. See http://www.icst.com/ for more information - * on these devices. - */ -#include <linux/module.h> -#include <linux/kernel.h> - -#include <asm/hardware/icst525.h> - -/* - * Divisors for each OD setting. - */ -static unsigned char s2div[8] = { 10, 2, 8, 4, 5, 7, 9, 6 }; - -unsigned long icst525_khz(const struct icst525_params *p, struct icst525_vco vco) -{ - return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * s2div[vco.s]); -} - -EXPORT_SYMBOL(icst525_khz); - -/* - * Ascending divisor S values. - */ -static unsigned char idx2s[] = { 1, 3, 4, 7, 5, 2, 6, 0 }; - -struct icst525_vco -icst525_khz_to_vco(const struct icst525_params *p, unsigned long freq) -{ - struct icst525_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; - unsigned long f; - unsigned int i = 0, rd, best = (unsigned int)-1; - - /* - * First, find the PLL output divisor such - * that the PLL output is within spec. - */ - do { - f = freq * s2div[idx2s[i]]; - - /* - * f must be between 10MHz and - * 320MHz (5V) or 200MHz (3V) - */ - if (f > 10000 && f <= p->vco_max) - break; - } while (i < ARRAY_SIZE(idx2s)); - - if (i >= ARRAY_SIZE(idx2s)) - return vco; - - vco.s = idx2s[i]; - - /* - * Now find the closest divisor combination - * which gives a PLL output of 'f'. - */ - for (rd = p->rd_min; rd <= p->rd_max; rd++) { - unsigned long fref_div, f_pll; - unsigned int vd; - int f_diff; - - fref_div = (2 * p->ref) / rd; - - vd = (f + fref_div / 2) / fref_div; - if (vd < p->vd_min || vd > p->vd_max) - continue; - - f_pll = fref_div * vd; - f_diff = f_pll - f; - if (f_diff < 0) - f_diff = -f_diff; - - if ((unsigned)f_diff < best) { - vco.v = vd - 8; - vco.r = rd - 2; - if (f_diff == 0) - break; - best = f_diff; - } - } - - return vco; -} - -EXPORT_SYMBOL(icst525_khz_to_vco); - -struct icst525_vco -icst525_ps_to_vco(const struct icst525_params *p, unsigned long period) -{ - struct icst525_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; - unsigned long f, ps; - unsigned int i = 0, rd, best = (unsigned int)-1; - - ps = 1000000000UL / p->vco_max; - - /* - * First, find the PLL output divisor such - * that the PLL output is within spec. - */ - do { - f = period / s2div[idx2s[i]]; - - /* - * f must be between 10MHz and - * 320MHz (5V) or 200MHz (3V) - */ - if (f >= ps && f < 100000) - break; - } while (i < ARRAY_SIZE(idx2s)); - - if (i >= ARRAY_SIZE(idx2s)) - return vco; - - vco.s = idx2s[i]; - - ps = 500000000UL / p->ref; - - /* - * Now find the closest divisor combination - * which gives a PLL output of 'f'. - */ - for (rd = p->rd_min; rd <= p->rd_max; rd++) { - unsigned long f_in_div, f_pll; - unsigned int vd; - int f_diff; - - f_in_div = ps * rd; - - vd = (f_in_div + f / 2) / f; - if (vd < p->vd_min || vd > p->vd_max) - continue; - - f_pll = (f_in_div + vd / 2) / vd; - f_diff = f_pll - f; - if (f_diff < 0) - f_diff = -f_diff; - - if ((unsigned)f_diff < best) { - vco.v = vd - 8; - vco.r = rd - 2; - if (f_diff == 0) - break; - best = f_diff; - } - } - - return vco; -} - -EXPORT_SYMBOL(icst525_ps_to_vco); diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c new file mode 100644 index 00000000000..5ebbab6242a --- /dev/null +++ b/arch/arm/common/pl330.c @@ -0,0 +1,1966 @@ +/* linux/arch/arm/common/pl330.c + * + * Copyright (C) 2010 Samsung Electronics Co Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/string.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/dma-mapping.h> + +#include <asm/hardware/pl330.h> + +/* Register and Bit field Definitions */ +#define DS 0x0 +#define DS_ST_STOP 0x0 +#define DS_ST_EXEC 0x1 +#define DS_ST_CMISS 0x2 +#define DS_ST_UPDTPC 0x3 +#define DS_ST_WFE 0x4 +#define DS_ST_ATBRR 0x5 +#define DS_ST_QBUSY 0x6 +#define DS_ST_WFP 0x7 +#define DS_ST_KILL 0x8 +#define DS_ST_CMPLT 0x9 +#define DS_ST_FLTCMP 0xe +#define DS_ST_FAULT 0xf + +#define DPC 0x4 +#define INTEN 0x20 +#define ES 0x24 +#define INTSTATUS 0x28 +#define INTCLR 0x2c +#define FSM 0x30 +#define FSC 0x34 +#define FTM 0x38 + +#define _FTC 0x40 +#define FTC(n) (_FTC + (n)*0x4) + +#define _CS 0x100 +#define CS(n) (_CS + (n)*0x8) +#define CS_CNS (1 << 21) + +#define _CPC 0x104 +#define CPC(n) (_CPC + (n)*0x8) + +#define _SA 0x400 +#define SA(n) (_SA + (n)*0x20) + +#define _DA 0x404 +#define DA(n) (_DA + (n)*0x20) + +#define _CC 0x408 +#define CC(n) (_CC + (n)*0x20) + +#define CC_SRCINC (1 << 0) +#define CC_DSTINC (1 << 14) +#define CC_SRCPRI (1 << 8) +#define CC_DSTPRI (1 << 22) +#define CC_SRCNS (1 << 9) +#define CC_DSTNS (1 << 23) +#define CC_SRCIA (1 << 10) +#define CC_DSTIA (1 << 24) +#define CC_SRCBRSTLEN_SHFT 4 +#define CC_DSTBRSTLEN_SHFT 18 +#define CC_SRCBRSTSIZE_SHFT 1 +#define CC_DSTBRSTSIZE_SHFT 15 +#define CC_SRCCCTRL_SHFT 11 +#define CC_SRCCCTRL_MASK 0x7 +#define CC_DSTCCTRL_SHFT 25 +#define CC_DRCCCTRL_MASK 0x7 +#define CC_SWAP_SHFT 28 + +#define _LC0 0x40c +#define LC0(n) (_LC0 + (n)*0x20) + +#define _LC1 0x410 +#define LC1(n) (_LC1 + (n)*0x20) + +#define DBGSTATUS 0xd00 +#define DBG_BUSY (1 << 0) + +#define DBGCMD 0xd04 +#define DBGINST0 0xd08 +#define DBGINST1 0xd0c + +#define CR0 0xe00 +#define CR1 0xe04 +#define CR2 0xe08 +#define CR3 0xe0c +#define CR4 0xe10 +#define CRD 0xe14 + +#define PERIPH_ID 0xfe0 +#define PCELL_ID 0xff0 + +#define CR0_PERIPH_REQ_SET (1 << 0) +#define CR0_BOOT_EN_SET (1 << 1) +#define CR0_BOOT_MAN_NS (1 << 2) +#define CR0_NUM_CHANS_SHIFT 4 +#define CR0_NUM_CHANS_MASK 0x7 +#define CR0_NUM_PERIPH_SHIFT 12 +#define CR0_NUM_PERIPH_MASK 0x1f +#define CR0_NUM_EVENTS_SHIFT 17 +#define CR0_NUM_EVENTS_MASK 0x1f + +#define CR1_ICACHE_LEN_SHIFT 0 +#define CR1_ICACHE_LEN_MASK 0x7 +#define CR1_NUM_ICACHELINES_SHIFT 4 +#define CR1_NUM_ICACHELINES_MASK 0xf + +#define CRD_DATA_WIDTH_SHIFT 0 +#define CRD_DATA_WIDTH_MASK 0x7 +#define CRD_WR_CAP_SHIFT 4 +#define CRD_WR_CAP_MASK 0x7 +#define CRD_WR_Q_DEP_SHIFT 8 +#define CRD_WR_Q_DEP_MASK 0xf +#define CRD_RD_CAP_SHIFT 12 +#define CRD_RD_CAP_MASK 0x7 +#define CRD_RD_Q_DEP_SHIFT 16 +#define CRD_RD_Q_DEP_MASK 0xf +#define CRD_DATA_BUFF_SHIFT 20 +#define CRD_DATA_BUFF_MASK 0x3ff + +#define PART 0x330 +#define DESIGNER 0x41 +#define REVISION 0x0 +#define INTEG_CFG 0x0 +#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12) \ + | (REVISION << 20) | (INTEG_CFG << 24)) + +#define PCELL_ID_VAL 0xb105f00d + +#define PL330_STATE_STOPPED (1 << 0) +#define PL330_STATE_EXECUTING (1 << 1) +#define PL330_STATE_WFE (1 << 2) +#define PL330_STATE_FAULTING (1 << 3) +#define PL330_STATE_COMPLETING (1 << 4) +#define PL330_STATE_WFP (1 << 5) +#define PL330_STATE_KILLING (1 << 6) +#define PL330_STATE_FAULT_COMPLETING (1 << 7) +#define PL330_STATE_CACHEMISS (1 << 8) +#define PL330_STATE_UPDTPC (1 << 9) +#define PL330_STATE_ATBARRIER (1 << 10) +#define PL330_STATE_QUEUEBUSY (1 << 11) +#define PL330_STATE_INVALID (1 << 15) + +#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ + | PL330_STATE_WFE | PL330_STATE_FAULTING) + +#define CMD_DMAADDH 0x54 +#define CMD_DMAEND 0x00 +#define CMD_DMAFLUSHP 0x35 +#define CMD_DMAGO 0xa0 +#define CMD_DMALD 0x04 +#define CMD_DMALDP 0x25 +#define CMD_DMALP 0x20 +#define CMD_DMALPEND 0x28 +#define CMD_DMAKILL 0x01 +#define CMD_DMAMOV 0xbc +#define CMD_DMANOP 0x18 +#define CMD_DMARMB 0x12 +#define CMD_DMASEV 0x34 +#define CMD_DMAST 0x08 +#define CMD_DMASTP 0x29 +#define CMD_DMASTZ 0x0c +#define CMD_DMAWFE 0x36 +#define CMD_DMAWFP 0x30 +#define CMD_DMAWMB 0x13 + +#define SZ_DMAADDH 3 +#define SZ_DMAEND 1 +#define SZ_DMAFLUSHP 2 +#define SZ_DMALD 1 +#define SZ_DMALDP 2 +#define SZ_DMALP 2 +#define SZ_DMALPEND 2 +#define SZ_DMAKILL 1 +#define SZ_DMAMOV 6 +#define SZ_DMANOP 1 +#define SZ_DMARMB 1 +#define SZ_DMASEV 2 +#define SZ_DMAST 1 +#define SZ_DMASTP 2 +#define SZ_DMASTZ 1 +#define SZ_DMAWFE 2 +#define SZ_DMAWFP 2 +#define SZ_DMAWMB 1 +#define SZ_DMAGO 6 + +#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) +#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) + +#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) +#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) + +/* + * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req + * at 1byte/burst for P<->M and M<->M respectively. + * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req + * should be enough for P<->M and M<->M respectively. + */ +#define MCODE_BUFF_PER_REQ 256 + +/* + * Mark a _pl330_req as free. + * We do it by writing DMAEND as the first instruction + * because no valid request is going to have DMAEND as + * its first instruction to execute. + */ +#define MARK_FREE(req) do { \ + _emit_END(0, (req)->mc_cpu); \ + (req)->mc_len = 0; \ + } while (0) + +/* If the _pl330_req is available to the client */ +#define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND) + +/* Use this _only_ to wait on transient states */ +#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); + +#ifdef PL330_DEBUG_MCGEN +static unsigned cmd_line; +#define PL330_DBGCMD_DUMP(off, x...) do { \ + printk("%x:", cmd_line); \ + printk(x); \ + cmd_line += off; \ + } while (0) +#define PL330_DBGMC_START(addr) (cmd_line = addr) +#else +#define PL330_DBGCMD_DUMP(off, x...) do {} while (0) +#define PL330_DBGMC_START(addr) do {} while (0) +#endif + +struct _xfer_spec { + u32 ccr; + struct pl330_req *r; + struct pl330_xfer *x; +}; + +enum dmamov_dst { + SAR = 0, + CCR, + DAR, +}; + +enum pl330_dst { + SRC = 0, + DST, +}; + +enum pl330_cond { + SINGLE, + BURST, + ALWAYS, +}; + +struct _pl330_req { + u32 mc_bus; + void *mc_cpu; + /* Number of bytes taken to setup MC for the req */ + u32 mc_len; + struct pl330_req *r; + /* Hook to attach to DMAC's list of reqs with due callback */ + struct list_head rqd; +}; + +/* ToBeDone for tasklet */ +struct _pl330_tbd { + bool reset_dmac; + bool reset_mngr; + u8 reset_chan; +}; + +/* A DMAC Thread */ +struct pl330_thread { + u8 id; + int ev; + /* If the channel is not yet acquired by any client */ + bool free; + /* Parent DMAC */ + struct pl330_dmac *dmac; + /* Only two at a time */ + struct _pl330_req req[2]; + /* Index of the last submitted request */ + unsigned lstenq; +}; + +enum pl330_dmac_state { + UNINIT, + INIT, + DYING, +}; + +/* A DMAC */ +struct pl330_dmac { + spinlock_t lock; + /* Holds list of reqs with due callbacks */ + struct list_head req_done; + /* Pointer to platform specific stuff */ + struct pl330_info *pinfo; + /* Maximum possible events/irqs */ + int events[32]; + /* BUS address of MicroCode buffer */ + u32 mcode_bus; + /* CPU address of MicroCode buffer */ + void *mcode_cpu; + /* List of all Channel threads */ + struct pl330_thread *channels; + /* Pointer to the MANAGER thread */ + struct pl330_thread *manager; + /* To handle bad news in interrupt */ + struct tasklet_struct tasks; + struct _pl330_tbd dmac_tbd; + /* State of DMAC operation */ + enum pl330_dmac_state state; +}; + +static inline void _callback(struct pl330_req *r, enum pl330_op_err err) +{ + if (r && r->xfer_cb) + r->xfer_cb(r->token, err); +} + +static inline bool _queue_empty(struct pl330_thread *thrd) +{ + return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1])) + ? true : false; +} + +static inline bool _queue_full(struct pl330_thread *thrd) +{ + return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1])) + ? false : true; +} + +static inline bool is_manager(struct pl330_thread *thrd) +{ + struct pl330_dmac *pl330 = thrd->dmac; + + /* MANAGER is indexed at the end */ + if (thrd->id == pl330->pinfo->pcfg.num_chan) + return true; + else + return false; +} + +/* If manager of the thread is in Non-Secure mode */ +static inline bool _manager_ns(struct pl330_thread *thrd) +{ + struct pl330_dmac *pl330 = thrd->dmac; + + return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false; +} + +static inline u32 get_id(struct pl330_info *pi, u32 off) +{ + void __iomem *regs = pi->base; + u32 id = 0; + + id |= (readb(regs + off + 0x0) << 0); + id |= (readb(regs + off + 0x4) << 8); + id |= (readb(regs + off + 0x8) << 16); + id |= (readb(regs + off + 0xc) << 24); + + return id; +} + +static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], + enum pl330_dst da, u16 val) +{ + if (dry_run) + return SZ_DMAADDH; + + buf[0] = CMD_DMAADDH; + buf[0] |= (da << 1); + *((u16 *)&buf[1]) = val; + + PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", + da == 1 ? "DA" : "SA", val); + + return SZ_DMAADDH; +} + +static inline u32 _emit_END(unsigned dry_run, u8 buf[]) +{ + if (dry_run) + return SZ_DMAEND; + + buf[0] = CMD_DMAEND; + + PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); + + return SZ_DMAEND; +} + +static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) +{ + if (dry_run) + return SZ_DMAFLUSHP; + + buf[0] = CMD_DMAFLUSHP; + + peri &= 0x1f; + peri <<= 3; + buf[1] = peri; + + PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); + + return SZ_DMAFLUSHP; +} + +static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) +{ + if (dry_run) + return SZ_DMALD; + + buf[0] = CMD_DMALD; + + if (cond == SINGLE) + buf[0] |= (0 << 1) | (1 << 0); + else if (cond == BURST) + buf[0] |= (1 << 1) | (1 << 0); + + PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", + cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); + + return SZ_DMALD; +} + +static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], + enum pl330_cond cond, u8 peri) +{ + if (dry_run) + return SZ_DMALDP; + + buf[0] = CMD_DMALDP; + + if (cond == BURST) + buf[0] |= (1 << 1); + + peri &= 0x1f; + peri <<= 3; + buf[1] = peri; + + PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", + cond == SINGLE ? 'S' : 'B', peri >> 3); + + return SZ_DMALDP; +} + +static inline u32 _emit_LP(unsigned dry_run, u8 buf[], + unsigned loop, u8 cnt) +{ + if (dry_run) + return SZ_DMALP; + + buf[0] = CMD_DMALP; + + if (loop) + buf[0] |= (1 << 1); + + cnt--; /* DMAC increments by 1 internally */ + buf[1] = cnt; + + PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); + + return SZ_DMALP; +} + +struct _arg_LPEND { + enum pl330_cond cond; + bool forever; + unsigned loop; + u8 bjump; +}; + +static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], + const struct _arg_LPEND *arg) +{ + enum pl330_cond cond = arg->cond; + bool forever = arg->forever; + unsigned loop = arg->loop; + u8 bjump = arg->bjump; + + if (dry_run) + return SZ_DMALPEND; + + buf[0] = CMD_DMALPEND; + + if (loop) + buf[0] |= (1 << 2); + + if (!forever) + buf[0] |= (1 << 4); + + if (cond == SINGLE) + buf[0] |= (0 << 1) | (1 << 0); + else if (cond == BURST) + buf[0] |= (1 << 1) | (1 << 0); + + buf[1] = bjump; + + PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", + forever ? "FE" : "END", + cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), + loop ? '1' : '0', + bjump); + + return SZ_DMALPEND; +} + +static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) +{ + if (dry_run) + return SZ_DMAKILL; + + buf[0] = CMD_DMAKILL; + + return SZ_DMAKILL; +} + +static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], + enum dmamov_dst dst, u32 val) +{ + if (dry_run) + return SZ_DMAMOV; + + buf[0] = CMD_DMAMOV; + buf[1] = dst; + *((u32 *)&buf[2]) = val; + + PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", + dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); + + return SZ_DMAMOV; +} + +static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) +{ + if (dry_run) + return SZ_DMANOP; + + buf[0] = CMD_DMANOP; + + PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); + + return SZ_DMANOP; +} + +static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) +{ + if (dry_run) + return SZ_DMARMB; + + buf[0] = CMD_DMARMB; + + PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); + + return SZ_DMARMB; +} + +static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) +{ + if (dry_run) + return SZ_DMASEV; + + buf[0] = CMD_DMASEV; + + ev &= 0x1f; + ev <<= 3; + buf[1] = ev; + + PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); + + return SZ_DMASEV; +} + +static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) +{ + if (dry_run) + return SZ_DMAST; + + buf[0] = CMD_DMAST; + + if (cond == SINGLE) + buf[0] |= (0 << 1) | (1 << 0); + else if (cond == BURST) + buf[0] |= (1 << 1) | (1 << 0); + + PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", + cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); + + return SZ_DMAST; +} + +static inline u32 _emit_STP(unsigned dry_run, u8 buf[], + enum pl330_cond cond, u8 peri) +{ + if (dry_run) + return SZ_DMASTP; + + buf[0] = CMD_DMASTP; + + if (cond == BURST) + buf[0] |= (1 << 1); + + peri &= 0x1f; + peri <<= 3; + buf[1] = peri; + + PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", + cond == SINGLE ? 'S' : 'B', peri >> 3); + + return SZ_DMASTP; +} + +static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) +{ + if (dry_run) + return SZ_DMASTZ; + + buf[0] = CMD_DMASTZ; + + PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); + + return SZ_DMASTZ; +} + +static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, + unsigned invalidate) +{ + if (dry_run) + return SZ_DMAWFE; + + buf[0] = CMD_DMAWFE; + + ev &= 0x1f; + ev <<= 3; + buf[1] = ev; + + if (invalidate) + buf[1] |= (1 << 1); + + PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", + ev >> 3, invalidate ? ", I" : ""); + + return SZ_DMAWFE; +} + +static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], + enum pl330_cond cond, u8 peri) +{ + if (dry_run) + return SZ_DMAWFP; + + buf[0] = CMD_DMAWFP; + + if (cond == SINGLE) + buf[0] |= (0 << 1) | (0 << 0); + else if (cond == BURST) + buf[0] |= (1 << 1) | (0 << 0); + else + buf[0] |= (0 << 1) | (1 << 0); + + peri &= 0x1f; + peri <<= 3; + buf[1] = peri; + + PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", + cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); + + return SZ_DMAWFP; +} + +static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) +{ + if (dry_run) + return SZ_DMAWMB; + + buf[0] = CMD_DMAWMB; + + PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); + + return SZ_DMAWMB; +} + +struct _arg_GO { + u8 chan; + u32 addr; + unsigned ns; +}; + +static inline u32 _emit_GO(unsigned dry_run, u8 buf[], + const struct _arg_GO *arg) +{ + u8 chan = arg->chan; + u32 addr = arg->addr; + unsigned ns = arg->ns; + + if (dry_run) + return SZ_DMAGO; + + buf[0] = CMD_DMAGO; + buf[0] |= (ns << 1); + + buf[1] = chan & 0x7; + + *((u32 *)&buf[2]) = addr; + + return SZ_DMAGO; +} + +#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) + +/* Returns Time-Out */ +static bool _until_dmac_idle(struct pl330_thread *thrd) +{ + void __iomem *regs = thrd->dmac->pinfo->base; + unsigned long loops = msecs_to_loops(5); + + do { + /* Until Manager is Idle */ + if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) + break; + + cpu_relax(); + } while (--loops); + + if (!loops) + return true; + + return false; +} + +static inline void _execute_DBGINSN(struct pl330_thread *thrd, + u8 insn[], bool as_manager) +{ + void __iomem *regs = thrd->dmac->pinfo->base; + u32 val; + + val = (insn[0] << 16) | (insn[1] << 24); + if (!as_manager) { + val |= (1 << 0); + val |= (thrd->id << 8); /* Channel Number */ + } + writel(val, regs + DBGINST0); + + val = *((u32 *)&insn[2]); + writel(val, regs + DBGINST1); + + /* If timed out due to halted state-machine */ + if (_until_dmac_idle(thrd)) { + dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n"); + return; + } + + /* Get going */ + writel(0, regs + DBGCMD); +} + +static inline u32 _state(struct pl330_thread *thrd) +{ + void __iomem *regs = thrd->dmac->pinfo->base; + u32 val; + + if (is_manager(thrd)) + val = readl(regs + DS) & 0xf; + else + val = readl(regs + CS(thrd->id)) & 0xf; + + switch (val) { + case DS_ST_STOP: + return PL330_STATE_STOPPED; + case DS_ST_EXEC: + return PL330_STATE_EXECUTING; + case DS_ST_CMISS: + return PL330_STATE_CACHEMISS; + case DS_ST_UPDTPC: + return PL330_STATE_UPDTPC; + case DS_ST_WFE: + return PL330_STATE_WFE; + case DS_ST_FAULT: + return PL330_STATE_FAULTING; + case DS_ST_ATBRR: + if (is_manager(thrd)) + return PL330_STATE_INVALID; + else + return PL330_STATE_ATBARRIER; + case DS_ST_QBUSY: + if (is_manager(thrd)) + return PL330_STATE_INVALID; + else + return PL330_STATE_QUEUEBUSY; + case DS_ST_WFP: + if (is_manager(thrd)) + return PL330_STATE_INVALID; + else + return PL330_STATE_WFP; + case DS_ST_KILL: + if (is_manager(thrd)) + return PL330_STATE_INVALID; + else + return PL330_STATE_KILLING; + case DS_ST_CMPLT: + if (is_manager(thrd)) + return PL330_STATE_INVALID; + else + return PL330_STATE_COMPLETING; + case DS_ST_FLTCMP: + if (is_manager(thrd)) + return PL330_STATE_INVALID; + else + return PL330_STATE_FAULT_COMPLETING; + default: + return PL330_STATE_INVALID; + } +} + +/* If the request 'req' of thread 'thrd' is currently active */ +static inline bool _req_active(struct pl330_thread *thrd, + struct _pl330_req *req) +{ + void __iomem *regs = thrd->dmac->pinfo->base; + u32 buf = req->mc_bus, pc = readl(regs + CPC(thrd->id)); + + if (IS_FREE(req)) + return false; + + return (pc >= buf && pc <= buf + req->mc_len) ? true : false; +} + +/* Returns 0 if the thread is inactive, ID of active req + 1 otherwise */ +static inline unsigned _thrd_active(struct pl330_thread *thrd) +{ + if (_req_active(thrd, &thrd->req[0])) + return 1; /* First req active */ + + if (_req_active(thrd, &thrd->req[1])) + return 2; /* Second req active */ + + return 0; +} + +static void _stop(struct pl330_thread *thrd) +{ + void __iomem *regs = thrd->dmac->pinfo->base; + u8 insn[6] = {0, 0, 0, 0, 0, 0}; + + if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) + UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); + + /* Return if nothing needs to be done */ + if (_state(thrd) == PL330_STATE_COMPLETING + || _state(thrd) == PL330_STATE_KILLING + || _state(thrd) == PL330_STATE_STOPPED) + return; + + _emit_KILL(0, insn); + + /* Stop generating interrupts for SEV */ + writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); + + _execute_DBGINSN(thrd, insn, is_manager(thrd)); +} + +/* Start doing req 'idx' of thread 'thrd' */ +static bool _trigger(struct pl330_thread *thrd) +{ + void __iomem *regs = thrd->dmac->pinfo->base; + struct _pl330_req *req; + struct pl330_req *r; + struct _arg_GO go; + unsigned ns; + u8 insn[6] = {0, 0, 0, 0, 0, 0}; + + /* Return if already ACTIVE */ + if (_state(thrd) != PL330_STATE_STOPPED) + return true; + + if (!IS_FREE(&thrd->req[1 - thrd->lstenq])) + req = &thrd->req[1 - thrd->lstenq]; + else if (!IS_FREE(&thrd->req[thrd->lstenq])) + req = &thrd->req[thrd->lstenq]; + else + req = NULL; + + /* Return if no request */ + if (!req || !req->r) + return true; + + r = req->r; + + if (r->cfg) + ns = r->cfg->nonsecure ? 1 : 0; + else if (readl(regs + CS(thrd->id)) & CS_CNS) + ns = 1; + else + ns = 0; + + /* See 'Abort Sources' point-4 at Page 2-25 */ + if (_manager_ns(thrd) && !ns) + dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n", + __func__, __LINE__); + + go.chan = thrd->id; + go.addr = req->mc_bus; + go.ns = ns; + _emit_GO(0, insn, &go); + + /* Set to generate interrupts for SEV */ + writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); + + /* Only manager can execute GO */ + _execute_DBGINSN(thrd, insn, true); + + return true; +} + +static bool _start(struct pl330_thread *thrd) +{ + switch (_state(thrd)) { + case PL330_STATE_FAULT_COMPLETING: + UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); + + if (_state(thrd) == PL330_STATE_KILLING) + UNTIL(thrd, PL330_STATE_STOPPED) + + case PL330_STATE_FAULTING: + _stop(thrd); + + case PL330_STATE_KILLING: + case PL330_STATE_COMPLETING: + UNTIL(thrd, PL330_STATE_STOPPED) + + case PL330_STATE_STOPPED: + return _trigger(thrd); + + case PL330_STATE_WFP: + case PL330_STATE_QUEUEBUSY: + case PL330_STATE_ATBARRIER: + case PL330_STATE_UPDTPC: + case PL330_STATE_CACHEMISS: + case PL330_STATE_EXECUTING: + return true; + + case PL330_STATE_WFE: /* For RESUME, nothing yet */ + default: + return false; + } +} + +static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], + const struct _xfer_spec *pxs, int cyc) +{ + int off = 0; + + while (cyc--) { + off += _emit_LD(dry_run, &buf[off], ALWAYS); + off += _emit_RMB(dry_run, &buf[off]); + off += _emit_ST(dry_run, &buf[off], ALWAYS); + off += _emit_WMB(dry_run, &buf[off]); + } + + return off; +} + +static inline int _ldst_devtomem(unsigned dry_run, u8 buf[], + const struct _xfer_spec *pxs, int cyc) +{ + int off = 0; + + while (cyc--) { + off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); + off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri); + off += _emit_ST(dry_run, &buf[off], ALWAYS); + off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); + } + + return off; +} + +static inline int _ldst_memtodev(unsigned dry_run, u8 buf[], + const struct _xfer_spec *pxs, int cyc) +{ + int off = 0; + + while (cyc--) { + off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); + off += _emit_LD(dry_run, &buf[off], ALWAYS); + off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri); + off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); + } + + return off; +} + +static int _bursts(unsigned dry_run, u8 buf[], + const struct _xfer_spec *pxs, int cyc) +{ + int off = 0; + + switch (pxs->r->rqtype) { + case MEMTODEV: + off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc); + break; + case DEVTOMEM: + off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc); + break; + case MEMTOMEM: + off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); + break; + default: + off += 0x40000000; /* Scare off the Client */ + break; + } + + return off; +} + +/* Returns bytes consumed and updates bursts */ +static inline int _loop(unsigned dry_run, u8 buf[], + unsigned long *bursts, const struct _xfer_spec *pxs) +{ + int cyc, cycmax, szlp, szlpend, szbrst, off; + unsigned lcnt0, lcnt1, ljmp0, ljmp1; + struct _arg_LPEND lpend; + + /* Max iterations possibile in DMALP is 256 */ + if (*bursts >= 256*256) { + lcnt1 = 256; + lcnt0 = 256; + cyc = *bursts / lcnt1 / lcnt0; + } else if (*bursts > 256) { + lcnt1 = 256; + lcnt0 = *bursts / lcnt1; + cyc = 1; + } else { + lcnt1 = *bursts; + lcnt0 = 0; + cyc = 1; + } + + szlp = _emit_LP(1, buf, 0, 0); + szbrst = _bursts(1, buf, pxs, 1); + + lpend.cond = ALWAYS; + lpend.forever = false; + lpend.loop = 0; + lpend.bjump = 0; + szlpend = _emit_LPEND(1, buf, &lpend); + + if (lcnt0) { + szlp *= 2; + szlpend *= 2; + } + + /* + * Max bursts that we can unroll due to limit on the + * size of backward jump that can be encoded in DMALPEND + * which is 8-bits and hence 255 + */ + cycmax = (255 - (szlp + szlpend)) / szbrst; + + cyc = (cycmax < cyc) ? cycmax : cyc; + + off = 0; + + if (lcnt0) { + off += _emit_LP(dry_run, &buf[off], 0, lcnt0); + ljmp0 = off; + } + + off += _emit_LP(dry_run, &buf[off], 1, lcnt1); + ljmp1 = off; + + off += _bursts(dry_run, &buf[off], pxs, cyc); + + lpend.cond = ALWAYS; + lpend.forever = false; + lpend.loop = 1; + lpend.bjump = off - ljmp1; + off += _emit_LPEND(dry_run, &buf[off], &lpend); + + if (lcnt0) { + lpend.cond = ALWAYS; + lpend.forever = false; + lpend.loop = 0; + lpend.bjump = off - ljmp0; + off += _emit_LPEND(dry_run, &buf[off], &lpend); + } + + *bursts = lcnt1 * cyc; + if (lcnt0) + *bursts *= lcnt0; + + return off; +} + +static inline int _setup_loops(unsigned dry_run, u8 buf[], + const struct _xfer_spec *pxs) +{ + struct pl330_xfer *x = pxs->x; + u32 ccr = pxs->ccr; + unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); + int off = 0; + + while (bursts) { + c = bursts; + off += _loop(dry_run, &buf[off], &c, pxs); + bursts -= c; + } + + return off; +} + +static inline int _setup_xfer(unsigned dry_run, u8 buf[], + const struct _xfer_spec *pxs) +{ + struct pl330_xfer *x = pxs->x; + int off = 0; + + /* DMAMOV SAR, x->src_addr */ + off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); + /* DMAMOV DAR, x->dst_addr */ + off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); + + /* Setup Loop(s) */ + off += _setup_loops(dry_run, &buf[off], pxs); + + return off; +} + +/* + * A req is a sequence of one or more xfer units. + * Returns the number of bytes taken to setup the MC for the req. + */ +static int _setup_req(unsigned dry_run, struct pl330_thread *thrd, + unsigned index, struct _xfer_spec *pxs) +{ + struct _pl330_req *req = &thrd->req[index]; + struct pl330_xfer *x; + u8 *buf = req->mc_cpu; + int off = 0; + + PL330_DBGMC_START(req->mc_bus); + + /* DMAMOV CCR, ccr */ + off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); + + x = pxs->r->x; + do { + /* Error if xfer length is not aligned at burst size */ + if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) + return -EINVAL; + + pxs->x = x; + off += _setup_xfer(dry_run, &buf[off], pxs); + + x = x->next; + } while (x); + + /* DMASEV peripheral/event */ + off += _emit_SEV(dry_run, &buf[off], thrd->ev); + /* DMAEND */ + off += _emit_END(dry_run, &buf[off]); + + return off; +} + +static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) +{ + u32 ccr = 0; + + if (rqc->src_inc) + ccr |= CC_SRCINC; + + if (rqc->dst_inc) + ccr |= CC_DSTINC; + + /* We set same protection levels for Src and DST for now */ + if (rqc->privileged) + ccr |= CC_SRCPRI | CC_DSTPRI; + if (rqc->nonsecure) + ccr |= CC_SRCNS | CC_DSTNS; + if (rqc->insnaccess) + ccr |= CC_SRCIA | CC_DSTIA; + + ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); + ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); + + ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); + ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); + + ccr |= (rqc->dcctl << CC_SRCCCTRL_SHFT); + ccr |= (rqc->scctl << CC_DSTCCTRL_SHFT); + + ccr |= (rqc->swap << CC_SWAP_SHFT); + + return ccr; +} + +static inline bool _is_valid(u32 ccr) +{ + enum pl330_dstcachectrl dcctl; + enum pl330_srccachectrl scctl; + + dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK; + scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK; + + if (dcctl == DINVALID1 || dcctl == DINVALID2 + || scctl == SINVALID1 || scctl == SINVALID2) + return false; + else + return true; +} + +/* + * Submit a list of xfers after which the client wants notification. + * Client is not notified after each xfer unit, just once after all + * xfer units are done or some error occurs. + */ +int pl330_submit_req(void *ch_id, struct pl330_req *r) +{ + struct pl330_thread *thrd = ch_id; + struct pl330_dmac *pl330; + struct pl330_info *pi; + struct _xfer_spec xs; + unsigned long flags; + void __iomem *regs; + unsigned idx; + u32 ccr; + int ret = 0; + + /* No Req or Unacquired Channel or DMAC */ + if (!r || !thrd || thrd->free) + return -EINVAL; + + pl330 = thrd->dmac; + pi = pl330->pinfo; + regs = pi->base; + + if (pl330->state == DYING + || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { + dev_info(thrd->dmac->pinfo->dev, "%s:%d\n", + __func__, __LINE__); + return -EAGAIN; + } + + /* If request for non-existing peripheral */ + if (r->rqtype != MEMTOMEM && r->peri >= pi->pcfg.num_peri) { + dev_info(thrd->dmac->pinfo->dev, + "%s:%d Invalid peripheral(%u)!\n", + __func__, __LINE__, r->peri); + return -EINVAL; + } + + spin_lock_irqsave(&pl330->lock, flags); + + if (_queue_full(thrd)) { + ret = -EAGAIN; + goto xfer_exit; + } + + /* Prefer Secure Channel */ + if (!_manager_ns(thrd)) + r->cfg->nonsecure = 0; + else + r->cfg->nonsecure = 1; + + /* Use last settings, if not provided */ + if (r->cfg) + ccr = _prepare_ccr(r->cfg); + else + ccr = readl(regs + CC(thrd->id)); + + /* If this req doesn't have valid xfer settings */ + if (!_is_valid(ccr)) { + ret = -EINVAL; + dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n", + __func__, __LINE__, ccr); + goto xfer_exit; + } + + idx = IS_FREE(&thrd->req[0]) ? 0 : 1; + + xs.ccr = ccr; + xs.r = r; + + /* First dry run to check if req is acceptable */ + ret = _setup_req(1, thrd, idx, &xs); + if (ret < 0) + goto xfer_exit; + + if (ret > pi->mcbufsz / 2) { + dev_info(thrd->dmac->pinfo->dev, + "%s:%d Trying increasing mcbufsz\n", + __func__, __LINE__); + ret = -ENOMEM; + goto xfer_exit; + } + + /* Hook the request */ + thrd->lstenq = idx; + thrd->req[idx].mc_len = _setup_req(0, thrd, idx, &xs); + thrd->req[idx].r = r; + + ret = 0; + +xfer_exit: + spin_unlock_irqrestore(&pl330->lock, flags); + + return ret; +} +EXPORT_SYMBOL(pl330_submit_req); + +static void pl330_dotask(unsigned long data) +{ + struct pl330_dmac *pl330 = (struct pl330_dmac *) data; + struct pl330_info *pi = pl330->pinfo; + unsigned long flags; + int i; + + spin_lock_irqsave(&pl330->lock, flags); + + /* The DMAC itself gone nuts */ + if (pl330->dmac_tbd.reset_dmac) { + pl330->state = DYING; + /* Reset the manager too */ + pl330->dmac_tbd.reset_mngr = true; + /* Clear the reset flag */ + pl330->dmac_tbd.reset_dmac = false; + } + + if (pl330->dmac_tbd.reset_mngr) { + _stop(pl330->manager); + /* Reset all channels */ + pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1; + /* Clear the reset flag */ + pl330->dmac_tbd.reset_mngr = false; + } + + for (i = 0; i < pi->pcfg.num_chan; i++) { + + if (pl330->dmac_tbd.reset_chan & (1 << i)) { + struct pl330_thread *thrd = &pl330->channels[i]; + void __iomem *regs = pi->base; + enum pl330_op_err err; + + _stop(thrd); + + if (readl(regs + FSC) & (1 << thrd->id)) + err = PL330_ERR_FAIL; + else + err = PL330_ERR_ABORT; + + spin_unlock_irqrestore(&pl330->lock, flags); + + _callback(thrd->req[1 - thrd->lstenq].r, err); + _callback(thrd->req[thrd->lstenq].r, err); + + spin_lock_irqsave(&pl330->lock, flags); + + thrd->req[0].r = NULL; + thrd->req[1].r = NULL; + MARK_FREE(&thrd->req[0]); + MARK_FREE(&thrd->req[1]); + + /* Clear the reset flag */ + pl330->dmac_tbd.reset_chan &= ~(1 << i); + } + } + + spin_unlock_irqrestore(&pl330->lock, flags); + + return; +} + +/* Returns 1 if state was updated, 0 otherwise */ +int pl330_update(const struct pl330_info *pi) +{ + struct _pl330_req *rqdone; + struct pl330_dmac *pl330; + unsigned long flags; + void __iomem *regs; + u32 val; + int id, ev, ret = 0; + + if (!pi || !pi->pl330_data) + return 0; + + regs = pi->base; + pl330 = pi->pl330_data; + + spin_lock_irqsave(&pl330->lock, flags); + + val = readl(regs + FSM) & 0x1; + if (val) + pl330->dmac_tbd.reset_mngr = true; + else + pl330->dmac_tbd.reset_mngr = false; + + val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1); + pl330->dmac_tbd.reset_chan |= val; + if (val) { + int i = 0; + while (i < pi->pcfg.num_chan) { + if (val & (1 << i)) { + dev_info(pi->dev, + "Reset Channel-%d\t CS-%x FTC-%x\n", + i, readl(regs + CS(i)), + readl(regs + FTC(i))); + _stop(&pl330->channels[i]); + } + i++; + } + } + + /* Check which event happened i.e, thread notified */ + val = readl(regs + ES); + if (pi->pcfg.num_events < 32 + && val & ~((1 << pi->pcfg.num_events) - 1)) { + pl330->dmac_tbd.reset_dmac = true; + dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__); + ret = 1; + goto updt_exit; + } + + for (ev = 0; ev < pi->pcfg.num_events; ev++) { + if (val & (1 << ev)) { /* Event occured */ + struct pl330_thread *thrd; + u32 inten = readl(regs + INTEN); + int active; + + /* Clear the event */ + if (inten & (1 << ev)) + writel(1 << ev, regs + INTCLR); + + ret = 1; + + id = pl330->events[ev]; + + thrd = &pl330->channels[id]; + + active = _thrd_active(thrd); + if (!active) /* Aborted */ + continue; + + active -= 1; + + rqdone = &thrd->req[active]; + MARK_FREE(rqdone); + + /* Get going again ASAP */ + _start(thrd); + + /* For now, just make a list of callbacks to be done */ + list_add_tail(&rqdone->rqd, &pl330->req_done); + } + } + + /* Now that we are in no hurry, do the callbacks */ + while (!list_empty(&pl330->req_done)) { + rqdone = container_of(pl330->req_done.next, + struct _pl330_req, rqd); + + list_del_init(&rqdone->rqd); + + spin_unlock_irqrestore(&pl330->lock, flags); + _callback(rqdone->r, PL330_ERR_NONE); + spin_lock_irqsave(&pl330->lock, flags); + } + +updt_exit: + spin_unlock_irqrestore(&pl330->lock, flags); + + if (pl330->dmac_tbd.reset_dmac + || pl330->dmac_tbd.reset_mngr + || pl330->dmac_tbd.reset_chan) { + ret = 1; + tasklet_schedule(&pl330->tasks); + } + + return ret; +} +EXPORT_SYMBOL(pl330_update); + +int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op) +{ + struct pl330_thread *thrd = ch_id; + struct pl330_dmac *pl330; + unsigned long flags; + int ret = 0, active; + + if (!thrd || thrd->free || thrd->dmac->state == DYING) + return -EINVAL; + + pl330 = thrd->dmac; + + spin_lock_irqsave(&pl330->lock, flags); + + switch (op) { + case PL330_OP_FLUSH: + /* Make sure the channel is stopped */ + _stop(thrd); + + thrd->req[0].r = NULL; + thrd->req[1].r = NULL; + MARK_FREE(&thrd->req[0]); + MARK_FREE(&thrd->req[1]); + break; + + case PL330_OP_ABORT: + active = _thrd_active(thrd); + + /* Make sure the channel is stopped */ + _stop(thrd); + + /* ABORT is only for the active req */ + if (!active) + break; + + active--; + + thrd->req[active].r = NULL; + MARK_FREE(&thrd->req[active]); + + /* Start the next */ + case PL330_OP_START: + if (!_start(thrd)) + ret = -EIO; + break; + + default: + ret = -EINVAL; + } + + spin_unlock_irqrestore(&pl330->lock, flags); + return ret; +} +EXPORT_SYMBOL(pl330_chan_ctrl); + +int pl330_chan_status(void *ch_id, struct pl330_chanstatus *pstatus) +{ + struct pl330_thread *thrd = ch_id; + struct pl330_dmac *pl330; + struct pl330_info *pi; + void __iomem *regs; + int active; + u32 val; + + if (!pstatus || !thrd || thrd->free) + return -EINVAL; + + pl330 = thrd->dmac; + pi = pl330->pinfo; + regs = pi->base; + + /* The client should remove the DMAC and add again */ + if (pl330->state == DYING) + pstatus->dmac_halted = true; + else + pstatus->dmac_halted = false; + + val = readl(regs + FSC); + if (val & (1 << thrd->id)) + pstatus->faulting = true; + else + pstatus->faulting = false; + + active = _thrd_active(thrd); + + if (!active) { + /* Indicate that the thread is not running */ + pstatus->top_req = NULL; + pstatus->wait_req = NULL; + } else { + active--; + pstatus->top_req = thrd->req[active].r; + pstatus->wait_req = !IS_FREE(&thrd->req[1 - active]) + ? thrd->req[1 - active].r : NULL; + } + + pstatus->src_addr = readl(regs + SA(thrd->id)); + pstatus->dst_addr = readl(regs + DA(thrd->id)); + + return 0; +} +EXPORT_SYMBOL(pl330_chan_status); + +/* Reserve an event */ +static inline int _alloc_event(struct pl330_thread *thrd) +{ + struct pl330_dmac *pl330 = thrd->dmac; + struct pl330_info *pi = pl330->pinfo; + int ev; + + for (ev = 0; ev < pi->pcfg.num_events; ev++) + if (pl330->events[ev] == -1) { + pl330->events[ev] = thrd->id; + return ev; + } + + return -1; +} + +/* Upon success, returns IdentityToken for the + * allocated channel, NULL otherwise. + */ +void *pl330_request_channel(const struct pl330_info *pi) +{ + struct pl330_thread *thrd = NULL; + struct pl330_dmac *pl330; + unsigned long flags; + int chans, i; + + if (!pi || !pi->pl330_data) + return NULL; + + pl330 = pi->pl330_data; + + if (pl330->state == DYING) + return NULL; + + chans = pi->pcfg.num_chan; + + spin_lock_irqsave(&pl330->lock, flags); + + for (i = 0; i < chans; i++) { + thrd = &pl330->channels[i]; + if (thrd->free) { + thrd->ev = _alloc_event(thrd); + if (thrd->ev >= 0) { + thrd->free = false; + thrd->lstenq = 1; + thrd->req[0].r = NULL; + MARK_FREE(&thrd->req[0]); + thrd->req[1].r = NULL; + MARK_FREE(&thrd->req[1]); + break; + } + } + thrd = NULL; + } + + spin_unlock_irqrestore(&pl330->lock, flags); + + return thrd; +} +EXPORT_SYMBOL(pl330_request_channel); + +/* Release an event */ +static inline void _free_event(struct pl330_thread *thrd, int ev) +{ + struct pl330_dmac *pl330 = thrd->dmac; + struct pl330_info *pi = pl330->pinfo; + + /* If the event is valid and was held by the thread */ + if (ev >= 0 && ev < pi->pcfg.num_events + && pl330->events[ev] == thrd->id) + pl330->events[ev] = -1; +} + +void pl330_release_channel(void *ch_id) +{ + struct pl330_thread *thrd = ch_id; + struct pl330_dmac *pl330; + unsigned long flags; + + if (!thrd || thrd->free) + return; + + _stop(thrd); + + _callback(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT); + _callback(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT); + + pl330 = thrd->dmac; + + spin_lock_irqsave(&pl330->lock, flags); + _free_event(thrd, thrd->ev); + thrd->free = true; + spin_unlock_irqrestore(&pl330->lock, flags); +} +EXPORT_SYMBOL(pl330_release_channel); + +/* Initialize the structure for PL330 configuration, that can be used + * by the client driver the make best use of the DMAC + */ +static void read_dmac_config(struct pl330_info *pi) +{ + void __iomem *regs = pi->base; + u32 val; + + val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; + val &= CRD_DATA_WIDTH_MASK; + pi->pcfg.data_bus_width = 8 * (1 << val); + + val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; + val &= CRD_DATA_BUFF_MASK; + pi->pcfg.data_buf_dep = val + 1; + + val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; + val &= CR0_NUM_CHANS_MASK; + val += 1; + pi->pcfg.num_chan = val; + + val = readl(regs + CR0); + if (val & CR0_PERIPH_REQ_SET) { + val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; + val += 1; + pi->pcfg.num_peri = val; + pi->pcfg.peri_ns = readl(regs + CR4); + } else { + pi->pcfg.num_peri = 0; + } + + val = readl(regs + CR0); + if (val & CR0_BOOT_MAN_NS) + pi->pcfg.mode |= DMAC_MODE_NS; + else + pi->pcfg.mode &= ~DMAC_MODE_NS; + + val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; + val &= CR0_NUM_EVENTS_MASK; + val += 1; + pi->pcfg.num_events = val; + + pi->pcfg.irq_ns = readl(regs + CR3); + + pi->pcfg.periph_id = get_id(pi, PERIPH_ID); + pi->pcfg.pcell_id = get_id(pi, PCELL_ID); +} + +static inline void _reset_thread(struct pl330_thread *thrd) +{ + struct pl330_dmac *pl330 = thrd->dmac; + struct pl330_info *pi = pl330->pinfo; + + thrd->req[0].mc_cpu = pl330->mcode_cpu + + (thrd->id * pi->mcbufsz); + thrd->req[0].mc_bus = pl330->mcode_bus + + (thrd->id * pi->mcbufsz); + thrd->req[0].r = NULL; + MARK_FREE(&thrd->req[0]); + + thrd->req[1].mc_cpu = thrd->req[0].mc_cpu + + pi->mcbufsz / 2; + thrd->req[1].mc_bus = thrd->req[0].mc_bus + + pi->mcbufsz / 2; + thrd->req[1].r = NULL; + MARK_FREE(&thrd->req[1]); +} + +static int dmac_alloc_threads(struct pl330_dmac *pl330) +{ + struct pl330_info *pi = pl330->pinfo; + int chans = pi->pcfg.num_chan; + struct pl330_thread *thrd; + int i; + + /* Allocate 1 Manager and 'chans' Channel threads */ + pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), + GFP_KERNEL); + if (!pl330->channels) + return -ENOMEM; + + /* Init Channel threads */ + for (i = 0; i < chans; i++) { + thrd = &pl330->channels[i]; + thrd->id = i; + thrd->dmac = pl330; + _reset_thread(thrd); + thrd->free = true; + } + + /* MANAGER is indexed at the end */ + thrd = &pl330->channels[chans]; + thrd->id = chans; + thrd->dmac = pl330; + thrd->free = false; + pl330->manager = thrd; + + return 0; +} + +static int dmac_alloc_resources(struct pl330_dmac *pl330) +{ + struct pl330_info *pi = pl330->pinfo; + int chans = pi->pcfg.num_chan; + int ret; + + /* + * Alloc MicroCode buffer for 'chans' Channel threads. + * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) + */ + pl330->mcode_cpu = dma_alloc_coherent(pi->dev, + chans * pi->mcbufsz, + &pl330->mcode_bus, GFP_KERNEL); + if (!pl330->mcode_cpu) { + dev_err(pi->dev, "%s:%d Can't allocate memory!\n", + __func__, __LINE__); + return -ENOMEM; + } + + ret = dmac_alloc_threads(pl330); + if (ret) { + dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n", + __func__, __LINE__); + dma_free_coherent(pi->dev, + chans * pi->mcbufsz, + pl330->mcode_cpu, pl330->mcode_bus); + return ret; + } + + return 0; +} + +int pl330_add(struct pl330_info *pi) +{ + struct pl330_dmac *pl330; + void __iomem *regs; + int i, ret; + + if (!pi || !pi->dev) + return -EINVAL; + + /* If already added */ + if (pi->pl330_data) + return -EINVAL; + + /* + * If the SoC can perform reset on the DMAC, then do it + * before reading its configuration. + */ + if (pi->dmac_reset) + pi->dmac_reset(pi); + + regs = pi->base; + + /* Check if we can handle this DMAC */ + if (get_id(pi, PERIPH_ID) != PERIPH_ID_VAL + || get_id(pi, PCELL_ID) != PCELL_ID_VAL) { + dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n", + readl(regs + PERIPH_ID), readl(regs + PCELL_ID)); + return -EINVAL; + } + + /* Read the configuration of the DMAC */ + read_dmac_config(pi); + + if (pi->pcfg.num_events == 0) { + dev_err(pi->dev, "%s:%d Can't work without events!\n", + __func__, __LINE__); + return -EINVAL; + } + + pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL); + if (!pl330) { + dev_err(pi->dev, "%s:%d Can't allocate memory!\n", + __func__, __LINE__); + return -ENOMEM; + } + + /* Assign the info structure and private data */ + pl330->pinfo = pi; + pi->pl330_data = pl330; + + spin_lock_init(&pl330->lock); + + INIT_LIST_HEAD(&pl330->req_done); + + /* Use default MC buffer size if not provided */ + if (!pi->mcbufsz) + pi->mcbufsz = MCODE_BUFF_PER_REQ * 2; + + /* Mark all events as free */ + for (i = 0; i < pi->pcfg.num_events; i++) + pl330->events[i] = -1; + + /* Allocate resources needed by the DMAC */ + ret = dmac_alloc_resources(pl330); + if (ret) { + dev_err(pi->dev, "Unable to create channels for DMAC\n"); + kfree(pl330); + return ret; + } + + tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); + + pl330->state = INIT; + + return 0; +} +EXPORT_SYMBOL(pl330_add); + +static int dmac_free_threads(struct pl330_dmac *pl330) +{ + struct pl330_info *pi = pl330->pinfo; + int chans = pi->pcfg.num_chan; + struct pl330_thread *thrd; + int i; + + /* Release Channel threads */ + for (i = 0; i < chans; i++) { + thrd = &pl330->channels[i]; + pl330_release_channel((void *)thrd); + } + + /* Free memory */ + kfree(pl330->channels); + + return 0; +} + +static void dmac_free_resources(struct pl330_dmac *pl330) +{ + struct pl330_info *pi = pl330->pinfo; + int chans = pi->pcfg.num_chan; + + dmac_free_threads(pl330); + + dma_free_coherent(pi->dev, chans * pi->mcbufsz, + pl330->mcode_cpu, pl330->mcode_bus); +} + +void pl330_del(struct pl330_info *pi) +{ + struct pl330_dmac *pl330; + + if (!pi || !pi->pl330_data) + return; + + pl330 = pi->pl330_data; + + pl330->state = UNINIT; + + tasklet_kill(&pl330->tasks); + + /* Free DMAC resources */ + dmac_free_resources(pl330); + + kfree(pl330); + pi->pl330_data = NULL; +} +EXPORT_SYMBOL(pl330_del); diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index 1cf999ade4b..ba65f6eedca 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -266,13 +266,53 @@ static int vic_set_wake(unsigned int irq, unsigned int on) #endif /* CONFIG_PM */ static struct irq_chip vic_chip = { - .name = "VIC", - .ack = vic_ack_irq, - .mask = vic_mask_irq, - .unmask = vic_unmask_irq, - .set_wake = vic_set_wake, + .name = "VIC", + .ack = vic_ack_irq, + .mask = vic_mask_irq, + .unmask = vic_unmask_irq, + .set_wake = vic_set_wake, }; +static void __init vic_disable(void __iomem *base) +{ + writel(0, base + VIC_INT_SELECT); + writel(0, base + VIC_INT_ENABLE); + writel(~0, base + VIC_INT_ENABLE_CLEAR); + writel(0, base + VIC_IRQ_STATUS); + writel(0, base + VIC_ITCR); + writel(~0, base + VIC_INT_SOFT_CLEAR); +} + +static void __init vic_clear_interrupts(void __iomem *base) +{ + unsigned int i; + + writel(0, base + VIC_PL190_VECT_ADDR); + for (i = 0; i < 19; i++) { + unsigned int value; + + value = readl(base + VIC_PL190_VECT_ADDR); + writel(value, base + VIC_PL190_VECT_ADDR); + } +} + +static void __init vic_set_irq_sources(void __iomem *base, + unsigned int irq_start, u32 vic_sources) +{ + unsigned int i; + + for (i = 0; i < 32; i++) { + if (vic_sources & (1 << i)) { + unsigned int irq = irq_start + i; + + set_irq_chip(irq, &vic_chip); + set_irq_chip_data(irq, base); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + } + } +} + /* * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. * The original cell has 32 interrupts, while the modified one has 64, @@ -287,13 +327,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start, int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; /* Disable all interrupts initially. */ - - writel(0, base + VIC_INT_SELECT); - writel(0, base + VIC_INT_ENABLE); - writel(~0, base + VIC_INT_ENABLE_CLEAR); - writel(0, base + VIC_IRQ_STATUS); - writel(0, base + VIC_ITCR); - writel(~0, base + VIC_INT_SOFT_CLEAR); + vic_disable(base); /* * Make sure we clear all existing interrupts. The vector registers @@ -302,13 +336,8 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start, * the second base address, which is 0x20 in the page */ if (vic_2nd_block) { - writel(0, base + VIC_PL190_VECT_ADDR); - for (i = 0; i < 19; i++) { - unsigned int value; + vic_clear_interrupts(base); - value = readl(base + VIC_PL190_VECT_ADDR); - writel(value, base + VIC_PL190_VECT_ADDR); - } /* ST has 16 vectors as well, but we don't enable them by now */ for (i = 0; i < 16; i++) { void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); @@ -318,16 +347,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start, writel(32, base + VIC_PL190_DEF_VECT_ADDR); } - for (i = 0; i < 32; i++) { - if (vic_sources & (1 << i)) { - unsigned int irq = irq_start + i; - - set_irq_chip(irq, &vic_chip); - set_irq_chip_data(irq, base); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - } + vic_set_irq_sources(base, irq_start, vic_sources); } /** @@ -365,37 +385,14 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, } /* Disable all interrupts initially. */ + vic_disable(base); - writel(0, base + VIC_INT_SELECT); - writel(0, base + VIC_INT_ENABLE); - writel(~0, base + VIC_INT_ENABLE_CLEAR); - writel(0, base + VIC_IRQ_STATUS); - writel(0, base + VIC_ITCR); - writel(~0, base + VIC_INT_SOFT_CLEAR); - - /* - * Make sure we clear all existing interrupts - */ - writel(0, base + VIC_PL190_VECT_ADDR); - for (i = 0; i < 19; i++) { - unsigned int value; - - value = readl(base + VIC_PL190_VECT_ADDR); - writel(value, base + VIC_PL190_VECT_ADDR); - } + /* Make sure we clear all existing interrupts */ + vic_clear_interrupts(base); vic_init2(base); - for (i = 0; i < 32; i++) { - if (vic_sources & (1 << i)) { - unsigned int irq = irq_start + i; - - set_irq_chip(irq, &vic_chip); - set_irq_chip_data(irq, base); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - } + vic_set_irq_sources(base, irq_start, vic_sources); vic_pm_register(base, irq_start, resume_sources); } diff --git a/arch/arm/configs/am3517_evm_defconfig b/arch/arm/configs/am3517_evm_defconfig index 66a10b50d93..e4f4fb522ba 100644 --- a/arch/arm/configs/am3517_evm_defconfig +++ b/arch/arm/configs/am3517_evm_defconfig @@ -422,15 +422,29 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +CONFIG_CAN_BCM=y + +# +# CAN Device Drivers +# +CONFIG_CAN_VCAN=y +CONFIG_CAN_DEV=y +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_TI_HECC=y +# CONFIG_CAN_SJA1000 is not set + +# +# CAN USB interfaces +# +# CONFIG_CAN_EMS_USB is not set +CONFIG_CAN_DEBUG_DEVICES=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -# CONFIG_WIRELESS_OLD_REGULATORY is not set -# CONFIG_WIRELESS_EXT is not set # CONFIG_LIB80211 is not set # @@ -517,7 +531,75 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_OSD_INITIATOR is not set # CONFIG_ATA is not set # CONFIG_MD is not set -# CONFIG_NETDEVICES is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +CONFIG_TI_DAVINCI_EMAC=y +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set @@ -692,7 +774,57 @@ CONFIG_SSB_POSSIBLE=y # # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set +CONFIG_OMAP2_VRAM=y +CONFIG_OMAP2_VRFB=y +CONFIG_OMAP2_DSS=y +CONFIG_OMAP2_VRAM_SIZE=4 +CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y +# CONFIG_OMAP2_DSS_RFBI is not set +CONFIG_OMAP2_DSS_VENC=y +# CONFIG_OMAP2_DSS_SDI is not set +# CONFIG_OMAP2_DSS_DSI is not set +# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set +CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 +CONFIG_FB_OMAP2=y +CONFIG_FB_OMAP2_DEBUG_SUPPORT=y +# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set +CONFIG_FB_OMAP2_NUM_FBS=3 + +# +# OMAP2/3 Display Device Drivers +# +CONFIG_PANEL_GENERIC=y +# CONFIG_PANEL_SHARP_LS037V7DW01 is not set +CONFIG_PANEL_SHARP_LQ043T1DG01=y # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # diff --git a/arch/arm/configs/ams_delta_defconfig b/arch/arm/configs/ams_delta_defconfig index 3b3a3775bbf..6d8a0c891f8 100644 --- a/arch/arm/configs/ams_delta_defconfig +++ b/arch/arm/configs/ams_delta_defconfig @@ -47,6 +47,7 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_TASKSTATS is not set # CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set +CONFIG_TREE_PREEMPT_RCU=y # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED=y @@ -95,9 +96,8 @@ CONFIG_KMOD=y # Block layer # CONFIG_BLOCK=y -# CONFIG_LBD is not set +# CONFIG_LBDAF is not set # CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set # # IO Schedulers @@ -699,6 +699,7 @@ CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set +CONFIG_SERIO_AMS_DELTA=y # CONFIG_GAMEPORT is not set # @@ -835,7 +836,8 @@ CONFIG_DAB=y # # Graphics support # -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y # # Display device support @@ -1283,7 +1285,7 @@ CONFIG_DEBUG_PREEMPT=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_LIST is not set diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig new file mode 100644 index 00000000000..d5c088149e4 --- /dev/null +++ b/arch/arm/configs/cns3420vb_defconfig @@ -0,0 +1,831 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.34-rc6 +# Sun May 2 21:58:08 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_OPROFILE_ARMV6=y +CONFIG_OPROFILE_ARM11_CORE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set +# CONFIG_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_SLOW_WORK=y +# CONFIG_SLOW_WORK_DEBUG is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=m +# CONFIG_CFQ_GROUP_IOSCHED is not set +CONFIG_DEFAULT_DEADLINE=y +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="deadline" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +CONFIG_ARCH_CNS3XXX=y +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# CNS3XXX platform type +# +CONFIG_MACH_CNS3420VB=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_411920 is not set +CONFIG_ARM_GIC=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,38400 mem=128M root=/dev/mmcblk0p1 ro rootwait" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=20000 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +# CONFIG_SATA_PMP is not set +# CONFIG_ATA_SFF is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +CONFIG_FSCACHE=y +# CONFIG_FSCACHE_STATS is not set +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +# CONFIG_CACHEFILES is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LKDTM is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/configs/devkit8000_defconfig b/arch/arm/configs/devkit8000_defconfig index 61a817e8cf8..c7a68202fa3 100644 --- a/arch/arm/configs/devkit8000_defconfig +++ b/arch/arm/configs/devkit8000_defconfig @@ -1,13 +1,14 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.33-rc6 -# Thu Feb 4 15:42:56 2010 +# Linux kernel version: 2.6.34-rc2 +# Wed Mar 24 13:27:25 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y @@ -19,7 +20,9 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_CONSTRUCTORS=y @@ -60,11 +63,6 @@ CONFIG_RCU_FANOUT=32 CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set # CONFIG_CGROUPS is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set @@ -96,10 +94,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_COMPAT_BRK=y CONFIG_SLAB=y @@ -170,7 +172,7 @@ CONFIG_INLINE_WRITE_UNLOCK=y CONFIG_INLINE_WRITE_UNLOCK_IRQ=y # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set # CONFIG_MUTEX_SPIN_ON_OWNER is not set -# CONFIG_FREEZER is not set +CONFIG_FREEZER=y # # System Type @@ -181,6 +183,7 @@ CONFIG_MMU=y # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set @@ -190,7 +193,6 @@ CONFIG_MMU=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -207,21 +209,26 @@ CONFIG_MMU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set # CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set # # TI OMAP Implementations @@ -237,16 +244,20 @@ CONFIG_ARCH_OMAP3=y # OMAP Feature Selections # # CONFIG_OMAP_RESET_CLOCKS is not set -# CONFIG_OMAP_MUX is not set +CONFIG_OMAP_MUX=y +# CONFIG_OMAP_MUX_DEBUG is not set +CONFIG_OMAP_MUX_WARNINGS=y CONFIG_OMAP_MCBSP=y # CONFIG_OMAP_MBOX_FWK is not set # CONFIG_OMAP_MPU_TIMER is not set CONFIG_OMAP_32K_TIMER=y +# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set CONFIG_OMAP_32K_TIMER_HZ=128 CONFIG_OMAP_DM_TIMER=y # CONFIG_OMAP_PM_NONE is not set CONFIG_OMAP_PM_NOOP=y CONFIG_ARCH_OMAP3430=y +CONFIG_OMAP_PACKAGE_CUS=y # # OMAP Board Type @@ -295,6 +306,7 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_CPU_HAS_PMU=y # CONFIG_ARM_ERRATA_430973 is not set # CONFIG_ARM_ERRATA_458693 is not set # CONFIG_ARM_ERRATA_460075 is not set @@ -387,7 +399,14 @@ CONFIG_HAVE_AOUT=y # # Power management options # -# CONFIG_PM is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y @@ -395,7 +414,6 @@ CONFIG_NET=y # Networking options # CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set @@ -666,6 +684,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y @@ -717,6 +736,7 @@ CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_AX88796 is not set # CONFIG_SMC91X is not set +# CONFIG_TI_DAVINCI_EMAC is not set CONFIG_DM9000=y CONFIG_DM9000_DEBUGLEVEL=4 CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y @@ -863,6 +883,7 @@ CONFIG_SERIAL_8250_RSA=y # CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set @@ -891,6 +912,7 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_OCORES is not set CONFIG_I2C_OMAP=y # CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set # # External I2C/SMBus adapter drivers @@ -904,15 +926,9 @@ CONFIG_I2C_OMAP=y # # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set CONFIG_SPI=y # CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y @@ -944,10 +960,12 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set @@ -984,10 +1002,12 @@ CONFIG_SSB_POSSIBLE=y # Multifunction device drivers # CONFIG_MFD_CORE=y +# CONFIG_MFD_88PM860X is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set # CONFIG_TPS65010 is not set CONFIG_TWL4030_CORE=y CONFIG_TWL4030_POWER=y @@ -998,22 +1018,25 @@ CONFIG_TWL4030_CODEC=y # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set # CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_MC13783 is not set # CONFIG_AB3100_CORE is not set # CONFIG_EZX_PCAP is not set -# CONFIG_MFD_88PM8607 is not set # CONFIG_AB4500_CORE is not set CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set # CONFIG_REGULATOR_FIXED_VOLTAGE is not set # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set # CONFIG_REGULATOR_BQ24022 is not set # CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set CONFIG_REGULATOR_TWL4030=y # CONFIG_REGULATOR_LP3971 is not set @@ -1072,7 +1095,6 @@ CONFIG_OMAP2_DSS_VENC=y CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 CONFIG_FB_OMAP2=y CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set CONFIG_FB_OMAP2_NUM_FBS=3 # @@ -1080,7 +1102,9 @@ CONFIG_FB_OMAP2_NUM_FBS=3 # CONFIG_PANEL_GENERIC=y # CONFIG_PANEL_SHARP_LS037V7DW01 is not set -CONFIG_PANEL_INNOLUX_AT070TN83=y +# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set +# CONFIG_PANEL_TOPPOLY_TDO35S is not set +# CONFIG_PANEL_TPO_TD043MTEA1 is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -1136,6 +1160,7 @@ CONFIG_SND_ARM=y CONFIG_SND_SPI=y CONFIG_SND_USB=y # CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_UA101 is not set # CONFIG_SND_USB_CAIAQ is not set CONFIG_SND_SOC=y CONFIG_SND_OMAP_SOC=y @@ -1147,42 +1172,44 @@ CONFIG_SND_SOC_TWL4030=y # CONFIG_SOUND_PRIME is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y -CONFIG_HIDRAW=y +# CONFIG_HIDRAW is not set # # USB Input Devices # CONFIG_USB_HID=y # CONFIG_HID_PID is not set -CONFIG_USB_HIDDEV=y +# CONFIG_USB_HIDDEV is not set # # Special HID drivers # -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set # CONFIG_HID_DRAGONRISE is not set -CONFIG_HID_EZKEY=y +# CONFIG_HID_EZKEY is not set # CONFIG_HID_KYE is not set -CONFIG_HID_GYRATION=y +# CONFIG_HID_GYRATION is not set # CONFIG_HID_TWINHAN is not set # CONFIG_HID_KENSINGTON is not set -CONFIG_HID_LOGITECH=y -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set # CONFIG_HID_NTRIG is not set -CONFIG_HID_PANTHERLORD=y -# CONFIG_PANTHERLORD_FF is not set -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set # CONFIG_HID_GREENASIA is not set # CONFIG_HID_SMARTJOYPLUS is not set # CONFIG_HID_TOPSEED is not set @@ -1193,7 +1220,7 @@ CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=y -# CONFIG_USB_DEBUG is not set +CONFIG_USB_DEBUG=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # @@ -1202,7 +1229,7 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # CONFIG_USB_DEVICEFS is not set # CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set +CONFIG_USB_OTG=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y @@ -1230,15 +1257,15 @@ CONFIG_USB_MUSB_SOC=y # # OMAP 343x high speed USB support # -CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_PERIPHERAL is not set -# CONFIG_USB_MUSB_OTG is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set +CONFIG_USB_MUSB_OTG=y +CONFIG_USB_GADGET_MUSB_HDRC=y CONFIG_USB_MUSB_HDRC_HCD=y # CONFIG_MUSB_PIO_ONLY is not set CONFIG_USB_INVENTRA_DMA=y # CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_MUSB_DEBUG is not set +CONFIG_USB_MUSB_DEBUG=y # # USB Device Class drivers @@ -1291,7 +1318,6 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set @@ -1304,9 +1330,8 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set +CONFIG_USB_GADGET_DEBUG=y # CONFIG_USB_GADGET_DEBUG_FILES is not set CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_SELECTED=y @@ -1314,8 +1339,7 @@ CONFIG_USB_GADGET_SELECTED=y # CONFIG_USB_GADGET_ATMEL_USBA is not set # CONFIG_USB_GADGET_FSL_USB2 is not set # CONFIG_USB_GADGET_LH7A40X is not set -CONFIG_USB_GADGET_OMAP=y -CONFIG_USB_OMAP=y +# CONFIG_USB_GADGET_OMAP is not set # CONFIG_USB_GADGET_PXA25X is not set # CONFIG_USB_GADGET_R8A66597 is not set # CONFIG_USB_GADGET_PXA27X is not set @@ -1330,19 +1354,20 @@ CONFIG_USB_OMAP=y # CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_LANGWELL is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGET_DUALSPEED is not set +CONFIG_USB_GADGET_DUALSPEED=y # CONFIG_USB_ZERO is not set -CONFIG_USB_AUDIO=m -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -CONFIG_USB_ETH_EEM=y -CONFIG_USB_GADGETFS=m +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=y +# CONFIG_USB_ETH_RNDIS is not set +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_GADGETFS is not set # CONFIG_USB_FILE_STORAGE is not set # CONFIG_USB_MASS_STORAGE is not set -CONFIG_USB_G_SERIAL=m +# CONFIG_USB_G_SERIAL is not set # CONFIG_USB_MIDI_GADGET is not set -CONFIG_USB_G_PRINTER=m +# CONFIG_USB_G_PRINTER is not set # CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set # CONFIG_USB_G_MULTI is not set # @@ -1373,8 +1398,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=m # CONFIG_MMC_OMAP is not set CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set CONFIG_MMC_SPI=m # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y @@ -1392,11 +1415,11 @@ CONFIG_LEDS_GPIO_PLATFORM=y # CONFIG_LEDS_REGULATOR is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y # # LED Triggers # -CONFIG_LEDS_TRIGGERS=y # CONFIG_LEDS_TRIGGER_TIMER is not set CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set @@ -1580,6 +1603,7 @@ CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y # CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -1606,6 +1630,7 @@ CONFIG_SUNRPC_GSS=y CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig index 03f76cfc941..4b55dcb6002 100644 --- a/arch/arm/configs/mmp2_defconfig +++ b/arch/arm/configs/mmp2_defconfig @@ -1,13 +1,14 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.33-rc2 -# Tue Jan 5 13:55:22 2010 +# Linux kernel version: 2.6.34-rc5 +# Wed Apr 28 11:23:19 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y @@ -18,6 +19,7 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -32,6 +34,12 @@ CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -52,7 +60,6 @@ CONFIG_RCU_FANOUT=32 # CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y @@ -85,10 +92,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_COMPAT_BRK=y CONFIG_SLAB=y @@ -104,6 +115,7 @@ CONFIG_HAVE_CLK=y # # GCOV-based kernel profiling # +# CONFIG_GCOV_KERNEL is not set # CONFIG_SLOW_WORK is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y @@ -170,6 +182,7 @@ CONFIG_MMU=y # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set @@ -179,7 +192,6 @@ CONFIG_MMU=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -196,21 +208,26 @@ CONFIG_ARCH_MMP=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set # CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set # CONFIG_MACH_TAVOREVB is not set # @@ -218,8 +235,10 @@ CONFIG_ARCH_MMP=y # # CONFIG_MACH_ASPENITE is not set # CONFIG_MACH_ZYLONITE2 is not set +# CONFIG_MACH_AVENGERS_LITE is not set # CONFIG_MACH_TTC_DKB is not set CONFIG_MACH_FLINT=y +CONFIG_MACH_MARVELL_JASPER=y CONFIG_CPU_MMP2=y CONFIG_PLAT_PXA=y @@ -246,7 +265,10 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_TAUROS2=y CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_CPU_HAS_PMU=y # CONFIG_ARM_ERRATA_411920 is not set CONFIG_COMMON_CLKDEV=y @@ -298,7 +320,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M user_debug=255" +CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=128M user_debug=255" # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set @@ -338,7 +360,6 @@ CONFIG_NET=y # Networking options # CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set @@ -532,6 +553,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # CONFIG_SCSI_DMA is not set @@ -640,6 +662,7 @@ CONFIG_SERIAL_PXA=y CONFIG_SERIAL_PXA_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set @@ -667,6 +690,7 @@ CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_PXA=y # CONFIG_I2C_PXA_SLAVE is not set # CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set # # External I2C/SMBus adapter drivers @@ -679,15 +703,9 @@ CONFIG_I2C_PXA=y # # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set # @@ -702,13 +720,16 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -737,10 +758,12 @@ CONFIG_SSB_POSSIBLE=y # Multifunction device drivers # CONFIG_MFD_CORE=y +# CONFIG_MFD_88PM860X is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set # CONFIG_TPS65010 is not set # CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set @@ -749,24 +772,27 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set # CONFIG_PMIC_ADP5520 is not set +CONFIG_MFD_MAX8925=y # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_AB3100_CORE is not set -CONFIG_MFD_88PM8607=y CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set # CONFIG_REGULATOR_FIXED_VOLTAGE is not set # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set # CONFIG_REGULATOR_BQ24022 is not set # CONFIG_REGULATOR_MAX1586 is not set -CONFIG_REGULATOR_MAX8660=y +CONFIG_REGULATOR_MAX8649=y +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_MAX8925=y # CONFIG_REGULATOR_LP3971 is not set # CONFIG_REGULATOR_TPS65023 is not set # CONFIG_REGULATOR_TPS6507X is not set -CONFIG_REGULATOR_88PM8607=y # CONFIG_MEDIA_SUPPORT is not set # @@ -781,6 +807,7 @@ CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_PLATFORM is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GENERIC=y +CONFIG_BACKLIGHT_MAX8925=y # # Display device support @@ -821,6 +848,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_DS1374 is not set # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_MAX8925=y # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_X1205 is not set @@ -872,7 +900,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set # CONFIG_EXT4_FS is not set -CONFIG_EXT4_USE_FOR_EXT23=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y @@ -883,7 +910,7 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_NILFS2_FS is not set CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y +# CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set @@ -940,6 +967,7 @@ CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -967,6 +995,7 @@ CONFIG_SUNRPC_GSS=y CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set @@ -990,7 +1019,7 @@ CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set +CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set @@ -1032,6 +1061,7 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set # CONFIG_SYSCTL_SYSCALL_CHECK is not set @@ -1052,6 +1082,7 @@ CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_DYNAMIC_DEBUG=y # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1059,9 +1090,7 @@ CONFIG_ARM_UNWIND=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set -CONFIG_DEBUG_LL=y -# CONFIG_EARLY_PRINTK is not set -# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_LL is not set # CONFIG_OC_ETM is not set # diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig index d6ad9217732..94dfcf0aa67 100644 --- a/arch/arm/configs/omap3_defconfig +++ b/arch/arm/configs/omap3_defconfig @@ -1,13 +1,14 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.33-rc5 -# Tue Jan 26 11:05:31 2010 +# Linux kernel version: 2.6.34-rc7 +# Thu May 13 10:54:43 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y @@ -19,7 +20,9 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y CONFIG_OPROFILE_ARMV6=y CONFIG_OPROFILE_ARM11_CORE=y CONFIG_OPROFILE_ARMV7=y @@ -63,12 +66,7 @@ CONFIG_RCU_FANOUT=32 # CONFIG_TREE_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set +CONFIG_LOG_BUF_SHIFT=16 # CONFIG_CGROUPS is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set @@ -100,17 +98,21 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y CONFIG_OPROFILE=y CONFIG_HAVE_OPROFILE=y CONFIG_KPROBES=y @@ -189,6 +191,7 @@ CONFIG_MMU=y # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set @@ -198,7 +201,6 @@ CONFIG_MMU=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -215,21 +217,26 @@ CONFIG_MMU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set # CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set # # TI OMAP Implementations @@ -254,6 +261,7 @@ CONFIG_OMAP_MCBSP=y # CONFIG_OMAP_MBOX_FWK is not set # CONFIG_OMAP_MPU_TIMER is not set CONFIG_OMAP_32K_TIMER=y +# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set CONFIG_OMAP_32K_TIMER_HZ=128 CONFIG_OMAP_DM_TIMER=y # CONFIG_OMAP_PM_NONE is not set @@ -264,7 +272,7 @@ CONFIG_MACH_OMAP_GENERIC=y # OMAP Core Type # CONFIG_ARCH_OMAP2420=y -# CONFIG_ARCH_OMAP2430 is not set +CONFIG_ARCH_OMAP2430=y CONFIG_ARCH_OMAP3430=y CONFIG_OMAP_PACKAGE_CBB=y CONFIG_OMAP_PACKAGE_CUS=y @@ -276,8 +284,9 @@ CONFIG_OMAP_PACKAGE_CBP=y CONFIG_MACH_OMAP2_TUSB6010=y CONFIG_MACH_OMAP_H4=y CONFIG_MACH_OMAP_APOLLON=y -# CONFIG_MACH_OMAP_2430SDP is not set +CONFIG_MACH_OMAP_2430SDP=y CONFIG_MACH_OMAP3_BEAGLE=y +CONFIG_MACH_DEVKIT8000=y CONFIG_MACH_OMAP_LDP=y CONFIG_MACH_OVERO=y CONFIG_MACH_OMAP3EVM=y @@ -294,6 +303,7 @@ CONFIG_MACH_OMAP_ZOOM2=y CONFIG_MACH_OMAP_ZOOM3=y CONFIG_MACH_CM_T35=y CONFIG_MACH_IGEP0020=y +CONFIG_MACH_SBC3530=y CONFIG_MACH_OMAP_3630SDP=y CONFIG_MACH_OMAP_4430SDP=y # CONFIG_OMAP3_EMU is not set @@ -330,11 +340,16 @@ CONFIG_ARM_THUMBEE=y # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_CACHE_L2X0=y CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_CPU_HAS_PMU=y # CONFIG_ARM_ERRATA_411920 is not set # CONFIG_ARM_ERRATA_430973 is not set # CONFIG_ARM_ERRATA_458693 is not set # CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_PL310_ERRATA_588369 is not set CONFIG_ARM_GIC=y CONFIG_COMMON_CLKDEV=y @@ -368,6 +383,7 @@ CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set # CONFIG_HIGHMEM is not set +CONFIG_HW_PERF_EVENTS=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set @@ -390,7 +406,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" +CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyS2,115200" # CONFIG_XIP_KERNEL is not set CONFIG_KEXEC=y CONFIG_ATAGS_PROC=y @@ -443,7 +459,8 @@ CONFIG_BINFMT_MISC=y # CONFIG_PM=y CONFIG_PM_DEBUG=y -CONFIG_PM_VERBOSE=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_VERBOSE is not set CONFIG_CAN_PM_TRACE=y CONFIG_PM_SLEEP=y CONFIG_SUSPEND=y @@ -451,6 +468,7 @@ CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y # CONFIG_APM_EMULATION is not set CONFIG_PM_RUNTIME=y +CONFIG_PM_OPS=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y @@ -458,7 +476,6 @@ CONFIG_NET=y # Networking options # CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y CONFIG_XFRM_USER=y @@ -544,7 +561,6 @@ CONFIG_NETFILTER_ADVANCED=y # # CONFIG_NET_PKTGEN is not set # CONFIG_NET_TCPPROBE is not set -# CONFIG_NET_DROP_MONITOR is not set # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set # CONFIG_IRDA is not set @@ -584,7 +600,7 @@ CONFIG_CFG80211=y # CONFIG_CFG80211_REG_DEBUG is not set CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_DEBUGFS is not set -CONFIG_WIRELESS_OLD_REGULATORY=y +# CONFIG_CFG80211_INTERNAL_REGDB is not set CONFIG_CFG80211_WEXT=y CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_LIB80211=y @@ -676,7 +692,6 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set # CONFIG_MTD_ARM_INTEGRATOR is not set -CONFIG_MTD_OMAP_NOR=y # CONFIG_MTD_PLATRAM is not set # @@ -754,6 +769,7 @@ CONFIG_MISC_DEVICES=y # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set # CONFIG_DS1682 is not set # CONFIG_TI_DAC7512 is not set # CONFIG_C2PORT is not set @@ -773,6 +789,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y @@ -839,12 +856,14 @@ CONFIG_SMSC_PHY=y # CONFIG_NATIONAL_PHY is not set # CONFIG_STE10XP is not set # CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_AX88796 is not set CONFIG_SMC91X=y +# CONFIG_TI_DAVINCI_EMAC is not set # CONFIG_DM9000 is not set # CONFIG_ENC28J60 is not set # CONFIG_ETHOC is not set @@ -881,6 +900,7 @@ CONFIG_LIBERTAS_USB=y CONFIG_LIBERTAS_SDIO=y # CONFIG_LIBERTAS_SPI is not set CONFIG_LIBERTAS_DEBUG=y +# CONFIG_LIBERTAS_MESH is not set # CONFIG_P54_COMMON is not set # CONFIG_RT2X00 is not set # CONFIG_WL12XX is not set @@ -902,6 +922,7 @@ CONFIG_USB_NET_AX8817X=y CONFIG_USB_NET_CDCETHER=y # CONFIG_USB_NET_CDC_EEM is not set # CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC75XX is not set # CONFIG_USB_NET_SMSC95XX is not set # CONFIG_USB_NET_GL620A is not set CONFIG_USB_NET_NET1080=y @@ -917,6 +938,8 @@ CONFIG_USB_EPSON2888=y CONFIG_USB_KC2190=y CONFIG_USB_NET_ZAURUS=y # CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_SIERRA_NET is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -1012,6 +1035,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set CONFIG_INPUT_TWL4030_PWRBUTTON=y +# CONFIG_INPUT_TWL4030_VIBRA is not set # CONFIG_INPUT_UINPUT is not set # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set @@ -1055,6 +1079,7 @@ CONFIG_SERIAL_8250_RSA=y # CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set @@ -1083,6 +1108,7 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_OCORES is not set CONFIG_I2C_OMAP=y # CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set # # External I2C/SMBus adapter drivers @@ -1096,15 +1122,9 @@ CONFIG_I2C_OMAP=y # # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set CONFIG_SPI=y # CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y @@ -1136,10 +1156,12 @@ CONFIG_GPIO_SYSFS=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set @@ -1204,10 +1226,11 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -1262,7 +1285,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_THERMAL is not set CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y +# CONFIG_WATCHDOG_NOWAYOUT is not set # # Watchdog Device Drivers @@ -1270,6 +1293,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y # CONFIG_SOFT_WATCHDOG is not set CONFIG_OMAP_WATCHDOG=y CONFIG_TWL4030_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set # # USB-based Watchdog Cards @@ -1286,14 +1310,16 @@ CONFIG_SSB_POSSIBLE=y # Multifunction device drivers # CONFIG_MFD_CORE=y +# CONFIG_MFD_88PM860X is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set # CONFIG_TPS65010 is not set -# CONFIG_MENELAUS is not set +CONFIG_MENELAUS=y CONFIG_TWL4030_CORE=y -# CONFIG_TWL4030_POWER is not set +CONFIG_TWL4030_POWER=y CONFIG_TWL4030_CODEC=y # CONFIG_MFD_TMIO is not set # CONFIG_MFD_T7L66XB is not set @@ -1301,27 +1327,30 @@ CONFIG_TWL4030_CODEC=y # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set # CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_MC13783 is not set # CONFIG_AB3100_CORE is not set # CONFIG_EZX_PCAP is not set -# CONFIG_MFD_88PM8607 is not set # CONFIG_AB4500_CORE is not set CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set -CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set # CONFIG_REGULATOR_BQ24022 is not set # CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set CONFIG_REGULATOR_TWL4030=y # CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_TPS65023=y +CONFIG_REGULATOR_TPS6507X=y # CONFIG_MEDIA_SUPPORT is not set # @@ -1333,9 +1362,9 @@ CONFIG_FB=y CONFIG_FIRMWARE_EDID=y # CONFIG_FB_DDC is not set # CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set # CONFIG_FB_SYS_FILLRECT is not set # CONFIG_FB_SYS_COPYAREA is not set @@ -1358,19 +1387,12 @@ CONFIG_FB_TILEBLITTING=y # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_BROADSHEET is not set -CONFIG_FB_OMAP=y +# CONFIG_FB_OMAP is not set CONFIG_FB_OMAP_LCD_VGA=y -# CONFIG_FB_OMAP_031M3R is not set -# CONFIG_FB_OMAP_048M3R is not set -CONFIG_FB_OMAP_079M3R=y -# CONFIG_FB_OMAP_092M9R is not set -# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set -# CONFIG_FB_OMAP_LCD_MIPID is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2 # CONFIG_OMAP2_DSS is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_L4F00242T03 is not set # CONFIG_LCD_LMS283GF05 is not set # CONFIG_LCD_LTV350QV is not set # CONFIG_LCD_ILI9320 is not set @@ -1448,6 +1470,7 @@ CONFIG_SND_ARM=y CONFIG_SND_SPI=y CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_UA101 is not set # CONFIG_SND_USB_CAIAQ is not set CONFIG_SND_SOC=y CONFIG_SND_OMAP_SOC=y @@ -1479,6 +1502,7 @@ CONFIG_USB_HID=y # # Special HID drivers # +# CONFIG_HID_3M_PCT is not set # CONFIG_HID_A4TECH is not set # CONFIG_HID_APPLE is not set # CONFIG_HID_BELKIN is not set @@ -1492,13 +1516,18 @@ CONFIG_USB_HID=y # CONFIG_HID_TWINHAN is not set # CONFIG_HID_KENSINGTON is not set # CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set # CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set # CONFIG_HID_MONTEREY is not set # CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set # CONFIG_HID_PANTHERLORD is not set # CONFIG_HID_PETALYNX is not set +# CONFIG_HID_QUANTA is not set # CONFIG_HID_SAMSUNG is not set # CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set # CONFIG_HID_SUNPLUS is not set # CONFIG_HID_GREENASIA is not set # CONFIG_HID_SMARTJOYPLUS is not set @@ -1545,6 +1574,10 @@ CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SOC=y # +# OMAP 243x high speed USB support +# + +# # OMAP 343x high speed USB support # # CONFIG_USB_MUSB_HOST is not set @@ -1608,7 +1641,6 @@ CONFIG_USB_LIBUSUAL=y # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set @@ -1621,7 +1653,6 @@ CONFIG_USB_LIBUSUAL=y # CONFIG_USB_IOWARRIOR is not set CONFIG_USB_TEST=y # CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DEBUG=y CONFIG_USB_GADGET_DEBUG_FILES=y @@ -1659,6 +1690,7 @@ CONFIG_USB_ZERO=m # CONFIG_USB_MIDI_GADGET is not set # CONFIG_USB_G_PRINTER is not set # CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set # CONFIG_USB_G_MULTI is not set # @@ -1686,10 +1718,8 @@ CONFIG_SDIO_UART=y # MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set +CONFIG_MMC_OMAP=y CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set # CONFIG_MMC_SPI is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y @@ -1707,11 +1737,11 @@ CONFIG_LEDS_GPIO_PLATFORM=y # CONFIG_LEDS_REGULATOR is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y # # LED Triggers # -CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set @@ -1751,6 +1781,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_BQ32K is not set +CONFIG_RTC_DRV_TWL92330=y CONFIG_RTC_DRV_TWL4030=y # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set @@ -1799,6 +1830,11 @@ CONFIG_RTC_DRV_TWL4030=y # CONFIG_STAGING is not set # +# CBUS support +# +# CONFIG_CBUS is not set + +# # File systems # CONFIG_EXT2_FS=y @@ -1826,6 +1862,7 @@ CONFIG_INOTIFY_USER=y CONFIG_QUOTA=y # CONFIG_QUOTA_NETLINK_INTERFACE is not set CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set CONFIG_QUOTA_TREE=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y @@ -1897,6 +1934,7 @@ CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y # CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -1924,6 +1962,7 @@ CONFIG_SUNRPC_GSS=y CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set @@ -2024,6 +2063,7 @@ CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_PROVE_LOCKING=y +# CONFIG_PROVE_RCU is not set CONFIG_LOCKDEP=y CONFIG_LOCK_STAT=y # CONFIG_DEBUG_LOCKDEP is not set @@ -2053,13 +2093,9 @@ CONFIG_DEBUG_INFO=y # CONFIG_LATENCYTOP is not set # CONFIG_SYSCTL_SYSCALL_CHECK is not set # CONFIG_PAGE_POISONING is not set -CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_TRACING=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set @@ -2199,7 +2235,7 @@ CONFIG_CRYPTO_LZO=y # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y -CONFIG_BINARY_PRINTF=y +# CONFIG_BINARY_PRINTF is not set # # Library routines @@ -2222,3 +2258,4 @@ CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/configs/omap3_evm_defconfig b/arch/arm/configs/omap3_evm_defconfig index a6dd6d1af80..b02e371b099 100644 --- a/arch/arm/configs/omap3_evm_defconfig +++ b/arch/arm/configs/omap3_evm_defconfig @@ -911,7 +911,56 @@ CONFIG_DAB=y # # CONFIG_VGASTATE is not set CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_FB is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set +CONFIG_OMAP2_VRAM=y +CONFIG_OMAP2_VRFB=y +CONFIG_OMAP2_DSS=y +CONFIG_OMAP2_VRAM_SIZE=4 +# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set +# CONFIG_OMAP2_DSS_RFBI is not set +CONFIG_OMAP2_DSS_VENC=y +# CONFIG_OMAP2_DSS_SDI is not set +# CONFIG_OMAP2_DSS_DSI is not set +# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set +CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 +CONFIG_FB_OMAP2=y +# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set +# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set +CONFIG_FB_OMAP2_NUM_FBS=3 + +# +# OMAP2/3 Display Device Drivers +# +CONFIG_PANEL_GENERIC=y +# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set +CONFIG_PANEL_SHARP_LS037V7DW01=y # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # diff --git a/arch/arm/configs/omap3_stalker_lks_defconfig b/arch/arm/configs/omap3_stalker_lks_defconfig new file mode 100644 index 00000000000..83365f075ce --- /dev/null +++ b/arch/arm/configs/omap3_stalker_lks_defconfig @@ -0,0 +1,1691 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.34-rc7 +# Mon May 17 16:57:28 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y + +# +# TI OMAP Implementations +# +CONFIG_ARCH_OMAP_OTG=y +# CONFIG_ARCH_OMAP1 is not set +CONFIG_ARCH_OMAP2PLUS=y +# CONFIG_ARCH_OMAP2 is not set +CONFIG_ARCH_OMAP3=y +# CONFIG_ARCH_OMAP4 is not set + +# +# OMAP Feature Selections +# +CONFIG_OMAP_RESET_CLOCKS=y +CONFIG_OMAP_MUX=y +# CONFIG_OMAP_MUX_DEBUG is not set +CONFIG_OMAP_MUX_WARNINGS=y +# CONFIG_OMAP_MCBSP is not set +# CONFIG_OMAP_MBOX_FWK is not set +# CONFIG_OMAP_MPU_TIMER is not set +CONFIG_OMAP_32K_TIMER=y +# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set +CONFIG_OMAP_32K_TIMER_HZ=128 +CONFIG_OMAP_DM_TIMER=y +# CONFIG_OMAP_PM_NONE is not set +CONFIG_OMAP_PM_NOOP=y +CONFIG_ARCH_OMAP3430=y +CONFIG_OMAP_PACKAGE_CUS=y + +# +# OMAP Board Type +# +# CONFIG_MACH_OMAP3_BEAGLE is not set +# CONFIG_MACH_DEVKIT8000 is not set +# CONFIG_MACH_OMAP_LDP is not set +# CONFIG_MACH_OVERO is not set +# CONFIG_MACH_OMAP3EVM is not set +# CONFIG_MACH_OMAP3517EVM is not set +# CONFIG_MACH_OMAP3_PANDORA is not set +# CONFIG_MACH_OMAP3_TOUCHBOOK is not set +# CONFIG_MACH_OMAP_3430SDP is not set +# CONFIG_MACH_NOKIA_RX51 is not set +# CONFIG_MACH_OMAP_ZOOM2 is not set +# CONFIG_MACH_OMAP_ZOOM3 is not set +# CONFIG_MACH_CM_T35 is not set +# CONFIG_MACH_IGEP0020 is not set +CONFIG_MACH_SBC3530=y +# CONFIG_MACH_OMAP_3630SDP is not set +# CONFIG_OMAP3_EMU is not set +# CONFIG_OMAP3_SDRC_AC_TIMING is not set + +# +# Processor Type +# +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=128 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_VERBOSE is not set +CONFIG_CAN_PM_TRACE=y +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_OMAP2 is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_ONENAND=y +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +# CONFIG_MTD_ONENAND_GENERIC is not set +CONFIG_MTD_ONENAND_OMAP2=y +# CONFIG_MTD_ONENAND_OTP is not set +# CONFIG_MTD_ONENAND_2X_PROGRAM is not set +# CONFIG_MTD_ONENAND_SIM is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_TI_DAVINCI_EMAC is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +CONFIG_SMSC911X=y +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +CONFIG_KEYBOARD_TWL4030=y +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_OMAP=y +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_OMAP24XX=y +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +CONFIG_GPIO_TWL4030=y +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_OMAP_WATCHDOG=y +# CONFIG_TWL4030_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +CONFIG_TWL4030_CORE=y +# CONFIG_TWL4030_POWER is not set +# CONFIG_TWL4030_CODEC is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB4500_CORE is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_TWL4030=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_FB is not set +# CONFIG_OMAP2_DSS is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_SOC=y + +# +# OMAP 343x high speed USB support +# +# CONFIG_USB_MUSB_HOST is not set +# CONFIG_USB_MUSB_PERIPHERAL is not set +CONFIG_USB_MUSB_OTG=y +CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_USB_MUSB_HDRC_HCD=y +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_USB_INVENTRA_DMA=y +# CONFIG_USB_TI_CPPI_DMA is not set +# CONFIG_USB_MUSB_DEBUG is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=y +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +# CONFIG_USB_ZERO_HNPTEST is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_ISP1301_OMAP is not set +# CONFIG_USB_ULPI is not set +CONFIG_TWL4030_USB=y +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_OMAP is not set +CONFIG_MMC_OMAP_HS=y +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig index a96bca290cd..1fb04567f6e 100644 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ b/arch/arm/configs/omap_4430sdp_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Sun Dec 6 23:37:45 2009 +# Linux kernel version: 2.6.34-rc7 +# Wed May 12 12:26:05 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -9,6 +9,7 @@ CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_HAVE_PROC_CPU=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y @@ -20,6 +21,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -33,28 +35,33 @@ CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set # # RCU Subsystem # CONFIG_TREE_RCU=y # CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=32 # CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set # CONFIG_CGROUPS is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set @@ -64,6 +71,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -85,10 +93,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y @@ -127,14 +139,41 @@ CONFIG_LBDAF=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y # CONFIG_FREEZER is not set # @@ -146,6 +185,7 @@ CONFIG_MMU=y # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set @@ -155,7 +195,6 @@ CONFIG_MMU=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -163,6 +202,7 @@ CONFIG_MMU=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_KIRKWOOD is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set @@ -171,25 +211,32 @@ CONFIG_MMU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set # CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set # # TI OMAP Implementations # # CONFIG_ARCH_OMAP1 is not set +CONFIG_ARCH_OMAP2PLUS=y # CONFIG_ARCH_OMAP2 is not set # CONFIG_ARCH_OMAP3 is not set CONFIG_ARCH_OMAP4=y @@ -205,10 +252,6 @@ CONFIG_OMAP_MCBSP=y CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_LL_DEBUG_NONE is not set # CONFIG_OMAP_PM_NONE is not set CONFIG_OMAP_PM_NOOP=y @@ -243,13 +286,16 @@ CONFIG_CPU_CP15_MMU=y # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y CONFIG_CACHE_L2X0=y CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_CPU_HAS_PMU=y # CONFIG_ARM_ERRATA_430973 is not set # CONFIG_ARM_ERRATA_458693 is not set # CONFIG_ARM_ERRATA_460075 is not set CONFIG_PL310_ERRATA_588369=y CONFIG_ARM_GIC=y +CONFIG_COMMON_CLKDEV=y # # Bus support @@ -280,6 +326,7 @@ CONFIG_HZ=128 # CONFIG_THUMB2_KERNEL is not set CONFIG_AEABI=y CONFIG_OABI_COMPAT=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set # CONFIG_HIGHMEM is not set @@ -294,8 +341,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 # CONFIG_LEDS is not set @@ -343,7 +388,83 @@ CONFIG_BINFMT_MISC=y # # CONFIG_PM is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_NET is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_UNIX is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -360,17 +481,24 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set # CONFIG_MTD is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set # CONFIG_MG_DISK is not set # CONFIG_MISC_DEVICES is not set CONFIG_HAVE_IDE=y @@ -379,12 +507,56 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set # CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +CONFIG_KS8851=y +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set # CONFIG_PHONE is not set # @@ -393,6 +565,7 @@ CONFIG_HAVE_IDE=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -445,8 +618,10 @@ CONFIG_SERIAL_8250_RSA=y # # Non-8250 serial port support # +# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set @@ -456,8 +631,58 @@ CONFIG_HW_RANDOM=y # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_OMAP=y +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_OMAP24XX=y +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set # # PPS support @@ -471,10 +696,17 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_TWL4030 is not set +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -483,6 +715,9 @@ CONFIG_GPIOLIB=y # # SPI GPIO expanders: # +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set # # AC97 GPIO expanders: @@ -492,7 +727,15 @@ CONFIG_GPIOLIB=y # CONFIG_HWMON is not set # CONFIG_THERMAL is not set CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set CONFIG_OMAP_WATCHDOG=y +# CONFIG_TWL4030_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y # @@ -504,15 +747,46 @@ CONFIG_SSB_POSSIBLE=y # Multifunction device drivers # # CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +CONFIG_TWL4030_CORE=y +# CONFIG_TWL4030_POWER is not set +# CONFIG_TWL4030_CODEC is not set # CONFIG_MFD_TMIO is not set # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set -# CONFIG_REGULATOR is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB4500_CORE is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_TWL4030=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set # CONFIG_MEDIA_SUPPORT is not set # @@ -536,12 +810,94 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_SOUND is not set # CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set -# CONFIG_MMC is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_OMAP is not set +CONFIG_MMC_OMAP_HS=y # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +CONFIG_RTC_DRV_TWL4030=y +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set @@ -564,9 +920,10 @@ CONFIG_EXT3_FS=y CONFIG_JBD=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set +CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set CONFIG_FILE_LOCKING=y @@ -575,7 +932,9 @@ CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set CONFIG_QUOTA_TREE=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y @@ -624,6 +983,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set # CONFIG_CRAMFS is not set # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -634,6 +994,28 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types @@ -696,6 +1078,7 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set # # Kernel hacking @@ -750,13 +1133,11 @@ CONFIG_FRAME_POINTER=y # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set # CONFIG_PAGE_POISONING is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set -# CONFIG_BRANCH_PROFILE_NONE is not set -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -765,6 +1146,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_ERRORS is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set # # Security options @@ -772,7 +1154,11 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # @@ -791,6 +1177,7 @@ CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCRYPT is not set CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set @@ -889,3 +1276,4 @@ CONFIG_DECOMPRESS_GZIP=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig index 473f9e13f08..56d4928cd4c 100644 --- a/arch/arm/configs/rx51_defconfig +++ b/arch/arm/configs/rx51_defconfig @@ -784,6 +784,7 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_STOWAWAY is not set CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_TWL4030=y # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -809,6 +810,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_TWL4030_PWRBUTTON=y CONFIG_INPUT_UINPUT=m # @@ -1110,7 +1112,40 @@ CONFIG_RADIO_ADAPTERS=y # # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y + +# Frame buffer hardware drivers +# +CONFIG_OMAP2_VRAM=y +CONFIG_OMAP2_VRFB=y +CONFIG_OMAP2_DSS=y +CONFIG_OMAP2_VRAM_SIZE=0 +# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set +# CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set +# CONFIG_OMAP2_DSS_DPI is not set +# CONFIG_OMAP2_DSS_RFBI is not set +# CONFIG_OMAP2_DSS_VENC is not set +CONFIG_OMAP2_DSS_SDI=y +# CONFIG_OMAP2_DSS_DSI is not set +# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set +CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 +CONFIG_FB_OMAP2=y +CONFIG_FB_OMAP2_DEBUG_SUPPORT=y +CONFIG_FB_OMAP2_NUM_FBS=3 + +# +# OMAP2/3 Display Device Drivers +# +# CONFIG_PANEL_GENERIC is not set +# CONFIG_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set +# CONFIG_PANEL_TOPPOLY_TDO35S is not set +# CONFIG_PANEL_TPO_TD043MTEA1 is not set +CONFIG_PANEL_ACX565AKM=y + # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -1127,6 +1162,8 @@ CONFIG_DISPLAY_SUPPORT=y # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y CONFIG_SOUND=y # CONFIG_SOUND_OSS_CORE is not set CONFIG_SND=y diff --git a/arch/arm/configs/spear300_defconfig b/arch/arm/configs/spear300_defconfig new file mode 100644 index 00000000000..35e64d1cb75 --- /dev/null +++ b/arch/arm/configs/spear300_defconfig @@ -0,0 +1,773 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.32 +# Tue Mar 23 14:36:23 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +CONFIG_PLAT_SPEAR=y +CONFIG_ARCH_SPEAR3XX=y +# CONFIG_ARCH_SPEAR6XX is not set +CONFIG_MACH_SPEAR300=y +# CONFIG_MACH_SPEAR310 is not set +# CONFIG_MACH_SPEAR320 is not set +CONFIG_BOARD_SPEAR300_EVB=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +CONFIG_GPIO_PL061=y + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/spear310_defconfig b/arch/arm/configs/spear310_defconfig new file mode 100644 index 00000000000..cbbfd290bba --- /dev/null +++ b/arch/arm/configs/spear310_defconfig @@ -0,0 +1,775 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.32 +# Tue Mar 23 14:37:01 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +CONFIG_PLAT_SPEAR=y +CONFIG_ARCH_SPEAR3XX=y +# CONFIG_ARCH_SPEAR6XX is not set +# CONFIG_MACH_SPEAR300 is not set +CONFIG_MACH_SPEAR310=y +# CONFIG_MACH_SPEAR320 is not set +# CONFIG_BOARD_SPEAR300_EVB is not set +CONFIG_BOARD_SPEAR310_EVB=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +CONFIG_GPIO_PL061=y + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/spear320_defconfig b/arch/arm/configs/spear320_defconfig new file mode 100644 index 00000000000..2ae3c110a21 --- /dev/null +++ b/arch/arm/configs/spear320_defconfig @@ -0,0 +1,775 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.32 +# Tue Mar 23 14:37:12 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +CONFIG_PLAT_SPEAR=y +CONFIG_ARCH_SPEAR3XX=y +# CONFIG_ARCH_SPEAR6XX is not set +# CONFIG_MACH_SPEAR300 is not set +# CONFIG_MACH_SPEAR310 is not set +CONFIG_MACH_SPEAR320=y +# CONFIG_BOARD_SPEAR300_EVB is not set +CONFIG_BOARD_SPEAR320_EVB=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +CONFIG_GPIO_PL061=y + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/spear600_defconfig b/arch/arm/configs/spear600_defconfig new file mode 100644 index 00000000000..c85a02924ec --- /dev/null +++ b/arch/arm/configs/spear600_defconfig @@ -0,0 +1,760 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.32 +# Tue Mar 23 14:37:26 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +CONFIG_PLAT_SPEAR=y +# CONFIG_ARCH_SPEAR3XX is not set +CONFIG_ARCH_SPEAR6XX=y +# CONFIG_MACH_SPEAR300 is not set +# CONFIG_MACH_SPEAR310 is not set +# CONFIG_MACH_SPEAR320 is not set +# CONFIG_BOARD_SPEAR300_EVB is not set +CONFIG_MACH_SPEAR600=y +CONFIG_BOARD_SPEAR600_EVB=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y +# CONFIG_ARTHUR is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +CONFIG_GPIO_PL061=y + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/stamp9g20_defconfig b/arch/arm/configs/stamp9g20_defconfig new file mode 100644 index 00000000000..06a8293c61c --- /dev/null +++ b/arch/arm/configs/stamp9g20_defconfig @@ -0,0 +1,1456 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.34-rc1 +# Wed Mar 17 16:38:03 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +# CONFIG_TREE_RCU is not set +CONFIG_TREE_PREEMPT_RCU=y +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +CONFIG_ARCH_AT91=y +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_HAVE_AT91_USART3=y +CONFIG_HAVE_AT91_USART4=y +CONFIG_HAVE_AT91_USART5=y + +# +# Atmel AT91 System-on-Chip +# +# CONFIG_ARCH_AT91RM9200 is not set +# CONFIG_ARCH_AT91SAM9260 is not set +# CONFIG_ARCH_AT91SAM9261 is not set +# CONFIG_ARCH_AT91SAM9G10 is not set +# CONFIG_ARCH_AT91SAM9263 is not set +# CONFIG_ARCH_AT91SAM9RL is not set +CONFIG_ARCH_AT91SAM9G20=y +# CONFIG_ARCH_AT91SAM9G45 is not set +# CONFIG_ARCH_AT91CAP9 is not set +# CONFIG_ARCH_AT572D940HF is not set +# CONFIG_ARCH_AT91X40 is not set +CONFIG_AT91_PMC_UNIT=y + +# +# AT91SAM9G20 Board Type +# +# CONFIG_MACH_AT91SAM9G20EK is not set +# CONFIG_MACH_AT91SAM9G20EK_2MMC is not set +# CONFIG_MACH_CPU9G20 is not set +CONFIG_MACH_PORTUXG20=y +CONFIG_MACH_STAMP9G20=y + +# +# AT91 Board Options +# + +# +# AT91 Feature Selections +# +CONFIG_AT91_PROGRAMMABLE_CLOCKS=y +CONFIG_AT91_SLOW_CLOCK=y +CONFIG_AT91_TIMER_HZ=100 +CONFIG_AT91_EARLY_DBGU=y +# CONFIG_AT91_EARLY_USART0 is not set +# CONFIG_AT91_EARLY_USART1 is not set +# CONFIG_AT91_EARLY_USART2 is not set +# CONFIG_AT91_EARLY_USART3 is not set +# CONFIG_AT91_EARLY_USART4 is not set +# CONFIG_AT91_EARLY_USART5 is not set + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +CONFIG_MTD_NAND_ATMEL=y +# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set +CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y +# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +CONFIG_MACB=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +CONFIG_I2C_GPIO=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_ATMEL=y +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# +CONFIG_W1=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_DS2482 is not set +# CONFIG_W1_MASTER_DS1WM is not set +CONFIG_W1_MASTER_GPIO=y + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=y +# CONFIG_W1_SLAVE_SMEM is not set +CONFIG_W1_SLAVE_DS2431=y +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_AT91SAM9X_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB4500_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +CONFIG_USB_GADGET_AT91=y +CONFIG_USB_AT91=m +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_DUALSPEED is not set +CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_AT91 is not set +CONFIG_MMC_ATMELMCI=y +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_RTC_DRV_AT91SAM9_RTT=0 +CONFIG_RTC_DRV_AT91SAM9_GPBR=0 +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=y +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index e8ddec2cb15..a0162fa9456 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -24,7 +24,7 @@ * strex/ldrex monitor on some implementations. The reason we can use it for * atomic_set() is the clrex or dummy strex done on every exception return. */ -#define atomic_read(v) ((v)->counter) +#define atomic_read(v) (*(volatile int *)&(v)->counter) #define atomic_set(v,i) (((v)->counter) = (i)) #if __LINUX_ARM_ARCH__ >= 6 diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h index 04be3bdf46b..c0f4e7bf22d 100644 --- a/arch/arm/include/asm/hardware/arm_timer.h +++ b/arch/arm/include/asm/hardware/arm_timer.h @@ -1,21 +1,30 @@ #ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H #define __ASM_ARM_HARDWARE_ARM_TIMER_H -#define TIMER_LOAD 0x00 -#define TIMER_VALUE 0x04 -#define TIMER_CTRL 0x08 -#define TIMER_CTRL_ONESHOT (1 << 0) -#define TIMER_CTRL_32BIT (1 << 1) -#define TIMER_CTRL_DIV1 (0 << 2) -#define TIMER_CTRL_DIV16 (1 << 2) -#define TIMER_CTRL_DIV256 (2 << 2) -#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ -#define TIMER_CTRL_PERIODIC (1 << 6) -#define TIMER_CTRL_ENABLE (1 << 7) +/* + * ARM timer implementation, found in Integrator, Versatile and Realview + * platforms. Not all platforms support all registers and bits in these + * registers, so we mark them with A for Integrator AP, C for Integrator + * CP, V for Versatile and R for Realview. + * + * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview + * can have 16-bit or 32-bit selectable via a bit in the control register. + */ +#define TIMER_LOAD 0x00 /* ACVR rw */ +#define TIMER_VALUE 0x04 /* ACVR ro */ +#define TIMER_CTRL 0x08 /* ACVR rw */ +#define TIMER_CTRL_ONESHOT (1 << 0) /* CVR */ +#define TIMER_CTRL_32BIT (1 << 1) /* CVR */ +#define TIMER_CTRL_DIV1 (0 << 2) /* ACVR */ +#define TIMER_CTRL_DIV16 (1 << 2) /* ACVR */ +#define TIMER_CTRL_DIV256 (2 << 2) /* ACVR */ +#define TIMER_CTRL_IE (1 << 5) /* VR */ +#define TIMER_CTRL_PERIODIC (1 << 6) /* ACVR */ +#define TIMER_CTRL_ENABLE (1 << 7) /* ACVR */ -#define TIMER_INTCLR 0x0c -#define TIMER_RIS 0x10 -#define TIMER_MIS 0x14 -#define TIMER_BGLOAD 0x18 +#define TIMER_INTCLR 0x0c /* ACVR wo */ +#define TIMER_RIS 0x10 /* CVR ro */ +#define TIMER_MIS 0x14 /* CVR ro */ +#define TIMER_BGLOAD 0x18 /* CVR rw */ #endif diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index cdb9022716f..6bcba48800f 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -21,6 +21,9 @@ #define __ASM_ARM_HARDWARE_L2X0_H #define L2X0_CACHE_ID 0x000 +#define L2X0_CACHE_ID_PART_MASK (0xf << 6) +#define L2X0_CACHE_ID_PART_L210 (1 << 6) +#define L2X0_CACHE_ID_PART_L310 (3 << 6) #define L2X0_CACHE_TYPE 0x004 #define L2X0_CTRL 0x100 #define L2X0_AUX_CTRL 0x104 diff --git a/arch/arm/include/asm/hardware/icst.h b/arch/arm/include/asm/hardware/icst.h new file mode 100644 index 00000000000..10382a3dcec --- /dev/null +++ b/arch/arm/include/asm/hardware/icst.h @@ -0,0 +1,59 @@ +/* + * arch/arm/include/asm/hardware/icst.h + * + * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Support functions for calculating clocks/divisors for the ICST + * clock generators. See http://www.icst.com/ for more information + * on these devices. + */ +#ifndef ASMARM_HARDWARE_ICST_H +#define ASMARM_HARDWARE_ICST_H + +struct icst_params { + unsigned long ref; + unsigned long vco_max; /* inclusive */ + unsigned long vco_min; /* exclusive */ + unsigned short vd_min; /* inclusive */ + unsigned short vd_max; /* inclusive */ + unsigned char rd_min; /* inclusive */ + unsigned char rd_max; /* inclusive */ + const unsigned char *s2div; /* chip specific s2div array */ + const unsigned char *idx2s; /* chip specific idx2s array */ +}; + +struct icst_vco { + unsigned short v; + unsigned char r; + unsigned char s; +}; + +unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco); +struct icst_vco icst_hz_to_vco(const struct icst_params *p, unsigned long freq); + +/* + * ICST307 VCO frequency must be between 6MHz and 200MHz (3.3 or 5V). + * This frequency is pre-output divider. + */ +#define ICST307_VCO_MIN 6000000 +#define ICST307_VCO_MAX 200000000 + +extern const unsigned char icst307_s2div[]; +extern const unsigned char icst307_idx2s[]; + +/* + * ICST525 VCO frequency must be between 10MHz and 200MHz (3V) or 320MHz (5V). + * This frequency is pre-output divider. + */ +#define ICST525_VCO_MIN 10000000 +#define ICST525_VCO_MAX_3V 200000000 +#define ICST525_VCO_MAX_5V 320000000 + +extern const unsigned char icst525_s2div[]; +extern const unsigned char icst525_idx2s[]; + +#endif diff --git a/arch/arm/include/asm/hardware/icst307.h b/arch/arm/include/asm/hardware/icst307.h deleted file mode 100644 index 554f128a104..00000000000 --- a/arch/arm/include/asm/hardware/icst307.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * arch/arm/include/asm/hardware/icst307.h - * - * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Support functions for calculating clocks/divisors for the ICS307 - * clock generators. See http://www.icst.com/ for more information - * on these devices. - * - * This file is similar to the icst525.h file - */ -#ifndef ASMARM_HARDWARE_ICST307_H -#define ASMARM_HARDWARE_ICST307_H - -struct icst307_params { - unsigned long ref; - unsigned long vco_max; /* inclusive */ - unsigned short vd_min; /* inclusive */ - unsigned short vd_max; /* inclusive */ - unsigned char rd_min; /* inclusive */ - unsigned char rd_max; /* inclusive */ -}; - -struct icst307_vco { - unsigned short v; - unsigned char r; - unsigned char s; -}; - -unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco); -struct icst307_vco icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq); -struct icst307_vco icst307_ps_to_vco(const struct icst307_params *p, unsigned long period); - -#endif diff --git a/arch/arm/include/asm/hardware/icst525.h b/arch/arm/include/asm/hardware/icst525.h deleted file mode 100644 index 58f0dc43e2e..00000000000 --- a/arch/arm/include/asm/hardware/icst525.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/include/asm/hardware/icst525.h - * - * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Support functions for calculating clocks/divisors for the ICST525 - * clock generators. See http://www.icst.com/ for more information - * on these devices. - */ -#ifndef ASMARM_HARDWARE_ICST525_H -#define ASMARM_HARDWARE_ICST525_H - -struct icst525_params { - unsigned long ref; - unsigned long vco_max; /* inclusive */ - unsigned short vd_min; /* inclusive */ - unsigned short vd_max; /* inclusive */ - unsigned char rd_min; /* inclusive */ - unsigned char rd_max; /* inclusive */ -}; - -struct icst525_vco { - unsigned short v; - unsigned char r; - unsigned char s; -}; - -unsigned long icst525_khz(const struct icst525_params *p, struct icst525_vco vco); -struct icst525_vco icst525_khz_to_vco(const struct icst525_params *p, unsigned long freq); -struct icst525_vco icst525_ps_to_vco(const struct icst525_params *p, unsigned long period); - -#endif diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h new file mode 100644 index 00000000000..575fa8186ca --- /dev/null +++ b/arch/arm/include/asm/hardware/pl330.h @@ -0,0 +1,217 @@ +/* linux/include/asm/hardware/pl330.h + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __PL330_CORE_H +#define __PL330_CORE_H + +#define PL330_MAX_CHAN 8 +#define PL330_MAX_IRQS 32 +#define PL330_MAX_PERI 32 + +enum pl330_srccachectrl { + SCCTRL0 = 0, /* Noncacheable and nonbufferable */ + SCCTRL1, /* Bufferable only */ + SCCTRL2, /* Cacheable, but do not allocate */ + SCCTRL3, /* Cacheable and bufferable, but do not allocate */ + SINVALID1, + SINVALID2, + SCCTRL6, /* Cacheable write-through, allocate on reads only */ + SCCTRL7, /* Cacheable write-back, allocate on reads only */ +}; + +enum pl330_dstcachectrl { + DCCTRL0 = 0, /* Noncacheable and nonbufferable */ + DCCTRL1, /* Bufferable only */ + DCCTRL2, /* Cacheable, but do not allocate */ + DCCTRL3, /* Cacheable and bufferable, but do not allocate */ + DINVALID1 = 8, + DINVALID2, + DCCTRL6, /* Cacheable write-through, allocate on writes only */ + DCCTRL7, /* Cacheable write-back, allocate on writes only */ +}; + +/* Populated by the PL330 core driver for DMA API driver's info */ +struct pl330_config { + u32 periph_id; + u32 pcell_id; +#define DMAC_MODE_NS (1 << 0) + unsigned int mode; + unsigned int data_bus_width:10; /* In number of bits */ + unsigned int data_buf_dep:10; + unsigned int num_chan:4; + unsigned int num_peri:6; + u32 peri_ns; + unsigned int num_events:6; + u32 irq_ns; +}; + +/* Handle to the DMAC provided to the PL330 core */ +struct pl330_info { + /* Owning device */ + struct device *dev; + /* Size of MicroCode buffers for each channel. */ + unsigned mcbufsz; + /* ioremap'ed address of PL330 registers. */ + void __iomem *base; + /* Client can freely use it. */ + void *client_data; + /* PL330 core data, Client must not touch it. */ + void *pl330_data; + /* Populated by the PL330 core driver during pl330_add */ + struct pl330_config pcfg; + /* + * If the DMAC has some reset mechanism, then the + * client may want to provide pointer to the method. + */ + void (*dmac_reset)(struct pl330_info *pi); +}; + +enum pl330_byteswap { + SWAP_NO = 0, + SWAP_2, + SWAP_4, + SWAP_8, + SWAP_16, +}; + +/** + * Request Configuration. + * The PL330 core does not modify this and uses the last + * working configuration if the request doesn't provide any. + * + * The Client may want to provide this info only for the + * first request and a request with new settings. + */ +struct pl330_reqcfg { + /* Address Incrementing */ + unsigned dst_inc:1; + unsigned src_inc:1; + + /* + * For now, the SRC & DST protection levels + * and burst size/length are assumed same. + */ + bool nonsecure; + bool privileged; + bool insnaccess; + unsigned brst_len:5; + unsigned brst_size:3; /* in power of 2 */ + + enum pl330_dstcachectrl dcctl; + enum pl330_srccachectrl scctl; + enum pl330_byteswap swap; +}; + +/* + * One cycle of DMAC operation. + * There may be more than one xfer in a request. + */ +struct pl330_xfer { + u32 src_addr; + u32 dst_addr; + /* Size to xfer */ + u32 bytes; + /* + * Pointer to next xfer in the list. + * The last xfer in the req must point to NULL. + */ + struct pl330_xfer *next; +}; + +/* The xfer callbacks are made with one of these arguments. */ +enum pl330_op_err { + /* The all xfers in the request were success. */ + PL330_ERR_NONE, + /* If req aborted due to global error. */ + PL330_ERR_ABORT, + /* If req failed due to problem with Channel. */ + PL330_ERR_FAIL, +}; + +enum pl330_reqtype { + MEMTOMEM, + MEMTODEV, + DEVTOMEM, + DEVTODEV, +}; + +/* A request defining Scatter-Gather List ending with NULL xfer. */ +struct pl330_req { + enum pl330_reqtype rqtype; + /* Index of peripheral for the xfer. */ + unsigned peri:5; + /* Unique token for this xfer, set by the client. */ + void *token; + /* Callback to be called after xfer. */ + void (*xfer_cb)(void *token, enum pl330_op_err err); + /* If NULL, req will be done at last set parameters. */ + struct pl330_reqcfg *cfg; + /* Pointer to first xfer in the request. */ + struct pl330_xfer *x; +}; + +/* + * To know the status of the channel and DMAC, the client + * provides a pointer to this structure. The PL330 core + * fills it with current information. + */ +struct pl330_chanstatus { + /* + * If the DMAC engine halted due to some error, + * the client should remove-add DMAC. + */ + bool dmac_halted; + /* + * If channel is halted due to some error, + * the client should ABORT/FLUSH and START the channel. + */ + bool faulting; + /* Location of last load */ + u32 src_addr; + /* Location of last store */ + u32 dst_addr; + /* + * Pointer to the currently active req, NULL if channel is + * inactive, even though the requests may be present. + */ + struct pl330_req *top_req; + /* Pointer to req waiting second in the queue if any. */ + struct pl330_req *wait_req; +}; + +enum pl330_chan_op { + /* Start the channel */ + PL330_OP_START, + /* Abort the active xfer */ + PL330_OP_ABORT, + /* Stop xfer and flush queue */ + PL330_OP_FLUSH, +}; + +extern int pl330_add(struct pl330_info *); +extern void pl330_del(struct pl330_info *pi); +extern int pl330_update(const struct pl330_info *pi); +extern void pl330_release_channel(void *ch_id); +extern void *pl330_request_channel(const struct pl330_info *pi); +extern int pl330_chan_status(void *ch_id, struct pl330_chanstatus *pstatus); +extern int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op); +extern int pl330_submit_req(void *ch_id, struct pl330_req *r); + +#endif /* __PL330_CORE_H */ diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h new file mode 100644 index 00000000000..a101f10bb5b --- /dev/null +++ b/arch/arm/include/asm/hardware/sp810.h @@ -0,0 +1,59 @@ +/* + * arch/arm/include/asm/hardware/sp810.h + * + * ARM PrimeXsys System Controller SP810 header file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARM_SP810_H +#define __ASM_ARM_SP810_H + +#include <linux/io.h> + +/* sysctl registers offset */ +#define SCCTRL 0x000 +#define SCSYSSTAT 0x004 +#define SCIMCTRL 0x008 +#define SCIMSTAT 0x00C +#define SCXTALCTRL 0x010 +#define SCPLLCTRL 0x014 +#define SCPLLFCTRL 0x018 +#define SCPERCTRL0 0x01C +#define SCPERCTRL1 0x020 +#define SCPEREN 0x024 +#define SCPERDIS 0x028 +#define SCPERCLKEN 0x02C +#define SCPERSTAT 0x030 +#define SCSYSID0 0xEE0 +#define SCSYSID1 0xEE4 +#define SCSYSID2 0xEE8 +#define SCSYSID3 0xEEC +#define SCITCR 0xF00 +#define SCITIR0 0xF04 +#define SCITIR1 0xF08 +#define SCITOR 0xF0C +#define SCCNTCTRL 0xF10 +#define SCCNTDATA 0xF14 +#define SCCNTSTEP 0xF18 +#define SCPERIPHID0 0xFE0 +#define SCPERIPHID1 0xFE4 +#define SCPERIPHID2 0xFE8 +#define SCPERIPHID3 0xFEC +#define SCPCELLID0 0xFF0 +#define SCPCELLID1 0xFF4 +#define SCPCELLID2 0xFF8 +#define SCPCELLID3 0xFFC + +static inline void sysctl_soft_reset(void __iomem *base) +{ + /* writing any value to SCSYSSTAT reg will reset system */ + writel(0, base + SCSYSSTAT); +} + +#endif /* __ASM_ARM_SP810_H */ diff --git a/arch/arm/include/asm/ioctls.h b/arch/arm/include/asm/ioctls.h index a91d8a1523c..7f0b6d13296 100644 --- a/arch/arm/include/asm/ioctls.h +++ b/arch/arm/include/asm/ioctls.h @@ -53,6 +53,9 @@ #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ +#define TIOCGRS485 0x542E +#define TIOCSRS485 0x542F + #define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ #define FIOCLEX 0x5451 #define FIOASYNC 0x5452 diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h index c4b2ea3fbe4..e51b1e81df0 100644 --- a/arch/arm/include/asm/kmap_types.h +++ b/arch/arm/include/asm/kmap_types.h @@ -20,6 +20,7 @@ enum km_type { KM_SOFTIRQ1, KM_L1_CACHE, KM_L2_CACHE, + KM_KDB, KM_TYPE_NR }; diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index a38bdc7afa3..52f0da1e97d 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -8,10 +8,16 @@ * published by the Free Software Foundation. */ +#ifndef __ASM_MACH_PCI_H +#define __ASM_MACH_PCI_H + struct pci_sys_data; struct pci_bus; struct hw_pci { +#ifdef CONFIG_PCI_DOMAINS + int domain; +#endif struct list_head buses; int nr_controllers; int (*setup)(int nr, struct pci_sys_data *); @@ -26,6 +32,9 @@ struct hw_pci { * Per-controller structure */ struct pci_sys_data { +#ifdef CONFIG_PCI_DOMAINS + int domain; +#endif struct list_head node; int busnr; /* primary bus number */ u64 mem_offset; /* bus->cpu memory mapping offset */ @@ -70,3 +79,5 @@ extern int pci_v3_setup(int nr, struct pci_sys_data *); extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *); extern void pci_v3_preinit(void); extern void pci_v3_postinit(void); + +#endif /* __ASM_MACH_PCI_H */ diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h index 8bffc3ff3ac..35d408f6dcc 100644 --- a/arch/arm/include/asm/mach/time.h +++ b/arch/arm/include/asm/mach/time.h @@ -38,7 +38,7 @@ struct sys_timer { void (*init)(void); void (*suspend)(void); void (*resume)(void); -#ifndef CONFIG_GENERIC_TIME +#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET unsigned long (*offset)(void); #endif }; diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h index 47980118d0a..92e2a833693 100644 --- a/arch/arm/include/asm/pci.h +++ b/arch/arm/include/asm/pci.h @@ -4,8 +4,23 @@ #ifdef __KERNEL__ #include <asm-generic/pci-dma-compat.h> +#include <asm/mach/pci.h> /* for pci_sys_data */ #include <mach/hardware.h> /* for PCIBIOS_MIN_* */ +#ifdef CONFIG_PCI_DOMAINS +static inline int pci_domain_nr(struct pci_bus *bus) +{ + struct pci_sys_data *root = bus->sysdata; + + return root->domain; +} + +static inline int pci_proc_domain(struct pci_bus *bus) +{ + return pci_domain_nr(bus); +} +#endif /* CONFIG_PCI_DOMAINS */ + #ifdef CONFIG_PCI_HOST_ITE8152 /* ITE bridge requires setting latency timer to avoid early bus access termination by PIC bus mater devices diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h index 49e3049aba3..48837e6d888 100644 --- a/arch/arm/include/asm/perf_event.h +++ b/arch/arm/include/asm/perf_event.h @@ -28,4 +28,21 @@ set_perf_event_pending(void) * same indexes here for consistency. */ #define PERF_EVENT_INDEX_OFFSET 1 +/* ARM perf PMU IDs for use by internal perf clients. */ +enum arm_perf_pmu_ids { + ARM_PERF_PMU_ID_XSCALE1 = 0, + ARM_PERF_PMU_ID_XSCALE2, + ARM_PERF_PMU_ID_V6, + ARM_PERF_PMU_ID_V6MP, + ARM_PERF_PMU_ID_CA8, + ARM_PERF_PMU_ID_CA9, + ARM_NUM_PMU_IDS, +}; + +extern enum arm_perf_pmu_ids +armpmu_get_pmu_id(void); + +extern int +armpmu_get_max_events(void); + #endif /* __ARM_PERF_EVENT_H__ */ diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 11397687f42..ab68cf1ef80 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -314,7 +314,7 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; } __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED) #define pgprot_writecombine(prot) \ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE) -#if __LINUX_ARM_ARCH__ >= 7 +#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE #define pgprot_dmacoherent(prot) \ __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE) #else diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h index 2829b9f981a..8ccea012722 100644 --- a/arch/arm/include/asm/pmu.h +++ b/arch/arm/include/asm/pmu.h @@ -12,33 +12,33 @@ #ifndef __ARM_PMU_H__ #define __ARM_PMU_H__ -#ifdef CONFIG_CPU_HAS_PMU - -struct pmu_irqs { - const int *irqs; - int num_irqs; +enum arm_pmu_type { + ARM_PMU_DEVICE_CPU = 0, + ARM_NUM_PMU_DEVICES, }; +#ifdef CONFIG_CPU_HAS_PMU + /** * reserve_pmu() - reserve the hardware performance counters * * Reserve the hardware performance counters in the system for exclusive use. - * The 'struct pmu_irqs' for the system is returned on success, ERR_PTR() + * The platform_device for the system is returned on success, ERR_PTR() * encoded error on failure. */ -extern const struct pmu_irqs * -reserve_pmu(void); +extern struct platform_device * +reserve_pmu(enum arm_pmu_type device); /** * release_pmu() - Relinquish control of the performance counters * * Release the performance counters and allow someone else to use them. * Callers must have disabled the counters and released IRQs before calling - * this. The 'struct pmu_irqs' returned from reserve_pmu() must be passed as + * this. The platform_device returned from reserve_pmu() must be passed as * a cookie. */ extern int -release_pmu(const struct pmu_irqs *irqs); +release_pmu(struct platform_device *pdev); /** * init_pmu() - Initialise the PMU. @@ -48,24 +48,26 @@ release_pmu(const struct pmu_irqs *irqs); * the actual hardware initialisation. */ extern int -init_pmu(void); +init_pmu(enum arm_pmu_type device); #else /* CONFIG_CPU_HAS_PMU */ -static inline const struct pmu_irqs * -reserve_pmu(void) +#include <linux/err.h> + +static inline struct platform_device * +reserve_pmu(enum arm_pmu_type device) { return ERR_PTR(-ENODEV); } static inline int -release_pmu(const struct pmu_irqs *irqs) +release_pmu(struct platform_device *pdev) { return -ENODEV; } static inline int -init_pmu(void) +init_pmu(enum arm_pmu_type device) { return -ENODEV; } diff --git a/arch/arm/include/asm/scatterlist.h b/arch/arm/include/asm/scatterlist.h index ca0a37d0340..bcda59f3994 100644 --- a/arch/arm/include/asm/scatterlist.h +++ b/arch/arm/include/asm/scatterlist.h @@ -4,24 +4,8 @@ #include <asm/memory.h> #include <asm/types.h> -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; /* buffer offset */ - dma_addr_t dma_address; /* dma address */ - unsigned int length; /* length */ -}; +#include <asm-generic/scatterlist.h> -/* - * These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns, or alternatively stop on the first sg_dma_len(sg) which - * is 0. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) +#undef ARCH_HAS_SG_CHAIN #endif /* _ASMARM_SCATTERLIST_H */ diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index e0d763be184..3d05190797c 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -82,7 +82,7 @@ struct secondary_data { extern struct secondary_data secondary_data; extern int __cpu_disable(void); -extern int mach_cpu_disable(unsigned int cpu); +extern int platform_cpu_disable(unsigned int cpu); extern void __cpu_die(unsigned int cpu); extern void cpu_die(void); diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 4ace45ec3ef..5f4f4800273 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -141,7 +141,7 @@ extern unsigned int user_debug; #ifdef CONFIG_ARCH_HAS_BARRIERS #include <mach/barriers.h> -#elif __LINUX_ARM_ARCH__ >= 7 || defined(CONFIG_SMP) +#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP) #define mb() do { dsb(); outer_sync(); } while (0) #define rmb() dmb() #define wmb() mb() diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index b74970ec02c..763e29fa853 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -141,7 +141,7 @@ extern void vfp_flush_hwstate(struct thread_info *); #define TIF_SYSCALL_TRACE 8 #define TIF_POLLING_NRFLAG 16 #define TIF_USING_IWMMXT 17 -#define TIF_MEMDIE 18 +#define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define TIF_FREEZE 19 #define TIF_RESTORE_SIGMASK 20 diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index bd397e0b663..c6273a3bfc2 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -527,6 +527,9 @@ static void __init pcibios_init_hw(struct hw_pci *hw) if (!sys) panic("PCI: unable to allocate sys data!"); +#ifdef CONFIG_PCI_DOMAINS + sys->domain = hw->domain; +#endif sys->hw = hw; sys->busnr = busnr; sys->swizzle = hw->swizzle; diff --git a/arch/arm/kernel/dma.c b/arch/arm/kernel/dma.c index 7d5b9fb01e7..2c4a185f92c 100644 --- a/arch/arm/kernel/dma.c +++ b/arch/arm/kernel/dma.c @@ -16,6 +16,8 @@ #include <linux/spinlock.h> #include <linux/errno.h> #include <linux/scatterlist.h> +#include <linux/seq_file.h> +#include <linux/proc_fs.h> #include <asm/dma.h> @@ -264,3 +266,37 @@ int get_dma_residue(unsigned int chan) return ret; } EXPORT_SYMBOL(get_dma_residue); + +#ifdef CONFIG_PROC_FS +static int proc_dma_show(struct seq_file *m, void *v) +{ + int i; + + for (i = 0 ; i < MAX_DMA_CHANNELS ; i++) { + dma_t *dma = dma_channel(i); + if (dma && dma->lock) + seq_printf(m, "%2d: %s\n", i, dma->device_id); + } + return 0; +} + +static int proc_dma_open(struct inode *inode, struct file *file) +{ + return single_open(file, proc_dma_show, NULL); +} + +static const struct file_operations proc_dma_operations = { + .open = proc_dma_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init proc_dma_init(void) +{ + proc_create("dma", 0, NULL, &proc_dma_operations); + return 0; +} + +__initcall(proc_dma_init); +#endif diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c index a5b846b9895..c868a886411 100644 --- a/arch/arm/kernel/kgdb.c +++ b/arch/arm/kernel/kgdb.c @@ -98,6 +98,11 @@ sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task) gdb_regs[_CPSR] = thread_regs->ARM_cpsr; } +void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc) +{ + regs->ARM_pc = pc; +} + static int compiled_break; int kgdb_arch_handle_exception(int exception_vector, int signo, diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 9e70f2053f9..c45768614c8 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -16,7 +16,9 @@ #include <linux/interrupt.h> #include <linux/kernel.h> +#include <linux/module.h> #include <linux/perf_event.h> +#include <linux/platform_device.h> #include <linux/spinlock.h> #include <linux/uaccess.h> @@ -26,7 +28,7 @@ #include <asm/pmu.h> #include <asm/stacktrace.h> -static const struct pmu_irqs *pmu_irqs; +static struct platform_device *pmu_device; /* * Hardware lock to serialize accesses to PMU registers. Needed for the @@ -67,8 +69,18 @@ struct cpu_hw_events { }; DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); +/* PMU names. */ +static const char *arm_pmu_names[] = { + [ARM_PERF_PMU_ID_XSCALE1] = "xscale1", + [ARM_PERF_PMU_ID_XSCALE2] = "xscale2", + [ARM_PERF_PMU_ID_V6] = "v6", + [ARM_PERF_PMU_ID_V6MP] = "v6mpcore", + [ARM_PERF_PMU_ID_CA8] = "ARMv7 Cortex-A8", + [ARM_PERF_PMU_ID_CA9] = "ARMv7 Cortex-A9", +}; + struct arm_pmu { - char *name; + enum arm_perf_pmu_ids id; irqreturn_t (*handle_irq)(int irq_num, void *dev); void (*enable)(struct hw_perf_event *evt, int idx); void (*disable)(struct hw_perf_event *evt, int idx); @@ -87,6 +99,30 @@ struct arm_pmu { /* Set at runtime when we know what CPU type we are. */ static const struct arm_pmu *armpmu; +enum arm_perf_pmu_ids +armpmu_get_pmu_id(void) +{ + int id = -ENODEV; + + if (armpmu != NULL) + id = armpmu->id; + + return id; +} +EXPORT_SYMBOL_GPL(armpmu_get_pmu_id); + +int +armpmu_get_max_events(void) +{ + int max_events = 0; + + if (armpmu != NULL) + max_events = armpmu->num_events; + + return max_events; +} +EXPORT_SYMBOL_GPL(armpmu_get_max_events); + #define HW_OP_UNSUPPORTED 0xFFFF #define C(_x) \ @@ -314,38 +350,44 @@ validate_group(struct perf_event *event) static int armpmu_reserve_hardware(void) { - int i; - int err; + int i, err = -ENODEV, irq; - pmu_irqs = reserve_pmu(); - if (IS_ERR(pmu_irqs)) { + pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU); + if (IS_ERR(pmu_device)) { pr_warning("unable to reserve pmu\n"); - return PTR_ERR(pmu_irqs); + return PTR_ERR(pmu_device); } - init_pmu(); + init_pmu(ARM_PMU_DEVICE_CPU); - if (pmu_irqs->num_irqs < 1) { + if (pmu_device->num_resources < 1) { pr_err("no irqs for PMUs defined\n"); return -ENODEV; } - for (i = 0; i < pmu_irqs->num_irqs; ++i) { - err = request_irq(pmu_irqs->irqs[i], armpmu->handle_irq, + for (i = 0; i < pmu_device->num_resources; ++i) { + irq = platform_get_irq(pmu_device, i); + if (irq < 0) + continue; + + err = request_irq(irq, armpmu->handle_irq, IRQF_DISABLED | IRQF_NOBALANCING, "armpmu", NULL); if (err) { - pr_warning("unable to request IRQ%d for ARM " - "perf counters\n", pmu_irqs->irqs[i]); + pr_warning("unable to request IRQ%d for ARM perf " + "counters\n", irq); break; } } if (err) { - for (i = i - 1; i >= 0; --i) - free_irq(pmu_irqs->irqs[i], NULL); - release_pmu(pmu_irqs); - pmu_irqs = NULL; + for (i = i - 1; i >= 0; --i) { + irq = platform_get_irq(pmu_device, i); + if (irq >= 0) + free_irq(irq, NULL); + } + release_pmu(pmu_device); + pmu_device = NULL; } return err; @@ -354,14 +396,17 @@ armpmu_reserve_hardware(void) static void armpmu_release_hardware(void) { - int i; + int i, irq; - for (i = pmu_irqs->num_irqs - 1; i >= 0; --i) - free_irq(pmu_irqs->irqs[i], NULL); + for (i = pmu_device->num_resources - 1; i >= 0; --i) { + irq = platform_get_irq(pmu_device, i); + if (irq >= 0) + free_irq(irq, NULL); + } armpmu->stop(); - release_pmu(pmu_irqs); - pmu_irqs = NULL; + release_pmu(pmu_device); + pmu_device = NULL; } static atomic_t active_events = ATOMIC_INIT(0); @@ -1144,7 +1189,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc, } static const struct arm_pmu armv6pmu = { - .name = "v6", + .id = ARM_PERF_PMU_ID_V6, .handle_irq = armv6pmu_handle_irq, .enable = armv6pmu_enable_event, .disable = armv6pmu_disable_event, @@ -1167,7 +1212,7 @@ static const struct arm_pmu armv6pmu = { * reset the period and enable the interrupt reporting. */ static const struct arm_pmu armv6mpcore_pmu = { - .name = "v6mpcore", + .id = ARM_PERF_PMU_ID_V6MP, .handle_irq = armv6pmu_handle_irq, .enable = armv6pmu_enable_event, .disable = armv6mpcore_pmu_disable_event, @@ -1197,10 +1242,6 @@ static const struct arm_pmu armv6mpcore_pmu = { * counter and all 4 performance counters together can be reset separately. */ -#define ARMV7_PMU_CORTEX_A8_NAME "ARMv7 Cortex-A8" - -#define ARMV7_PMU_CORTEX_A9_NAME "ARMv7 Cortex-A9" - /* Common ARMv7 event types */ enum armv7_perf_types { ARMV7_PERFCTR_PMNC_SW_INCR = 0x00, @@ -2079,6 +2120,803 @@ static u32 __init armv7_reset_read_pmnc(void) return nb_cnt + 1; } +/* + * ARMv5 [xscale] Performance counter handling code. + * + * Based on xscale OProfile code. + * + * There are two variants of the xscale PMU that we support: + * - xscale1pmu: 2 event counters and a cycle counter + * - xscale2pmu: 4 event counters and a cycle counter + * The two variants share event definitions, but have different + * PMU structures. + */ + +enum xscale_perf_types { + XSCALE_PERFCTR_ICACHE_MISS = 0x00, + XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01, + XSCALE_PERFCTR_DATA_STALL = 0x02, + XSCALE_PERFCTR_ITLB_MISS = 0x03, + XSCALE_PERFCTR_DTLB_MISS = 0x04, + XSCALE_PERFCTR_BRANCH = 0x05, + XSCALE_PERFCTR_BRANCH_MISS = 0x06, + XSCALE_PERFCTR_INSTRUCTION = 0x07, + XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08, + XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09, + XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A, + XSCALE_PERFCTR_DCACHE_MISS = 0x0B, + XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C, + XSCALE_PERFCTR_PC_CHANGED = 0x0D, + XSCALE_PERFCTR_BCU_REQUEST = 0x10, + XSCALE_PERFCTR_BCU_FULL = 0x11, + XSCALE_PERFCTR_BCU_DRAIN = 0x12, + XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14, + XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15, + XSCALE_PERFCTR_RMW = 0x16, + /* XSCALE_PERFCTR_CCNT is not hardware defined */ + XSCALE_PERFCTR_CCNT = 0xFE, + XSCALE_PERFCTR_UNUSED = 0xFF, +}; + +enum xscale_counters { + XSCALE_CYCLE_COUNTER = 1, + XSCALE_COUNTER0, + XSCALE_COUNTER1, + XSCALE_COUNTER2, + XSCALE_COUNTER3, +}; + +static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT, + [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION, + [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, + [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH, + [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS, + [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, +}; + +static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { + [C(L1D)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, + [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, + [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(DTLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(BPU)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, +}; + +#define XSCALE_PMU_ENABLE 0x001 +#define XSCALE_PMN_RESET 0x002 +#define XSCALE_CCNT_RESET 0x004 +#define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET) +#define XSCALE_PMU_CNT64 0x008 + +static inline int +xscalepmu_event_map(int config) +{ + int mapping = xscale_perf_map[config]; + if (HW_OP_UNSUPPORTED == mapping) + mapping = -EOPNOTSUPP; + return mapping; +} + +static u64 +xscalepmu_raw_event(u64 config) +{ + return config & 0xff; +} + +#define XSCALE1_OVERFLOWED_MASK 0x700 +#define XSCALE1_CCOUNT_OVERFLOW 0x400 +#define XSCALE1_COUNT0_OVERFLOW 0x100 +#define XSCALE1_COUNT1_OVERFLOW 0x200 +#define XSCALE1_CCOUNT_INT_EN 0x040 +#define XSCALE1_COUNT0_INT_EN 0x010 +#define XSCALE1_COUNT1_INT_EN 0x020 +#define XSCALE1_COUNT0_EVT_SHFT 12 +#define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT) +#define XSCALE1_COUNT1_EVT_SHFT 20 +#define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT) + +static inline u32 +xscale1pmu_read_pmnc(void) +{ + u32 val; + asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val)); + return val; +} + +static inline void +xscale1pmu_write_pmnc(u32 val) +{ + /* upper 4bits and 7, 11 are write-as-0 */ + val &= 0xffff77f; + asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val)); +} + +static inline int +xscale1_pmnc_counter_has_overflowed(unsigned long pmnc, + enum xscale_counters counter) +{ + int ret = 0; + + switch (counter) { + case XSCALE_CYCLE_COUNTER: + ret = pmnc & XSCALE1_CCOUNT_OVERFLOW; + break; + case XSCALE_COUNTER0: + ret = pmnc & XSCALE1_COUNT0_OVERFLOW; + break; + case XSCALE_COUNTER1: + ret = pmnc & XSCALE1_COUNT1_OVERFLOW; + break; + default: + WARN_ONCE(1, "invalid counter number (%d)\n", counter); + } + + return ret; +} + +static irqreturn_t +xscale1pmu_handle_irq(int irq_num, void *dev) +{ + unsigned long pmnc; + struct perf_sample_data data; + struct cpu_hw_events *cpuc; + struct pt_regs *regs; + int idx; + + /* + * NOTE: there's an A stepping erratum that states if an overflow + * bit already exists and another occurs, the previous + * Overflow bit gets cleared. There's no workaround. + * Fixed in B stepping or later. + */ + pmnc = xscale1pmu_read_pmnc(); + + /* + * Write the value back to clear the overflow flags. Overflow + * flags remain in pmnc for use below. We also disable the PMU + * while we process the interrupt. + */ + xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE); + + if (!(pmnc & XSCALE1_OVERFLOWED_MASK)) + return IRQ_NONE; + + regs = get_irq_regs(); + + perf_sample_data_init(&data, 0); + + cpuc = &__get_cpu_var(cpu_hw_events); + for (idx = 0; idx <= armpmu->num_events; ++idx) { + struct perf_event *event = cpuc->events[idx]; + struct hw_perf_event *hwc; + + if (!test_bit(idx, cpuc->active_mask)) + continue; + + if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx)) + continue; + + hwc = &event->hw; + armpmu_event_update(event, hwc, idx); + data.period = event->hw.last_period; + if (!armpmu_event_set_period(event, hwc, idx)) + continue; + + if (perf_event_overflow(event, 0, &data, regs)) + armpmu->disable(hwc, idx); + } + + perf_event_do_pending(); + + /* + * Re-enable the PMU. + */ + pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE; + xscale1pmu_write_pmnc(pmnc); + + return IRQ_HANDLED; +} + +static void +xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx) +{ + unsigned long val, mask, evt, flags; + + switch (idx) { + case XSCALE_CYCLE_COUNTER: + mask = 0; + evt = XSCALE1_CCOUNT_INT_EN; + break; + case XSCALE_COUNTER0: + mask = XSCALE1_COUNT0_EVT_MASK; + evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | + XSCALE1_COUNT0_INT_EN; + break; + case XSCALE_COUNTER1: + mask = XSCALE1_COUNT1_EVT_MASK; + evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | + XSCALE1_COUNT1_INT_EN; + break; + default: + WARN_ONCE(1, "invalid counter number (%d)\n", idx); + return; + } + + spin_lock_irqsave(&pmu_lock, flags); + val = xscale1pmu_read_pmnc(); + val &= ~mask; + val |= evt; + xscale1pmu_write_pmnc(val); + spin_unlock_irqrestore(&pmu_lock, flags); +} + +static void +xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx) +{ + unsigned long val, mask, evt, flags; + + switch (idx) { + case XSCALE_CYCLE_COUNTER: + mask = XSCALE1_CCOUNT_INT_EN; + evt = 0; + break; + case XSCALE_COUNTER0: + mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK; + evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT; + break; + case XSCALE_COUNTER1: + mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK; + evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT; + break; + default: + WARN_ONCE(1, "invalid counter number (%d)\n", idx); + return; + } + + spin_lock_irqsave(&pmu_lock, flags); + val = xscale1pmu_read_pmnc(); + val &= ~mask; + val |= evt; + xscale1pmu_write_pmnc(val); + spin_unlock_irqrestore(&pmu_lock, flags); +} + +static int +xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc, + struct hw_perf_event *event) +{ + if (XSCALE_PERFCTR_CCNT == event->config_base) { + if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask)) + return -EAGAIN; + + return XSCALE_CYCLE_COUNTER; + } else { + if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) { + return XSCALE_COUNTER1; + } + + if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) { + return XSCALE_COUNTER0; + } + + return -EAGAIN; + } +} + +static void +xscale1pmu_start(void) +{ + unsigned long flags, val; + + spin_lock_irqsave(&pmu_lock, flags); + val = xscale1pmu_read_pmnc(); + val |= XSCALE_PMU_ENABLE; + xscale1pmu_write_pmnc(val); + spin_unlock_irqrestore(&pmu_lock, flags); +} + +static void +xscale1pmu_stop(void) +{ + unsigned long flags, val; + + spin_lock_irqsave(&pmu_lock, flags); + val = xscale1pmu_read_pmnc(); + val &= ~XSCALE_PMU_ENABLE; + xscale1pmu_write_pmnc(val); + spin_unlock_irqrestore(&pmu_lock, flags); +} + +static inline u32 +xscale1pmu_read_counter(int counter) +{ + u32 val = 0; + + switch (counter) { + case XSCALE_CYCLE_COUNTER: + asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val)); + break; + case XSCALE_COUNTER0: + asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val)); + break; + case XSCALE_COUNTER1: + asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val)); + break; + } + + return val; +} + +static inline void +xscale1pmu_write_counter(int counter, u32 val) +{ + switch (counter) { + case XSCALE_CYCLE_COUNTER: + asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val)); + break; + case XSCALE_COUNTER0: + asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val)); + break; + case XSCALE_COUNTER1: + asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val)); + break; + } +} + +static const struct arm_pmu xscale1pmu = { + .id = ARM_PERF_PMU_ID_XSCALE1, + .handle_irq = xscale1pmu_handle_irq, + .enable = xscale1pmu_enable_event, + .disable = xscale1pmu_disable_event, + .event_map = xscalepmu_event_map, + .raw_event = xscalepmu_raw_event, + .read_counter = xscale1pmu_read_counter, + .write_counter = xscale1pmu_write_counter, + .get_event_idx = xscale1pmu_get_event_idx, + .start = xscale1pmu_start, + .stop = xscale1pmu_stop, + .num_events = 3, + .max_period = (1LLU << 32) - 1, +}; + +#define XSCALE2_OVERFLOWED_MASK 0x01f +#define XSCALE2_CCOUNT_OVERFLOW 0x001 +#define XSCALE2_COUNT0_OVERFLOW 0x002 +#define XSCALE2_COUNT1_OVERFLOW 0x004 +#define XSCALE2_COUNT2_OVERFLOW 0x008 +#define XSCALE2_COUNT3_OVERFLOW 0x010 +#define XSCALE2_CCOUNT_INT_EN 0x001 +#define XSCALE2_COUNT0_INT_EN 0x002 +#define XSCALE2_COUNT1_INT_EN 0x004 +#define XSCALE2_COUNT2_INT_EN 0x008 +#define XSCALE2_COUNT3_INT_EN 0x010 +#define XSCALE2_COUNT0_EVT_SHFT 0 +#define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT) +#define XSCALE2_COUNT1_EVT_SHFT 8 +#define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT) +#define XSCALE2_COUNT2_EVT_SHFT 16 +#define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT) +#define XSCALE2_COUNT3_EVT_SHFT 24 +#define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT) + +static inline u32 +xscale2pmu_read_pmnc(void) +{ + u32 val; + asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val)); + /* bits 1-2 and 4-23 are read-unpredictable */ + return val & 0xff000009; +} + +static inline void +xscale2pmu_write_pmnc(u32 val) +{ + /* bits 4-23 are write-as-0, 24-31 are write ignored */ + val &= 0xf; + asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val)); +} + +static inline u32 +xscale2pmu_read_overflow_flags(void) +{ + u32 val; + asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val)); + return val; +} + +static inline void +xscale2pmu_write_overflow_flags(u32 val) +{ + asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val)); +} + +static inline u32 +xscale2pmu_read_event_select(void) +{ + u32 val; + asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val)); + return val; +} + +static inline void +xscale2pmu_write_event_select(u32 val) +{ + asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val)); +} + +static inline u32 +xscale2pmu_read_int_enable(void) +{ + u32 val; + asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val)); + return val; +} + +static void +xscale2pmu_write_int_enable(u32 val) +{ + asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val)); +} + +static inline int +xscale2_pmnc_counter_has_overflowed(unsigned long of_flags, + enum xscale_counters counter) +{ + int ret = 0; + + switch (counter) { + case XSCALE_CYCLE_COUNTER: + ret = of_flags & XSCALE2_CCOUNT_OVERFLOW; + break; + case XSCALE_COUNTER0: + ret = of_flags & XSCALE2_COUNT0_OVERFLOW; + break; + case XSCALE_COUNTER1: + ret = of_flags & XSCALE2_COUNT1_OVERFLOW; + break; + case XSCALE_COUNTER2: + ret = of_flags & XSCALE2_COUNT2_OVERFLOW; + break; + case XSCALE_COUNTER3: + ret = of_flags & XSCALE2_COUNT3_OVERFLOW; + break; + default: + WARN_ONCE(1, "invalid counter number (%d)\n", counter); + } + + return ret; +} + +static irqreturn_t +xscale2pmu_handle_irq(int irq_num, void *dev) +{ + unsigned long pmnc, of_flags; + struct perf_sample_data data; + struct cpu_hw_events *cpuc; + struct pt_regs *regs; + int idx; + + /* Disable the PMU. */ + pmnc = xscale2pmu_read_pmnc(); + xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE); + + /* Check the overflow flag register. */ + of_flags = xscale2pmu_read_overflow_flags(); + if (!(of_flags & XSCALE2_OVERFLOWED_MASK)) + return IRQ_NONE; + + /* Clear the overflow bits. */ + xscale2pmu_write_overflow_flags(of_flags); + + regs = get_irq_regs(); + + perf_sample_data_init(&data, 0); + + cpuc = &__get_cpu_var(cpu_hw_events); + for (idx = 0; idx <= armpmu->num_events; ++idx) { + struct perf_event *event = cpuc->events[idx]; + struct hw_perf_event *hwc; + + if (!test_bit(idx, cpuc->active_mask)) + continue; + + if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx)) + continue; + + hwc = &event->hw; + armpmu_event_update(event, hwc, idx); + data.period = event->hw.last_period; + if (!armpmu_event_set_period(event, hwc, idx)) + continue; + + if (perf_event_overflow(event, 0, &data, regs)) + armpmu->disable(hwc, idx); + } + + perf_event_do_pending(); + + /* + * Re-enable the PMU. + */ + pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE; + xscale2pmu_write_pmnc(pmnc); + + return IRQ_HANDLED; +} + +static void +xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx) +{ + unsigned long flags, ien, evtsel; + + ien = xscale2pmu_read_int_enable(); + evtsel = xscale2pmu_read_event_select(); + + switch (idx) { + case XSCALE_CYCLE_COUNTER: + ien |= XSCALE2_CCOUNT_INT_EN; + break; + case XSCALE_COUNTER0: + ien |= XSCALE2_COUNT0_INT_EN; + evtsel &= ~XSCALE2_COUNT0_EVT_MASK; + evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT; + break; + case XSCALE_COUNTER1: + ien |= XSCALE2_COUNT1_INT_EN; + evtsel &= ~XSCALE2_COUNT1_EVT_MASK; + evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT; + break; + case XSCALE_COUNTER2: + ien |= XSCALE2_COUNT2_INT_EN; + evtsel &= ~XSCALE2_COUNT2_EVT_MASK; + evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT; + break; + case XSCALE_COUNTER3: + ien |= XSCALE2_COUNT3_INT_EN; + evtsel &= ~XSCALE2_COUNT3_EVT_MASK; + evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT; + break; + default: + WARN_ONCE(1, "invalid counter number (%d)\n", idx); + return; + } + + spin_lock_irqsave(&pmu_lock, flags); + xscale2pmu_write_event_select(evtsel); + xscale2pmu_write_int_enable(ien); + spin_unlock_irqrestore(&pmu_lock, flags); +} + +static void +xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx) +{ + unsigned long flags, ien, evtsel; + + ien = xscale2pmu_read_int_enable(); + evtsel = xscale2pmu_read_event_select(); + + switch (idx) { + case XSCALE_CYCLE_COUNTER: + ien &= ~XSCALE2_CCOUNT_INT_EN; + break; + case XSCALE_COUNTER0: + ien &= ~XSCALE2_COUNT0_INT_EN; + evtsel &= ~XSCALE2_COUNT0_EVT_MASK; + evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT; + break; + case XSCALE_COUNTER1: + ien &= ~XSCALE2_COUNT1_INT_EN; + evtsel &= ~XSCALE2_COUNT1_EVT_MASK; + evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT; + break; + case XSCALE_COUNTER2: + ien &= ~XSCALE2_COUNT2_INT_EN; + evtsel &= ~XSCALE2_COUNT2_EVT_MASK; + evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT; + break; + case XSCALE_COUNTER3: + ien &= ~XSCALE2_COUNT3_INT_EN; + evtsel &= ~XSCALE2_COUNT3_EVT_MASK; + evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT; + break; + default: + WARN_ONCE(1, "invalid counter number (%d)\n", idx); + return; + } + + spin_lock_irqsave(&pmu_lock, flags); + xscale2pmu_write_event_select(evtsel); + xscale2pmu_write_int_enable(ien); + spin_unlock_irqrestore(&pmu_lock, flags); +} + +static int +xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc, + struct hw_perf_event *event) +{ + int idx = xscale1pmu_get_event_idx(cpuc, event); + if (idx >= 0) + goto out; + + if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask)) + idx = XSCALE_COUNTER3; + else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask)) + idx = XSCALE_COUNTER2; +out: + return idx; +} + +static void +xscale2pmu_start(void) +{ + unsigned long flags, val; + + spin_lock_irqsave(&pmu_lock, flags); + val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64; + val |= XSCALE_PMU_ENABLE; + xscale2pmu_write_pmnc(val); + spin_unlock_irqrestore(&pmu_lock, flags); +} + +static void +xscale2pmu_stop(void) +{ + unsigned long flags, val; + + spin_lock_irqsave(&pmu_lock, flags); + val = xscale2pmu_read_pmnc(); + val &= ~XSCALE_PMU_ENABLE; + xscale2pmu_write_pmnc(val); + spin_unlock_irqrestore(&pmu_lock, flags); +} + +static inline u32 +xscale2pmu_read_counter(int counter) +{ + u32 val = 0; + + switch (counter) { + case XSCALE_CYCLE_COUNTER: + asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val)); + break; + case XSCALE_COUNTER0: + asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val)); + break; + case XSCALE_COUNTER1: + asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val)); + break; + case XSCALE_COUNTER2: + asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val)); + break; + case XSCALE_COUNTER3: + asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val)); + break; + } + + return val; +} + +static inline void +xscale2pmu_write_counter(int counter, u32 val) +{ + switch (counter) { + case XSCALE_CYCLE_COUNTER: + asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val)); + break; + case XSCALE_COUNTER0: + asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val)); + break; + case XSCALE_COUNTER1: + asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val)); + break; + case XSCALE_COUNTER2: + asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val)); + break; + case XSCALE_COUNTER3: + asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val)); + break; + } +} + +static const struct arm_pmu xscale2pmu = { + .id = ARM_PERF_PMU_ID_XSCALE2, + .handle_irq = xscale2pmu_handle_irq, + .enable = xscale2pmu_enable_event, + .disable = xscale2pmu_disable_event, + .event_map = xscalepmu_event_map, + .raw_event = xscalepmu_raw_event, + .read_counter = xscale2pmu_read_counter, + .write_counter = xscale2pmu_write_counter, + .get_event_idx = xscale2pmu_get_event_idx, + .start = xscale2pmu_start, + .stop = xscale2pmu_stop, + .num_events = 5, + .max_period = (1LLU << 32) - 1, +}; + static int __init init_hw_perf_events(void) { @@ -2086,7 +2924,7 @@ init_hw_perf_events(void) unsigned long implementor = (cpuid & 0xFF000000) >> 24; unsigned long part_number = (cpuid & 0xFFF0); - /* We only support ARM CPUs implemented by ARM at the moment. */ + /* ARM Ltd CPUs. */ if (0x41 == implementor) { switch (part_number) { case 0xB360: /* ARM1136 */ @@ -2105,7 +2943,7 @@ init_hw_perf_events(void) perf_max_events = armv6mpcore_pmu.num_events; break; case 0xC080: /* Cortex-A8 */ - armv7pmu.name = ARMV7_PMU_CORTEX_A8_NAME; + armv7pmu.id = ARM_PERF_PMU_ID_CA8; memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map, sizeof(armv7_a8_perf_cache_map)); armv7pmu.event_map = armv7_a8_pmu_event_map; @@ -2117,7 +2955,7 @@ init_hw_perf_events(void) perf_max_events = armv7pmu.num_events; break; case 0xC090: /* Cortex-A9 */ - armv7pmu.name = ARMV7_PMU_CORTEX_A9_NAME; + armv7pmu.id = ARM_PERF_PMU_ID_CA9; memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map, sizeof(armv7_a9_perf_cache_map)); armv7pmu.event_map = armv7_a9_pmu_event_map; @@ -2128,15 +2966,33 @@ init_hw_perf_events(void) armv7pmu.num_events = armv7_reset_read_pmnc(); perf_max_events = armv7pmu.num_events; break; - default: - pr_info("no hardware support available\n"); - perf_max_events = -1; + } + /* Intel CPUs [xscale]. */ + } else if (0x69 == implementor) { + part_number = (cpuid >> 13) & 0x7; + switch (part_number) { + case 1: + armpmu = &xscale1pmu; + memcpy(armpmu_perf_cache_map, xscale_perf_cache_map, + sizeof(xscale_perf_cache_map)); + perf_max_events = xscale1pmu.num_events; + break; + case 2: + armpmu = &xscale2pmu; + memcpy(armpmu_perf_cache_map, xscale_perf_cache_map, + sizeof(xscale_perf_cache_map)); + perf_max_events = xscale2pmu.num_events; + break; } } - if (armpmu) + if (armpmu) { pr_info("enabled with %s PMU driver, %d counters available\n", - armpmu->name, armpmu->num_events); + arm_pmu_names[armpmu->id], armpmu->num_events); + } else { + pr_info("no hardware support available\n"); + perf_max_events = -1; + } return 0; } diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c index a124312e343..b8af96ea62e 100644 --- a/arch/arm/kernel/pmu.c +++ b/arch/arm/kernel/pmu.c @@ -2,6 +2,7 @@ * linux/arch/arm/kernel/pmu.c * * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles + * Copyright (C) 2010 ARM Ltd, Will Deacon * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -9,65 +10,78 @@ * */ +#define pr_fmt(fmt) "PMU: " fmt + #include <linux/cpumask.h> #include <linux/err.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/platform_device.h> #include <asm/pmu.h> -/* - * Define the IRQs for the system. We could use something like a platform - * device but that seems fairly heavyweight for this. Also, the performance - * counters can't be removed or hotplugged. - * - * Ordering is important: init_pmu() will use the ordering to set the affinity - * to the corresponding core. e.g. the first interrupt will go to cpu 0, the - * second goes to cpu 1 etc. - */ -static const int irqs[] = { -#if defined(CONFIG_ARCH_OMAP2) - 3, -#elif defined(CONFIG_ARCH_BCMRING) - IRQ_PMUIRQ, -#elif defined(CONFIG_MACH_REALVIEW_EB) - IRQ_EB11MP_PMU_CPU0, - IRQ_EB11MP_PMU_CPU1, - IRQ_EB11MP_PMU_CPU2, - IRQ_EB11MP_PMU_CPU3, -#elif defined(CONFIG_ARCH_OMAP3) - INT_34XX_BENCH_MPU_EMUL, -#elif defined(CONFIG_ARCH_IOP32X) - IRQ_IOP32X_CORE_PMU, -#elif defined(CONFIG_ARCH_IOP33X) - IRQ_IOP33X_CORE_PMU, -#elif defined(CONFIG_ARCH_PXA) - IRQ_PMU, -#endif -}; +static volatile long pmu_lock; + +static struct platform_device *pmu_devices[ARM_NUM_PMU_DEVICES]; + +static int __devinit pmu_device_probe(struct platform_device *pdev) +{ + + if (pdev->id < 0 || pdev->id >= ARM_NUM_PMU_DEVICES) { + pr_warning("received registration request for unknown " + "device %d\n", pdev->id); + return -EINVAL; + } + + if (pmu_devices[pdev->id]) + pr_warning("registering new PMU device type %d overwrites " + "previous registration!\n", pdev->id); + else + pr_info("registered new PMU device of type %d\n", + pdev->id); -static const struct pmu_irqs pmu_irqs = { - .irqs = irqs, - .num_irqs = ARRAY_SIZE(irqs), + pmu_devices[pdev->id] = pdev; + return 0; +} + +static struct platform_driver pmu_driver = { + .driver = { + .name = "arm-pmu", + }, + .probe = pmu_device_probe, }; -static volatile long pmu_lock; +static int __init register_pmu_driver(void) +{ + return platform_driver_register(&pmu_driver); +} +device_initcall(register_pmu_driver); -const struct pmu_irqs * -reserve_pmu(void) +struct platform_device * +reserve_pmu(enum arm_pmu_type device) { - return test_and_set_bit_lock(0, &pmu_lock) ? ERR_PTR(-EBUSY) : - &pmu_irqs; + struct platform_device *pdev; + + if (test_and_set_bit_lock(device, &pmu_lock)) { + pdev = ERR_PTR(-EBUSY); + } else if (pmu_devices[device] == NULL) { + clear_bit_unlock(device, &pmu_lock); + pdev = ERR_PTR(-ENODEV); + } else { + pdev = pmu_devices[device]; + } + + return pdev; } EXPORT_SYMBOL_GPL(reserve_pmu); int -release_pmu(const struct pmu_irqs *irqs) +release_pmu(struct platform_device *pdev) { - if (WARN_ON(irqs != &pmu_irqs)) + if (WARN_ON(pdev != pmu_devices[pdev->id])) return -EINVAL; - clear_bit_unlock(0, &pmu_lock); + clear_bit_unlock(pdev->id, &pmu_lock); return 0; } EXPORT_SYMBOL_GPL(release_pmu); @@ -87,17 +101,42 @@ set_irq_affinity(int irq, #endif } -int -init_pmu(void) +static int +init_cpu_pmu(void) { int i, err = 0; + struct platform_device *pdev = pmu_devices[ARM_PMU_DEVICE_CPU]; + + if (!pdev) { + err = -ENODEV; + goto out; + } - for (i = 0; i < pmu_irqs.num_irqs; ++i) { - err = set_irq_affinity(pmu_irqs.irqs[i], i); + for (i = 0; i < pdev->num_resources; ++i) { + err = set_irq_affinity(platform_get_irq(pdev, i), i); if (err) break; } +out: + return err; +} + +int +init_pmu(enum arm_pmu_type device) +{ + int err = 0; + + switch (device) { + case ARM_PMU_DEVICE_CPU: + err = init_cpu_pmu(); + break; + default: + pr_warning("attempt to initialise unknown device %d\n", + device); + err = -EINVAL; + } + return err; } EXPORT_SYMBOL_GPL(init_pmu); diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index a01194e583f..b8c3d0f689d 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -168,7 +168,7 @@ int __cpu_disable(void) struct task_struct *p; int ret; - ret = mach_cpu_disable(cpu); + ret = platform_cpu_disable(cpu); if (ret) return ret; diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 28753805d2d..38c261f9951 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -72,12 +72,15 @@ unsigned long profile_pc(struct pt_regs *regs) EXPORT_SYMBOL(profile_pc); #endif -#ifndef CONFIG_GENERIC_TIME -static unsigned long dummy_gettimeoffset(void) +#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET +u32 arch_gettimeoffset(void) { + if (system_timer->offset != NULL) + return system_timer->offset() * 1000; + return 0; } -#endif +#endif /* CONFIG_ARCH_USES_GETTIMEOFFSET */ #ifdef CONFIG_LEDS_TIMER static inline void do_leds(void) @@ -93,63 +96,6 @@ static inline void do_leds(void) #define do_leds() #endif -#ifndef CONFIG_GENERIC_TIME -void do_gettimeofday(struct timeval *tv) -{ - unsigned long flags; - unsigned long seq; - unsigned long usec, sec; - - do { - seq = read_seqbegin_irqsave(&xtime_lock, flags); - usec = system_timer->offset(); - sec = xtime.tv_sec; - usec += xtime.tv_nsec / 1000; - } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); - - /* usec may have gone up a lot: be safe */ - while (usec >= 1000000) { - usec -= 1000000; - sec++; - } - - tv->tv_sec = sec; - tv->tv_usec = usec; -} - -EXPORT_SYMBOL(do_gettimeofday); - -int do_settimeofday(struct timespec *tv) -{ - time_t wtm_sec, sec = tv->tv_sec; - long wtm_nsec, nsec = tv->tv_nsec; - - if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) - return -EINVAL; - - write_seqlock_irq(&xtime_lock); - /* - * This is revolting. We need to set "xtime" correctly. However, the - * value in this location is the value at the most recent update of - * wall time. Discover what correction gettimeofday() would have - * done, and then undo it! - */ - nsec -= system_timer->offset() * NSEC_PER_USEC; - - wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec); - wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec); - - set_normalized_timespec(&xtime, sec, nsec); - set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - - ntp_clear(); - write_sequnlock_irq(&xtime_lock); - clock_was_set(); - return 0; -} - -EXPORT_SYMBOL(do_settimeofday); -#endif /* !CONFIG_GENERIC_TIME */ #ifndef CONFIG_GENERIC_CLOCKEVENTS /* @@ -214,10 +160,6 @@ device_initcall(timer_init_sysfs); void __init time_init(void) { -#ifndef CONFIG_GENERIC_TIME - if (system_timer->offset == NULL) - system_timer->offset = dummy_gettimeoffset; -#endif system_timer->init(); } diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 2db43a5ddd9..841eaf8f27e 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -23,14 +23,12 @@ choice config ARCH_AT91RM9200 bool "AT91RM9200" select CPU_ARM920T - select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_AT91_USART3 config ARCH_AT91SAM9260 bool "AT91SAM9260 or AT91SAM9XE" select CPU_ARM926T - select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_AT91_USART3 select HAVE_AT91_USART4 @@ -39,28 +37,24 @@ config ARCH_AT91SAM9260 config ARCH_AT91SAM9261 bool "AT91SAM9261" select CPU_ARM926T - select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL config ARCH_AT91SAM9G10 bool "AT91SAM9G10" select CPU_ARM926T - select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL config ARCH_AT91SAM9263 bool "AT91SAM9263" select CPU_ARM926T - select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL config ARCH_AT91SAM9RL bool "AT91SAM9RL" select CPU_ARM926T - select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_AT91_USART3 select HAVE_FB_ATMEL @@ -68,7 +62,6 @@ config ARCH_AT91SAM9RL config ARCH_AT91SAM9G20 bool "AT91SAM9G20" select CPU_ARM926T - select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_AT91_USART3 select HAVE_AT91_USART4 @@ -77,7 +70,6 @@ config ARCH_AT91SAM9G20 config ARCH_AT91SAM9G45 bool "AT91SAM9G45" select CPU_ARM926T - select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_AT91_USART3 select HAVE_FB_ATMEL @@ -85,18 +77,17 @@ config ARCH_AT91SAM9G45 config ARCH_AT91CAP9 bool "AT91CAP9" select CPU_ARM926T - select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL config ARCH_AT572D940HF bool "AT572D940HF" select CPU_ARM926T - select GENERIC_TIME select GENERIC_CLOCKEVENTS config ARCH_AT91X40 bool "AT91x40" + select ARCH_USES_GETTIMEOFFSET endchoice @@ -360,6 +351,19 @@ config MACH_CPU9G20 Select this if you are using a Eukrea Electromatique's CPU9G20 Board <http://www.eukrea.com/> +config MACH_PORTUXG20 + bool "taskit PortuxG20" + help + Select this if you are using taskit's PortuxG20. + <http://www.taskit.de/en/> + +config MACH_STAMP9G20 + bool "taskit Stamp9G20 CPU module" + help + Select this if you are using taskit's Stamp9G20 CPU module on its + evaluation board. + <http://www.taskit.de/en/> + endif # ---------------------------------------------------------- diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index d4004557532..c1f821e5822 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -63,6 +63,8 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o obj-$(CONFIG_MACH_AT91SAM9G20EK_2MMC) += board-sam9g20ek-2slot-mmc.o obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o +obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o +obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o # AT91SAM9G45 board-specific support obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c new file mode 100644 index 00000000000..87958274290 --- /dev/null +++ b/arch/arm/mach-at91/board-stamp9g20.c @@ -0,0 +1,315 @@ +/* + * Copyright (C) 2010 Christian Glindkamp <christian.glindkamp@taskit.de> + * taskit GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/mm.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/w1-gpio.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/board.h> +#include <mach/at91sam9_smc.h> + +#include "sam9_smc.h" +#include "generic.h" + + +static void __init portuxg20_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91sam9260_initialize(18432000); + + /* DGBU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR + | ATMEL_UART_DCD | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* USART4 on ttyS5. (Rx, Tx only) */ + at91_register_uart(AT91SAM9260_ID_US4, 5, 0); + + /* USART5 on ttyS6. (Rx, Tx only) */ + at91_register_uart(AT91SAM9260_ID_US5, 6, 0); + + /* set serial console to ttyS0 (ie, DBGU) */ + at91_set_serial_console(0); +} + +static void __init stamp9g20_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91sam9260_initialize(18432000); + + /* DGBU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR + | ATMEL_UART_DCD | ATMEL_UART_RI); + + /* set serial console to ttyS0 (ie, DBGU) */ + at91_set_serial_console(0); +} + +static void __init init_irq(void) +{ + at91sam9260_init_interrupts(NULL); +} + + +/* + * NAND flash + */ +static struct atmel_nand_data __initdata nand_data = { + .ale = 21, + .cle = 22, + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, + .bus_width_16 = 0, +}; + +static struct sam9_smc_config __initdata nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 4, + .nrd_pulse = 4, + .ncs_write_pulse = 4, + .nwe_pulse = 4, + + .read_cycle = 7, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 3, +}; + +static void __init add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &nand_smc_config); + + at91_add_device_nand(&nand_data); +} + + +/* + * MCI (SD/MMC) + * det_pin, wp_pin and vcc_pin are not connected + */ +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) +static struct mci_platform_data __initdata mmc_data = { + .slot[0] = { + .bus_width = 4, + }, +}; +#else +static struct at91_mmc_data __initdata mmc_data = { + .slot_b = 0, + .wire4 = 1, +}; +#endif + + +/* + * USB Host port + */ +static struct at91_usbh_data __initdata usbh_data = { + .ports = 2, +}; + + +/* + * USB Device port + */ +static struct at91_udc_data __initdata portuxg20_udc_data = { + .vbus_pin = AT91_PIN_PC7, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + +static struct at91_udc_data __initdata stamp9g20_udc_data = { + .vbus_pin = AT91_PIN_PA22, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + + +/* + * MACB Ethernet device + */ +static struct at91_eth_data __initdata macb_data = { + .phy_irq_pin = AT91_PIN_PA28, + .is_rmii = 1, +}; + + +/* + * LEDs + */ +static struct gpio_led portuxg20_leds[] = { + { + .name = "LED2", + .gpio = AT91_PIN_PC5, + .default_trigger = "none", + }, { + .name = "LED3", + .gpio = AT91_PIN_PC4, + .default_trigger = "none", + }, { + .name = "LED4", + .gpio = AT91_PIN_PC10, + .default_trigger = "heartbeat", + } +}; + +static struct gpio_led stamp9g20_leds[] = { + { + .name = "D8", + .gpio = AT91_PIN_PB18, + .active_low = 1, + .default_trigger = "none", + }, { + .name = "D9", + .gpio = AT91_PIN_PB19, + .active_low = 1, + .default_trigger = "none", + }, { + .name = "D10", + .gpio = AT91_PIN_PB20, + .active_low = 1, + .default_trigger = "heartbeat", + } +}; + + +/* + * SPI devices + */ +static struct spi_board_info portuxg20_spi_devices[] = { + { + .modalias = "spidev", + .chip_select = 0, + .max_speed_hz = 1 * 1000 * 1000, + .bus_num = 0, + }, { + .modalias = "spidev", + .chip_select = 0, + .max_speed_hz = 1 * 1000 * 1000, + .bus_num = 1, + }, +}; + + +/* + * Dallas 1-Wire + */ +static struct w1_gpio_platform_data w1_gpio_pdata = { + .pin = AT91_PIN_PA29, + .is_open_drain = 1, +}; + +static struct platform_device w1_device = { + .name = "w1-gpio", + .id = -1, + .dev.platform_data = &w1_gpio_pdata, +}; + +void add_w1(void) +{ + at91_set_GPIO_periph(w1_gpio_pdata.pin, 1); + at91_set_multi_drive(w1_gpio_pdata.pin, 1); + platform_device_register(&w1_device); +} + + +static void __init generic_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* NAND */ + add_device_nand(); + /* MMC */ +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) + at91_add_device_mci(0, &mmc_data); +#else + at91_add_device_mmc(0, &mmc_data); +#endif + /* USB Host */ + at91_add_device_usbh(&usbh_data); + /* Ethernet */ + at91_add_device_eth(&macb_data); + /* I2C */ + at91_add_device_i2c(NULL, 0); + /* W1 */ + add_w1(); +} + +static void __init portuxg20_board_init(void) +{ + generic_board_init(); + /* SPI */ + at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices)); + /* USB Device */ + at91_add_device_udc(&portuxg20_udc_data); + /* LEDs */ + at91_gpio_leds(portuxg20_leds, ARRAY_SIZE(portuxg20_leds)); +} + +static void __init stamp9g20_board_init(void) +{ + generic_board_init(); + /* USB Device */ + at91_add_device_udc(&stamp9g20_udc_data); + /* LEDs */ + at91_gpio_leds(stamp9g20_leds, ARRAY_SIZE(stamp9g20_leds)); +} + +MACHINE_START(PORTUXG20, "taskit PortuxG20") + /* Maintainer: taskit GmbH */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = portuxg20_map_io, + .init_irq = init_irq, + .init_machine = portuxg20_board_init, +MACHINE_END + +MACHINE_START(STAMP9G20, "taskit Stamp9G20") + /* Maintainer: taskit GmbH */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = stamp9g20_map_io, + .init_irq = init_irq, + .init_machine = stamp9g20_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index ceaec6c16eb..df2ed848c9f 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h @@ -39,6 +39,7 @@ #include <linux/usb/atmel_usba_udc.h> #include <linux/atmel-mci.h> #include <sound/atmel-ac97c.h> +#include <linux/serial.h> /* USB Device */ struct at91_udc_data { @@ -143,9 +144,10 @@ extern struct platform_device *atmel_default_console_device; extern void __init __deprecated at91_init_serial(struct at91_uart_config *config); struct atmel_uart_data { - short use_dma_tx; /* use transmit DMA? */ - short use_dma_rx; /* use receive DMA? */ - void __iomem *regs; /* virtual base address, if any */ + short use_dma_tx; /* use transmit DMA? */ + short use_dma_rx; /* use receive DMA? */ + void __iomem *regs; /* virt. base address, if any */ + struct serial_rs485 rs485; /* rs485 settings */ }; extern void __init at91_add_device_serial(void); diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index 5a0650101d4..833659d1200 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -21,7 +21,7 @@ #define ARCH_ID_AT91SAM9260 0x019803a0 #define ARCH_ID_AT91SAM9261 0x019703a0 #define ARCH_ID_AT91SAM9263 0x019607a0 -#define ARCH_ID_AT91SAM9G10 0x819903a0 +#define ARCH_ID_AT91SAM9G10 0x019903a0 #define ARCH_ID_AT91SAM9G20 0x019905a0 #define ARCH_ID_AT91SAM9RL64 0x019b03a0 #define ARCH_ID_AT91SAM9G45 0x819b05a0 @@ -108,7 +108,7 @@ static inline unsigned long at91cap9_rev_identify(void) #endif #ifdef CONFIG_ARCH_AT91SAM9G10 -#define cpu_is_at91sam9g10() (at91_cpu_identify() == ARCH_ID_AT91SAM9G10) +#define cpu_is_at91sam9g10() ((at91_cpu_identify() & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) #else #define cpu_is_at91sam9g10() (0) #endif diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h index 5268af3933c..c80e090b367 100644 --- a/arch/arm/mach-at91/include/mach/system.h +++ b/arch/arm/mach-at91/include/mach/system.h @@ -24,21 +24,24 @@ #include <mach/hardware.h> #include <mach/at91_st.h> #include <mach/at91_dbgu.h> +#include <mach/at91_pmc.h> static inline void arch_idle(void) { +#ifndef CONFIG_DEBUG_KERNEL /* * Disable the processor clock. The processor will be automatically * re-enabled by an interrupt or by a reset. */ -// at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); - + at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); +#else /* * Set the processor (CP15) into 'Wait for Interrupt' mode. * Unlike disabling the processor clock via the PMC (above) * this allows the processor to be woken via JTAG. */ cpu_do_idle(); +#endif } void (*at91_arch_reset)(void); diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c index 53dd2a9eecf..2f139196d63 100644 --- a/arch/arm/mach-bcmring/arch.c +++ b/arch/arm/mach-bcmring/arch.c @@ -29,6 +29,7 @@ #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/mach/time.h> +#include <asm/pmu.h> #include <asm/mach/arch.h> #include <mach/dma.h> @@ -85,8 +86,23 @@ static struct platform_device nand_device = { .num_resources = ARRAY_SIZE(nand_resource), }; +static struct resource pmu_resource = { + .start = IRQ_PMUIRQ, + .end = IRQ_PMUIRQ, + .flags = IORESOURCE_IRQ, +}; + +static struct platform_device pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .resource = &pmu_resource, + .num_resources = 1, +}; + + static struct platform_device *devices[] __initdata = { &nand_device, + &pmu_device, }; /**************************************************************************** diff --git a/arch/arm/mach-clps711x/mm.c b/arch/arm/mach-clps711x/mm.c index a7b4591205a..98659217676 100644 --- a/arch/arm/mach-clps711x/mm.c +++ b/arch/arm/mach-clps711x/mm.c @@ -22,7 +22,6 @@ #include <linux/kernel.h> #include <linux/mm.h> #include <linux/init.h> -#include <linux/bootmem.h> #include <asm/sizes.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig new file mode 100644 index 00000000000..9ebfcc46feb --- /dev/null +++ b/arch/arm/mach-cns3xxx/Kconfig @@ -0,0 +1,12 @@ +menu "CNS3XXX platform type" + depends on ARCH_CNS3XXX + +config MACH_CNS3420VB + bool "Support for CNS3420 Validation Board" + help + Include support for the Cavium Networks CNS3420 MPCore Platform + Baseboard. + This is a platform with an on-board ARM11 MPCore and has support + for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc. + +endmenu diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile new file mode 100644 index 00000000000..427507a2d69 --- /dev/null +++ b/arch/arm/mach-cns3xxx/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o +obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o diff --git a/arch/arm/mach-cns3xxx/Makefile.boot b/arch/arm/mach-cns3xxx/Makefile.boot new file mode 100644 index 00000000000..77701286522 --- /dev/null +++ b/arch/arm/mach-cns3xxx/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00C00000 diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c new file mode 100644 index 00000000000..2e30c828874 --- /dev/null +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -0,0 +1,148 @@ +/* + * Cavium Networks CNS3420 Validation Board + * + * Copyright 2000 Deep Blue Solutions Ltd + * Copyright 2008 ARM Limited + * Copyright 2008 Cavium Networks + * Scott Shu + * Copyright 2010 MontaVista Software, LLC. + * Anton Vorontsov <avorontsov@mvista.com> + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/compiler.h> +#include <linux/io.h> +#include <linux/serial_core.h> +#include <linux/serial_8250.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/partitions.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <mach/hardware.h> +#include <mach/cns3xxx.h> +#include <mach/irqs.h> +#include "core.h" + +/* + * NOR Flash + */ +static struct mtd_partition cns3420_nor_partitions[] = { + { + .name = "uboot", + .size = 0x00040000, + .offset = 0, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .size = 0x004C0000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "filesystem", + .size = 0x7000000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "filesystem2", + .size = 0x0AE0000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "ubootenv", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + }, +}; + +static struct physmap_flash_data cns3420_nor_pdata = { + .width = 2, + .parts = cns3420_nor_partitions, + .nr_parts = ARRAY_SIZE(cns3420_nor_partitions), +}; + +static struct resource cns3420_nor_res = { + .start = CNS3XXX_FLASH_BASE, + .end = CNS3XXX_FLASH_BASE + SZ_128M - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, +}; + +static struct platform_device cns3420_nor_pdev = { + .name = "physmap-flash", + .id = 0, + .resource = &cns3420_nor_res, + .num_resources = 1, + .dev = { + .platform_data = &cns3420_nor_pdata, + }, +}; + +/* + * UART + */ +static void __init cns3420_early_serial_setup(void) +{ +#ifdef CONFIG_SERIAL_8250_CONSOLE + static struct uart_port cns3420_serial_port = { + .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT, + .mapbase = CNS3XXX_UART0_BASE, + .irq = IRQ_CNS3XXX_UART0, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, + .regshift = 2, + .uartclk = 24000000, + .line = 0, + .type = PORT_16550A, + .fifosize = 16, + }; + + early_serial_setup(&cns3420_serial_port); +#endif +} + +/* + * Initialization + */ +static struct platform_device *cns3420_pdevs[] __initdata = { + &cns3420_nor_pdev, +}; + +static void __init cns3420_init(void) +{ + platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); + + pm_power_off = cns3xxx_power_off; +} + +static struct map_desc cns3420_io_desc[] __initdata = { + { + .virtual = CNS3XXX_UART0_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static void __init cns3420_map_io(void) +{ + cns3xxx_map_io(); + iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc)); + + cns3420_early_serial_setup(); +} + +MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") + .phys_io = CNS3XXX_UART0_BASE, + .io_pg_offst = (CNS3XXX_UART0_BASE_VIRT >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = cns3420_map_io, + .init_irq = cns3xxx_init_irq, + .timer = &cns3xxx_timer, + .init_machine = cns3420_init, +MACHINE_END diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c new file mode 100644 index 00000000000..9ca4d581016 --- /dev/null +++ b/arch/arm/mach-cns3xxx/core.c @@ -0,0 +1,249 @@ +/* + * Copyright 1999 - 2003 ARM Limited + * Copyright 2000 Deep Blue Solutions Ltd + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/clockchips.h> +#include <linux/io.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/mach/irq.h> +#include <asm/hardware/gic.h> +#include <mach/cns3xxx.h> +#include "core.h" + +static struct map_desc cns3xxx_io_desc[] __initdata = { + { + .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_GPIOA_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_GPIOB_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_MISC_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_PM_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PM_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +void __init cns3xxx_map_io(void) +{ + iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc)); +} + +/* used by entry-macro.S */ +void __iomem *gic_cpu_base_addr; + +void __init cns3xxx_init_irq(void) +{ + gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT); + gic_dist_init(0, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), 29); + gic_cpu_init(0, gic_cpu_base_addr); +} + +void cns3xxx_power_off(void) +{ + u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT); + u32 clkctrl; + + printk(KERN_INFO "powering system down...\n"); + + clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET); + clkctrl &= 0xfffff1ff; + clkctrl |= (0x5 << 9); /* Hibernate */ + writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET); + +} + +/* + * Timer + */ +static void __iomem *cns3xxx_tmr1; + +static void cns3xxx_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + int pclk = cns3xxx_cpu_clock() / 8; + int reload; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + reload = pclk * 20 / (3 * HZ) * 0x25000; + writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); + ctrl |= (1 << 0) | (1 << 2) | (1 << 9); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ + ctrl |= (1 << 2) | (1 << 9); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + ctrl = 0; + } + + writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); +} + +static int cns3xxx_timer_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + + writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); + writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + + return 0; +} + +static struct clock_event_device cns3xxx_tmr1_clockevent = { + .name = "cns3xxx timer1", + .shift = 8, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = cns3xxx_timer_set_mode, + .set_next_event = cns3xxx_timer_set_next_event, + .rating = 350, + .cpumask = cpu_all_mask, +}; + +static void __init cns3xxx_clockevents_init(unsigned int timer_irq) +{ + cns3xxx_tmr1_clockevent.irq = timer_irq; + cns3xxx_tmr1_clockevent.mult = + div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC, + cns3xxx_tmr1_clockevent.shift); + cns3xxx_tmr1_clockevent.max_delta_ns = + clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent); + cns3xxx_tmr1_clockevent.min_delta_ns = + clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent); + + clockevents_register_device(&cns3xxx_tmr1_clockevent); +} + +/* + * IRQ handler for the timer + */ +static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &cns3xxx_tmr1_clockevent; + u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET; + u32 val; + + /* Clear the interrupt */ + val = readl(stat); + writel(val & ~(1 << 2), stat); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction cns3xxx_timer_irq = { + .name = "timer", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = cns3xxx_timer_interrupt, +}; + +/* + * Set up the clock source and clock events devices + */ +static void __init __cns3xxx_timer_init(unsigned int timer_irq) +{ + u32 val; + u32 irq_mask; + + /* + * Initialise to a known state (all timers off) + */ + + /* disable timer1 and timer2 */ + writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + /* stop free running timer3 */ + writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); + + /* timer1 */ + writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); + writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); + + writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); + writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); + + /* mask irq, non-mask timer1 overflow */ + irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); + irq_mask &= ~(1 << 2); + irq_mask |= 0x03; + writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); + + /* down counter */ + val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + val |= (1 << 9); + writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + + /* timer2 */ + writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); + writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); + + /* mask irq */ + irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); + irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); + writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); + + /* down counter */ + val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + val |= (1 << 10); + writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + + /* Make irqs happen for the system timer */ + setup_irq(timer_irq, &cns3xxx_timer_irq); + + cns3xxx_clockevents_init(timer_irq); +} + +static void __init cns3xxx_timer_init(void) +{ + cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT); + + __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0); +} + +struct sys_timer cns3xxx_timer = { + .init = cns3xxx_timer_init, +}; diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h new file mode 100644 index 00000000000..6b33ec11346 --- /dev/null +++ b/arch/arm/mach-cns3xxx/core.h @@ -0,0 +1,23 @@ +/* + * Copyright 2000 Deep Blue Solutions Ltd + * Copyright 2004 ARM Limited + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __CNS3XXX_CORE_H +#define __CNS3XXX_CORE_H + +extern void __iomem *gic_cpu_base_addr; +extern struct sys_timer cns3xxx_timer; + +void __init cns3xxx_map_io(void); +void __init cns3xxx_init_irq(void); +void cns3xxx_power_off(void); +void cns3xxx_pwr_power_up(unsigned int block); +void cns3xxx_pwr_power_down(unsigned int block); + +#endif /* __CNS3XXX_CORE_H */ diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h new file mode 100644 index 00000000000..8a2f5a21d4e --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h @@ -0,0 +1,635 @@ +/* + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_BOARD_CNS3XXXH +#define __MACH_BOARD_CNS3XXXH + +/* + * Memory map + */ +#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */ +#define CNS3XXX_FLASH_SIZE SZ_256M + +#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */ + +#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ + +#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ +#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000 + +#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ +#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000 + +#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ +#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000 + +#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ +#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000 + +#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ +#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000 + +#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ +#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000 + +#define SMC_MEMC_STATUS_OFFSET 0x000 +#define SMC_MEMIF_CFG_OFFSET 0x004 +#define SMC_MEMC_CFG_SET_OFFSET 0x008 +#define SMC_MEMC_CFG_CLR_OFFSET 0x00C +#define SMC_DIRECT_CMD_OFFSET 0x010 +#define SMC_SET_CYCLES_OFFSET 0x014 +#define SMC_SET_OPMODE_OFFSET 0x018 +#define SMC_REFRESH_PERIOD_0_OFFSET 0x020 +#define SMC_REFRESH_PERIOD_1_OFFSET 0x024 +#define SMC_SRAM_CYCLES0_0_OFFSET 0x100 +#define SMC_NAND_CYCLES0_0_OFFSET 0x100 +#define SMC_OPMODE0_0_OFFSET 0x104 +#define SMC_SRAM_CYCLES0_1_OFFSET 0x120 +#define SMC_NAND_CYCLES0_1_OFFSET 0x120 +#define SMC_OPMODE0_1_OFFSET 0x124 +#define SMC_USER_STATUS_OFFSET 0x200 +#define SMC_USER_CONFIG_OFFSET 0x204 +#define SMC_ECC_STATUS_OFFSET 0x300 +#define SMC_ECC_MEMCFG_OFFSET 0x304 +#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308 +#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C +#define SMC_ECC_ADDR0_OFFSET 0x310 +#define SMC_ECC_ADDR1_OFFSET 0x314 +#define SMC_ECC_VALUE0_OFFSET 0x318 +#define SMC_ECC_VALUE1_OFFSET 0x31C +#define SMC_ECC_VALUE2_OFFSET 0x320 +#define SMC_ECC_VALUE3_OFFSET 0x324 +#define SMC_PERIPH_ID_0_OFFSET 0xFE0 +#define SMC_PERIPH_ID_1_OFFSET 0xFE4 +#define SMC_PERIPH_ID_2_OFFSET 0xFE8 +#define SMC_PERIPH_ID_3_OFFSET 0xFEC +#define SMC_PCELL_ID_0_OFFSET 0xFF0 +#define SMC_PCELL_ID_1_OFFSET 0xFF4 +#define SMC_PCELL_ID_2_OFFSET 0xFF8 +#define SMC_PCELL_ID_3_OFFSET 0xFFC + +#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ +#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000 + +#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ +#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000 + +#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ +#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000 + +#define RTC_SEC_OFFSET 0x00 +#define RTC_MIN_OFFSET 0x04 +#define RTC_HOUR_OFFSET 0x08 +#define RTC_DAY_OFFSET 0x0C +#define RTC_SEC_ALM_OFFSET 0x10 +#define RTC_MIN_ALM_OFFSET 0x14 +#define RTC_HOUR_ALM_OFFSET 0x18 +#define RTC_REC_OFFSET 0x1C +#define RTC_CTRL_OFFSET 0x20 +#define RTC_INTR_STS_OFFSET 0x34 + +#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ +#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ + +#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ +#define CNS3XXX_PM_BASE_VIRT 0xFFF08000 + +#define PM_CLK_GATE_OFFSET 0x00 +#define PM_SOFT_RST_OFFSET 0x04 +#define PM_HS_CFG_OFFSET 0x08 +#define PM_CACTIVE_STA_OFFSET 0x0C +#define PM_PWR_STA_OFFSET 0x10 +#define PM_SYS_CLK_CTRL_OFFSET 0x14 +#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18 +#define PM_PLL_HM_PD_OFFSET 0x1C + +#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ +#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 + +#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ +#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 + +#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ +#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000 + +#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ +#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000 + +#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ +#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000 + +#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ +#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000 + +#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ +#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 + +#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ +#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 + +#define TIMER1_COUNTER_OFFSET 0x00 +#define TIMER1_AUTO_RELOAD_OFFSET 0x04 +#define TIMER1_MATCH_V1_OFFSET 0x08 +#define TIMER1_MATCH_V2_OFFSET 0x0C + +#define TIMER2_COUNTER_OFFSET 0x10 +#define TIMER2_AUTO_RELOAD_OFFSET 0x14 +#define TIMER2_MATCH_V1_OFFSET 0x18 +#define TIMER2_MATCH_V2_OFFSET 0x1C + +#define TIMER1_2_CONTROL_OFFSET 0x30 +#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34 +#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38 + +#define TIMER_FREERUN_OFFSET 0x40 +#define TIMER_FREERUN_CONTROL_OFFSET 0x44 + +#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ +#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000 + +#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ +#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000 + +#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ +#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000 + +#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ +#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000 + +#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ +#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 + +#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ +#define CNS3XXX_USB_BASE_VIRT 0xFFF16000 + +#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ +#define CNS3XXX_SATA2_SIZE SZ_16M +#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000 + +#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ +#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000 + +#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ +#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000 + +#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ +#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000 + +#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ +#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 + +#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ +#define CNS3XXX_USB_OHCI_BASE_VIRT 0xFFF1C000 + +#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ +#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 + +#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ +#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 + +#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ +#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 + +#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ +#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000 + +#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ +#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 + +#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */ +#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 + +#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ +#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000 + +#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ +#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000 + +#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ +#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 + +#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ +#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000 + +#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ +#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 + +#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */ +#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 + +#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ +#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000 + +/* + * Testchip peripheral and fpga gic regions + */ +#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ +#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 + +#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ +#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 + +#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 +#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 + +#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ +#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 + +#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ +#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 + +/* + * Misc block + */ +#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) +#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset)))) + +#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00) +#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04) +#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08) +#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C) +#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10) +#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14) +#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18) +#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C) +#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20) +#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24) +#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28) +#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C) +#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30) +#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34) +#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40) +#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44) +#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48) +#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C) +#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50) +#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54) + +#define MISC_SATA_POWER_MODE MISC_MEM_MAP_VALUE(0x310) + +#define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800) +#define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804) +#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808) +#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c) +#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810) +#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814) + +#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) +#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) +#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100) +#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100) +#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100) +#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100) +#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100) +#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100) +#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100) +#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100) +#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100) +#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100) +#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100) +#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100) +#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100) +#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) +#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) + +/* + * Power management and clock control + */ +#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset)))) + +#define PM_CLK_GATE_REG PMU_REG_VALUE(0x000) +#define PM_SOFT_RST_REG PMU_REG_VALUE(0x004) +#define PM_HS_CFG_REG PMU_REG_VALUE(0x008) +#define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C) +#define PM_PWR_STA_REG PMU_REG_VALUE(0x010) +#define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014) +#define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018) +#define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C) +#define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020) +#define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024) +#define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028) +#define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C) +#define PM_CSR_REG PMU_REG_VALUE(0x030) + +/* PM_CLK_GATE_REG */ +#define PM_CLK_GATE_REG_OFFSET_SDIO (25) +#define PM_CLK_GATE_REG_OFFSET_GPU (24) +#define PM_CLK_GATE_REG_OFFSET_CIM (23) +#define PM_CLK_GATE_REG_OFFSET_LCDC (22) +#define PM_CLK_GATE_REG_OFFSET_I2S (21) +#define PM_CLK_GATE_REG_OFFSET_RAID (20) +#define PM_CLK_GATE_REG_OFFSET_SATA (19) +#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x)) +#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16) +#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15) +#define PM_CLK_GATE_REG_OFFSET_TIMER (14) +#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13) +#define PM_CLK_GATE_REG_OFFSET_HCIE (12) +#define PM_CLK_GATE_REG_OFFSET_SWITCH (11) +#define PM_CLK_GATE_REG_OFFSET_GPIO (10) +#define PM_CLK_GATE_REG_OFFSET_UART3 (9) +#define PM_CLK_GATE_REG_OFFSET_UART2 (8) +#define PM_CLK_GATE_REG_OFFSET_UART1 (7) +#define PM_CLK_GATE_REG_OFFSET_RTC (5) +#define PM_CLK_GATE_REG_OFFSET_GDMA (4) +#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3) +#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1) +#define PM_CLK_GATE_REG_MASK (0x03FFFFBA) + +/* PM_SOFT_RST_REG */ +#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31) +#define PM_SOFT_RST_REG_OFFST_CPU1 (29) +#define PM_SOFT_RST_REG_OFFST_CPU0 (28) +#define PM_SOFT_RST_REG_OFFST_SDIO (25) +#define PM_SOFT_RST_REG_OFFST_GPU (24) +#define PM_SOFT_RST_REG_OFFST_CIM (23) +#define PM_SOFT_RST_REG_OFFST_LCDC (22) +#define PM_SOFT_RST_REG_OFFST_I2S (21) +#define PM_SOFT_RST_REG_OFFST_RAID (20) +#define PM_SOFT_RST_REG_OFFST_SATA (19) +#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x)) +#define PM_SOFT_RST_REG_OFFST_USB_HOST (16) +#define PM_SOFT_RST_REG_OFFST_USB_OTG (15) +#define PM_SOFT_RST_REG_OFFST_TIMER (14) +#define PM_SOFT_RST_REG_OFFST_CRYPTO (13) +#define PM_SOFT_RST_REG_OFFST_HCIE (12) +#define PM_SOFT_RST_REG_OFFST_SWITCH (11) +#define PM_SOFT_RST_REG_OFFST_GPIO (10) +#define PM_SOFT_RST_REG_OFFST_UART3 (9) +#define PM_SOFT_RST_REG_OFFST_UART2 (8) +#define PM_SOFT_RST_REG_OFFST_UART1 (7) +#define PM_SOFT_RST_REG_OFFST_RTC (5) +#define PM_SOFT_RST_REG_OFFST_GDMA (4) +#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3) +#define PM_SOFT_RST_REG_OFFST_DMC (2) +#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1) +#define PM_SOFT_RST_REG_OFFST_GLOBAL (0) +#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF) + +/* PMHS_CFG_REG */ +#define PM_HS_CFG_REG_OFFSET_SDIO (25) +#define PM_HS_CFG_REG_OFFSET_GPU (24) +#define PM_HS_CFG_REG_OFFSET_CIM (23) +#define PM_HS_CFG_REG_OFFSET_LCDC (22) +#define PM_HS_CFG_REG_OFFSET_I2S (21) +#define PM_HS_CFG_REG_OFFSET_RAID (20) +#define PM_HS_CFG_REG_OFFSET_SATA (19) +#define PM_HS_CFG_REG_OFFSET_PCIE1 (18) +#define PM_HS_CFG_REG_OFFSET_PCIE0 (17) +#define PM_HS_CFG_REG_OFFSET_USB_HOST (16) +#define PM_HS_CFG_REG_OFFSET_USB_OTG (15) +#define PM_HS_CFG_REG_OFFSET_TIMER (14) +#define PM_HS_CFG_REG_OFFSET_CRYPTO (13) +#define PM_HS_CFG_REG_OFFSET_HCIE (12) +#define PM_HS_CFG_REG_OFFSET_SWITCH (11) +#define PM_HS_CFG_REG_OFFSET_GPIO (10) +#define PM_HS_CFG_REG_OFFSET_UART3 (9) +#define PM_HS_CFG_REG_OFFSET_UART2 (8) +#define PM_HS_CFG_REG_OFFSET_UART1 (7) +#define PM_HS_CFG_REG_OFFSET_RTC (5) +#define PM_HS_CFG_REG_OFFSET_GDMA (4) +#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3) +#define PM_HS_CFG_REG_OFFSET_DMC (2) +#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1) +#define PM_HS_CFG_REG_MASK (0x03FFFFBE) +#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806) + +/* PM_CACTIVE_STA_REG */ +#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25) +#define PM_CACTIVE_STA_REG_OFFSET_GPU (24) +#define PM_CACTIVE_STA_REG_OFFSET_CIM (23) +#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22) +#define PM_CACTIVE_STA_REG_OFFSET_I2S (21) +#define PM_CACTIVE_STA_REG_OFFSET_RAID (20) +#define PM_CACTIVE_STA_REG_OFFSET_SATA (19) +#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18) +#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17) +#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16) +#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15) +#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14) +#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13) +#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12) +#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11) +#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10) +#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9) +#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8) +#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7) +#define PM_CACTIVE_STA_REG_OFFSET_RTC (5) +#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4) +#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3) +#define PM_CACTIVE_STA_REG_OFFSET_DMC (2) +#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1) +#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE) + +/* PM_PWR_STA_REG */ +#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25) +#define PM_PWR_STA_REG_REG_OFFSET_GPU (24) +#define PM_PWR_STA_REG_REG_OFFSET_CIM (23) +#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22) +#define PM_PWR_STA_REG_REG_OFFSET_I2S (21) +#define PM_PWR_STA_REG_REG_OFFSET_RAID (20) +#define PM_PWR_STA_REG_REG_OFFSET_SATA (19) +#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18) +#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17) +#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16) +#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15) +#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14) +#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13) +#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12) +#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11) +#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10) +#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9) +#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8) +#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7) +#define PM_PWR_STA_REG_REG_OFFSET_RTC (5) +#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4) +#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3) +#define PM_PWR_STA_REG_REG_OFFSET_DMC (2) +#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1) +#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE) + +/* PM_CLK_CTRL_REG */ +#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31) +#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30) +#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29) +#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28) +#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27) +#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24) +#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22) +#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20) +#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16) +#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14) +#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12) +#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9) +#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7) +#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6) +#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4) +#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0) + +#define PM_CPU_CLK_DIV(DIV) { \ + PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ + PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ +} + +#define PM_PLL_CPU_SEL(CPU) { \ + PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ + PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ +} + +/* PM_PLL_LCD_I2S_CTRL_REG */ +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0) + +/* PM_PLL_HM_PD_CTRL_REG */ +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2) +#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C) + +/* PM_WDT_CTRL_REG */ +#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0) + +/* PM_CSR_REG - Clock Scaling Register*/ +#define PM_CSR_REG_OFFSET_CSR_EN (30) +#define PM_CSR_REG_OFFSET_CSR_NUM (0) + +#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK) + +/* Software reset*/ +#define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK) + +/* + * CNS3XXX support several power saving mode as following, + * DFS, IDLE, HALT, DOZE, SLEEP, Hibernate + */ +#define CNS3XXX_PWR_CPU_MODE_DFS (0) +#define CNS3XXX_PWR_CPU_MODE_IDLE (1) +#define CNS3XXX_PWR_CPU_MODE_HALT (2) +#define CNS3XXX_PWR_CPU_MODE_DOZE (3) +#define CNS3XXX_PWR_CPU_MODE_SLEEP (4) +#define CNS3XXX_PWR_CPU_MODE_HIBERNATE (5) + +#define CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK) +#define CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK + +/* Change CPU frequency and divider */ +#define CNS3XXX_PWR_PLL_CPU_300MHZ (0) +#define CNS3XXX_PWR_PLL_CPU_333MHZ (1) +#define CNS3XXX_PWR_PLL_CPU_366MHZ (2) +#define CNS3XXX_PWR_PLL_CPU_400MHZ (3) +#define CNS3XXX_PWR_PLL_CPU_433MHZ (4) +#define CNS3XXX_PWR_PLL_CPU_466MHZ (5) +#define CNS3XXX_PWR_PLL_CPU_500MHZ (6) +#define CNS3XXX_PWR_PLL_CPU_533MHZ (7) +#define CNS3XXX_PWR_PLL_CPU_566MHZ (8) +#define CNS3XXX_PWR_PLL_CPU_600MHZ (9) +#define CNS3XXX_PWR_PLL_CPU_633MHZ (10) +#define CNS3XXX_PWR_PLL_CPU_666MHZ (11) +#define CNS3XXX_PWR_PLL_CPU_700MHZ (12) + +#define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0) +#define CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1) +#define CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2) + +/* Change DDR2 frequency */ +#define CNS3XXX_PWR_PLL_DDR2_200MHZ (0) +#define CNS3XXX_PWR_PLL_DDR2_266MHZ (1) +#define CNS3XXX_PWR_PLL_DDR2_333MHZ (2) +#define CNS3XXX_PWR_PLL_DDR2_400MHZ (3) + +void cns3xxx_pwr_soft_rst(unsigned int block); +void cns3xxx_pwr_clk_en(unsigned int block); +int cns3xxx_cpu_clock(void); + +/* + * ARM11 MPCore interrupt sources (primary GIC) + */ +#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0) +#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1) +#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2) +#define IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3) +#define IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4) +#define IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5) +#define IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6) +#define IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7) +#define IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8) +#define IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9) +#define IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10) +#define IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11) +#define IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12) +#define IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13) +#define IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14) +#define IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15) +#define IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16) + +#define IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17) +#define IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18) +#define IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19) +#define IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20) +#define IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21) +#define IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22) +#define IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23) +#define IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24) +#define IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25) +#define IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26) + +#define IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27) +#define IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28) +#define IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29) +#define IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30) +#define IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31) +#define IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32) +#define IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33) +#define IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34) +#define IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35) + +#define IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36) +#define IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37) +#define IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38) +#define IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39) +#define IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40) +#define IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41) +#define IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42) +#define IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43) +#define IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44) +#define IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45) +#define IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46) +#define IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47) +#define IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48) +#define IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49) +#define IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50) +#define IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51) +#define IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52) +#define IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53) +#define IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54) + +#define IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55) +#define IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56) +#define IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57) +#define IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58) +#define IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59) +#define IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60) +#define IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61) +#define IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62) +#define IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63) + +#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64) + +#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_CNS3XXX +#endif + +#endif /* __MACH_BOARD_CNS3XXX_H */ diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S new file mode 100644 index 00000000000..d16ce7eb00e --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S @@ -0,0 +1,21 @@ +/* + * Debugging macro include header + * + * Copyright 1994-1999 Russell King + * Copyright 2008 Cavium Networks + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x10000000 + movne \rx, #0xf0000000 @ virtual base + orr \rx, \rx, #0x00009000 + .endm + +#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S new file mode 100644 index 00000000000..5e1c5545680 --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S @@ -0,0 +1,82 @@ +/* + * Low-level IRQ helper macros for Cavium Networks platforms + * + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include <mach/hardware.h> +#include <asm/hardware/gic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =gic_cpu_base_addr + ldr \base, [\base] + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + /* + * The interrupt numbering scheme is defined in the + * interrupt controller spec. To wit: + * + * Interrupts 0-15 are IPI + * 16-28 are reserved + * 29-31 are local. We allow 30 to be used for the watchdog. + * 32-1020 are global + * 1021-1022 are reserved + * 1023 is "spurious" (no interrupt) + * + * For now, we ignore all local interrupts so only return an interrupt if it's + * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. + * + * A simple read from the controller will tell us the number of the highest + * priority enabled interrupt. We then just need to check whether it is in the + * valid range for an IRQ (30-1020 inclusive). + */ + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ + + ldr \tmp, =1021 + + bic \irqnr, \irqstat, #0x1c00 + + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr + + .endm + + /* We assume that irqstat (the raw value of the IRQ acknowledge + * register) is preserved from the macro above. + * If there is an IPI, we immediately signal end of interrupt on the + * controller, since this requires the original irqstat value which + * we won't easily be able to recreate later. + */ + + .macro test_for_ipi, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #16 + strcc \irqstat, [\base, #GIC_CPU_EOI] + cmpcs \irqnr, \irqnr + .endm + + /* As above, this assumes that irqstat and base are preserved.. */ + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #29 + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm diff --git a/arch/arm/mach-cns3xxx/include/mach/hardware.h b/arch/arm/mach-cns3xxx/include/mach/hardware.h new file mode 100644 index 00000000000..57e09836f9d --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/hardware.h @@ -0,0 +1,22 @@ +/* + * This file contains the hardware definitions of the Cavium Networks boards. + * + * Copyright 2003 ARM Limited. + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H + +#include <asm/sizes.h> + +/* macro to get at IO space when running virtually */ +#define PCIBIOS_MIN_IO 0x00000000 +#define PCIBIOS_MIN_MEM 0x00000000 +#define pcibios_assign_all_busses() 1 + +#endif diff --git a/arch/arm/mach-cns3xxx/include/mach/io.h b/arch/arm/mach-cns3xxx/include/mach/io.h new file mode 100644 index 00000000000..33b6fc1ece7 --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/io.h @@ -0,0 +1,17 @@ +/* + * Copyright 2008 Cavium Networks + * Copyright 2003 ARM Limited + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ +#ifndef __MACH_IO_H +#define __MACH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-cns3xxx/include/mach/irqs.h b/arch/arm/mach-cns3xxx/include/mach/irqs.h new file mode 100644 index 00000000000..2ab96f8085c --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h @@ -0,0 +1,24 @@ +/* + * Copyright 2000 Deep Blue Solutions Ltd. + * Copyright 2003 ARM Limited + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define IRQ_LOCALTIMER 29 +#define IRQ_LOCALWDOG 30 +#define IRQ_TC11MP_GIC_START 32 + +#include <mach/cns3xxx.h> + +#ifndef NR_IRQS +#error "NR_IRQS not defined by the board-specific files" +#endif + +#endif diff --git a/arch/arm/mach-cns3xxx/include/mach/memory.h b/arch/arm/mach-cns3xxx/include/mach/memory.h new file mode 100644 index 00000000000..3b6b769b7a2 --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/memory.h @@ -0,0 +1,26 @@ +/* + * Copyright 2003 ARM Limited + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_MEMORY_H +#define __MACH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x00000000) + +#define __phys_to_bus(x) ((x) + PHYS_OFFSET) +#define __bus_to_phys(x) ((x) - PHYS_OFFSET) + +#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v)) +#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b)) +#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p)) +#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b)) + +#endif diff --git a/arch/arm/mach-cns3xxx/include/mach/system.h b/arch/arm/mach-cns3xxx/include/mach/system.h new file mode 100644 index 00000000000..58bb03ae3cf --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/system.h @@ -0,0 +1,29 @@ +/* + * Copyright 2000 Deep Blue Solutions Ltd + * Copyright 2003 ARM Limited + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_SYSTEM_H +#define __MACH_SYSTEM_H + +#include <linux/io.h> +#include <asm/proc-fns.h> +#include <mach/hardware.h> + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +void arch_reset(char mode, const char *cmd); + +#endif diff --git a/arch/arm/mach-cns3xxx/include/mach/timex.h b/arch/arm/mach-cns3xxx/include/mach/timex.h new file mode 100644 index 00000000000..1fd04217cac --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/timex.h @@ -0,0 +1,12 @@ +/* + * Cavium Networks architecture timex specifications + * + * Copyright 2003 ARM Limited + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h new file mode 100644 index 00000000000..de8ead9b91f --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h @@ -0,0 +1,55 @@ +/* + * Copyright 2003 ARM Limited + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include <asm/mach-types.h> +#include <mach/hardware.h> +#include <mach/cns3xxx.h> + +#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) +#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) +#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) +#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) + +/* + * Return the UART base address + */ +static inline unsigned long get_uart_base(void) +{ + if (machine_is_cns3420vb()) + return CNS3XXX_UART0_BASE; + else + return 0; +} + +/* + * This does not append a newline + */ +static inline void putc(int c) +{ + unsigned long base = get_uart_base(); + + while (AMBA_UART_FR(base) & (1 << 5)) + barrier(); + + AMBA_UART_DR(base) = c; +} + +static inline void flush(void) +{ + unsigned long base = get_uart_base(); + + while (AMBA_UART_FR(base) & (1 << 3)) + barrier(); +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h new file mode 100644 index 00000000000..4d381ec0527 --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h @@ -0,0 +1,11 @@ +/* + * Copyright 2000 Russell King. + * Copyright 2003 ARM Limited + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#define VMALLOC_END 0xd8000000 diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c new file mode 100644 index 00000000000..725e1a4fc23 --- /dev/null +++ b/arch/arm/mach-cns3xxx/pm.c @@ -0,0 +1,86 @@ +/* + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/delay.h> +#include <mach/system.h> +#include <mach/cns3xxx.h> + +void cns3xxx_pwr_clk_en(unsigned int block) +{ + PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK); +} + +void cns3xxx_pwr_power_up(unsigned int block) +{ + PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL); + + /* Wait for 300us for the PLL output clock locked. */ + udelay(300); +}; + +void cns3xxx_pwr_power_down(unsigned int block) +{ + /* write '1' to power down */ + PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL); +}; + +static void cns3xxx_pwr_soft_rst_force(unsigned int block) +{ + /* + * bit 0, 28, 29 => program low to reset, + * the other else program low and then high + */ + if (block & 0x30000001) { + PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK); + } else { + PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK); + PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK); + } +} + +void cns3xxx_pwr_soft_rst(unsigned int block) +{ + static unsigned int soft_reset; + + if (soft_reset & block) { + /* SPI/I2C/GPIO use the same block, reset once. */ + return; + } else { + soft_reset |= block; + } + cns3xxx_pwr_soft_rst_force(block); +} + +void arch_reset(char mode, const char *cmd) +{ + /* + * To reset, we hit the on-board reset register + * in the system FPGA. + */ + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL)); +} + +/* + * cns3xxx_cpu_clock - return CPU/L2 clock + * aclk: cpu clock/2 + * hclk: cpu clock/4 + * pclk: cpu clock/8 + */ +int cns3xxx_cpu_clock(void) +{ + int cpu; + int cpu_sel; + int div_sel; + + cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; + div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; + + cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel; + + return cpu; +} diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 0ebe185610b..0316e201ada 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -7,6 +7,7 @@ config CP_INTC bool config ARCH_DAVINCI_DMx + select CPU_ARM926T bool menu "TI DaVinci Implementations" @@ -41,6 +42,7 @@ config ARCH_DAVINCI_DA850 select ARCH_HAS_CPUFREQ config ARCH_DAVINCI_DA8XX + select CPU_ARM926T bool config ARCH_DAVINCI_DM365 diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index dc19870b23c..212d97084bd 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -33,9 +33,6 @@ #define DA830_EVM_PHY_MASK 0x0 #define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ -#define DA830_EMIF25_ASYNC_DATA_CE3_BASE 0x62000000 -#define DA830_EMIF25_CONTROL_BASE 0x68000000 - /* * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. */ @@ -157,7 +154,7 @@ static __init void da830_evm_usb_init(void) __func__, ret); } - ret = da8xx_pinmux_setup(da830_evm_usb11_pins); + ret = davinci_cfg_reg_list(da830_evm_usb11_pins); if (ret) { pr_warning("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret); @@ -229,15 +226,22 @@ static const short da830_evm_mmc_sd_pins[] = { }; #define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1) +#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2) static int da830_evm_mmc_get_ro(int index) { return gpio_get_value(DA830_MMCSD_WP_PIN); } +static int da830_evm_mmc_get_cd(int index) +{ + return !gpio_get_value(DA830_MMCSD_CD_PIN); +} + static struct davinci_mmc_config da830_evm_mmc_config = { .get_ro = da830_evm_mmc_get_ro, - .wires = 4, + .get_cd = da830_evm_mmc_get_cd, + .wires = 8, .max_freq = 50000000, .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, .version = MMC_CTLR_VERSION_2, @@ -247,7 +251,7 @@ static inline void da830_evm_init_mmc(void) { int ret; - ret = da8xx_pinmux_setup(da830_evm_mmc_sd_pins); + ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins); if (ret) { pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n", ret); @@ -262,6 +266,14 @@ static inline void da830_evm_init_mmc(void) } gpio_direction_input(DA830_MMCSD_WP_PIN); + ret = gpio_request(DA830_MMCSD_CD_PIN, "MMC CD\n"); + if (ret) { + pr_warning("da830_evm_init: can not open GPIO %d\n", + DA830_MMCSD_CD_PIN); + return; + } + gpio_direction_input(DA830_MMCSD_CD_PIN); + ret = da8xx_register_mmcsd0(&da830_evm_mmc_config); if (ret) { pr_warning("da830_evm_init: mmc/sd registration failed: %d\n", @@ -360,13 +372,13 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = { static struct resource da830_evm_nand_resources[] = { [0] = { /* First memory resource is NAND I/O window */ - .start = DA830_EMIF25_ASYNC_DATA_CE3_BASE, - .end = DA830_EMIF25_ASYNC_DATA_CE3_BASE + PAGE_SIZE - 1, + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1, .flags = IORESOURCE_MEM, }, [1] = { /* Second memory resource is AEMIF control registers */ - .start = DA830_EMIF25_CONTROL_BASE, - .end = DA830_EMIF25_CONTROL_BASE + SZ_32K - 1, + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, .flags = IORESOURCE_MEM, }, }; @@ -392,7 +404,7 @@ static inline void da830_evm_init_nand(int mux_mode) return; } - ret = da8xx_pinmux_setup(da830_evm_emif25_pins); + ret = davinci_cfg_reg_list(da830_evm_emif25_pins); if (ret) pr_warning("da830_evm_init: emif25 mux setup failed: %d\n", ret); @@ -412,7 +424,7 @@ static inline void da830_evm_init_lcdc(int mux_mode) { int ret; - ret = da8xx_pinmux_setup(da830_lcdcntl_pins); + ret = davinci_cfg_reg_list(da830_lcdcntl_pins); if (ret) pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n", ret); @@ -492,7 +504,7 @@ static __init void da830_evm_init(void) pr_warning("da830_evm_init: edma registration failed: %d\n", ret); - ret = da8xx_pinmux_setup(da830_i2c0_pins); + ret = davinci_cfg_reg_list(da830_i2c0_pins); if (ret) pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n", ret); @@ -508,7 +520,7 @@ static __init void da830_evm_init(void) soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY; soc_info->emac_pdata->rmii_en = 1; - ret = da8xx_pinmux_setup(da830_cpgmac_pins); + ret = davinci_cfg_reg_list(da830_cpgmac_pins); if (ret) pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n", ret); @@ -527,7 +539,7 @@ static __init void da830_evm_init(void) i2c_register_board_info(1, da830_evm_i2c_devices, ARRAY_SIZE(da830_evm_i2c_devices)); - ret = da8xx_pinmux_setup(da830_evm_mcasp1_pins); + ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins); if (ret) pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n", ret); @@ -549,14 +561,6 @@ static int __init da830_evm_console_init(void) console_initcall(da830_evm_console_init); #endif -static __init void da830_evm_irq_init(void) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - - cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ, - soc_info->intc_irq_prios); -} - static void __init da830_evm_map_io(void) { da830_init(); @@ -567,7 +571,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM") .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DA8XX_DDR_BASE + 0x100), .map_io = da830_evm_map_io, - .init_irq = da830_evm_irq_init, + .init_irq = cp_intc_init, .timer = &davinci_timer, .init_machine = da830_evm_init, MACHINE_END diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 411284d0b0f..abd04932917 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -206,12 +206,12 @@ static __init void da850_evm_setup_nor_nand(void) int ret = 0; if (ui_card_detected & !HAS_MMC) { - ret = da8xx_pinmux_setup(da850_nand_pins); + ret = davinci_cfg_reg_list(da850_nand_pins); if (ret) pr_warning("da850_evm_init: nand mux setup failed: " "%d\n", ret); - ret = da8xx_pinmux_setup(da850_nor_pins); + ret = davinci_cfg_reg_list(da850_nor_pins); if (ret) pr_warning("da850_evm_init: nor mux setup failed: %d\n", ret); @@ -568,12 +568,12 @@ static int __init da850_evm_config_emac(void) if (rmii_en) { val |= BIT(8); - ret = da8xx_pinmux_setup(da850_rmii_pins); + ret = davinci_cfg_reg_list(da850_rmii_pins); pr_info("EMAC: RMII PHY configured, MII PHY will not be" " functional\n"); } else { val &= ~BIT(8); - ret = da8xx_pinmux_setup(da850_cpgmac_pins); + ret = davinci_cfg_reg_list(da850_cpgmac_pins); pr_info("EMAC: MII PHY configured, RMII PHY will not be" " functional\n"); } @@ -626,7 +626,7 @@ static __init void da850_evm_init(void) pr_warning("da850_evm_init: edma registration failed: %d\n", ret); - ret = da8xx_pinmux_setup(da850_i2c0_pins); + ret = davinci_cfg_reg_list(da850_i2c0_pins); if (ret) pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n", ret); @@ -643,7 +643,7 @@ static __init void da850_evm_init(void) ret); if (HAS_MMC) { - ret = da8xx_pinmux_setup(da850_mmcsd0_pins); + ret = davinci_cfg_reg_list(da850_mmcsd0_pins); if (ret) pr_warning("da850_evm_init: mmcsd0 mux setup failed:" " %d\n", ret); @@ -679,20 +679,20 @@ static __init void da850_evm_init(void) __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30); __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30); - ret = da8xx_pinmux_setup(da850_mcasp_pins); + ret = davinci_cfg_reg_list(da850_mcasp_pins); if (ret) pr_warning("da850_evm_init: mcasp mux setup failed: %d\n", ret); da8xx_register_mcasp(0, &da850_evm_snd_data); - ret = da8xx_pinmux_setup(da850_lcdcntl_pins); + ret = davinci_cfg_reg_list(da850_lcdcntl_pins); if (ret) pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n", ret); /* Handle board specific muxing for LCD here */ - ret = da8xx_pinmux_setup(da850_evm_lcdc_pins); + ret = davinci_cfg_reg_list(da850_evm_lcdc_pins); if (ret) pr_warning("da850_evm_init: evm specific lcd mux setup " "failed: %d\n", ret); @@ -736,14 +736,6 @@ static int __init da850_evm_console_init(void) console_initcall(da850_evm_console_init); #endif -static __init void da850_evm_irq_init(void) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - - cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ, - soc_info->intc_irq_prios); -} - static void __init da850_evm_map_io(void) { da850_init(); @@ -754,7 +746,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM") .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DA8XX_DDR_BASE + 0x100), .map_io = da850_evm_map_io, - .init_irq = da850_evm_irq_init, + .init_irq = cp_intc_init, .timer = &davinci_timer, .init_machine = da850_evm_init, MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index aa48e3f6971..a3191015efe 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -33,9 +33,6 @@ #include <mach/mmc.h> #include <mach/usb.h> -#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 - /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you * swap chips, maybe with a different block size, partitioning may @@ -86,12 +83,12 @@ static struct davinci_nand_pdata davinci_nand_data = { static struct resource davinci_nand_resources[] = { { - .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, - .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, + .start = DM355_ASYNC_EMIF_DATA_CE0_BASE, + .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, .flags = IORESOURCE_MEM, }, { - .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, - .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .start = DM355_ASYNC_EMIF_CONTROL_BASE, + .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; @@ -353,17 +350,12 @@ static __init void dm355_evm_init(void) dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data); } -static __init void dm355_evm_irq_init(void) -{ - davinci_irq_init(); -} - MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (0x80000100), .map_io = dm355_evm_map_io, - .init_irq = dm355_evm_irq_init, + .init_irq = davinci_irq_init, .timer = &davinci_timer, .init_machine = dm355_evm_init, MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index 21f32eb41e8..f1d8132cf0c 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -30,9 +30,6 @@ #include <mach/mmc.h> #include <mach/usb.h> -#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 - /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you * swap chips, maybe with a different block size, partitioning may @@ -82,12 +79,12 @@ static struct davinci_nand_pdata davinci_nand_data = { static struct resource davinci_nand_resources[] = { { - .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, - .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, + .start = DM355_ASYNC_EMIF_DATA_CE0_BASE, + .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, .flags = IORESOURCE_MEM, }, { - .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, - .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .start = DM355_ASYNC_EMIF_CONTROL_BASE, + .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; @@ -272,17 +269,12 @@ static __init void dm355_leopard_init(void) ARRAY_SIZE(dm355_leopard_spi_info)); } -static __init void dm355_leopard_irq_init(void) -{ - davinci_irq_init(); -} - MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (0x80000100), .map_io = dm355_leopard_map_io, - .init_irq = dm355_leopard_irq_init, + .init_irq = davinci_irq_init, .timer = &davinci_timer, .init_machine = dm355_leopard_init, MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index df4ab210586..84acef1d0b3 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -54,11 +54,6 @@ static inline int have_tvp7002(void) return 0; } - -#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000 -#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 -#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 - #define DM365_EVM_PHY_MASK (0x2) #define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ @@ -605,7 +600,11 @@ static __init void dm365_evm_init(void) /* maybe setup mmc1/etc ... _after_ mmc0 */ evm_init_cpld(); +#ifdef CONFIG_SND_DM365_AIC3X_CODEC dm365_init_asp(&dm365_evm_snd_data); +#elif defined(CONFIG_SND_DM365_VOICE_CODEC) + dm365_init_vc(&dm365_evm_snd_data); +#endif dm365_init_rtc(); dm365_init_ks(&dm365evm_ks_data); @@ -613,17 +612,12 @@ static __init void dm365_evm_init(void) ARRAY_SIZE(dm365_evm_spi_info)); } -static __init void dm365_evm_irq_init(void) -{ - davinci_irq_init(); -} - MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (0x80000100), .map_io = dm365_evm_map_io, - .init_irq = dm365_evm_irq_init, + .init_irq = davinci_irq_init, .timer = &davinci_timer, .init_machine = dm365_evm_init, MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 976e11b7fa4..34c8b418cd7 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -41,14 +41,6 @@ #define DM644X_EVM_PHY_MASK (0x2) #define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ -#define DAVINCI_CFC_ATA_BASE 0x01C66000 - -#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000 - #define LXT971_PHY_ID (0x001378e2) #define LXT971_PHY_MASK (0xfffffff0) @@ -92,8 +84,8 @@ static struct physmap_flash_data davinci_evm_norflash_data = { /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF * limits addresses to 16M, so using addresses past 16M will wrap */ static struct resource davinci_evm_norflash_resource = { - .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, - .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, + .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE, + .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, .flags = IORESOURCE_MEM, }; @@ -111,7 +103,7 @@ static struct platform_device davinci_evm_norflash_device = { * It may used instead of the (default) NOR chip to boot, using TI's * tools to install the secondary boot loader (UBL) and U-Boot. */ -struct mtd_partition davinci_evm_nandflash_partition[] = { +static struct mtd_partition davinci_evm_nandflash_partition[] = { /* Bootloader layout depends on whose u-boot is installed, but we * can hide all the details. * - block 0 for u-boot environment ... in mainline u-boot @@ -154,12 +146,12 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = { static struct resource davinci_evm_nandflash_resource[] = { { - .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, - .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, + .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE, + .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, .flags = IORESOURCE_MEM, }, { - .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, - .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .start = DM644X_ASYNC_EMIF_CONTROL_BASE, + .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; @@ -258,32 +250,6 @@ static struct platform_device rtc_dev = { .id = -1, }; -static struct resource ide_resources[] = { - { - .start = DAVINCI_CFC_ATA_BASE, - .end = DAVINCI_CFC_ATA_BASE + 0x7ff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_IDE, - .end = IRQ_IDE, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ide_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device ide_dev = { - .name = "palm_bk3710", - .id = -1, - .resource = ide_resources, - .num_resources = ARRAY_SIZE(ide_resources), - .dev = { - .dma_mask = &ide_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - static struct snd_platform_data dm644x_evm_snd_data; /*----------------------------------------------------------------------*/ @@ -704,10 +670,7 @@ static __init void davinci_evm_init(void) pr_warning("WARNING: both IDE and Flash are " "enabled, but they share AEMIF pins.\n" "\tDisable IDE for NAND/NOR support.\n"); - davinci_cfg_reg(DM644X_HPIEN_DISABLE); - davinci_cfg_reg(DM644X_ATAEN); - davinci_cfg_reg(DM644X_HDIREN); - platform_device_register(&ide_dev); + davinci_init_ide(); } else if (HAS_NAND || HAS_NOR) { davinci_cfg_reg(DM644X_HPIEN_DISABLE); davinci_cfg_reg(DM644X_ATAEN_DISABLE); @@ -741,18 +704,13 @@ static __init void davinci_evm_init(void) } -static __init void davinci_evm_irq_init(void) -{ - davinci_irq_init(); -} - MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") /* Maintainer: MontaVista Software <source@mvista.com> */ .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DAVINCI_DDR_BASE + 0x100), .map_io = davinci_evm_map_io, - .init_irq = davinci_evm_irq_init, + .init_irq = davinci_irq_init, .timer = &davinci_timer, .init_machine = davinci_evm_init, MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 5ba3cb2daaa..6d8889342c9 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -80,17 +80,14 @@ static struct davinci_nand_pdata davinci_nand_data = { .options = 0, }; -#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000 - static struct resource davinci_nand_resources[] = { { - .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, - .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, + .start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE, + .end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1, .flags = IORESOURCE_MEM, }, { - .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, - .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .start = DM646X_ASYNC_EMIF_CONTROL_BASE, + .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; @@ -736,17 +733,12 @@ static __init void evm_init(void) platform_device_register(&davinci_nand_device); if (HAS_ATA) - dm646x_init_ide(); + davinci_init_ide(); soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; } -static __init void davinci_dm646x_evm_irq_init(void) -{ - davinci_irq_init(); -} - #define DM646X_EVM_REF_FREQ 27000000 #define DM6467T_EVM_REF_FREQ 33000000 @@ -763,7 +755,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (0x80000100), .map_io = davinci_map_io, - .init_irq = davinci_dm646x_evm_irq_init, + .init_irq = davinci_irq_init, .timer = &davinci_timer, .init_machine = evm_init, MACHINE_END @@ -773,7 +765,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM") .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (0x80000100), .map_io = davinci_map_io, - .init_irq = davinci_dm646x_evm_irq_init, + .init_irq = davinci_irq_init, .timer = &davinci_timer, .init_machine = evm_init, MACHINE_END diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index bd9ca079b69..4c30e929bbf 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -31,6 +31,7 @@ #include <asm/mach/arch.h> #include <mach/dm644x.h> +#include <mach/common.h> #include <mach/i2c.h> #include <mach/serial.h> #include <mach/mux.h> @@ -41,11 +42,6 @@ #define NEUROS_OSD2_PHY_MASK 0x2 #define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ -#define DAVINCI_CFC_ATA_BASE 0x01C66000 - -#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 - #define LXT971_PHY_ID 0x001378e2 #define LXT971_PHY_MASK 0xfffffff0 @@ -60,7 +56,7 @@ #define NAND_BLOCK_SIZE SZ_128K -struct mtd_partition davinci_ntosd2_nandflash_partition[] = { +static struct mtd_partition davinci_ntosd2_nandflash_partition[] = { { /* UBL (a few copies) plus U-Boot */ .name = "bootloader", @@ -98,12 +94,12 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = { static struct resource davinci_ntosd2_nandflash_resource[] = { { - .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, - .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, + .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE, + .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, .flags = IORESOURCE_MEM, }, { - .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, - .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .start = DM644X_ASYNC_EMIF_CONTROL_BASE, + .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; @@ -130,32 +126,6 @@ static struct platform_device davinci_fb_device = { .num_resources = 0, }; -static struct resource ide_resources[] = { - { - .start = DAVINCI_CFC_ATA_BASE, - .end = DAVINCI_CFC_ATA_BASE + 0x7ff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_IDE, - .end = IRQ_IDE, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ide_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device ide_dev = { - .name = "palm_bk3710", - .id = -1, - .resource = ide_resources, - .num_resources = ARRAY_SIZE(ide_resources), - .dev = { - .dma_mask = &ide_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - static struct snd_platform_data dm644x_ntosd2_snd_data; static struct gpio_led ntosd2_leds[] = { @@ -259,10 +229,7 @@ static __init void davinci_ntosd2_init(void) pr_warning("WARNING: both IDE and Flash are " "enabled, but they share AEMIF pins.\n" "\tDisable IDE for NAND/NOR support.\n"); - davinci_cfg_reg(DM644X_HPIEN_DISABLE); - davinci_cfg_reg(DM644X_ATAEN); - davinci_cfg_reg(DM644X_HDIREN); - platform_device_register(&ide_dev); + davinci_init_ide(); } else if (HAS_NAND) { davinci_cfg_reg(DM644X_HPIEN_DISABLE); davinci_cfg_reg(DM644X_ATAEN_DISABLE); @@ -306,18 +273,13 @@ static __init void davinci_ntosd2_init(void) davinci_setup_mmc(0, &davinci_ntosd2_mmc_config); } -static __init void davinci_ntosd2_irq_init(void) -{ - davinci_irq_init(); -} - MACHINE_START(NEUROS_OSD2, "Neuros OSD2") /* Maintainer: Neuros Technologies <neuros@groups.google.com> */ .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DAVINCI_DDR_BASE + 0x100), .map_io = davinci_ntosd2_map_io, - .init_irq = davinci_ntosd2_irq_init, + .init_irq = davinci_irq_init, .timer = &davinci_timer, .init_machine = davinci_ntosd2_init, MACHINE_END diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index 08d373bfcc8..23e664a1a80 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c @@ -45,10 +45,7 @@ #define SFFSDR_PHY_MASK (0x2) #define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ -#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 - -struct mtd_partition davinci_sffsdr_nandflash_partition[] = { +static struct mtd_partition davinci_sffsdr_nandflash_partition[] = { /* U-Boot Environment: Block 0 * UBL: Block 1 * U-Boot: Blocks 6-7 (256 kb) @@ -76,12 +73,12 @@ static struct flash_platform_data davinci_sffsdr_nandflash_data = { static struct resource davinci_sffsdr_nandflash_resource[] = { { - .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, - .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, + .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE, + .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, .flags = IORESOURCE_MEM, }, { - .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, - .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .start = DM644X_ASYNC_EMIF_CONTROL_BASE, + .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; @@ -155,18 +152,13 @@ static __init void davinci_sffsdr_init(void) davinci_cfg_reg(DM644X_VLYNQWD); } -static __init void davinci_sffsdr_irq_init(void) -{ - davinci_irq_init(); -} - MACHINE_START(SFFSDR, "Lyrtech SFFSDR") /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */ .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DAVINCI_DDR_BASE + 0x100), .map_io = davinci_sffsdr_map_io, - .init_irq = davinci_sffsdr_irq_init, + .init_irq = davinci_irq_init, .timer = &davinci_timer, .init_machine = davinci_sffsdr_init, MACHINE_END diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c index aec37569054..ba8b12b2913 100644 --- a/arch/arm/mach-davinci/cdce949.c +++ b/arch/arm/mach-davinci/cdce949.c @@ -19,6 +19,7 @@ #include <linux/i2c.h> #include <mach/clock.h> +#include <mach/cdce949.h> #include "clock.h" diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index bf6218ee94e..054c303caea 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -22,6 +22,7 @@ #include <mach/hardware.h> +#include <mach/clock.h> #include <mach/psc.h> #include <mach/cputype.h> #include "clock.h" @@ -42,7 +43,8 @@ static void __clk_enable(struct clk *clk) if (clk->parent) __clk_enable(clk->parent); if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) - davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 1); + davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, + PSC_STATE_ENABLE); } static void __clk_disable(struct clk *clk) @@ -51,7 +53,9 @@ static void __clk_disable(struct clk *clk) return; if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC)) - davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0); + davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, + (clk->flags & PSC_SWRSTDISABLE) ? + PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE); if (clk->parent) __clk_disable(clk->parent); } @@ -233,7 +237,10 @@ static int __init clk_disable_unused(void) continue; pr_info("Clocks: disable unused %s\n", ck->name); - davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 0); + + davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, + (ck->flags & PSC_SWRSTDISABLE) ? + PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE); } spin_unlock_irq(&clockfw_lock); @@ -272,7 +279,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) v = __raw_readl(pll->base + clk->div_reg); if (v & PLLDIV_EN) { - plldiv = (v & PLLDIV_RATIO_MASK) + 1; + plldiv = (v & pll->div_ratio_mask) + 1; if (plldiv) rate /= plldiv; } @@ -295,7 +302,6 @@ static unsigned long clk_pllclk_recalc(struct clk *clk) struct pll_data *pll = clk->pll_data; unsigned long rate = clk->rate; - pll->base = IO_ADDRESS(pll->phys_base); ctrl = __raw_readl(pll->base + PLLCTL); rate = pll->input_rate = clk->parent->rate; @@ -312,7 +318,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk) if (pll->flags & PLL_HAS_PREDIV) { prediv = __raw_readl(pll->base + PREDIV); if (prediv & PLLDIV_EN) - prediv = (prediv & PLLDIV_RATIO_MASK) + 1; + prediv = (prediv & pll->div_ratio_mask) + 1; else prediv = 1; } @@ -324,7 +330,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk) if (pll->flags & PLL_HAS_POSTDIV) { postdiv = __raw_readl(pll->base + POSTDIV); if (postdiv & PLLDIV_EN) - postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; + postdiv = (postdiv & pll->div_ratio_mask) + 1; else postdiv = 1; } @@ -451,6 +457,18 @@ int __init davinci_clk_init(struct clk_lookup *clocks) clk->recalc = clk_leafclk_recalc; } + if (clk->pll_data) { + struct pll_data *pll = clk->pll_data; + + if (!pll->div_ratio_mask) + pll->div_ratio_mask = PLLDIV_RATIO_MASK; + + if (pll->phys_base && !pll->base) { + pll->base = ioremap(pll->phys_base, SZ_4K); + WARN_ON(!pll->base); + } + } + if (clk->recalc) clk->rate = clk->recalc(clk); diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index aa0a6115032..01e36483ac3 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -76,6 +76,7 @@ struct pll_data { u32 num; u32 flags; u32 input_rate; + u32 div_ratio_mask; }; #define PLL_HAS_PREDIV 0x01 #define PLL_HAS_POSTDIV 0x02 @@ -101,10 +102,11 @@ struct clk { /* Clock flags: SoC-specific flags start at BIT(16) */ #define ALWAYS_ENABLED BIT(1) -#define CLK_PSC BIT(2) -#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ +#define CLK_PSC BIT(2) +#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ #define CLK_PLL BIT(4) /* PLL-derived clock */ -#define PRE_PLL BIT(5) /* source is before PLL mult/div */ +#define PRE_PLL BIT(5) /* source is before PLL mult/div */ +#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */ #define CLK(dev, con, ck) \ { \ @@ -118,6 +120,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, unsigned int mult, unsigned int postdiv); extern struct platform_device davinci_wdt_device; +extern void davinci_watchdog_reset(struct platform_device *); #endif diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c index 94f27cbcd55..1d255739423 100644 --- a/arch/arm/mach-davinci/common.c +++ b/arch/arm/mach-davinci/common.c @@ -37,26 +37,43 @@ void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context) pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr); } -static struct davinci_id * __init davinci_get_id(u32 jtag_id) +static int __init davinci_init_id(struct davinci_soc_info *soc_info) { - int i; - struct davinci_id *dip; - u8 variant = (jtag_id & 0xf0000000) >> 28; - u16 part_no = (jtag_id & 0x0ffff000) >> 12; + int i; + struct davinci_id *dip; + u8 variant; + u16 part_no; + void __iomem *base; + + base = ioremap(soc_info->jtag_id_reg, SZ_4K); + if (!base) { + pr_err("Unable to map JTAG ID register\n"); + return -ENOMEM; + } + + soc_info->jtag_id = __raw_readl(base); + iounmap(base); + + variant = (soc_info->jtag_id & 0xf0000000) >> 28; + part_no = (soc_info->jtag_id & 0x0ffff000) >> 12; - for (i = 0, dip = davinci_soc_info.ids; i < davinci_soc_info.ids_num; + for (i = 0, dip = soc_info->ids; i < soc_info->ids_num; i++, dip++) /* Don't care about the manufacturer right now */ - if ((dip->part_no == part_no) && (dip->variant == variant)) - return dip; - - return NULL; + if ((dip->part_no == part_no) && (dip->variant == variant)) { + soc_info->cpu_id = dip->cpu_id; + pr_info("DaVinci %s variant 0x%x\n", dip->name, + dip->variant); + return 0; + } + + pr_err("Unknown DaVinci JTAG ID 0x%x\n", soc_info->jtag_id); + return -EINVAL; } void __init davinci_common_init(struct davinci_soc_info *soc_info) { int ret; - struct davinci_id *dip; if (!soc_info) { ret = -EINVAL; @@ -77,22 +94,16 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info) local_flush_tlb_all(); flush_cache_all(); + if (!davinci_soc_info.reset) + davinci_soc_info.reset = davinci_watchdog_reset; + /* * We want to check CPU revision early for cpu_is_xxxx() macros. * IO space mapping must be initialized before we can do that. */ - davinci_soc_info.jtag_id = __raw_readl(davinci_soc_info.jtag_id_base); - - dip = davinci_get_id(davinci_soc_info.jtag_id); - if (!dip) { - ret = -EINVAL; - pr_err("Unknown DaVinci JTAG ID 0x%x\n", - davinci_soc_info.jtag_id); + ret = davinci_init_id(&davinci_soc_info); + if (ret < 0) goto err; - } - - davinci_soc_info.cpu_id = dip->cpu_id; - pr_info("DaVinci %s variant 0x%x\n", dip->name, dip->variant); if (davinci_soc_info.cpu_clks) { ret = davinci_clk_init(davinci_soc_info.cpu_clks); @@ -101,8 +112,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info) goto err; } - davinci_intc_base = davinci_soc_info.intc_base; - davinci_intc_type = davinci_soc_info.intc_type; return; err: diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 37311d1830e..bb4c40ecb80 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -13,18 +13,17 @@ #include <linux/irq.h> #include <linux/io.h> +#include <mach/common.h> #include <mach/cp_intc.h> -static void __iomem *cp_intc_base; - static inline unsigned int cp_intc_read(unsigned offset) { - return __raw_readl(cp_intc_base + offset); + return __raw_readl(davinci_intc_base + offset); } static inline void cp_intc_write(unsigned long value, unsigned offset) { - __raw_writel(value, cp_intc_base + offset); + __raw_writel(value, davinci_intc_base + offset); } static void cp_intc_ack_irq(unsigned int irq) @@ -100,13 +99,18 @@ static struct irq_chip cp_intc_irq_chip = { .set_wake = cp_intc_set_wake, }; -void __init cp_intc_init(void __iomem *base, unsigned short num_irq, - u8 *irq_prio) +void __init cp_intc_init(void) { + unsigned long num_irq = davinci_soc_info.intc_irq_num; + u8 *irq_prio = davinci_soc_info.intc_irq_prios; + u32 *host_map = davinci_soc_info.intc_host_map; unsigned num_reg = BITS_TO_LONGS(num_irq); int i; - cp_intc_base = base; + davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC; + davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); + if (WARN_ON(!davinci_intc_base)) + return; cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); @@ -157,6 +161,10 @@ void __init cp_intc_init(void __iomem *base, unsigned short num_irq, cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i)); } + if (host_map) + for (i = 0; host_map[i] != -1; i++) + cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i)); + /* Set up genirq dispatching for cp_intc */ for (i = 0; i < num_irq; i++) { set_irq_chip(i, &cp_intc_irq_chip); diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index e8cb982f5e8..23e9eda5a37 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -19,6 +19,7 @@ #include <mach/common.h> #include <mach/time.h> #include <mach/da8xx.h> +#include <mach/gpio.h> #include "clock.h" #include "mux.h" @@ -1126,10 +1127,7 @@ static struct map_desc da830_io_desc[] = { }, }; -static void __iomem *da830_psc_bases[] = { - IO_ADDRESS(DA8XX_PSC0_BASE), - IO_ADDRESS(DA8XX_PSC1_BASE), -}; +static u32 da830_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE }; /* Contents of JTAG ID register used to identify exact cpu type */ static struct davinci_id da830_ids[] = { @@ -1158,14 +1156,14 @@ static struct davinci_id da830_ids[] = { static struct davinci_timer_instance da830_timer_instance[2] = { { - .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), + .base = DA8XX_TIMER64P0_BASE, .bottom_irq = IRQ_DA8XX_TINT12_0, .top_irq = IRQ_DA8XX_TINT34_0, .cmp_off = DA830_CMP12_0, .cmp_irq = IRQ_DA830_T12CMPINT0_0, }, { - .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), + .base = DA8XX_TIMER64P1_BASE, .bottom_irq = IRQ_DA8XX_TINT12_1, .top_irq = IRQ_DA8XX_TINT34_1, .cmp_off = DA830_CMP12_0, @@ -1187,34 +1185,33 @@ static struct davinci_timer_info da830_timer_info = { static struct davinci_soc_info davinci_soc_info_da830 = { .io_desc = da830_io_desc, .io_desc_num = ARRAY_SIZE(da830_io_desc), + .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, .ids = da830_ids, .ids_num = ARRAY_SIZE(da830_ids), .cpu_clks = da830_clks, .psc_bases = da830_psc_bases, .psc_bases_num = ARRAY_SIZE(da830_psc_bases), + .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da830_pins, .pinmux_pins_num = ARRAY_SIZE(da830_pins), - .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, + .intc_base = DA8XX_CP_INTC_BASE, .intc_type = DAVINCI_INTC_TYPE_CP_INTC, .intc_irq_prios = da830_default_priorities, .intc_irq_num = DA830_N_CP_INTC_IRQ, .timer_info = &da830_timer_info, - .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DA8XX_GPIO_BASE, .gpio_num = 128, .gpio_irq = IRQ_DA8XX_GPIO0, .serial_dev = &da8xx_serial_device, .emac_pdata = &da8xx_emac_pdata, + .reset_device = &da8xx_wdt_device, }; void __init da830_init(void) { - da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); - if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module")) - return; - - davinci_soc_info_da830.jtag_id_base = - DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG); - davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120); - davinci_common_init(&davinci_soc_info_da830); + + da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); + WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); } diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index d0fd7566712..6b8331bf8cf 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -27,6 +27,7 @@ #include <mach/da8xx.h> #include <mach/cpufreq.h> #include <mach/pm.h> +#include <mach/gpio.h> #include "clock.h" #include "mux.h" @@ -781,10 +782,7 @@ static struct map_desc da850_io_desc[] = { }, }; -static void __iomem *da850_psc_bases[] = { - IO_ADDRESS(DA8XX_PSC0_BASE), - IO_ADDRESS(DA8XX_PSC1_BASE), -}; +static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE }; /* Contents of JTAG ID register used to identify exact cpu type */ static struct davinci_id da850_ids[] = { @@ -799,22 +797,22 @@ static struct davinci_id da850_ids[] = { static struct davinci_timer_instance da850_timer_instance[4] = { { - .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), + .base = DA8XX_TIMER64P0_BASE, .bottom_irq = IRQ_DA8XX_TINT12_0, .top_irq = IRQ_DA8XX_TINT34_0, }, { - .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), + .base = DA8XX_TIMER64P1_BASE, .bottom_irq = IRQ_DA8XX_TINT12_1, .top_irq = IRQ_DA8XX_TINT34_1, }, { - .base = IO_ADDRESS(DA850_TIMER64P2_BASE), + .base = DA850_TIMER64P2_BASE, .bottom_irq = IRQ_DA850_TINT12_2, .top_irq = IRQ_DA850_TINT34_2, }, { - .base = IO_ADDRESS(DA850_TIMER64P3_BASE), + .base = DA850_TIMER64P3_BASE, .bottom_irq = IRQ_DA850_TINT12_3, .top_irq = IRQ_DA850_TINT34_3, }, @@ -1072,31 +1070,37 @@ no_ddrpll_mem: static struct davinci_soc_info davinci_soc_info_da850 = { .io_desc = da850_io_desc, .io_desc_num = ARRAY_SIZE(da850_io_desc), + .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, .ids = da850_ids, .ids_num = ARRAY_SIZE(da850_ids), .cpu_clks = da850_clks, .psc_bases = da850_psc_bases, .psc_bases_num = ARRAY_SIZE(da850_psc_bases), + .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da850_pins, .pinmux_pins_num = ARRAY_SIZE(da850_pins), - .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, + .intc_base = DA8XX_CP_INTC_BASE, .intc_type = DAVINCI_INTC_TYPE_CP_INTC, .intc_irq_prios = da850_default_priorities, .intc_irq_num = DA850_N_CP_INTC_IRQ, .timer_info = &da850_timer_info, - .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DA8XX_GPIO_BASE, .gpio_num = 144, .gpio_irq = IRQ_DA8XX_GPIO0, .serial_dev = &da8xx_serial_device, .emac_pdata = &da8xx_emac_pdata, .sram_dma = DA8XX_ARM_RAM_BASE, .sram_len = SZ_8K, + .reset_device = &da8xx_wdt_device, }; void __init da850_init(void) { unsigned int v; + davinci_common_init(&davinci_soc_info_da850); + da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module")) return; @@ -1105,12 +1109,6 @@ void __init da850_init(void) if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module")) return; - davinci_soc_info_da850.jtag_id_base = - DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG); - davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120); - - davinci_common_init(&davinci_soc_info_da850); - /* * Move the clock source of Async3 domain to PLL1 SYSCLK2. * This helps keeping the peripherals on this domain insulated diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 0a96791d3b0..8cda729be27 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -326,7 +326,7 @@ static struct resource da8xx_watchdog_resources[] = { }, }; -struct platform_device davinci_wdt_device = { +struct platform_device da8xx_wdt_device = { .name = "watchdog", .id = -1, .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), @@ -335,7 +335,7 @@ struct platform_device davinci_wdt_device = { int __init da8xx_register_watchdog(void) { - return platform_device_register(&davinci_wdt_device); + return platform_device_register(&da8xx_wdt_device); } static struct resource da8xx_emac_resources[] = { @@ -584,10 +584,17 @@ static struct platform_device da8xx_rtc_device = { int da8xx_register_rtc(void) { int ret; + void __iomem *base; + + base = ioremap(DA8XX_RTC_BASE, SZ_4K); + if (WARN_ON(!base)) + return -ENOMEM; /* Unlock the rtc's registers */ - __raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c)); - __raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70)); + __raw_writel(0x83e70b13, base + 0x6c); + __raw_writel(0x95a4f1e0, base + 0x70); + + iounmap(base); ret = platform_device_register(&da8xx_rtc_device); if (!ret) diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 147949650c2..8b7201e4c79 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -23,7 +23,10 @@ #include <mach/mmc.h> #include <mach/time.h> +#include "clock.h" + #define DAVINCI_I2C_BASE 0x01C21000 +#define DAVINCI_ATA_BASE 0x01C66000 #define DAVINCI_MMCSD0_BASE 0x01E10000 #define DM355_MMCSD0_BASE 0x01E11000 #define DM355_MMCSD1_BASE 0x01E00000 @@ -58,6 +61,49 @@ void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) (void) platform_device_register(&davinci_i2c_device); } +static struct resource ide_resources[] = { + { + .start = DAVINCI_ATA_BASE, + .end = DAVINCI_ATA_BASE + 0x7ff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_IDE, + .end = IRQ_IDE, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ide_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device ide_device = { + .name = "palm_bk3710", + .id = -1, + .resource = ide_resources, + .num_resources = ARRAY_SIZE(ide_resources), + .dev = { + .dma_mask = &ide_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init davinci_init_ide(void) +{ + if (cpu_is_davinci_dm644x()) { + davinci_cfg_reg(DM644X_HPIEN_DISABLE); + davinci_cfg_reg(DM644X_ATAEN); + davinci_cfg_reg(DM644X_HDIREN); + } else if (cpu_is_davinci_dm646x()) { + /* IRQ_DM646X_IDE is the same as IRQ_IDE */ + davinci_cfg_reg(DM646X_ATAEN); + } else { + WARN_ON(1); + return; + } + + platform_device_register(&ide_device); +} + #if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE) static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32); @@ -251,12 +297,12 @@ static void davinci_init_wdt(void) struct davinci_timer_instance davinci_timer_instance[2] = { { - .base = IO_ADDRESS(DAVINCI_TIMER0_BASE), + .base = DAVINCI_TIMER0_BASE, .bottom_irq = IRQ_TINT0_TINT12, .top_irq = IRQ_TINT0_TINT34, }, { - .base = IO_ADDRESS(DAVINCI_TIMER1_BASE), + .base = DAVINCI_TIMER1_BASE, .bottom_irq = IRQ_TINT1_TINT12, .top_irq = IRQ_TINT1_TINT34, }, diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 3dc0a88712e..383478116ef 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -450,11 +450,6 @@ void __init dm355_init_spi0(unsigned chipselect_mask, /*----------------------------------------------------------------------*/ -#define PINMUX0 0x00 -#define PINMUX1 0x04 -#define PINMUX2 0x08 -#define PINMUX3 0x0c -#define PINMUX4 0x10 #define INTMUX 0x18 #define EVTMUX 0x1c @@ -788,9 +783,7 @@ static struct davinci_id dm355_ids[] = { }, }; -static void __iomem *dm355_psc_bases[] = { - IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), -}; +static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; /* * T0_BOT: Timer 0, bottom: clockevent source for hrtimers @@ -798,7 +791,7 @@ static void __iomem *dm355_psc_bases[] = { * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) * T1_TOP: Timer 1, top : <unused> */ -struct davinci_timer_info dm355_timer_info = { +static struct davinci_timer_info dm355_timer_info = { .timers = davinci_timer_instance, .clockevent_id = T0_BOT, .clocksource_id = T0_TOP, @@ -845,26 +838,28 @@ static struct platform_device dm355_serial_device = { static struct davinci_soc_info davinci_soc_info_dm355 = { .io_desc = dm355_io_desc, .io_desc_num = ARRAY_SIZE(dm355_io_desc), - .jtag_id_base = IO_ADDRESS(0x01c40028), + .jtag_id_reg = 0x01c40028, .ids = dm355_ids, .ids_num = ARRAY_SIZE(dm355_ids), .cpu_clks = dm355_clks, .psc_bases = dm355_psc_bases, .psc_bases_num = ARRAY_SIZE(dm355_psc_bases), - .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), + .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm355_pins, .pinmux_pins_num = ARRAY_SIZE(dm355_pins), - .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), + .intc_base = DAVINCI_ARM_INTC_BASE, .intc_type = DAVINCI_INTC_TYPE_AINTC, .intc_irq_prios = dm355_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm355_timer_info, - .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DAVINCI_GPIO_BASE, .gpio_num = 104, .gpio_irq = IRQ_DM355_GPIOBNK0, .serial_dev = &dm355_serial_device, .sram_dma = 0x00010000, .sram_len = SZ_32K, + .reset_device = &davinci_wdt_device, }; void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata) diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 0d6ee583f65..a146849d78f 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -467,11 +467,6 @@ static struct clk_lookup dm365_clks[] = { /*----------------------------------------------------------------------*/ -#define PINMUX0 0x00 -#define PINMUX1 0x04 -#define PINMUX2 0x08 -#define PINMUX3 0x0c -#define PINMUX4 0x10 #define INTMUX 0x18 #define EVTMUX 0x1c @@ -490,11 +485,14 @@ MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false) MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false) MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false) -MUX_CFG(DM365, AEMIF_AR, 2, 0, 3, 1, false) +MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false) +MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false) MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false) MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false) MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false) MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false) +MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false) +MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false) MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false) MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false) @@ -573,9 +571,17 @@ MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false) MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false) MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false) +MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false) +MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false) +MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false) + MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false) +MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false) +MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false) +MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false) MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false) MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false) +MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false) MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false) MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false) @@ -1006,11 +1012,9 @@ static struct davinci_id dm365_ids[] = { }, }; -static void __iomem *dm365_psc_bases[] = { - IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), -}; +static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; -struct davinci_timer_info dm365_timer_info = { +static struct davinci_timer_info dm365_timer_info = { .timers = davinci_timer_instance, .clockevent_id = T0_BOT, .clocksource_id = T0_TOP, @@ -1049,21 +1053,22 @@ static struct platform_device dm365_serial_device = { static struct davinci_soc_info davinci_soc_info_dm365 = { .io_desc = dm365_io_desc, .io_desc_num = ARRAY_SIZE(dm365_io_desc), - .jtag_id_base = IO_ADDRESS(0x01c40028), + .jtag_id_reg = 0x01c40028, .ids = dm365_ids, .ids_num = ARRAY_SIZE(dm365_ids), .cpu_clks = dm365_clks, .psc_bases = dm365_psc_bases, .psc_bases_num = ARRAY_SIZE(dm365_psc_bases), - .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), + .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm365_pins, .pinmux_pins_num = ARRAY_SIZE(dm365_pins), - .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), + .intc_base = DAVINCI_ARM_INTC_BASE, .intc_type = DAVINCI_INTC_TYPE_AINTC, .intc_irq_prios = dm365_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm365_timer_info, - .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DAVINCI_GPIO_BASE, .gpio_num = 104, .gpio_irq = IRQ_DM365_GPIO0, .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ @@ -1071,6 +1076,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = { .emac_pdata = &dm365_emac_pdata, .sram_dma = 0x00010000, .sram_len = SZ_32K, + .reset_device = &davinci_wdt_device, }; void __init dm365_init_asp(struct snd_platform_data *pdata) diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 2f2ae8bc77b..7ad15208b84 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -277,7 +277,7 @@ static struct clk timer2_clk = { .usecount = 1, /* REVISIT: why cant' this be disabled? */ }; -struct clk_lookup dm644x_clks[] = { +static struct clk_lookup dm644x_clks[] = { CLK(NULL, "ref", &ref_clk), CLK(NULL, "pll1", &pll1_clk), CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), @@ -350,9 +350,6 @@ static struct platform_device dm644x_emac_device = { .resource = dm644x_emac_resources, }; -#define PINMUX0 0x00 -#define PINMUX1 0x04 - /* * Device specific mux setup * @@ -677,9 +674,7 @@ static struct davinci_id dm644x_ids[] = { }, }; -static void __iomem *dm644x_psc_bases[] = { - IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), -}; +static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; /* * T0_BOT: Timer 0, bottom: clockevent source for hrtimers @@ -687,7 +682,7 @@ static void __iomem *dm644x_psc_bases[] = { * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) * T1_TOP: Timer 1, top : <unused> */ -struct davinci_timer_info dm644x_timer_info = { +static struct davinci_timer_info dm644x_timer_info = { .timers = davinci_timer_instance, .clockevent_id = T0_BOT, .clocksource_id = T0_TOP, @@ -734,27 +729,29 @@ static struct platform_device dm644x_serial_device = { static struct davinci_soc_info davinci_soc_info_dm644x = { .io_desc = dm644x_io_desc, .io_desc_num = ARRAY_SIZE(dm644x_io_desc), - .jtag_id_base = IO_ADDRESS(0x01c40028), + .jtag_id_reg = 0x01c40028, .ids = dm644x_ids, .ids_num = ARRAY_SIZE(dm644x_ids), .cpu_clks = dm644x_clks, .psc_bases = dm644x_psc_bases, .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), - .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), + .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm644x_pins, .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), - .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), + .intc_base = DAVINCI_ARM_INTC_BASE, .intc_type = DAVINCI_INTC_TYPE_AINTC, .intc_irq_prios = dm644x_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm644x_timer_info, - .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DAVINCI_GPIO_BASE, .gpio_num = 71, .gpio_irq = IRQ_GPIOBNK0, .serial_dev = &dm644x_serial_device, .emac_pdata = &dm644x_emac_pdata, .sram_dma = 0x00008000, .sram_len = SZ_16K, + .reset_device = &davinci_wdt_device, }; void __init dm644x_init_asp(struct snd_platform_data *pdata) diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 893baf4ad37..94045656cff 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -311,7 +311,7 @@ static struct clk vpif1_clk = { .flags = ALWAYS_ENABLED, }; -struct clk_lookup dm646x_clks[] = { +static struct clk_lookup dm646x_clks[] = { CLK(NULL, "ref", &ref_clk), CLK(NULL, "aux", &aux_clkin), CLK(NULL, "pll1", &pll1_clk), @@ -401,9 +401,6 @@ static struct platform_device dm646x_emac_device = { .resource = dm646x_emac_resources, }; -#define PINMUX0 0x00 -#define PINMUX1 0x04 - /* * Device specific mux setup * @@ -596,32 +593,6 @@ static struct platform_device dm646x_edma_device = { .resource = edma_resources, }; -static struct resource ide_resources[] = { - { - .start = DM646X_ATA_REG_BASE, - .end = DM646X_ATA_REG_BASE + 0x7ff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_DM646X_IDE, - .end = IRQ_DM646X_IDE, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ide_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device ide_dev = { - .name = "palm_bk3710", - .id = -1, - .resource = ide_resources, - .num_resources = ARRAY_SIZE(ide_resources), - .dev = { - .dma_mask = &ide_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - static struct resource dm646x_mcasp0_resources[] = { { .name = "mcasp0", @@ -787,9 +758,7 @@ static struct davinci_id dm646x_ids[] = { }, }; -static void __iomem *dm646x_psc_bases[] = { - IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), -}; +static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; /* * T0_BOT: Timer 0, bottom: clockevent source for hrtimers @@ -797,7 +766,7 @@ static void __iomem *dm646x_psc_bases[] = { * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) * T1_TOP: Timer 1, top : <unused> */ -struct davinci_timer_info dm646x_timer_info = { +static struct davinci_timer_info dm646x_timer_info = { .timers = davinci_timer_instance, .clockevent_id = T0_BOT, .clocksource_id = T0_TOP, @@ -844,35 +813,31 @@ static struct platform_device dm646x_serial_device = { static struct davinci_soc_info davinci_soc_info_dm646x = { .io_desc = dm646x_io_desc, .io_desc_num = ARRAY_SIZE(dm646x_io_desc), - .jtag_id_base = IO_ADDRESS(0x01c40028), + .jtag_id_reg = 0x01c40028, .ids = dm646x_ids, .ids_num = ARRAY_SIZE(dm646x_ids), .cpu_clks = dm646x_clks, .psc_bases = dm646x_psc_bases, .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), - .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), + .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm646x_pins, .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), - .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), + .intc_base = DAVINCI_ARM_INTC_BASE, .intc_type = DAVINCI_INTC_TYPE_AINTC, .intc_irq_prios = dm646x_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm646x_timer_info, - .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DAVINCI_GPIO_BASE, .gpio_num = 43, /* Only 33 usable */ .gpio_irq = IRQ_DM646X_GPIOBNK0, .serial_dev = &dm646x_serial_device, .emac_pdata = &dm646x_emac_pdata, .sram_dma = 0x10010000, .sram_len = SZ_32K, + .reset_device = &davinci_wdt_device, }; -void __init dm646x_init_ide() -{ - davinci_cfg_reg(DM646X_ATAEN); - platform_device_register(&ide_dev); -} - void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) { dm646x_mcasp0_device.dev.platform_data = pdata; diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 53137387aee..d33827aadda 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -243,7 +243,7 @@ struct edma { } intr_data[EDMA_MAX_DMACH]; }; -static struct edma *edma_info[EDMA_MAX_CC]; +static struct edma *edma_cc[EDMA_MAX_CC]; static int arch_num_cc; /* dummy param set used to (re)initialize parameter RAM slots */ @@ -261,7 +261,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no, /* default to low priority queue */ if (queue_no == EVENTQ_DEFAULT) - queue_no = edma_info[ctlr]->default_queue; + queue_no = edma_cc[ctlr]->default_queue; queue_no &= 7; edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), @@ -310,29 +310,27 @@ setup_dma_interrupt(unsigned lch, ctlr = EDMA_CTLR(lch); lch = EDMA_CHAN_SLOT(lch); - if (!callback) { + if (!callback) edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, - (1 << (lch & 0x1f))); - } + BIT(lch & 0x1f)); - edma_info[ctlr]->intr_data[lch].callback = callback; - edma_info[ctlr]->intr_data[lch].data = data; + edma_cc[ctlr]->intr_data[lch].callback = callback; + edma_cc[ctlr]->intr_data[lch].data = data; if (callback) { edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, - (1 << (lch & 0x1f))); + BIT(lch & 0x1f)); edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, - (1 << (lch & 0x1f))); + BIT(lch & 0x1f)); } } static int irq2ctlr(int irq) { - if (irq >= edma_info[0]->irq_res_start && - irq <= edma_info[0]->irq_res_end) + if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) return 0; - else if (irq >= edma_info[1]->irq_res_start && - irq <= edma_info[1]->irq_res_end) + else if (irq >= edma_cc[1]->irq_res_start && + irq <= edma_cc[1]->irq_res_end) return 1; return -1; @@ -353,15 +351,17 @@ static irqreturn_t dma_irq_handler(int irq, void *data) dev_dbg(data, "dma_irq_handler\n"); - if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) - && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) + if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) && + (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) return IRQ_NONE; while (1) { int j; - if (edma_shadow0_read_array(ctlr, SH_IPR, 0)) + if (edma_shadow0_read_array(ctlr, SH_IPR, 0) & + edma_shadow0_read_array(ctlr, SH_IER, 0)) j = 0; - else if (edma_shadow0_read_array(ctlr, SH_IPR, 1)) + else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) & + edma_shadow0_read_array(ctlr, SH_IER, 1)) j = 1; else break; @@ -369,17 +369,17 @@ static irqreturn_t dma_irq_handler(int irq, void *data) edma_shadow0_read_array(ctlr, SH_IPR, j)); for (i = 0; i < 32; i++) { int k = (j << 5) + i; - if (edma_shadow0_read_array(ctlr, SH_IPR, j) & - (1 << i)) { + if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i)) + && (edma_shadow0_read_array(ctlr, + SH_IER, j) & BIT(i))) { /* Clear the corresponding IPR bits */ edma_shadow0_write_array(ctlr, SH_ICR, j, - (1 << i)); - if (edma_info[ctlr]->intr_data[k].callback) { - edma_info[ctlr]->intr_data[k].callback( + BIT(i)); + if (edma_cc[ctlr]->intr_data[k].callback) + edma_cc[ctlr]->intr_data[k].callback( k, DMA_COMPLETE, - edma_info[ctlr]->intr_data[k]. + edma_cc[ctlr]->intr_data[k]. data); - } } } cnt++; @@ -423,19 +423,19 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) for (i = 0; i < 32; i++) { int k = (j << 5) + i; if (edma_read_array(ctlr, EDMA_EMR, j) & - (1 << i)) { + BIT(i)) { /* Clear the corresponding EMR bits */ edma_write_array(ctlr, EDMA_EMCR, j, - 1 << i); + BIT(i)); /* Clear any SER */ edma_shadow0_write_array(ctlr, SH_SECR, - j, (1 << i)); - if (edma_info[ctlr]->intr_data[k]. + j, BIT(i)); + if (edma_cc[ctlr]->intr_data[k]. callback) { - edma_info[ctlr]->intr_data[k]. + edma_cc[ctlr]->intr_data[k]. callback(k, DMA_CC_ERROR, - edma_info[ctlr]->intr_data + edma_cc[ctlr]->intr_data [k].data); } } @@ -444,11 +444,11 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) dev_dbg(data, "QEMR %02x\n", edma_read(ctlr, EDMA_QEMR)); for (i = 0; i < 8; i++) { - if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) { + if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { /* Clear the corresponding IPR bits */ - edma_write(ctlr, EDMA_QEMCR, 1 << i); + edma_write(ctlr, EDMA_QEMCR, BIT(i)); edma_shadow0_write(ctlr, SH_QSECR, - (1 << i)); + BIT(i)); /* NOTE: not reported!! */ } @@ -460,20 +460,19 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) * to just write CCERRCLR with CCERR value... */ for (i = 0; i < 8; i++) { - if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) { + if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { /* Clear the corresponding IPR bits */ - edma_write(ctlr, EDMA_CCERRCLR, 1 << i); + edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); /* NOTE: not reported!! */ } } } - if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) - && (edma_read_array(ctlr, EDMA_EMR, 1) == 0) - && (edma_read(ctlr, EDMA_QEMR) == 0) - && (edma_read(ctlr, EDMA_CCERR) == 0)) { + if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && + (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && + (edma_read(ctlr, EDMA_QEMR) == 0) && + (edma_read(ctlr, EDMA_CCERR) == 0)) break; - } cnt++; if (cnt > 10) break; @@ -511,9 +510,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id, int stop_slot = start_slot; DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); - for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) { + for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { j = EDMA_CHAN_SLOT(i); - if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) { + if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { /* Record our current beginning slot */ if (count == num_slots) stop_slot = i; @@ -529,8 +528,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id, if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { stop_slot = i; break; - } else + } else { count = num_slots; + } } } @@ -540,12 +540,12 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id, * of contiguous parameter RAM slots but do not find the exact number * requested as we may reach the total number of parameter RAM slots */ - if (i == edma_info[ctlr]->num_slots) + if (i == edma_cc[ctlr]->num_slots) stop_slot = i; for (j = start_slot; j < stop_slot; j++) if (test_bit(j, tmp_inuse)) - clear_bit(j, edma_info[ctlr]->edma_inuse); + clear_bit(j, edma_cc[ctlr]->edma_inuse); if (count) return -EBUSY; @@ -567,7 +567,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data) (int)pdev->resource[i].start >= 0) { ctlr = EDMA_CTLR(pdev->resource[i].start); clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), - edma_info[ctlr]->edma_unused); + edma_cc[ctlr]->edma_unused); } } @@ -641,14 +641,13 @@ int edma_alloc_channel(int channel, for (i = 0; i < arch_num_cc; i++) { channel = 0; for (;;) { - channel = find_next_bit(edma_info[i]-> - edma_unused, - edma_info[i]->num_channels, + channel = find_next_bit(edma_cc[i]->edma_unused, + edma_cc[i]->num_channels, channel); - if (channel == edma_info[i]->num_channels) + if (channel == edma_cc[i]->num_channels) break; if (!test_and_set_bit(channel, - edma_info[i]->edma_inuse)) { + edma_cc[i]->edma_inuse)) { done = 1; ctlr = i; break; @@ -660,14 +659,14 @@ int edma_alloc_channel(int channel, } if (!done) return -ENOMEM; - } else if (channel >= edma_info[ctlr]->num_channels) { + } else if (channel >= edma_cc[ctlr]->num_channels) { return -EINVAL; - } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) { + } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { return -EBUSY; } /* ensure access through shadow region 0 */ - edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); + edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); /* ensure no events are pending */ edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); @@ -703,7 +702,7 @@ void edma_free_channel(unsigned channel) ctlr = EDMA_CTLR(channel); channel = EDMA_CHAN_SLOT(channel); - if (channel >= edma_info[ctlr]->num_channels) + if (channel >= edma_cc[ctlr]->num_channels) return; setup_dma_interrupt(channel, NULL, NULL); @@ -711,7 +710,7 @@ void edma_free_channel(unsigned channel) memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), &dummy_paramset, PARM_SIZE); - clear_bit(channel, edma_info[ctlr]->edma_inuse); + clear_bit(channel, edma_cc[ctlr]->edma_inuse); } EXPORT_SYMBOL(edma_free_channel); @@ -735,20 +734,19 @@ int edma_alloc_slot(unsigned ctlr, int slot) slot = EDMA_CHAN_SLOT(slot); if (slot < 0) { - slot = edma_info[ctlr]->num_channels; + slot = edma_cc[ctlr]->num_channels; for (;;) { - slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse, - edma_info[ctlr]->num_slots, slot); - if (slot == edma_info[ctlr]->num_slots) + slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, + edma_cc[ctlr]->num_slots, slot); + if (slot == edma_cc[ctlr]->num_slots) return -ENOMEM; - if (!test_and_set_bit(slot, - edma_info[ctlr]->edma_inuse)) + if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) break; } - } else if (slot < edma_info[ctlr]->num_channels || - slot >= edma_info[ctlr]->num_slots) { + } else if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots) { return -EINVAL; - } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) { + } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { return -EBUSY; } @@ -774,13 +772,13 @@ void edma_free_slot(unsigned slot) ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_info[ctlr]->num_channels || - slot >= edma_info[ctlr]->num_slots) + if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots) return; memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE); - clear_bit(slot, edma_info[ctlr]->edma_inuse); + clear_bit(slot, edma_cc[ctlr]->edma_inuse); } EXPORT_SYMBOL(edma_free_slot); @@ -818,8 +816,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) * of slots */ if ((id != EDMA_CONT_PARAMS_ANY) && - (slot < edma_info[ctlr]->num_channels || - slot >= edma_info[ctlr]->num_slots)) + (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots)) return -EINVAL; /* @@ -828,13 +826,13 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) * channels */ if (count < 1 || count > - (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels)) + (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) return -EINVAL; switch (id) { case EDMA_CONT_PARAMS_ANY: return reserve_contiguous_slots(ctlr, id, count, - edma_info[ctlr]->num_channels); + edma_cc[ctlr]->num_channels); case EDMA_CONT_PARAMS_FIXED_EXACT: case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: return reserve_contiguous_slots(ctlr, id, count, slot); @@ -866,8 +864,8 @@ int edma_free_cont_slots(unsigned slot, int count) ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_info[ctlr]->num_channels || - slot >= edma_info[ctlr]->num_slots || + if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots || count < 1) return -EINVAL; @@ -877,7 +875,7 @@ int edma_free_cont_slots(unsigned slot, int count) memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), &dummy_paramset, PARM_SIZE); - clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse); + clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); } return 0; @@ -907,7 +905,7 @@ void edma_set_src(unsigned slot, dma_addr_t src_port, ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_info[ctlr]->num_slots) { + if (slot < edma_cc[ctlr]->num_slots) { unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); if (mode) { @@ -945,7 +943,7 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port, ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_info[ctlr]->num_slots) { + if (slot < edma_cc[ctlr]->num_slots) { unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); if (mode) { @@ -1005,7 +1003,7 @@ void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_info[ctlr]->num_slots) { + if (slot < edma_cc[ctlr]->num_slots) { edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, 0xffff0000, src_bidx); edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, @@ -1031,7 +1029,7 @@ void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_info[ctlr]->num_slots) { + if (slot < edma_cc[ctlr]->num_slots) { edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, 0x0000ffff, dest_bidx << 16); edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, @@ -1078,7 +1076,7 @@ void edma_set_transfer_params(unsigned slot, ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_info[ctlr]->num_slots) { + if (slot < edma_cc[ctlr]->num_slots) { edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, 0x0000ffff, bcnt_rld << 16); if (sync_mode == ASYNC) @@ -1108,9 +1106,9 @@ void edma_link(unsigned from, unsigned to) ctlr_to = EDMA_CTLR(to); to = EDMA_CHAN_SLOT(to); - if (from >= edma_info[ctlr_from]->num_slots) + if (from >= edma_cc[ctlr_from]->num_slots) return; - if (to >= edma_info[ctlr_to]->num_slots) + if (to >= edma_cc[ctlr_to]->num_slots) return; edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to)); @@ -1131,7 +1129,7 @@ void edma_unlink(unsigned from) ctlr = EDMA_CTLR(from); from = EDMA_CHAN_SLOT(from); - if (from >= edma_info[ctlr]->num_slots) + if (from >= edma_cc[ctlr]->num_slots) return; edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); } @@ -1158,7 +1156,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param) ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - if (slot >= edma_info[ctlr]->num_slots) + if (slot >= edma_cc[ctlr]->num_slots) return; memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, PARM_SIZE); @@ -1180,7 +1178,7 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param) ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - if (slot >= edma_info[ctlr]->num_slots) + if (slot >= edma_cc[ctlr]->num_slots) return; memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), PARM_SIZE); @@ -1205,8 +1203,8 @@ void edma_pause(unsigned channel) ctlr = EDMA_CTLR(channel); channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_info[ctlr]->num_channels) { - unsigned int mask = (1 << (channel & 0x1f)); + if (channel < edma_cc[ctlr]->num_channels) { + unsigned int mask = BIT(channel & 0x1f); edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); } @@ -1226,8 +1224,8 @@ void edma_resume(unsigned channel) ctlr = EDMA_CTLR(channel); channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_info[ctlr]->num_channels) { - unsigned int mask = (1 << (channel & 0x1f)); + if (channel < edma_cc[ctlr]->num_channels) { + unsigned int mask = BIT(channel & 0x1f); edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); } @@ -1252,12 +1250,12 @@ int edma_start(unsigned channel) ctlr = EDMA_CTLR(channel); channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_info[ctlr]->num_channels) { + if (channel < edma_cc[ctlr]->num_channels) { int j = channel >> 5; - unsigned int mask = (1 << (channel & 0x1f)); + unsigned int mask = BIT(channel & 0x1f); /* EDMA channels without event association */ - if (test_bit(channel, edma_info[ctlr]->edma_unused)) { + if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { pr_debug("EDMA: ESR%d %08x\n", j, edma_shadow0_read_array(ctlr, SH_ESR, j)); edma_shadow0_write_array(ctlr, SH_ESR, j, mask); @@ -1298,9 +1296,9 @@ void edma_stop(unsigned channel) ctlr = EDMA_CTLR(channel); channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_info[ctlr]->num_channels) { + if (channel < edma_cc[ctlr]->num_channels) { int j = channel >> 5; - unsigned int mask = (1 << (channel & 0x1f)); + unsigned int mask = BIT(channel & 0x1f); edma_shadow0_write_array(ctlr, SH_EECR, j, mask); edma_shadow0_write_array(ctlr, SH_ECR, j, mask); @@ -1337,9 +1335,9 @@ void edma_clean_channel(unsigned channel) ctlr = EDMA_CTLR(channel); channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_info[ctlr]->num_channels) { + if (channel < edma_cc[ctlr]->num_channels) { int j = (channel >> 5); - unsigned int mask = 1 << (channel & 0x1f); + unsigned int mask = BIT(channel & 0x1f); pr_debug("EDMA: EMR%d %08x\n", j, edma_read_array(ctlr, EDMA_EMR, j)); @@ -1348,7 +1346,7 @@ void edma_clean_channel(unsigned channel) edma_write_array(ctlr, EDMA_EMCR, j, mask); /* Clear any SER */ edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3); + edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); } } EXPORT_SYMBOL(edma_clean_channel); @@ -1365,12 +1363,12 @@ void edma_clear_event(unsigned channel) ctlr = EDMA_CTLR(channel); channel = EDMA_CHAN_SLOT(channel); - if (channel >= edma_info[ctlr]->num_channels) + if (channel >= edma_cc[ctlr]->num_channels) return; if (channel < 32) - edma_write(ctlr, EDMA_ECR, 1 << channel); + edma_write(ctlr, EDMA_ECR, BIT(channel)); else - edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32)); + edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); } EXPORT_SYMBOL(edma_clear_event); @@ -1402,8 +1400,9 @@ static int __init edma_probe(struct platform_device *pdev) break; else return -ENODEV; - } else + } else { found = 1; + } len[j] = resource_size(r[j]); @@ -1420,38 +1419,37 @@ static int __init edma_probe(struct platform_device *pdev) goto fail1; } - edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); - if (!edma_info[j]) { + edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); + if (!edma_cc[j]) { status = -ENOMEM; goto fail1; } - memset(edma_info[j], 0, sizeof(struct edma)); + memset(edma_cc[j], 0, sizeof(struct edma)); - edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel, + edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel, EDMA_MAX_DMACH); - edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot, + edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot, EDMA_MAX_PARAMENTRY); - edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc, - EDMA_MAX_CC); + edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC); - edma_info[j]->default_queue = info[j].default_queue; - if (!edma_info[j]->default_queue) - edma_info[j]->default_queue = EVENTQ_1; + edma_cc[j]->default_queue = info[j].default_queue; + if (!edma_cc[j]->default_queue) + edma_cc[j]->default_queue = EVENTQ_1; dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base[j]); - for (i = 0; i < edma_info[j]->num_slots; i++) + for (i = 0; i < edma_cc[j]->num_slots; i++) memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), &dummy_paramset, PARM_SIZE); /* Mark all channels as unused */ - memset(edma_info[j]->edma_unused, 0xff, - sizeof(edma_info[j]->edma_unused)); + memset(edma_cc[j]->edma_unused, 0xff, + sizeof(edma_cc[j]->edma_unused)); sprintf(irq_name, "edma%d", j); irq[j] = platform_get_irq_byname(pdev, irq_name); - edma_info[j]->irq_res_start = irq[j]; + edma_cc[j]->irq_res_start = irq[j]; status = request_irq(irq[j], dma_irq_handler, 0, "edma", &pdev->dev); if (status < 0) { @@ -1462,7 +1460,7 @@ static int __init edma_probe(struct platform_device *pdev) sprintf(irq_name, "edma%d_err", j); err_irq[j] = platform_get_irq_byname(pdev, irq_name); - edma_info[j]->irq_res_end = err_irq[j]; + edma_cc[j]->irq_res_end = err_irq[j]; status = request_irq(err_irq[j], dma_ccerr_handler, 0, "edma_error", &pdev->dev); if (status < 0) { @@ -1475,7 +1473,7 @@ static int __init edma_probe(struct platform_device *pdev) * specified. This way, long transfers on the low priority queue * started by the codec engine will not cause audio defects. */ - for (i = 0; i < edma_info[j]->num_channels; i++) + for (i = 0; i < edma_cc[j]->num_channels; i++) map_dmach_queue(j, i, EVENTQ_1); queue_tc_mapping = info[j].queue_tc_mapping; @@ -1538,7 +1536,7 @@ fail1: release_mem_region(r[i]->start, len[i]); if (edmacc_regs_base[i]) iounmap(edmacc_regs_base[i]); - kfree(edma_info[i]); + kfree(edma_cc[i]); } return status; } diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 744755b5323..bf0ff587e46 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -20,46 +20,92 @@ #include <asm/mach/irq.h> -static DEFINE_SPINLOCK(gpio_lock); - -struct davinci_gpio { - struct gpio_chip chip; - struct gpio_controller *__iomem regs; - int irq_base; +struct davinci_gpio_regs { + u32 dir; + u32 out_data; + u32 set_data; + u32 clr_data; + u32 in_data; + u32 set_rising; + u32 clr_rising; + u32 set_falling; + u32 clr_falling; + u32 intstat; }; -static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; +#define chip2controller(chip) \ + container_of(chip, struct davinci_gpio_controller, chip) + +static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; +static void __iomem *gpio_base; + +static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio) +{ + void __iomem *ptr; + + if (gpio < 32 * 1) + ptr = gpio_base + 0x10; + else if (gpio < 32 * 2) + ptr = gpio_base + 0x38; + else if (gpio < 32 * 3) + ptr = gpio_base + 0x60; + else if (gpio < 32 * 4) + ptr = gpio_base + 0x88; + else if (gpio < 32 * 5) + ptr = gpio_base + 0xb0; + else + ptr = NULL; + return ptr; +} -/* create a non-inlined version */ -static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio) +static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) { - return __gpio_to_controller(gpio); + struct davinci_gpio_regs __iomem *g; + + g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); + + return g; } static int __init davinci_gpio_irq_setup(void); /*--------------------------------------------------------------------------*/ -/* - * board setup code *MUST* set PINMUX0 and PINMUX1 as - * needed, and enable the GPIO clock. - */ - -static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) +/* board setup code *MUST* setup pinmux and enable the GPIO clock. */ +static inline int __davinci_direction(struct gpio_chip *chip, + unsigned offset, bool out, int value) { - struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); - struct gpio_controller *__iomem g = d->regs; + struct davinci_gpio_controller *d = chip2controller(chip); + struct davinci_gpio_regs __iomem *g = d->regs; + unsigned long flags; u32 temp; + u32 mask = 1 << offset; - spin_lock(&gpio_lock); + spin_lock_irqsave(&d->lock, flags); temp = __raw_readl(&g->dir); - temp |= (1 << offset); + if (out) { + temp &= ~mask; + __raw_writel(mask, value ? &g->set_data : &g->clr_data); + } else { + temp |= mask; + } __raw_writel(temp, &g->dir); - spin_unlock(&gpio_lock); + spin_unlock_irqrestore(&d->lock, flags); return 0; } +static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) +{ + return __davinci_direction(chip, offset, false, 0); +} + +static int +davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) +{ + return __davinci_direction(chip, offset, true, value); +} + /* * Read the pin's value (works even if it's set up as output); * returns zero/nonzero. @@ -69,37 +115,20 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) */ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) { - struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); - struct gpio_controller *__iomem g = d->regs; + struct davinci_gpio_controller *d = chip2controller(chip); + struct davinci_gpio_regs __iomem *g = d->regs; return (1 << offset) & __raw_readl(&g->in_data); } -static int -davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) -{ - struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); - struct gpio_controller *__iomem g = d->regs; - u32 temp; - u32 mask = 1 << offset; - - spin_lock(&gpio_lock); - temp = __raw_readl(&g->dir); - temp &= ~mask; - __raw_writel(mask, value ? &g->set_data : &g->clr_data); - __raw_writel(temp, &g->dir); - spin_unlock(&gpio_lock); - return 0; -} - /* * Assuming the pin is muxed as a gpio output, set its output value. */ static void davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); - struct gpio_controller *__iomem g = d->regs; + struct davinci_gpio_controller *d = chip2controller(chip); + struct davinci_gpio_regs __iomem *g = d->regs; __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); } @@ -109,6 +138,10 @@ static int __init davinci_gpio_setup(void) int i, base; unsigned ngpio; struct davinci_soc_info *soc_info = &davinci_soc_info; + struct davinci_gpio_regs *regs; + + if (soc_info->gpio_type != GPIO_TYPE_DAVINCI) + return 0; /* * The gpio banks conceptually expose a segmented bitmap, @@ -124,6 +157,10 @@ static int __init davinci_gpio_setup(void) if (WARN_ON(DAVINCI_N_GPIO < ngpio)) ngpio = DAVINCI_N_GPIO; + gpio_base = ioremap(soc_info->gpio_base, SZ_4K); + if (WARN_ON(!gpio_base)) + return -ENOMEM; + for (i = 0, base = 0; base < ngpio; i++, base += 32) { chips[i].chip.label = "DaVinci"; @@ -137,11 +174,20 @@ static int __init davinci_gpio_setup(void) if (chips[i].chip.ngpio > 32) chips[i].chip.ngpio = 32; - chips[i].regs = gpio2controller(base); + spin_lock_init(&chips[i].lock); + + regs = gpio2regs(base); + chips[i].regs = regs; + chips[i].set_data = ®s->set_data; + chips[i].clr_data = ®s->clr_data; + chips[i].in_data = ®s->in_data; gpiochip_add(&chips[i].chip); } + soc_info->gpio_ctlrs = chips; + soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32); + davinci_gpio_irq_setup(); return 0; } @@ -161,7 +207,7 @@ pure_initcall(davinci_gpio_setup); static void gpio_irq_disable(unsigned irq) { - struct gpio_controller *__iomem g = get_irq_chip_data(irq); + struct davinci_gpio_regs __iomem *g = irq2regs(irq); u32 mask = (u32) get_irq_data(irq); __raw_writel(mask, &g->clr_falling); @@ -170,7 +216,7 @@ static void gpio_irq_disable(unsigned irq) static void gpio_irq_enable(unsigned irq) { - struct gpio_controller *__iomem g = get_irq_chip_data(irq); + struct davinci_gpio_regs __iomem *g = irq2regs(irq); u32 mask = (u32) get_irq_data(irq); unsigned status = irq_desc[irq].status; @@ -186,7 +232,7 @@ static void gpio_irq_enable(unsigned irq) static int gpio_irq_type(unsigned irq, unsigned trigger) { - struct gpio_controller *__iomem g = get_irq_chip_data(irq); + struct davinci_gpio_regs __iomem *g = irq2regs(irq); u32 mask = (u32) get_irq_data(irq); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) @@ -215,7 +261,7 @@ static struct irq_chip gpio_irqchip = { static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { - struct gpio_controller *__iomem g = get_irq_chip_data(irq); + struct davinci_gpio_regs __iomem *g = irq2regs(irq); u32 mask = 0xffff; /* we only care about one bank */ @@ -253,7 +299,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) { - struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); + struct davinci_gpio_controller *d = chip2controller(chip); if (d->irq_base >= 0) return d->irq_base + offset; @@ -276,7 +322,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) { - struct gpio_controller *__iomem g = get_irq_chip_data(irq); + struct davinci_gpio_regs __iomem *g = irq2regs(irq); u32 mask = (u32) get_irq_data(irq); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) @@ -305,7 +351,7 @@ static int __init davinci_gpio_irq_setup(void) u32 binten = 0; unsigned ngpio, bank_irq; struct davinci_soc_info *soc_info = &davinci_soc_info; - struct gpio_controller *__iomem g; + struct davinci_gpio_regs __iomem *g; ngpio = soc_info->gpio_num; @@ -354,7 +400,7 @@ static int __init davinci_gpio_irq_setup(void) gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked; /* default trigger: both edges */ - g = gpio2controller(0); + g = gpio2regs(0); __raw_writel(~0, &g->set_falling); __raw_writel(~0, &g->set_rising); @@ -362,7 +408,7 @@ static int __init davinci_gpio_irq_setup(void) for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { set_irq_chip(irq, &gpio_irqchip_unbanked); set_irq_data(irq, (void *) __gpio_mask(gpio)); - set_irq_chip_data(irq, g); + set_irq_chip_data(irq, (__force void *) g); irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; } @@ -379,18 +425,18 @@ static int __init davinci_gpio_irq_setup(void) unsigned i; /* disabled by default, enabled only as needed */ - g = gpio2controller(gpio); + g = gpio2regs(gpio); __raw_writel(~0, &g->clr_falling); __raw_writel(~0, &g->clr_rising); /* set up all irqs in this bank */ set_irq_chained_handler(bank_irq, gpio_irq_handler); - set_irq_chip_data(bank_irq, g); - set_irq_data(bank_irq, (void *)irq); + set_irq_chip_data(bank_irq, (__force void *) g); + set_irq_data(bank_irq, (void *) irq); for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { set_irq_chip(irq, &gpio_irqchip); - set_irq_chip_data(irq, g); + set_irq_chip_data(irq, (__force void *) g); set_irq_data(irq, (void *) __gpio_mask(gpio)); set_irq_handler(irq, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); @@ -403,7 +449,7 @@ done: /* BINTEN -- per-bank interrupt enable. genirq would also let these * bits be set/cleared dynamically. */ - __raw_writel(binten, soc_info->gpio_base + 0x08); + __raw_writel(binten, gpio_base + 0x08); printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index 50a955f05ef..a57cba21e21 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -12,6 +12,9 @@ #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H #define __ARCH_ARM_MACH_DAVINCI_COMMON_H +#include <linux/compiler.h> +#include <linux/types.h> + struct sys_timer; extern struct sys_timer davinci_timer; @@ -21,7 +24,7 @@ extern void __iomem *davinci_intc_base; extern int davinci_intc_type; struct davinci_timer_instance { - void __iomem *base; + u32 base; u32 bottom_irq; u32 top_irq; unsigned long cmp_off; @@ -34,39 +37,54 @@ struct davinci_timer_info { unsigned int clocksource_id; }; -/* SoC specific init support */ +struct davinci_gpio_controller; + +/* + * SoC info passed into common davinci modules. + * + * Base addresses in this structure should be physical and not virtual. + * Modules that take such base addresses, should internally ioremap() them to + * use. + */ struct davinci_soc_info { struct map_desc *io_desc; unsigned long io_desc_num; u32 cpu_id; u32 jtag_id; - void __iomem *jtag_id_base; + u32 jtag_id_reg; struct davinci_id *ids; unsigned long ids_num; struct clk_lookup *cpu_clks; - void __iomem **psc_bases; + u32 *psc_bases; unsigned long psc_bases_num; - void __iomem *pinmux_base; + u32 pinmux_base; const struct mux_config *pinmux_pins; unsigned long pinmux_pins_num; - void __iomem *intc_base; + u32 intc_base; int intc_type; u8 *intc_irq_prios; unsigned long intc_irq_num; + u32 *intc_host_map; struct davinci_timer_info *timer_info; - void __iomem *gpio_base; + int gpio_type; + u32 gpio_base; unsigned gpio_num; unsigned gpio_irq; unsigned gpio_unbanked; + struct davinci_gpio_controller *gpio_ctlrs; + int gpio_ctlrs_num; struct platform_device *serial_dev; struct emac_platform_data *emac_pdata; dma_addr_t sram_dma; unsigned sram_len; + struct platform_device *reset_device; + void (*reset)(struct platform_device *); }; extern struct davinci_soc_info davinci_soc_info; extern void davinci_common_init(struct davinci_soc_info *soc_info); +extern void davinci_init_ide(void); /* standard place to map on-chip SRAMs; they *may* support DMA */ #define SRAM_VIRT 0xfffe0000 diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h index c4d27eec806..4e8190eed67 100644 --- a/arch/arm/mach-davinci/include/mach/cp_intc.h +++ b/arch/arm/mach-davinci/include/mach/cp_intc.h @@ -51,7 +51,6 @@ #define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2)) #define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) -void __init cp_intc_init(void __iomem *base, unsigned short num_irq, - u8 *irq_prio); +void __init cp_intc_init(void); #endif /* __ASM_HARDWARE_CP_INTC_H */ diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index 189b1ff1364..cea6b897204 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -33,6 +33,7 @@ struct davinci_id { #define DAVINCI_CPU_ID_DM365 0x03650000 #define DAVINCI_CPU_ID_DA830 0x08300000 #define DAVINCI_CPU_ID_DA850 0x08500000 +#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000 #define IS_DAVINCI_CPU(type, id) \ static inline int is_davinci_ ##type(void) \ @@ -46,6 +47,7 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) +IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X) #ifdef CONFIG_ARCH_DAVINCI_DM644x #define cpu_is_davinci_dm644x() is_davinci_dm644x() @@ -83,4 +85,10 @@ IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) #define cpu_is_davinci_da850() 0 #endif +#ifdef CONFIG_ARCH_DAVINCI_TNETV107X +#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x() +#else +#define cpu_is_davinci_tnetv107x() 0 +#endif + #endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 03acfd39042..1b31a9aa8fb 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -64,27 +64,6 @@ extern void __iomem *da8xx_syscfg1_base; #define DA8XX_DDR2_CTL_BASE 0xb0000000 #define DA8XX_ARM_RAM_BASE 0xffff0000 -#define PINMUX0 0x00 -#define PINMUX1 0x04 -#define PINMUX2 0x08 -#define PINMUX3 0x0c -#define PINMUX4 0x10 -#define PINMUX5 0x14 -#define PINMUX6 0x18 -#define PINMUX7 0x1c -#define PINMUX8 0x20 -#define PINMUX9 0x24 -#define PINMUX10 0x28 -#define PINMUX11 0x2c -#define PINMUX12 0x30 -#define PINMUX13 0x34 -#define PINMUX14 0x38 -#define PINMUX15 0x3c -#define PINMUX16 0x40 -#define PINMUX17 0x44 -#define PINMUX18 0x48 -#define PINMUX19 0x4c - void __init da830_init(void); void __init da850_init(void); @@ -108,6 +87,8 @@ extern struct emac_platform_data da8xx_emac_pdata; extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; +extern struct platform_device da8xx_wdt_device; + extern const short da830_emif25_pins[]; extern const short da830_spi0_pins[]; extern const short da830_spi1_pins[]; @@ -146,10 +127,4 @@ extern const short da850_mmcsd0_pins[]; extern const short da850_nand_pins[]; extern const short da850_nor_pins[]; -#ifdef CONFIG_DAVINCI_MUX -int da8xx_pinmux_setup(const short pins[]); -#else -static inline int da8xx_pinmux_setup(const short pins[]) { return 0; } -#endif - #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h index 85536d8e833..36dff4a0ce3 100644 --- a/arch/arm/mach-davinci/include/mach/dm355.h +++ b/arch/arm/mach-davinci/include/mach/dm355.h @@ -15,6 +15,9 @@ #include <mach/asp.h> #include <media/davinci/vpfe_capture.h> +#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01E10000 +#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 + #define ASP1_TX_EVT_EN 1 #define ASP1_RX_EVT_EN 2 diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h index 3a37b5a6983..ea5df3b49ec 100644 --- a/arch/arm/mach-davinci/include/mach/dm365.h +++ b/arch/arm/mach-davinci/include/mach/dm365.h @@ -36,6 +36,10 @@ #define DAVINCI_DMA_VC_TX 2 #define DAVINCI_DMA_VC_RX 3 +#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01D10000 +#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 +#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 + void __init dm365_init(void); void __init dm365_init_asp(struct snd_platform_data *pdata); void __init dm365_init_vc(struct snd_platform_data *pdata); diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h index 1a8b09ccc3c..6fca568a0fd 100644 --- a/arch/arm/mach-davinci/include/mach/dm644x.h +++ b/arch/arm/mach-davinci/include/mach/dm644x.h @@ -34,6 +34,12 @@ #define DM644X_EMAC_MDIO_OFFSET (0x4000) #define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) +#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000 +#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 +#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 +#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000 +#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000 + void __init dm644x_init(void); void __init dm644x_init_asp(struct snd_platform_data *pdata); void dm644x_set_vpfe_config(struct vpfe_config *cfg); diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index 846da98b619..add6f794a36 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -25,10 +25,10 @@ #define DM646X_EMAC_MDIO_OFFSET (0x4000) #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) -#define DM646X_ATA_REG_BASE (0x01C66000) +#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000 +#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000 void __init dm646x_init(void); -void __init dm646x_init_ide(void); void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); void __init dm646x_board_setup_refclk(struct clk *clk); diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index f3b8ef87815..504cc180a60 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -14,6 +14,8 @@ #define __DAVINCI_GPIO_H #include <linux/io.h> +#include <linux/spinlock.h> + #include <asm-generic/gpio.h> #include <mach/irqs.h> @@ -21,6 +23,10 @@ #define DAVINCI_GPIO_BASE 0x01C67000 +enum davinci_gpio_type { + GPIO_TYPE_DAVINCI = 0, +}; + /* * basic gpio routines * @@ -45,17 +51,14 @@ /* Convert GPIO signal to GPIO pin number */ #define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) -struct gpio_controller { - u32 dir; - u32 out_data; - u32 set_data; - u32 clr_data; - u32 in_data; - u32 set_rising; - u32 clr_rising; - u32 set_falling; - u32 clr_falling; - u32 intstat; +struct davinci_gpio_controller { + struct gpio_chip chip; + int irq_base; + spinlock_t lock; + void __iomem *regs; + void __iomem *set_data; + void __iomem *clr_data; + void __iomem *in_data; }; /* The __gpio_to_controller() and __gpio_mask() functions inline to constants @@ -67,25 +70,16 @@ struct gpio_controller { * * These are NOT part of the cross-platform GPIO interface */ -static inline struct gpio_controller *__iomem +static inline struct davinci_gpio_controller * __gpio_to_controller(unsigned gpio) { - void *__iomem ptr; - void __iomem *base = davinci_soc_info.gpio_base; - - if (gpio < 32 * 1) - ptr = base + 0x10; - else if (gpio < 32 * 2) - ptr = base + 0x38; - else if (gpio < 32 * 3) - ptr = base + 0x60; - else if (gpio < 32 * 4) - ptr = base + 0x88; - else if (gpio < 32 * 5) - ptr = base + 0xb0; - else - ptr = NULL; - return ptr; + struct davinci_gpio_controller *ctlrs = davinci_soc_info.gpio_ctlrs; + int index = gpio / 32; + + if (!ctlrs || index >= davinci_soc_info.gpio_ctlrs_num) + return NULL; + + return ctlrs + index; } static inline u32 __gpio_mask(unsigned gpio) @@ -101,16 +95,16 @@ static inline u32 __gpio_mask(unsigned gpio) */ static inline void gpio_set_value(unsigned gpio, int value) { - if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) { - struct gpio_controller *__iomem g; - u32 mask; + if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) { + struct davinci_gpio_controller *ctlr; + u32 mask; - g = __gpio_to_controller(gpio); + ctlr = __gpio_to_controller(gpio); mask = __gpio_mask(gpio); if (value) - __raw_writel(mask, &g->set_data); + __raw_writel(mask, ctlr->set_data); else - __raw_writel(mask, &g->clr_data); + __raw_writel(mask, ctlr->clr_data); return; } @@ -128,18 +122,18 @@ static inline void gpio_set_value(unsigned gpio, int value) */ static inline int gpio_get_value(unsigned gpio) { - struct gpio_controller *__iomem g; + struct davinci_gpio_controller *ctlr; - if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO) + if (!__builtin_constant_p(gpio) || gpio >= davinci_soc_info.gpio_num) return __gpio_get_value(gpio); - g = __gpio_to_controller(gpio); - return __gpio_mask(gpio) & __raw_readl(&g->in_data); + ctlr = __gpio_to_controller(gpio); + return __gpio_mask(gpio) & __raw_readl(ctlr->in_data); } static inline int gpio_cansleep(unsigned gpio) { - if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO) + if (__builtin_constant_p(gpio) && gpio < davinci_soc_info.gpio_num) return 0; else return __gpio_cansleep(gpio); diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index 354af71798d..ec76c7775c2 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -401,6 +401,103 @@ #define DA850_N_CP_INTC_IRQ 101 + +/* TNETV107X specific interrupts */ +#define IRQ_TNETV107X_TDM1_TXDMA 0 +#define IRQ_TNETV107X_EXT_INT_0 1 +#define IRQ_TNETV107X_EXT_INT_1 2 +#define IRQ_TNETV107X_GPIO_INT12 3 +#define IRQ_TNETV107X_GPIO_INT13 4 +#define IRQ_TNETV107X_TIMER_0_TINT12 5 +#define IRQ_TNETV107X_TIMER_1_TINT12 6 +#define IRQ_TNETV107X_UART0 7 +#define IRQ_TNETV107X_TDM1_RXDMA 8 +#define IRQ_TNETV107X_MCDMA_INT0 9 +#define IRQ_TNETV107X_MCDMA_INT1 10 +#define IRQ_TNETV107X_TPCC 11 +#define IRQ_TNETV107X_TPCC_INT0 12 +#define IRQ_TNETV107X_TPCC_INT1 13 +#define IRQ_TNETV107X_TPCC_INT2 14 +#define IRQ_TNETV107X_TPCC_INT3 15 +#define IRQ_TNETV107X_TPTC0 16 +#define IRQ_TNETV107X_TPTC1 17 +#define IRQ_TNETV107X_TIMER_0_TINT34 18 +#define IRQ_TNETV107X_ETHSS 19 +#define IRQ_TNETV107X_TIMER_1_TINT34 20 +#define IRQ_TNETV107X_DSP2ARM_INT0 21 +#define IRQ_TNETV107X_DSP2ARM_INT1 22 +#define IRQ_TNETV107X_ARM_NPMUIRQ 23 +#define IRQ_TNETV107X_USB1 24 +#define IRQ_TNETV107X_VLYNQ 25 +#define IRQ_TNETV107X_UART0_DMATX 26 +#define IRQ_TNETV107X_UART0_DMARX 27 +#define IRQ_TNETV107X_TDM1_TXMCSP 28 +#define IRQ_TNETV107X_SSP 29 +#define IRQ_TNETV107X_MCDMA_INT2 30 +#define IRQ_TNETV107X_MCDMA_INT3 31 +#define IRQ_TNETV107X_TDM_CODECIF_EOT 32 +#define IRQ_TNETV107X_IMCOP_SQR_ARM 33 +#define IRQ_TNETV107X_USB0 34 +#define IRQ_TNETV107X_USB_CDMA 35 +#define IRQ_TNETV107X_LCD 36 +#define IRQ_TNETV107X_KEYPAD 37 +#define IRQ_TNETV107X_KEYPAD_FREE 38 +#define IRQ_TNETV107X_RNG 39 +#define IRQ_TNETV107X_PKA 40 +#define IRQ_TNETV107X_TDM0_TXDMA 41 +#define IRQ_TNETV107X_TDM0_RXDMA 42 +#define IRQ_TNETV107X_TDM0_TXMCSP 43 +#define IRQ_TNETV107X_TDM0_RXMCSP 44 +#define IRQ_TNETV107X_TDM1_RXMCSP 45 +#define IRQ_TNETV107X_SDIO1 46 +#define IRQ_TNETV107X_SDIO0 47 +#define IRQ_TNETV107X_TSC 48 +#define IRQ_TNETV107X_TS 49 +#define IRQ_TNETV107X_UART1 50 +#define IRQ_TNETV107X_MBX_LITE 51 +#define IRQ_TNETV107X_GPIO_INT00 52 +#define IRQ_TNETV107X_GPIO_INT01 53 +#define IRQ_TNETV107X_GPIO_INT02 54 +#define IRQ_TNETV107X_GPIO_INT03 55 +#define IRQ_TNETV107X_UART2 56 +#define IRQ_TNETV107X_UART2_DMATX 57 +#define IRQ_TNETV107X_UART2_DMARX 58 +#define IRQ_TNETV107X_IMCOP_IMX 59 +#define IRQ_TNETV107X_IMCOP_VLCD 60 +#define IRQ_TNETV107X_AES 61 +#define IRQ_TNETV107X_DES 62 +#define IRQ_TNETV107X_SHAMD5 63 +#define IRQ_TNETV107X_TPCC_ERR 68 +#define IRQ_TNETV107X_TPCC_PROT 69 +#define IRQ_TNETV107X_TPTC0_ERR 70 +#define IRQ_TNETV107X_TPTC1_ERR 71 +#define IRQ_TNETV107X_UART0_ERR 72 +#define IRQ_TNETV107X_UART1_ERR 73 +#define IRQ_TNETV107X_AEMIF_ERR 74 +#define IRQ_TNETV107X_DDR_ERR 75 +#define IRQ_TNETV107X_WDTARM_INT0 76 +#define IRQ_TNETV107X_MCDMA_ERR 77 +#define IRQ_TNETV107X_GPIO_ERR 78 +#define IRQ_TNETV107X_MPU_ADDR 79 +#define IRQ_TNETV107X_MPU_PROT 80 +#define IRQ_TNETV107X_IOPU_ADDR 81 +#define IRQ_TNETV107X_IOPU_PROT 82 +#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83 +#define IRQ_TNETV107X_WDT0_ADDR_ERR 84 +#define IRQ_TNETV107X_WDT1_ADDR_ERR 85 +#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86 +#define IRQ_TNETV107X_PLL_UNLOCK 87 +#define IRQ_TNETV107X_WDTDSP_INT0 88 +#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89 +#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90 +#define IRQ_TNETV107X_PBIST_CPU 91 +#define IRQ_TNETV107X_WDTARM 92 +#define IRQ_TNETV107X_PSC 93 +#define IRQ_TNETV107X_MMC0 94 +#define IRQ_TNETV107X_MMC1 95 + +#define TNETV107X_N_CP_INTC_IRQ 96 + /* da850 currently has the most gpio pins (144) */ #define DAVINCI_N_GPIO 144 /* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 2a68c1d8a24..de11aac76a8 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -194,11 +194,14 @@ enum davinci_dm365_index { DM365_I2C_SCL, /* AEMIF */ - DM365_AEMIF_AR, + DM365_AEMIF_AR_A14, + DM365_AEMIF_AR_BA0, DM365_AEMIF_A3, DM365_AEMIF_A7, DM365_AEMIF_D15_8, DM365_AEMIF_CE0, + DM365_AEMIF_CE1, + DM365_AEMIF_WE_OE, /* ASP0 function */ DM365_MCBSP0_BDX, @@ -287,10 +290,19 @@ enum davinci_dm365_index { DM365_SPI4_SDENA0, DM365_SPI4_SDENA1, + /* Clock */ + DM365_CLKOUT0, + DM365_CLKOUT1, + DM365_CLKOUT2, + /* GPIO */ DM365_GPIO20, + DM365_GPIO30, + DM365_GPIO31, + DM365_GPIO32, DM365_GPIO33, DM365_GPIO40, + DM365_GPIO64_57, /* Video */ DM365_VOUT_FIELD, @@ -904,12 +916,288 @@ enum davinci_da850_index { DA850_RTC_ALARM, }; +enum davinci_tnetv107x_index { + TNETV107X_ASR_A00, + TNETV107X_GPIO32, + TNETV107X_ASR_A01, + TNETV107X_GPIO33, + TNETV107X_ASR_A02, + TNETV107X_GPIO34, + TNETV107X_ASR_A03, + TNETV107X_GPIO35, + TNETV107X_ASR_A04, + TNETV107X_GPIO36, + TNETV107X_ASR_A05, + TNETV107X_GPIO37, + TNETV107X_ASR_A06, + TNETV107X_GPIO38, + TNETV107X_ASR_A07, + TNETV107X_GPIO39, + TNETV107X_ASR_A08, + TNETV107X_GPIO40, + TNETV107X_ASR_A09, + TNETV107X_GPIO41, + TNETV107X_ASR_A10, + TNETV107X_GPIO42, + TNETV107X_ASR_A11, + TNETV107X_BOOT_STRP_0, + TNETV107X_ASR_A12, + TNETV107X_BOOT_STRP_1, + TNETV107X_ASR_A13, + TNETV107X_GPIO43, + TNETV107X_ASR_A14, + TNETV107X_GPIO44, + TNETV107X_ASR_A15, + TNETV107X_GPIO45, + TNETV107X_ASR_A16, + TNETV107X_GPIO46, + TNETV107X_ASR_A17, + TNETV107X_GPIO47, + TNETV107X_ASR_A18, + TNETV107X_GPIO48, + TNETV107X_SDIO1_DATA3_0, + TNETV107X_ASR_A19, + TNETV107X_GPIO49, + TNETV107X_SDIO1_DATA2_0, + TNETV107X_ASR_A20, + TNETV107X_GPIO50, + TNETV107X_SDIO1_DATA1_0, + TNETV107X_ASR_A21, + TNETV107X_GPIO51, + TNETV107X_SDIO1_DATA0_0, + TNETV107X_ASR_A22, + TNETV107X_GPIO52, + TNETV107X_SDIO1_CMD_0, + TNETV107X_ASR_A23, + TNETV107X_GPIO53, + TNETV107X_SDIO1_CLK_0, + TNETV107X_ASR_BA_1, + TNETV107X_GPIO54, + TNETV107X_SYS_PLL_CLK, + TNETV107X_ASR_CS0, + TNETV107X_ASR_CS1, + TNETV107X_ASR_CS2, + TNETV107X_TDM_PLL_CLK, + TNETV107X_ASR_CS3, + TNETV107X_ETH_PHY_CLK, + TNETV107X_ASR_D00, + TNETV107X_GPIO55, + TNETV107X_ASR_D01, + TNETV107X_GPIO56, + TNETV107X_ASR_D02, + TNETV107X_GPIO57, + TNETV107X_ASR_D03, + TNETV107X_GPIO58, + TNETV107X_ASR_D04, + TNETV107X_GPIO59_0, + TNETV107X_ASR_D05, + TNETV107X_GPIO60_0, + TNETV107X_ASR_D06, + TNETV107X_GPIO61_0, + TNETV107X_ASR_D07, + TNETV107X_GPIO62_0, + TNETV107X_ASR_D08, + TNETV107X_GPIO63_0, + TNETV107X_ASR_D09, + TNETV107X_GPIO64_0, + TNETV107X_ASR_D10, + TNETV107X_SDIO1_DATA3_1, + TNETV107X_ASR_D11, + TNETV107X_SDIO1_DATA2_1, + TNETV107X_ASR_D12, + TNETV107X_SDIO1_DATA1_1, + TNETV107X_ASR_D13, + TNETV107X_SDIO1_DATA0_1, + TNETV107X_ASR_D14, + TNETV107X_SDIO1_CMD_1, + TNETV107X_ASR_D15, + TNETV107X_SDIO1_CLK_1, + TNETV107X_ASR_OE, + TNETV107X_BOOT_STRP_2, + TNETV107X_ASR_RNW, + TNETV107X_GPIO29_0, + TNETV107X_ASR_WAIT, + TNETV107X_GPIO30_0, + TNETV107X_ASR_WE, + TNETV107X_BOOT_STRP_3, + TNETV107X_ASR_WE_DQM0, + TNETV107X_GPIO31, + TNETV107X_LCD_PD17_0, + TNETV107X_ASR_WE_DQM1, + TNETV107X_ASR_BA0_0, + TNETV107X_VLYNQ_CLK, + TNETV107X_GPIO14, + TNETV107X_LCD_PD19_0, + TNETV107X_VLYNQ_RXD0, + TNETV107X_GPIO15, + TNETV107X_LCD_PD20_0, + TNETV107X_VLYNQ_RXD1, + TNETV107X_GPIO16, + TNETV107X_LCD_PD21_0, + TNETV107X_VLYNQ_TXD0, + TNETV107X_GPIO17, + TNETV107X_LCD_PD22_0, + TNETV107X_VLYNQ_TXD1, + TNETV107X_GPIO18, + TNETV107X_LCD_PD23_0, + TNETV107X_SDIO0_CLK, + TNETV107X_GPIO19, + TNETV107X_SDIO0_CMD, + TNETV107X_GPIO20, + TNETV107X_SDIO0_DATA0, + TNETV107X_GPIO21, + TNETV107X_SDIO0_DATA1, + TNETV107X_GPIO22, + TNETV107X_SDIO0_DATA2, + TNETV107X_GPIO23, + TNETV107X_SDIO0_DATA3, + TNETV107X_GPIO24, + TNETV107X_EMU0, + TNETV107X_EMU1, + TNETV107X_RTCK, + TNETV107X_TRST_N, + TNETV107X_TCK, + TNETV107X_TDI, + TNETV107X_TDO, + TNETV107X_TMS, + TNETV107X_TDM1_CLK, + TNETV107X_TDM1_RX, + TNETV107X_TDM1_TX, + TNETV107X_TDM1_FS, + TNETV107X_KEYPAD_R0, + TNETV107X_KEYPAD_R1, + TNETV107X_KEYPAD_R2, + TNETV107X_KEYPAD_R3, + TNETV107X_KEYPAD_R4, + TNETV107X_KEYPAD_R5, + TNETV107X_KEYPAD_R6, + TNETV107X_GPIO12, + TNETV107X_KEYPAD_R7, + TNETV107X_GPIO10, + TNETV107X_KEYPAD_C0, + TNETV107X_KEYPAD_C1, + TNETV107X_KEYPAD_C2, + TNETV107X_KEYPAD_C3, + TNETV107X_KEYPAD_C4, + TNETV107X_KEYPAD_C5, + TNETV107X_KEYPAD_C6, + TNETV107X_GPIO13, + TNETV107X_TEST_CLK_IN, + TNETV107X_KEYPAD_C7, + TNETV107X_GPIO11, + TNETV107X_SSP0_0, + TNETV107X_SCC_DCLK, + TNETV107X_LCD_PD20_1, + TNETV107X_SSP0_1, + TNETV107X_SCC_CS_N, + TNETV107X_LCD_PD21_1, + TNETV107X_SSP0_2, + TNETV107X_SCC_D, + TNETV107X_LCD_PD22_1, + TNETV107X_SSP0_3, + TNETV107X_SCC_RESETN, + TNETV107X_LCD_PD23_1, + TNETV107X_SSP1_0, + TNETV107X_GPIO25, + TNETV107X_UART2_CTS, + TNETV107X_SSP1_1, + TNETV107X_GPIO26, + TNETV107X_UART2_RD, + TNETV107X_SSP1_2, + TNETV107X_GPIO27, + TNETV107X_UART2_RTS, + TNETV107X_SSP1_3, + TNETV107X_GPIO28, + TNETV107X_UART2_TD, + TNETV107X_UART0_CTS, + TNETV107X_UART0_RD, + TNETV107X_UART0_RTS, + TNETV107X_UART0_TD, + TNETV107X_UART1_RD, + TNETV107X_UART1_TD, + TNETV107X_LCD_AC_NCS, + TNETV107X_LCD_HSYNC_RNW, + TNETV107X_LCD_VSYNC_A0, + TNETV107X_LCD_MCLK, + TNETV107X_LCD_PD16_0, + TNETV107X_LCD_PCLK_E, + TNETV107X_LCD_PD00, + TNETV107X_LCD_PD01, + TNETV107X_LCD_PD02, + TNETV107X_LCD_PD03, + TNETV107X_LCD_PD04, + TNETV107X_LCD_PD05, + TNETV107X_LCD_PD06, + TNETV107X_LCD_PD07, + TNETV107X_LCD_PD08, + TNETV107X_GPIO59_1, + TNETV107X_LCD_PD09, + TNETV107X_GPIO60_1, + TNETV107X_LCD_PD10, + TNETV107X_ASR_BA0_1, + TNETV107X_GPIO61_1, + TNETV107X_LCD_PD11, + TNETV107X_GPIO62_1, + TNETV107X_LCD_PD12, + TNETV107X_GPIO63_1, + TNETV107X_LCD_PD13, + TNETV107X_GPIO64_1, + TNETV107X_LCD_PD14, + TNETV107X_GPIO29_1, + TNETV107X_LCD_PD15, + TNETV107X_GPIO30_1, + TNETV107X_EINT0, + TNETV107X_GPIO08, + TNETV107X_EINT1, + TNETV107X_GPIO09, + TNETV107X_GPIO00, + TNETV107X_LCD_PD20_2, + TNETV107X_TDM_CLK_IN_2, + TNETV107X_GPIO01, + TNETV107X_LCD_PD21_2, + TNETV107X_24M_CLK_OUT_1, + TNETV107X_GPIO02, + TNETV107X_LCD_PD22_2, + TNETV107X_GPIO03, + TNETV107X_LCD_PD23_2, + TNETV107X_GPIO04, + TNETV107X_LCD_PD16_1, + TNETV107X_USB0_RXERR, + TNETV107X_GPIO05, + TNETV107X_LCD_PD17_1, + TNETV107X_TDM_CLK_IN_1, + TNETV107X_GPIO06, + TNETV107X_LCD_PD18, + TNETV107X_24M_CLK_OUT_2, + TNETV107X_GPIO07, + TNETV107X_LCD_PD19_1, + TNETV107X_USB1_RXERR, + TNETV107X_ETH_PLL_CLK, + TNETV107X_MDIO, + TNETV107X_MDC, + TNETV107X_AIC_MUTE_STAT_N, + TNETV107X_TDM0_CLK, + TNETV107X_AIC_HNS_EN_N, + TNETV107X_TDM0_FS, + TNETV107X_AIC_HDS_EN_STAT_N, + TNETV107X_TDM0_TX, + TNETV107X_AIC_HNF_EN_STAT_N, + TNETV107X_TDM0_RX, +}; + +#define PINMUX(x) (4 * (x)) + #ifdef CONFIG_DAVINCI_MUX /* setup pin muxing */ extern int davinci_cfg_reg(unsigned long reg_cfg); +extern int davinci_cfg_reg_list(const short pins[]); #else /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } +static inline int davinci_cfg_reg_list(const short pins[]) +{ + return 0; +} #endif #endif /* __INC_MACH_MUX_H */ diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 651f6d8158f..983da6e4554 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -180,6 +180,53 @@ #define DA8XX_LPSC1_CR_P3_SS 26 #define DA8XX_LPSC1_L3_CBA_RAM 31 +/* TNETV107X LPSC Assignments */ +#define TNETV107X_LPSC_ARM 0 +#define TNETV107X_LPSC_GEM 1 +#define TNETV107X_LPSC_DDR2_PHY 2 +#define TNETV107X_LPSC_TPCC 3 +#define TNETV107X_LPSC_TPTC0 4 +#define TNETV107X_LPSC_TPTC1 5 +#define TNETV107X_LPSC_RAM 6 +#define TNETV107X_LPSC_MBX_LITE 7 +#define TNETV107X_LPSC_LCD 8 +#define TNETV107X_LPSC_ETHSS 9 +#define TNETV107X_LPSC_AEMIF 10 +#define TNETV107X_LPSC_CHIP_CFG 11 +#define TNETV107X_LPSC_TSC 12 +#define TNETV107X_LPSC_ROM 13 +#define TNETV107X_LPSC_UART2 14 +#define TNETV107X_LPSC_PKTSEC 15 +#define TNETV107X_LPSC_SECCTL 16 +#define TNETV107X_LPSC_KEYMGR 17 +#define TNETV107X_LPSC_KEYPAD 18 +#define TNETV107X_LPSC_GPIO 19 +#define TNETV107X_LPSC_MDIO 20 +#define TNETV107X_LPSC_SDIO0 21 +#define TNETV107X_LPSC_UART0 22 +#define TNETV107X_LPSC_UART1 23 +#define TNETV107X_LPSC_TIMER0 24 +#define TNETV107X_LPSC_TIMER1 25 +#define TNETV107X_LPSC_WDT_ARM 26 +#define TNETV107X_LPSC_WDT_DSP 27 +#define TNETV107X_LPSC_SSP 28 +#define TNETV107X_LPSC_TDM0 29 +#define TNETV107X_LPSC_VLYNQ 30 +#define TNETV107X_LPSC_MCDMA 31 +#define TNETV107X_LPSC_USB0 32 +#define TNETV107X_LPSC_TDM1 33 +#define TNETV107X_LPSC_DEBUGSS 34 +#define TNETV107X_LPSC_ETHSS_RGMII 35 +#define TNETV107X_LPSC_SYSTEM 36 +#define TNETV107X_LPSC_IMCOP 37 +#define TNETV107X_LPSC_SPARE 38 +#define TNETV107X_LPSC_SDIO1 39 +#define TNETV107X_LPSC_USB1 40 +#define TNETV107X_LPSC_USBSS 41 +#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42 +#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43 +#define TNETV107X_LPSC_MAX 44 + /* PSC register offsets */ #define EPCPR 0x070 #define PTCMD 0x120 @@ -189,13 +236,19 @@ #define MDSTAT 0x800 #define MDCTL 0xA00 +/* PSC module states */ +#define PSC_STATE_SWRSTDISABLE 0 +#define PSC_STATE_SYNCRST 1 +#define PSC_STATE_DISABLE 2 +#define PSC_STATE_ENABLE 3 + #define MDSTAT_STATE_MASK 0x1f #ifndef __ASSEMBLER__ extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, - unsigned int id, char enable); + unsigned int id, u32 next_state); #endif diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index a584697a9e7..f6c4f34909a 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -13,7 +13,6 @@ #include <mach/hardware.h> -#define DAVINCI_MAX_NR_UARTS 3 #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h index 5a7d7581b8c..e65629c2076 100644 --- a/arch/arm/mach-davinci/include/mach/system.h +++ b/arch/arm/mach-davinci/include/mach/system.h @@ -11,7 +11,7 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H -extern void davinci_watchdog_reset(void); +#include <mach/common.h> static inline void arch_idle(void) { @@ -20,7 +20,8 @@ static inline void arch_idle(void) static inline void arch_reset(char mode, const char *cmd) { - davinci_watchdog_reset(); + if (davinci_soc_info.reset) + davinci_soc_info.reset(davinci_soc_info.reset_device); } #endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c index a1c0b6b99ed..8ea60a8b249 100644 --- a/arch/arm/mach-davinci/io.c +++ b/arch/arm/mach-davinci/io.c @@ -12,19 +12,29 @@ #include <linux/io.h> #include <asm/tlb.h> +#include <asm/mach/map.h> -#define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) -#define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst))) +#include <mach/common.h> /* * Intercept ioremap() requests for addresses in our fixed mapping regions. */ void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type) { - if (BETWEEN(p, IO_PHYS, IO_SIZE)) - return XLATE(p, IO_PHYS, IO_VIRT); + struct map_desc *desc = davinci_soc_info.io_desc; + int desc_num = davinci_soc_info.io_desc_num; + int i; - return __arm_ioremap_caller(p, size, type, __builtin_return_address(0)); + for (i = 0; i < desc_num; i++, desc++) { + unsigned long iophys = __pfn_to_phys(desc->pfn); + unsigned long iosize = desc->length; + + if (p >= iophys && (p + size) <= (iophys + iosize)) + return __io(desc->virtual + p - iophys); + } + + return __arm_ioremap_caller(p, size, type, + __builtin_return_address(0)); } EXPORT_SYMBOL(davinci_ioremap); diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index af92ffee847..784ddf3c5ad 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -116,6 +116,11 @@ void __init davinci_irq_init(void) unsigned i; const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios; + davinci_intc_type = DAVINCI_INTC_TYPE_AINTC; + davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K); + if (WARN_ON(!davinci_intc_base)) + return; + /* Clear all interrupt requests */ davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); @@ -148,7 +153,7 @@ void __init davinci_irq_init(void) } /* set up genirq dispatch for ARM INTC */ - for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) { + for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { set_irq_chip(i, &davinci_irq_chip_0); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); if (i != IRQ_TINT1_TINT34) diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c index f757e83415f..f34a8dcdae2 100644 --- a/arch/arm/mach-davinci/mux.c +++ b/arch/arm/mach-davinci/mux.c @@ -22,6 +22,8 @@ #include <mach/mux.h> #include <mach/common.h> +static void __iomem *pinmux_base; + /* * Sets the DAVINCI MUX register based on the table */ @@ -29,14 +31,19 @@ int __init_or_module davinci_cfg_reg(const unsigned long index) { static DEFINE_SPINLOCK(mux_spin_lock); struct davinci_soc_info *soc_info = &davinci_soc_info; - void __iomem *base = soc_info->pinmux_base; unsigned long flags; const struct mux_config *cfg; unsigned int reg_orig = 0, reg = 0; unsigned int mask, warn = 0; - if (!soc_info->pinmux_pins) - BUG(); + if (WARN_ON(!soc_info->pinmux_pins)) + return -ENODEV; + + if (!pinmux_base) { + pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K); + if (WARN_ON(!pinmux_base)) + return -ENOMEM; + } if (index >= soc_info->pinmux_pins_num) { printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", @@ -57,7 +64,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index) unsigned tmp1, tmp2; spin_lock_irqsave(&mux_spin_lock, flags); - reg_orig = __raw_readl(base + cfg->mux_reg); + reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); mask = (cfg->mask << cfg->mask_offset); tmp1 = reg_orig & mask; @@ -69,7 +76,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index) if (tmp1 != tmp2) warn = 1; - __raw_writel(reg, base + cfg->mux_reg); + __raw_writel(reg, pinmux_base + cfg->mux_reg); spin_unlock_irqrestore(&mux_spin_lock, flags); } @@ -91,7 +98,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index) } EXPORT_SYMBOL(davinci_cfg_reg); -int da8xx_pinmux_setup(const short pins[]) +int __init_or_module davinci_cfg_reg_list(const short pins[]) { int i, error = -EINVAL; diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h index adc86941337..5aad1e7dd21 100644 --- a/arch/arm/mach-davinci/mux.h +++ b/arch/arm/mach-davinci/mux.h @@ -20,7 +20,7 @@ .name = #desc, \ .debug = dbg, \ .mux_reg_name = "PINMUX"#muxreg, \ - .mux_reg = PINMUX##muxreg, \ + .mux_reg = PINMUX(muxreg), \ .mask_offset = mode_offset, \ .mask = mode_mask, \ .mode = mux_mode, \ diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index adf6b5c7f1e..1b15dbd0a77 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -38,8 +38,9 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) return 0; } - psc_base = soc_info->psc_bases[ctlr]; + psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); + iounmap(psc_base); /* if clocked, state can be "Enable" or "SyncReset" */ return mdstat & BIT(12); @@ -47,12 +48,11 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) /* Enable or disable a PSC domain */ void davinci_psc_config(unsigned int domain, unsigned int ctlr, - unsigned int id, char enable) + unsigned int id, u32 next_state) { u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; void __iomem *psc_base; struct davinci_soc_info *soc_info = &davinci_soc_info; - u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */ if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { pr_warning("PSC: Bad psc data: 0x%x[%d]\n", @@ -60,7 +60,7 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr, return; } - psc_base = soc_info->psc_bases[ctlr]; + psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); mdctl = __raw_readl(psc_base + MDCTL + 4 * id); mdctl &= ~MDSTAT_STATE_MASK; @@ -100,4 +100,6 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr, do { mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); + + iounmap(psc_base); } diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c index 7ce5ba08657..1875740fe27 100644 --- a/arch/arm/mach-davinci/serial.c +++ b/arch/arm/mach-davinci/serial.c @@ -35,14 +35,20 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, int offset) { offset <<= up->regshift; - return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset); + + WARN_ONCE(!up->membase, "unmapped read: uart[%d]\n", offset); + + return (unsigned int)__raw_readl(up->membase + offset); } static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, int value) { offset <<= p->regshift; - __raw_writel(value, IO_ADDRESS(p->mapbase) + offset); + + WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset); + + __raw_writel(value, p->membase + offset); } static void __init davinci_serial_reset(struct plat_serial8250_port *p) @@ -77,20 +83,32 @@ int __init davinci_serial_init(struct davinci_uart_config *info) * Make sure the serial ports are muxed on at this point. * You have to mux them off in device drivers later on if not needed. */ - for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++, p++) { + for (i = 0; p->flags; i++, p++) { if (!(info->enabled_uarts & (1 << i))) continue; sprintf(name, "uart%d", i); uart_clk = clk_get(dev, name); - if (IS_ERR(uart_clk)) + if (IS_ERR(uart_clk)) { printk(KERN_ERR "%s:%d: failed to get UART%d clock\n", __func__, __LINE__, i); - else { - clk_enable(uart_clk); - p->uartclk = clk_get_rate(uart_clk); - davinci_serial_reset(p); + continue; } + + clk_enable(uart_clk); + p->uartclk = clk_get_rate(uart_clk); + + if (!p->membase && p->mapbase) { + p->membase = ioremap(p->mapbase, SZ_4K); + + if (p->membase) + p->flags &= ~UPF_IOREMAP; + else + pr_err("uart regs ioremap failed\n"); + } + + if (p->membase && p->type != PORT_AR7) + davinci_serial_reset(p); } return platform_device_register(soc_info->serial_dev); diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 9e0b106b4f5..0f21c36e65d 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -197,32 +197,36 @@ static void __init timer_init(void) { struct davinci_soc_info *soc_info = &davinci_soc_info; struct davinci_timer_instance *dtip = soc_info->timer_info->timers; + void __iomem *base[2]; int i; /* Global init of each 64-bit timer as a whole */ for(i=0; i<2; i++) { u32 tgcr; - void __iomem *base = dtip[i].base; + + base[i] = ioremap(dtip[i].base, SZ_4K); + if (WARN_ON(!base[i])) + continue; /* Disabled, Internal clock source */ - __raw_writel(0, base + TCR); + __raw_writel(0, base[i] + TCR); /* reset both timers, no pre-scaler for timer34 */ tgcr = 0; - __raw_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base[i] + TGCR); /* Set both timers to unchained 32-bit */ tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; - __raw_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base[i] + TGCR); /* Unreset timers */ tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - __raw_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base[i] + TGCR); /* Init both counters to zero */ - __raw_writel(0, base + TIM12); - __raw_writel(0, base + TIM34); + __raw_writel(0, base[i] + TIM12); + __raw_writel(0, base[i] + TIM34); } /* Init of each timer as a 32-bit timer */ @@ -231,7 +235,9 @@ static void __init timer_init(void) int timer = ID_TO_TIMER(t->id); u32 irq; - t->base = dtip[timer].base; + t->base = base[timer]; + if (!t->base) + continue; if (IS_TIMER_BOT(t->id)) { t->enamode_shift = 6; @@ -361,13 +367,13 @@ static void __init davinci_timer_init(void) } } - /* init timer hw */ - timer_init(); - timer_clk = clk_get(NULL, "timer0"); BUG_ON(IS_ERR(timer_clk)); clk_enable(timer_clk); + /* init timer hw */ + timer_init(); + davinci_clock_tick_rate = clk_get_rate(timer_clk); /* setup clocksource */ @@ -399,13 +405,16 @@ struct sys_timer davinci_timer = { /* reset board using watchdog timer */ -void davinci_watchdog_reset(void) +void davinci_watchdog_reset(struct platform_device *pdev) { u32 tgcr, wdtcr; - struct platform_device *pdev = &davinci_wdt_device; - void __iomem *base = IO_ADDRESS(pdev->resource[0].start); + void __iomem *base; struct clk *wd_clk; + base = ioremap(pdev->resource[0].start, SZ_4K); + if (WARN_ON(!base)) + return; + wd_clk = clk_get(&pdev->dev, NULL); if (WARN_ON(IS_ERR(wd_clk))) return; diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c index caf6d5154ae..3a1a855bfdc 100644 --- a/arch/arm/mach-ep93xx/adssphere.c +++ b/arch/arm/mach-ep93xx/adssphere.c @@ -41,7 +41,7 @@ static struct platform_device adssphere_flash = { .resource = &adssphere_flash_resource, }; -static struct ep93xx_eth_data adssphere_eth_data = { +static struct ep93xx_eth_data __initdata adssphere_eth_data = { .phy_id = 1, }; diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index 5f80092b6ac..e29bdef9b2e 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c @@ -96,6 +96,10 @@ static struct clk clk_keypad = { .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN, .set_rate = set_keytchclk_rate, }; +static struct clk clk_spi = { + .parent = &clk_xtali, + .rate = EP93XX_EXT_CLK_RATE, +}; static struct clk clk_pwm = { .parent = &clk_xtali, .rate = EP93XX_EXT_CLK_RATE, @@ -186,6 +190,7 @@ static struct clk_lookup clocks[] = { INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), INIT_CK("ep93xx-keypad", NULL, &clk_keypad), INIT_CK("ep93xx-fb", NULL, &clk_video), + INIT_CK("ep93xx-spi.0", NULL, &clk_spi), INIT_CK(NULL, "pwm_clk", &clk_pwm), INIT_CK(NULL, "m2p0", &clk_m2p0), INIT_CK(NULL, "m2p1", &clk_m2p1), @@ -473,6 +478,14 @@ static int __init ep93xx_clock_init(void) /* Initialize the pll2 derived clocks */ clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); + /* + * EP93xx SSP clock rate was doubled in version E2. For more information + * see: + * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf + */ + if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) + clk_spi.rate /= 2; + pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 90fb591cbff..9092677f63e 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -31,10 +31,12 @@ #include <linux/amba/serial.h> #include <linux/i2c.h> #include <linux/i2c-gpio.h> +#include <linux/spi/spi.h> #include <mach/hardware.h> #include <mach/fb.h> #include <mach/ep93xx_keypad.h> +#include <mach/ep93xx_spi.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -222,6 +224,20 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits) } EXPORT_SYMBOL(ep93xx_devcfg_set_clear); +/** + * ep93xx_chip_revision() - returns the EP93xx chip revision + * + * See <mach/platform.h> for more information. + */ +unsigned int ep93xx_chip_revision(void) +{ + unsigned int v; + + v = __raw_readl(EP93XX_SYSCON_SYSCFG); + v &= EP93XX_SYSCON_SYSCFG_REV_MASK; + v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT; + return v; +} /************************************************************************* * EP93xx peripheral handling @@ -330,6 +346,10 @@ static struct platform_device ep93xx_ohci_device = { .resource = ep93xx_ohci_resources, }; + +/************************************************************************* + * EP93xx ethernet peripheral handling + *************************************************************************/ static struct ep93xx_eth_data ep93xx_eth_data; static struct resource ep93xx_eth_resource[] = { @@ -354,6 +374,12 @@ static struct platform_device ep93xx_eth_device = { .resource = ep93xx_eth_resource, }; +/** + * ep93xx_register_eth - Register the built-in ethernet platform device. + * @data: platform specific ethernet configuration (__initdata) + * @copy_addr: flag indicating that the MAC address should be copied + * from the IndAd registers (as programmed by the bootloader) + */ void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr) { if (copy_addr) @@ -370,11 +396,19 @@ void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr) static struct i2c_gpio_platform_data ep93xx_i2c_data; static struct platform_device ep93xx_i2c_device = { - .name = "i2c-gpio", - .id = 0, - .dev.platform_data = &ep93xx_i2c_data, + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &ep93xx_i2c_data, + }, }; +/** + * ep93xx_register_i2c - Register the i2c platform device. + * @data: platform specific i2c-gpio configuration (__initdata) + * @devices: platform specific i2c bus device information (__initdata) + * @num: the number of devices on the i2c bus + */ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data, struct i2c_board_info *devices, int num) { @@ -398,17 +432,67 @@ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data, platform_device_register(&ep93xx_i2c_device); } +/************************************************************************* + * EP93xx SPI peripheral handling + *************************************************************************/ +static struct ep93xx_spi_info ep93xx_spi_master_data; + +static struct resource ep93xx_spi_resources[] = { + { + .start = EP93XX_SPI_PHYS_BASE, + .end = EP93XX_SPI_PHYS_BASE + 0x18 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_EP93XX_SSP, + .end = IRQ_EP93XX_SSP, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ep93xx_spi_device = { + .name = "ep93xx-spi", + .id = 0, + .dev = { + .platform_data = &ep93xx_spi_master_data, + }, + .num_resources = ARRAY_SIZE(ep93xx_spi_resources), + .resource = ep93xx_spi_resources, +}; + +/** + * ep93xx_register_spi() - registers spi platform device + * @info: ep93xx board specific spi master info (__initdata) + * @devices: SPI devices to register (__initdata) + * @num: number of SPI devices to register + * + * This function registers platform device for the EP93xx SPI controller and + * also makes sure that SPI pins are muxed so that I2S is not using those pins. + */ +void __init ep93xx_register_spi(struct ep93xx_spi_info *info, + struct spi_board_info *devices, int num) +{ + /* + * When SPI is used, we need to make sure that I2S is muxed off from + * SPI pins. + */ + ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP); + + ep93xx_spi_master_data = *info; + spi_register_board_info(devices, num); + platform_device_register(&ep93xx_spi_device); +} /************************************************************************* * EP93xx LEDs *************************************************************************/ static struct gpio_led ep93xx_led_pins[] = { { - .name = "platform:grled", - .gpio = EP93XX_GPIO_LINE_GRLED, + .name = "platform:grled", + .gpio = EP93XX_GPIO_LINE_GRLED, }, { - .name = "platform:rdled", - .gpio = EP93XX_GPIO_LINE_RDLED, + .name = "platform:rdled", + .gpio = EP93XX_GPIO_LINE_RDLED, }, }; @@ -528,7 +612,7 @@ static struct platform_device ep93xx_fb_device = { .name = "ep93xx-fb", .id = -1, .dev = { - .platform_data = &ep93xxfb_data, + .platform_data = &ep93xxfb_data, .coherent_dma_mask = DMA_BIT_MASK(32), .dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask, }, @@ -536,6 +620,10 @@ static struct platform_device ep93xx_fb_device = { .resource = ep93xx_fb_resource, }; +/** + * ep93xx_register_fb - Register the framebuffer platform device. + * @data: platform specific framebuffer configuration (__initdata) + */ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) { ep93xxfb_data = *data; @@ -546,6 +634,8 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) /************************************************************************* * EP93xx matrix keypad peripheral handling *************************************************************************/ +static struct ep93xx_keypad_platform_data ep93xx_keypad_data; + static struct resource ep93xx_keypad_resource[] = { { .start = EP93XX_KEY_MATRIX_PHYS_BASE, @@ -559,15 +649,22 @@ static struct resource ep93xx_keypad_resource[] = { }; static struct platform_device ep93xx_keypad_device = { - .name = "ep93xx-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(ep93xx_keypad_resource), - .resource = ep93xx_keypad_resource, + .name = "ep93xx-keypad", + .id = -1, + .dev = { + .platform_data = &ep93xx_keypad_data, + }, + .num_resources = ARRAY_SIZE(ep93xx_keypad_resource), + .resource = ep93xx_keypad_resource, }; +/** + * ep93xx_register_keypad - Register the keypad platform device. + * @data: platform specific keypad configuration (__initdata) + */ void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data) { - ep93xx_keypad_device.dev.platform_data = data; + ep93xx_keypad_data = *data; platform_device_register(&ep93xx_keypad_device); } diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index d22d67ac8b9..3884182cd36 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -74,7 +74,7 @@ static void __init edb93xx_register_flash(void) } } -static struct ep93xx_eth_data edb93xx_eth_data = { +static struct ep93xx_eth_data __initdata edb93xx_eth_data = { .phy_id = 1, }; @@ -82,7 +82,7 @@ static struct ep93xx_eth_data edb93xx_eth_data = { /************************************************************************* * EDB93xx i2c peripheral handling *************************************************************************/ -static struct i2c_gpio_platform_data edb93xx_i2c_gpio_data = { +static struct i2c_gpio_platform_data __initdata edb93xx_i2c_gpio_data = { .sda_pin = EP93XX_GPIO_LINE_EEDAT, .sda_is_open_drain = 0, .scl_pin = EP93XX_GPIO_LINE_EECLK, diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c index 3da7ca816d1..a809618e9f0 100644 --- a/arch/arm/mach-ep93xx/gesbc9312.c +++ b/arch/arm/mach-ep93xx/gesbc9312.c @@ -41,7 +41,7 @@ static struct platform_device gesbc9312_flash = { .resource = &gesbc9312_flash_resource, }; -static struct ep93xx_eth_data gesbc9312_eth_data = { +static struct ep93xx_eth_data __initdata gesbc9312_eth_data = { .phy_id = 1, }; diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index 93e2ecc79ce..b1e096f0c2d 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h @@ -106,6 +106,7 @@ #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000) +#define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000) #define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000) #define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000) diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index c6dc14dbca1..9a4413dd44b 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h @@ -6,9 +6,11 @@ struct i2c_gpio_platform_data; struct i2c_board_info; +struct spi_board_info; struct platform_device; struct ep93xxfb_mach_info; struct ep93xx_keypad_platform_data; +struct ep93xx_spi_info; struct ep93xx_eth_data { @@ -33,9 +35,19 @@ static inline void ep93xx_devcfg_clear_bits(unsigned int bits) ep93xx_devcfg_set_clear(0x00, bits); } +#define EP93XX_CHIP_REV_D0 3 +#define EP93XX_CHIP_REV_D1 4 +#define EP93XX_CHIP_REV_E0 5 +#define EP93XX_CHIP_REV_E1 6 +#define EP93XX_CHIP_REV_E2 7 + +unsigned int ep93xx_chip_revision(void); + void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr); void ep93xx_register_i2c(struct i2c_gpio_platform_data *data, struct i2c_board_info *devices, int num); +void ep93xx_register_spi(struct ep93xx_spi_info *info, + struct spi_board_info *devices, int num); void ep93xx_register_fb(struct ep93xxfb_mach_info *data); void ep93xx_register_pwm(int pwm0, int pwm1); int ep93xx_pwm_acquire_gpio(struct platform_device *pdev); diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h index 93107d88ff3..0eabec62cd9 100644 --- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h +++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h @@ -9,9 +9,6 @@ * febff000 22000000 4K model number register * febfe000 22400000 4K options register * febfd000 22800000 4K options register #2 - * febfc000 [67]0000000 4K NAND data register - * febfb000 [67]0400000 4K NAND control register - * febfa000 [67]0800000 4K NAND busy register * febf9000 10800000 4K TS-5620 RTC index register * febf8000 11700000 4K TS-5620 RTC data register */ @@ -41,22 +38,6 @@ #define TS72XX_OPTIONS2_TS9420_BOOT 0x02 -#define TS72XX_NAND1_DATA_PHYS_BASE 0x60000000 -#define TS72XX_NAND2_DATA_PHYS_BASE 0x70000000 -#define TS72XX_NAND_DATA_VIRT_BASE 0xfebfc000 -#define TS72XX_NAND_DATA_SIZE 0x00001000 - -#define TS72XX_NAND1_CONTROL_PHYS_BASE 0x60400000 -#define TS72XX_NAND2_CONTROL_PHYS_BASE 0x70400000 -#define TS72XX_NAND_CONTROL_VIRT_BASE 0xfebfb000 -#define TS72XX_NAND_CONTROL_SIZE 0x00001000 - -#define TS72XX_NAND1_BUSY_PHYS_BASE 0x60800000 -#define TS72XX_NAND2_BUSY_PHYS_BASE 0x70800000 -#define TS72XX_NAND_BUSY_VIRT_BASE 0xfebfa000 -#define TS72XX_NAND_BUSY_SIZE 0x00001000 - - #define TS72XX_RTC_INDEX_VIRT_BASE 0xfebf9000 #define TS72XX_RTC_INDEX_PHYS_BASE 0x10800000 #define TS72XX_RTC_INDEX_SIZE 0x00001000 diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c index c33360e8286..1cc911b4efa 100644 --- a/arch/arm/mach-ep93xx/micro9.c +++ b/arch/arm/mach-ep93xx/micro9.c @@ -80,7 +80,7 @@ static void __init micro9_register_flash(void) /************************************************************************* * Micro9 Ethernet *************************************************************************/ -static struct ep93xx_eth_data micro9_eth_data = { +static struct ep93xx_eth_data __initdata micro9_eth_data = { .phy_id = 0x1f, }; diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index cd93990f1b9..388aec95f60 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -49,17 +49,17 @@ static struct platform_device simone_flash = { }, }; -static struct ep93xx_eth_data simone_eth_data = { +static struct ep93xx_eth_data __initdata simone_eth_data = { .phy_id = 1, }; -static struct ep93xxfb_mach_info simone_fb_info = { +static struct ep93xxfb_mach_info __initdata simone_fb_info = { .num_modes = EP93XXFB_USE_MODEDB, .bpp = 16, .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, }; -static struct i2c_gpio_platform_data simone_i2c_gpio_data = { +static struct i2c_gpio_platform_data __initdata simone_i2c_gpio_data = { .sda_pin = EP93XX_GPIO_LINE_EEDAT, .sda_is_open_drain = 0, .scl_pin = EP93XX_GPIO_LINE_EECLK, diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c index 51134b0382c..38deaee4039 100644 --- a/arch/arm/mach-ep93xx/snappercl15.c +++ b/arch/arm/mach-ep93xx/snappercl15.c @@ -125,11 +125,11 @@ static struct platform_device snappercl15_nand_device = { .num_resources = ARRAY_SIZE(snappercl15_nand_resource), }; -static struct ep93xx_eth_data snappercl15_eth_data = { +static struct ep93xx_eth_data __initdata snappercl15_eth_data = { .phy_id = 1, }; -static struct i2c_gpio_platform_data snappercl15_i2c_gpio_data = { +static struct i2c_gpio_platform_data __initdata snappercl15_i2c_gpio_data = { .sda_pin = EP93XX_GPIO_LINE_EEDAT, .sda_is_open_drain = 0, .scl_pin = EP93XX_GPIO_LINE_EECLK, @@ -145,7 +145,7 @@ static struct i2c_board_info __initdata snappercl15_i2c_data[] = { }, }; -static struct ep93xxfb_mach_info snappercl15_fb_info = { +static struct ep93xxfb_mach_info __initdata snappercl15_fb_info = { .num_modes = EP93XXFB_USE_MODEDB, .bpp = 16, }; diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index fac1ec7a60f..ae7319e588c 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -10,12 +10,16 @@ * your option) any later version. */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/m48t86.h> #include <linux/mtd/physmap.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> #include <mach/hardware.h> #include <mach/ts72xx.h> @@ -54,92 +58,162 @@ static struct map_desc ts72xx_io_desc[] __initdata = { } }; -static struct map_desc ts72xx_nand_io_desc[] __initdata = { - { - .virtual = TS72XX_NAND_DATA_VIRT_BASE, - .pfn = __phys_to_pfn(TS72XX_NAND1_DATA_PHYS_BASE), - .length = TS72XX_NAND_DATA_SIZE, - .type = MT_DEVICE, - }, { - .virtual = TS72XX_NAND_CONTROL_VIRT_BASE, - .pfn = __phys_to_pfn(TS72XX_NAND1_CONTROL_PHYS_BASE), - .length = TS72XX_NAND_CONTROL_SIZE, - .type = MT_DEVICE, - }, { - .virtual = TS72XX_NAND_BUSY_VIRT_BASE, - .pfn = __phys_to_pfn(TS72XX_NAND1_BUSY_PHYS_BASE), - .length = TS72XX_NAND_BUSY_SIZE, - .type = MT_DEVICE, +static void __init ts72xx_map_io(void) +{ + ep93xx_map_io(); + iotable_init(ts72xx_io_desc, ARRAY_SIZE(ts72xx_io_desc)); +} + + +/************************************************************************* + * NAND flash + *************************************************************************/ +#define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */ +#define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */ + +static void ts72xx_nand_hwcontrol(struct mtd_info *mtd, + int cmd, unsigned int ctrl) +{ + struct nand_chip *chip = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + void __iomem *addr = chip->IO_ADDR_R; + unsigned char bits; + + addr += (1 << TS72XX_NAND_CONTROL_ADDR_LINE); + + bits = __raw_readb(addr) & ~0x07; + bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ + bits |= (ctrl & NAND_CLE); /* bit 1 -> bit 1 */ + bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ + + __raw_writeb(bits, addr); } -}; -static struct map_desc ts72xx_alternate_nand_io_desc[] __initdata = { + if (cmd != NAND_CMD_NONE) + __raw_writeb(cmd, chip->IO_ADDR_W); +} + +static int ts72xx_nand_device_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + void __iomem *addr = chip->IO_ADDR_R; + + addr += (1 << TS72XX_NAND_BUSY_ADDR_LINE); + + return !!(__raw_readb(addr) & 0x20); +} + +static const char *ts72xx_nand_part_probes[] = { "cmdlinepart", NULL }; + +#define TS72XX_BOOTROM_PART_SIZE (SZ_16K) +#define TS72XX_REDBOOT_PART_SIZE (SZ_2M + SZ_1M) + +static struct mtd_partition ts72xx_nand_parts[] = { { - .virtual = TS72XX_NAND_DATA_VIRT_BASE, - .pfn = __phys_to_pfn(TS72XX_NAND2_DATA_PHYS_BASE), - .length = TS72XX_NAND_DATA_SIZE, - .type = MT_DEVICE, + .name = "TS-BOOTROM", + .offset = 0, + .size = TS72XX_BOOTROM_PART_SIZE, + .mask_flags = MTD_WRITEABLE, /* force read-only */ }, { - .virtual = TS72XX_NAND_CONTROL_VIRT_BASE, - .pfn = __phys_to_pfn(TS72XX_NAND2_CONTROL_PHYS_BASE), - .length = TS72XX_NAND_CONTROL_SIZE, - .type = MT_DEVICE, + .name = "Linux", + .offset = MTDPART_OFS_APPEND, + .size = 0, /* filled in later */ }, { - .virtual = TS72XX_NAND_BUSY_VIRT_BASE, - .pfn = __phys_to_pfn(TS72XX_NAND2_BUSY_PHYS_BASE), - .length = TS72XX_NAND_BUSY_SIZE, - .type = MT_DEVICE, - } + .name = "RedBoot", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, }; -static void __init ts72xx_map_io(void) +static void ts72xx_nand_set_parts(uint64_t size, + struct platform_nand_chip *chip) { - ep93xx_map_io(); - iotable_init(ts72xx_io_desc, ARRAY_SIZE(ts72xx_io_desc)); + /* Factory TS-72xx boards only come with 32MiB or 128MiB NAND options */ + if (size == SZ_32M || size == SZ_128M) { + /* Set the "Linux" partition size */ + ts72xx_nand_parts[1].size = size - TS72XX_REDBOOT_PART_SIZE; - /* - * The TS-7200 has NOR flash, the other models have NAND flash. - */ - if (!board_is_ts7200()) { - if (is_ts9420_installed()) { - iotable_init(ts72xx_alternate_nand_io_desc, - ARRAY_SIZE(ts72xx_alternate_nand_io_desc)); - } else { - iotable_init(ts72xx_nand_io_desc, - ARRAY_SIZE(ts72xx_nand_io_desc)); - } + chip->partitions = ts72xx_nand_parts; + chip->nr_partitions = ARRAY_SIZE(ts72xx_nand_parts); + } else { + pr_warning("Unknown nand disk size:%lluMiB\n", size >> 20); } } +static struct platform_nand_data ts72xx_nand_data = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, + .chip_delay = 15, + .part_probe_types = ts72xx_nand_part_probes, + .set_parts = ts72xx_nand_set_parts, + }, + .ctrl = { + .cmd_ctrl = ts72xx_nand_hwcontrol, + .dev_ready = ts72xx_nand_device_ready, + }, +}; + +static struct resource ts72xx_nand_resource[] = { + { + .start = 0, /* filled in later */ + .end = 0, /* filled in later */ + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ts72xx_nand_flash = { + .name = "gen_nand", + .id = -1, + .dev.platform_data = &ts72xx_nand_data, + .resource = ts72xx_nand_resource, + .num_resources = ARRAY_SIZE(ts72xx_nand_resource), +}; + + /************************************************************************* * NOR flash (TS-7200 only) *************************************************************************/ -static struct physmap_flash_data ts72xx_flash_data = { +static struct physmap_flash_data ts72xx_nor_data = { .width = 2, }; -static struct resource ts72xx_flash_resource = { +static struct resource ts72xx_nor_resource = { .start = EP93XX_CS6_PHYS_BASE, .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, .flags = IORESOURCE_MEM, }; -static struct platform_device ts72xx_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ts72xx_flash_data, - }, - .num_resources = 1, - .resource = &ts72xx_flash_resource, +static struct platform_device ts72xx_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev.platform_data = &ts72xx_nor_data, + .resource = &ts72xx_nor_resource, + .num_resources = 1, }; static void __init ts72xx_register_flash(void) { - if (board_is_ts7200()) - platform_device_register(&ts72xx_flash); + if (board_is_ts7200()) { + platform_device_register(&ts72xx_nor_flash); + } else { + resource_size_t start; + + if (is_ts9420_installed()) + start = EP93XX_CS7_PHYS_BASE; + else + start = EP93XX_CS6_PHYS_BASE; + + ts72xx_nand_resource[0].start = start; + ts72xx_nand_resource[0].end = start + SZ_16M - 1; + + platform_device_register(&ts72xx_nand_flash); + } } + static unsigned char ts72xx_rtc_readbyte(unsigned long addr) { __raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE); @@ -186,7 +260,7 @@ static struct platform_device ts72xx_wdt_device = { .resource = ts72xx_wdt_resources, }; -static struct ep93xx_eth_data ts72xx_eth_data = { +static struct ep93xx_eth_data __initdata ts72xx_eth_data = { .phy_id = 1, }; diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index df97d16390e..27db275b367 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -11,6 +11,7 @@ config ARCH_INTEGRATOR_AP config ARCH_INTEGRATOR_CP bool "Support Integrator/CP platform" select ARCH_CINTEGRATOR + select ARM_TIMER_SP804 help Include support for the ARM(R) Integrator CP platform. diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile index 6a5ef8d30b1..ebeef966e1f 100644 --- a/arch/arm/mach-integrator/Makefile +++ b/arch/arm/mach-integrator/Makefile @@ -4,7 +4,7 @@ # Object file lists. -obj-y := clock.o core.o lm.o +obj-y := core.o lm.o obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h deleted file mode 100644 index 609c49de3d4..00000000000 --- a/arch/arm/mach-integrator/common.h +++ /dev/null @@ -1,2 +0,0 @@ -extern void integrator_time_init(unsigned long, unsigned int); -extern unsigned long integrator_gettimeoffset(void); diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 8b390e36ba6..b02cfc06e0a 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -24,15 +24,13 @@ #include <asm/clkdev.h> #include <mach/clkdev.h> #include <mach/hardware.h> +#include <mach/platform.h> #include <asm/irq.h> -#include <asm/hardware/arm_timer.h> #include <mach/cm.h> #include <asm/system.h> #include <asm/leds.h> #include <asm/mach/time.h> -#include "common.h" - static struct amba_pl010_data integrator_uart_data; static struct amba_device rtc_device = { @@ -163,8 +161,8 @@ arch_initcall(integrator_init); * UART0 7 6 * UART1 5 4 */ -#define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET) -#define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET) +#define SC_CTRLC IO_ADDRESS(INTEGRATOR_SC_CTRLC) +#define SC_CTRLS IO_ADDRESS(INTEGRATOR_SC_CTRLS) static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl) { @@ -196,7 +194,7 @@ static struct amba_pl010_data integrator_uart_data = { .set_mctrl = integrator_uart_set_mctrl, }; -#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_CTRL_OFFSET +#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL) static DEFINE_SPINLOCK(cm_lock); @@ -217,120 +215,3 @@ void cm_control(u32 mask, u32 set) } EXPORT_SYMBOL(cm_control); - -/* - * Where is the timer (VA)? - */ -#define TIMER0_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000000) -#define TIMER1_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000100) -#define TIMER2_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000200) -#define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) - -/* - * How long is the timer interval? - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) -#if TIMER_INTERVAL >= 0x100000 -#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) -#elif TIMER_INTERVAL >= 0x10000 -#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) -#else -#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) -#endif - -static unsigned long timer_reload; - -/* - * Returns number of ms since last clock interrupt. Note that interrupts - * will have been disabled by do_gettimeoffset() - */ -unsigned long integrator_gettimeoffset(void) -{ - unsigned long ticks1, ticks2, status; - - /* - * Get the current number of ticks. Note that there is a race - * condition between us reading the timer and checking for - * an interrupt. We get around this by ensuring that the - * counter has not reloaded between our two reads. - */ - ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff; - do { - ticks1 = ticks2; - status = __raw_readl(VA_IC_BASE + IRQ_RAW_STATUS); - ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff; - } while (ticks2 > ticks1); - - /* - * Number of ticks since last interrupt. - */ - ticks1 = timer_reload - ticks2; - - /* - * Interrupt pending? If so, we've reloaded once already. - */ - if (status & (1 << IRQ_TIMERINT1)) - ticks1 += timer_reload; - - /* - * Convert the ticks to usecs - */ - return TICKS2USECS(ticks1); -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t -integrator_timer_interrupt(int irq, void *dev_id) -{ - /* - * clear the interrupt - */ - writel(1, TIMER1_VA_BASE + TIMER_INTCLR); - - timer_tick(); - - return IRQ_HANDLED; -} - -static struct irqaction integrator_timer_irq = { - .name = "Integrator Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = integrator_timer_interrupt, -}; - -/* - * Set up timer interrupt, and return the current time in seconds. - */ -void __init integrator_time_init(unsigned long reload, unsigned int ctrl) -{ - unsigned int timer_ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; - - timer_reload = reload; - timer_ctrl |= ctrl; - - if (timer_reload > 0x100000) { - timer_reload >>= 8; - timer_ctrl |= TIMER_CTRL_DIV256; - } else if (timer_reload > 0x010000) { - timer_reload >>= 4; - timer_ctrl |= TIMER_CTRL_DIV16; - } - - /* - * Initialise to a known state (all timers off) - */ - writel(0, TIMER0_VA_BASE + TIMER_CTRL); - writel(0, TIMER1_VA_BASE + TIMER_CTRL); - writel(0, TIMER2_VA_BASE + TIMER_CTRL); - - writel(timer_reload, TIMER1_VA_BASE + TIMER_LOAD); - writel(timer_reload, TIMER1_VA_BASE + TIMER_VALUE); - writel(timer_ctrl, TIMER1_VA_BASE + TIMER_CTRL); - - /* - * Make irqs happen for the system timer - */ - setup_irq(IRQ_TIMERINT1, &integrator_timer_irq); -} diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c index f77f2025504..a3fbcb3adc2 100644 --- a/arch/arm/mach-integrator/cpu.c +++ b/arch/arm/mach-integrator/cpu.c @@ -19,32 +19,39 @@ #include <linux/io.h> #include <mach/hardware.h> +#include <mach/platform.h> #include <asm/mach-types.h> -#include <asm/hardware/icst525.h> +#include <asm/hardware/icst.h> static struct cpufreq_driver integrator_driver; -#define CM_ID (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_ID_OFFSET) -#define CM_OSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_OSC_OFFSET) -#define CM_STAT (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_STAT_OFFSET) -#define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET) +#define CM_ID IO_ADDRESS(INTEGRATOR_HDR_ID) +#define CM_OSC IO_ADDRESS(INTEGRATOR_HDR_OSC) +#define CM_STAT IO_ADDRESS(INTEGRATOR_HDR_STAT) +#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK) -static const struct icst525_params lclk_params = { - .ref = 24000, - .vco_max = 320000, +static const struct icst_params lclk_params = { + .ref = 24000000, + .vco_max = ICST525_VCO_MAX_5V, + .vco_min = ICST525_VCO_MIN, .vd_min = 8, .vd_max = 132, .rd_min = 24, .rd_max = 24, + .s2div = icst525_s2div, + .idx2s = icst525_idx2s, }; -static const struct icst525_params cclk_params = { - .ref = 24000, - .vco_max = 320000, +static const struct icst_params cclk_params = { + .ref = 24000000, + .vco_max = ICST525_VCO_MAX_5V, + .vco_min = ICST525_VCO_MIN, .vd_min = 12, .vd_max = 160, .rd_min = 24, .rd_max = 24, + .s2div = icst525_s2div, + .idx2s = icst525_idx2s, }; /* @@ -52,17 +59,17 @@ static const struct icst525_params cclk_params = { */ static int integrator_verify_policy(struct cpufreq_policy *policy) { - struct icst525_vco vco; + struct icst_vco vco; cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); - vco = icst525_khz_to_vco(&cclk_params, policy->max); - policy->max = icst525_khz(&cclk_params, vco); + vco = icst_hz_to_vco(&cclk_params, policy->max * 1000); + policy->max = icst_hz(&cclk_params, vco) / 1000; - vco = icst525_khz_to_vco(&cclk_params, policy->min); - policy->min = icst525_khz(&cclk_params, vco); + vco = icst_hz_to_vco(&cclk_params, policy->min * 1000); + policy->min = icst_hz(&cclk_params, vco) / 1000; cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, @@ -78,7 +85,7 @@ static int integrator_set_target(struct cpufreq_policy *policy, { cpumask_t cpus_allowed; int cpu = policy->cpu; - struct icst525_vco vco; + struct icst_vco vco; struct cpufreq_freqs freqs; u_int cm_osc; @@ -104,17 +111,17 @@ static int integrator_set_target(struct cpufreq_policy *policy, } vco.v = cm_osc & 255; vco.r = 22; - freqs.old = icst525_khz(&cclk_params, vco); + freqs.old = icst_hz(&cclk_params, vco) / 1000; - /* icst525_khz_to_vco rounds down -- so we need the next + /* icst_hz_to_vco rounds down -- so we need the next * larger freq in case of CPUFREQ_RELATION_L. */ if (relation == CPUFREQ_RELATION_L) target_freq += 999; if (target_freq > policy->max) target_freq = policy->max; - vco = icst525_khz_to_vco(&cclk_params, target_freq); - freqs.new = icst525_khz(&cclk_params, vco); + vco = icst_hz_to_vco(&cclk_params, target_freq * 1000); + freqs.new = icst_hz(&cclk_params, vco) / 1000; freqs.cpu = policy->cpu; @@ -154,7 +161,7 @@ static unsigned int integrator_get(unsigned int cpu) cpumask_t cpus_allowed; unsigned int current_freq; u_int cm_osc; - struct icst525_vco vco; + struct icst_vco vco; cpus_allowed = current->cpus_allowed; @@ -172,7 +179,7 @@ static unsigned int integrator_get(unsigned int cpu) vco.v = cm_osc & 255; vco.r = 22; - current_freq = icst525_khz(&cclk_params, vco); /* current freq */ + current_freq = icst_hz(&cclk_params, vco) / 1000; /* current freq */ set_cpus_allowed(current, cpus_allowed); diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c index 41b10725cef..fd684bf205e 100644 --- a/arch/arm/mach-integrator/impd1.c +++ b/arch/arm/mach-integrator/impd1.c @@ -25,7 +25,7 @@ #include <asm/clkdev.h> #include <mach/clkdev.h> -#include <asm/hardware/icst525.h> +#include <asm/hardware/icst.h> #include <mach/lm.h> #include <mach/impd1.h> #include <asm/sizes.h> @@ -41,32 +41,25 @@ struct impd1_module { struct clk_lookup *clks[3]; }; -static const struct icst525_params impd1_vco_params = { - .ref = 24000, /* 24 MHz */ - .vco_max = 200000, /* 200 MHz */ +static const struct icst_params impd1_vco_params = { + .ref = 24000000, /* 24 MHz */ + .vco_max = ICST525_VCO_MAX_3V, + .vco_min = ICST525_VCO_MIN, .vd_min = 12, .vd_max = 519, .rd_min = 3, .rd_max = 120, + .s2div = icst525_s2div, + .idx2s = icst525_idx2s, }; -static void impd1_setvco(struct clk *clk, struct icst525_vco vco) +static void impd1_setvco(struct clk *clk, struct icst_vco vco) { struct impd1_module *impd1 = clk->data; - int vconr = clk - impd1->vcos; - u32 val; - - val = vco.v | (vco.r << 9) | (vco.s << 16); + u32 val = vco.v | (vco.r << 9) | (vco.s << 16); writel(0xa05f, impd1->base + IMPD1_LOCK); - switch (vconr) { - case 0: - writel(val, impd1->base + IMPD1_OSC1); - break; - case 1: - writel(val, impd1->base + IMPD1_OSC2); - break; - } + writel(val, clk->vcoreg); writel(0, impd1->base + IMPD1_LOCK); #ifdef DEBUG @@ -74,11 +67,17 @@ static void impd1_setvco(struct clk *clk, struct icst525_vco vco) vco.r = (val >> 9) & 0x7f; vco.s = (val >> 16) & 7; - pr_debug("IM-PD1: VCO%d clock is %ld kHz\n", - vconr, icst525_khz(&impd1_vco_params, vco)); + pr_debug("IM-PD1: VCO%d clock is %ld Hz\n", + vconr, icst525_hz(&impd1_vco_params, vco)); #endif } +static const struct clk_ops impd1_clk_ops = { + .round = icst_clk_round, + .set = icst_clk_set, + .setvco = impd1_setvco, +}; + void impd1_tweak_control(struct device *dev, u32 mask, u32 val) { struct impd1_module *impd1 = dev_get_drvdata(dev); @@ -374,11 +373,13 @@ static int impd1_probe(struct lm_device *dev) (unsigned long)dev->resource.start); for (i = 0; i < ARRAY_SIZE(impd1->vcos); i++) { + impd1->vcos[i].ops = &impd1_clk_ops, impd1->vcos[i].owner = THIS_MODULE, impd1->vcos[i].params = &impd1_vco_params, - impd1->vcos[i].data = impd1, - impd1->vcos[i].setvco = impd1_setvco; + impd1->vcos[i].data = impd1; } + impd1->vcos[0].vcoreg = impd1->base + IMPD1_OSC1; + impd1->vcos[1].vcoreg = impd1->base + IMPD1_OSC2; impd1->clks[0] = clkdev_alloc(&impd1->vcos[0], NULL, "lm%x:01000", dev->id); diff --git a/arch/arm/mach-integrator/include/mach/clkdev.h b/arch/arm/mach-integrator/include/mach/clkdev.h index 9293e410832..bfe07679fae 100644 --- a/arch/arm/mach-integrator/include/mach/clkdev.h +++ b/arch/arm/mach-integrator/include/mach/clkdev.h @@ -2,14 +2,15 @@ #define __ASM_MACH_CLKDEV_H #include <linux/module.h> -#include <asm/hardware/icst525.h> +#include <plat/clock.h> struct clk { unsigned long rate; + const struct clk_ops *ops; struct module *owner; - const struct icst525_params *params; + const struct icst_params *params; + void __iomem *vcoreg; void *data; - void (*setvco)(struct clk *, struct icst525_vco vco); }; static inline int __clk_get(struct clk *clk) diff --git a/arch/arm/mach-integrator/include/mach/entry-macro.S b/arch/arm/mach-integrator/include/mach/entry-macro.S index 7649c57acb5..3d029c9f3ef 100644 --- a/arch/arm/mach-integrator/include/mach/entry-macro.S +++ b/arch/arm/mach-integrator/include/mach/entry-macro.S @@ -8,6 +8,7 @@ * warranty of any kind, whether express or implied. */ #include <mach/hardware.h> +#include <mach/platform.h> #include <mach/irqs.h> .macro disable_fiq diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h index d795642fad2..8e26360ce9a 100644 --- a/arch/arm/mach-integrator/include/mach/hardware.h +++ b/arch/arm/mach-integrator/include/mach/hardware.h @@ -23,7 +23,6 @@ #define __ASM_ARCH_HARDWARE_H #include <asm/sizes.h> -#include <mach/platform.h> /* * Where in virtual memory the IO devices (timers, system controllers @@ -36,17 +35,19 @@ #define PCIO_BASE PCI_IO_VADDR #define PCIMEM_BASE PCI_MEMORY_VADDR -#ifdef CONFIG_MMU -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) (((x) >> 4) + IO_BASE) -#else -#define IO_ADDRESS(x) (x) -#endif - #define pcibios_assign_all_busses() 1 #define PCIBIOS_MIN_IO 0x6000 #define PCIBIOS_MIN_MEM 0x00100000 +/* macro to get at IO space when running virtually */ +#ifdef CONFIG_MMU +#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) +#else +#define IO_ADDRESS(x) (x) +#endif + +#define __io_address(n) ((void __iomem *)IO_ADDRESS(n)) + #endif diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index e00a2624f26..5e6ea5cfea6 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h @@ -23,9 +23,6 @@ * * Integrator address map * - * NOTE: This is a multi-hosted header file for use with uHAL and - * supported debuggers. - * * ***********************************************************************/ #ifndef __address_h @@ -290,12 +287,14 @@ #define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) #define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) +#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */ -#if defined(CONFIG_ARCH_INTEGRATOR_AP) -#define INTEGRATOR_GPIO_BASE 0x1B000000 /* GPIO */ -#elif defined(CONFIG_ARCH_INTEGRATOR_CP) -#define INTEGRATOR_GPIO_BASE 0xC9000000 /* GPIO */ -#endif +#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */ +#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */ +#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */ +#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */ +#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */ +#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */ /* ------------------------------------------------------------------------ * KMI keyboard/mouse definitions @@ -328,20 +327,6 @@ */ #define PHYS_PCI_V3_BASE 0x62000000 -#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE - -/* 'export' these to UHAL */ -#define UHAL_PCI_IO PCI_IO_BASE -#define UHAL_PCI_MEM PCI_MEM_BASE -#define UHAL_PCI_ALLOC_IO_BASE 0x00004000 -#define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE -#define UHAL_PCI_MAX_SLOT 20 - -/* ======================================================================== - * Start of uHAL definitions - * ======================================================================== - */ - /* ------------------------------------------------------------------------ * Integrator Interrupt Controllers * ------------------------------------------------------------------------ @@ -389,7 +374,7 @@ */ /* ------------------------------------------------------------------------ - * LED's - The header LED is not accessible via the uHAL API + * LED's * ------------------------------------------------------------------------ * */ @@ -402,34 +387,18 @@ #define LED_BANK INTEGRATOR_DBG_LEDS /* - * Memory definitions - run uHAL out of SSRAM. - * - */ -#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE - -/* - * Clean base - dummy - * - */ -#define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI - -/* * Timer definitions * * Only use timer 1 & 2 * (both run at 24MHz and will need the clock divider set to 16). * - * Timer 0 runs at bus frequency and therefore could vary and currently - * uHAL can't handle that. - * + * Timer 0 runs at bus frequency */ #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) -#define MAX_TIMER 2 -#define MAX_PERIOD 699050 #define TICKS_PER_uSEC 24 /* @@ -437,14 +406,9 @@ * */ #define mSEC_1 1000 -#define mSEC_5 (mSEC_1 * 5) #define mSEC_10 (mSEC_1 * 10) -#define mSEC_25 (mSEC_1 * 25) -#define SEC_1 (mSEC_1 * 1000) #define INTEGRATOR_CSR_BASE 0x10000000 #define INTEGRATOR_CSR_SIZE 0x10000000 #endif - -/* END */ diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 8138a7e2456..227cf4d0508 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -27,9 +27,14 @@ #include <linux/sysdev.h> #include <linux/amba/bus.h> #include <linux/amba/kmi.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/interrupt.h> #include <linux/io.h> #include <mach/hardware.h> +#include <mach/platform.h> +#include <asm/hardware/arm_timer.h> #include <asm/irq.h> #include <asm/setup.h> #include <asm/param.h> /* HZ */ @@ -43,8 +48,6 @@ #include <asm/mach/map.h> #include <asm/mach/time.h> -#include "common.h" - /* * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx * is the (PA >> 12). @@ -55,7 +58,7 @@ #define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) #define VA_SC_BASE IO_ADDRESS(INTEGRATOR_SC_BASE) #define VA_EBI_BASE IO_ADDRESS(INTEGRATOR_EBI_BASE) -#define VA_CMIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_IC_OFFSET +#define VA_CMIC_BASE IO_ADDRESS(INTEGRATOR_HDR_IC) /* * Logical Physical @@ -117,8 +120,8 @@ static struct map_desc ap_io_desc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE), + .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE), .length = SZ_4K, .type = MT_DEVICE }, { @@ -334,14 +337,163 @@ static void __init ap_init(void) } } +/* + * Where is the timer (VA)? + */ +#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE) +#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE) +#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE) + +/* + * How long is the timer interval? + */ +#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) +#if TIMER_INTERVAL >= 0x100000 +#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) +#elif TIMER_INTERVAL >= 0x10000 +#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) +#else +#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) +#endif + +static unsigned long timer_reload; + +static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE; + +static cycle_t timersp_read(struct clocksource *cs) +{ + return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff); +} + +static struct clocksource clocksource_timersp = { + .name = "timer2", + .rating = 200, + .read = timersp_read, + .mask = CLOCKSOURCE_MASK(16), + .shift = 16, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void integrator_clocksource_init(u32 khz) +{ + struct clocksource *cs = &clocksource_timersp; + void __iomem *base = clksrc_base; + u32 ctrl = TIMER_CTRL_ENABLE; + + if (khz >= 1500) { + khz /= 16; + ctrl = TIMER_CTRL_DIV16; + } + + writel(ctrl, base + TIMER_CTRL); + writel(0xffff, base + TIMER_LOAD); + + cs->mult = clocksource_khz2mult(khz, cs->shift); + clocksource_register(cs); +} + +static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE; + +/* + * IRQ handler for the timer + */ +static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + /* clear the interrupt */ + writel(1, clkevt_base + TIMER_INTCLR); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) +{ + u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; + + BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT); + + if (mode == CLOCK_EVT_MODE_PERIODIC) { + writel(ctrl, clkevt_base + TIMER_CTRL); + writel(timer_reload, clkevt_base + TIMER_LOAD); + ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; + } + + writel(ctrl, clkevt_base + TIMER_CTRL); +} + +static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt) +{ + unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); + + writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); + writel(next, clkevt_base + TIMER_LOAD); + writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); + + return 0; +} + +static struct clock_event_device integrator_clockevent = { + .name = "timer1", + .shift = 34, + .features = CLOCK_EVT_FEAT_PERIODIC, + .set_mode = clkevt_set_mode, + .set_next_event = clkevt_set_next_event, + .rating = 300, + .cpumask = cpu_all_mask, +}; + +static struct irqaction integrator_timer_irq = { + .name = "timer", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = integrator_timer_interrupt, + .dev_id = &integrator_clockevent, +}; + +static void integrator_clockevent_init(u32 khz) +{ + struct clock_event_device *evt = &integrator_clockevent; + unsigned int ctrl = 0; + + if (khz * 1000 > 0x100000 * HZ) { + khz /= 256; + ctrl |= TIMER_CTRL_DIV256; + } else if (khz * 1000 > 0x10000 * HZ) { + khz /= 16; + ctrl |= TIMER_CTRL_DIV16; + } + + timer_reload = khz * 1000 / HZ; + writel(ctrl, clkevt_base + TIMER_CTRL); + + evt->irq = IRQ_TIMERINT1; + evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift); + evt->max_delta_ns = clockevent_delta2ns(0xffff, evt); + evt->min_delta_ns = clockevent_delta2ns(0xf, evt); + + setup_irq(IRQ_TIMERINT1, &integrator_timer_irq); + clockevents_register_device(evt); +} + +/* + * Set up timer(s). + */ static void __init ap_init_timer(void) { - integrator_time_init(1000000 * TICKS_PER_uSEC / HZ, 0); + u32 khz = TICKS_PER_uSEC * 1000; + + writel(0, TIMER0_VA_BASE + TIMER_CTRL); + writel(0, TIMER1_VA_BASE + TIMER_CTRL); + writel(0, TIMER2_VA_BASE + TIMER_CTRL); + + integrator_clocksource_init(khz); + integrator_clockevent_init(khz); } static struct sys_timer ap_timer = { .init = ap_init_timer, - .offset = integrator_gettimeoffset, }; MACHINE_START(INTEGRATOR, "ARM-Integrator") diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 15e6cc5a352..cde57b2b83b 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -25,10 +25,12 @@ #include <asm/clkdev.h> #include <mach/clkdev.h> #include <mach/hardware.h> +#include <mach/platform.h> #include <asm/irq.h> #include <asm/setup.h> #include <asm/mach-types.h> -#include <asm/hardware/icst525.h> +#include <asm/hardware/arm_timer.h> +#include <asm/hardware/icst.h> #include <mach/cm.h> #include <mach/lm.h> @@ -39,24 +41,20 @@ #include <asm/mach/map.h> #include <asm/mach/time.h> -#include "common.h" - -#define INTCP_PA_MMC_BASE 0x1c000000 -#define INTCP_PA_AACI_BASE 0x1d000000 +#include <plat/timer-sp.h> #define INTCP_PA_FLASH_BASE 0x24000000 #define INTCP_FLASH_SIZE SZ_32M #define INTCP_PA_CLCD_BASE 0xc0000000 -#define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + 0x40 +#define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40) #define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) -#define INTCP_VA_SIC_BASE IO_ADDRESS(0xca000000) +#define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE) -#define INTCP_PA_ETH_BASE 0xc8000000 #define INTCP_ETH_SIZE 0x10 -#define INTCP_VA_CTRL_BASE IO_ADDRESS(0xcb000000) +#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE) #define INTCP_FLASHPROG 0x04 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) @@ -71,7 +69,9 @@ * f1600000 16000000 UART 0 * f1700000 17000000 UART 1 * f1a00000 1a000000 Debug LEDs - * f1b00000 1b000000 GPIO + * fc900000 c9000000 GPIO + * fca00000 ca000000 SIC + * fcb00000 cb000000 CP system control */ static struct map_desc intcp_io_desc[] __initdata = { @@ -116,18 +116,18 @@ static struct map_desc intcp_io_desc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE), + .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE), .length = SZ_4K, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(0xca000000), - .pfn = __phys_to_pfn(0xca000000), + .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE), .length = SZ_4K, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(0xcb000000), - .pfn = __phys_to_pfn(0xcb000000), + .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE), .length = SZ_4K, .type = MT_DEVICE } @@ -266,33 +266,43 @@ static void __init intcp_init_irq(void) /* * Clock handling */ -#define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET) -#define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c) +#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET) +#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c) -static const struct icst525_params cp_auxvco_params = { - .ref = 24000, - .vco_max = 320000, +static const struct icst_params cp_auxvco_params = { + .ref = 24000000, + .vco_max = ICST525_VCO_MAX_5V, + .vco_min = ICST525_VCO_MIN, .vd_min = 8, .vd_max = 263, .rd_min = 3, .rd_max = 65, + .s2div = icst525_s2div, + .idx2s = icst525_idx2s, }; -static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco) +static void cp_auxvco_set(struct clk *clk, struct icst_vco vco) { u32 val; - val = readl(CM_AUXOSC) & ~0x7ffff; + val = readl(clk->vcoreg) & ~0x7ffff; val |= vco.v | (vco.r << 9) | (vco.s << 16); writel(0xa05f, CM_LOCK); - writel(val, CM_AUXOSC); + writel(val, clk->vcoreg); writel(0, CM_LOCK); } +static const struct clk_ops cp_auxclk_ops = { + .round = icst_clk_round, + .set = icst_clk_set, + .setvco = cp_auxvco_set, +}; + static struct clk cp_auxclk = { + .ops = &cp_auxclk_ops, .params = &cp_auxvco_params, - .setvco = cp_auxvco_set, + .vcoreg = CM_AUXOSC, }; static struct clk_lookup cp_lookups[] = { @@ -363,8 +373,8 @@ static struct platform_device intcp_flash_device = { static struct resource smc91x_resources[] = { [0] = { - .start = INTCP_PA_ETH_BASE, - .end = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1, + .start = INTEGRATOR_CP_ETH_BASE, + .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -394,8 +404,8 @@ static struct platform_device *intcp_devs[] __initdata = { */ static unsigned int mmc_status(struct device *dev) { - unsigned int status = readl(IO_ADDRESS(0xca000000) + 4); - writel(8, IO_ADDRESS(0xcb000000) + 8); + unsigned int status = readl(IO_ADDRESS(0xca000000 + 4)); + writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8)); return status & 8; } @@ -413,8 +423,8 @@ static struct amba_device mmc_device = { .platform_data = &mmc_data, }, .res = { - .start = INTCP_PA_MMC_BASE, - .end = INTCP_PA_MMC_BASE + SZ_4K - 1, + .start = INTEGRATOR_CP_MMC_BASE, + .end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }, @@ -426,8 +436,8 @@ static struct amba_device aaci_device = { .init_name = "mb:1d", }, .res = { - .start = INTCP_PA_AACI_BASE, - .end = INTCP_PA_AACI_BASE + SZ_4K - 1, + .start = INTEGRATOR_CP_AACI_BASE, + .end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = { IRQ_CP_AACIINT, NO_IRQ }, @@ -567,16 +577,22 @@ static void __init intcp_init(void) } } -#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */ +#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) +#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE) +#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE) static void __init intcp_timer_init(void) { - integrator_time_init(1000000 / HZ, TIMER_CTRL_IE); + writel(0, TIMER0_VA_BASE + TIMER_CTRL); + writel(0, TIMER1_VA_BASE + TIMER_CTRL); + writel(0, TIMER2_VA_BASE + TIMER_CTRL); + + sp804_clocksource_init(TIMER2_VA_BASE); + sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1); } static struct sys_timer cp_timer = { .init = intcp_timer_init, - .offset = integrator_gettimeoffset, }; MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c index 8dcc823f413..28be186adb8 100644 --- a/arch/arm/mach-integrator/leds.c +++ b/arch/arm/mach-integrator/leds.c @@ -27,6 +27,7 @@ #include <linux/io.h> #include <mach/hardware.h> +#include <mach/platform.h> #include <asm/leds.h> #include <asm/system.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index ffbd349363a..9cef0590d5a 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -29,6 +29,7 @@ #include <linux/io.h> #include <mach/hardware.h> +#include <mach/platform.h> #include <asm/irq.h> #include <asm/signal.h> #include <asm/system.h> @@ -389,9 +390,9 @@ static int __init pci_v3_setup_resources(struct resource **resource) * means I can't get additional information on the reason for the pm2fb * problems. I suppose I'll just have to mind-meld with the machine. ;) */ -#define SC_PCI (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_PCIENABLE_OFFSET) -#define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x20) -#define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x24) +#define SC_PCI IO_ADDRESS(INTEGRATOR_SC_PCIENABLE) +#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20) +#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24) static int v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index 5d99039286e..f108a31afc2 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -176,7 +176,7 @@ static struct plat_serial8250_port n2100_serial_port[] = { .mapbase = N2100_UART, .membase = (char *)N2100_UART, .irq = 0, - .flags = UPF_SKIP_TEST, + .flags = UPF_SKIP_TEST | UPF_AUTO_IRQ | UPF_SHARE_IRQ, .iotype = UPIO_MEM, .regshift = 0, .uartclk = 1843200, diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 71728d36d50..0bce09799d1 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -21,7 +21,6 @@ #include <linux/tty.h> #include <linux/platform_device.h> #include <linux/serial_core.h> -#include <linux/bootmem.h> #include <linux/interrupt.h> #include <linux/bitops.h> #include <linux/time.h> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 17879a876be..29b2163b1fe 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -38,6 +38,12 @@ config MACH_ESATA_SHEEVAPLUG Say 'Y' here if you want your kernel to support the Marvell eSATA SheevaPlug Reference Board. +config MACH_GURUPLUG + bool "Marvell GuruPlug Reference Board" + help + Say 'Y' here if you want your kernel to support the + Marvell GuruPlug Reference Board. + config MACH_TS219 bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS" help @@ -81,6 +87,18 @@ config MACH_INETSPACE_V2 Say 'Y' here if you want your kernel to support the LaCie Internet Space v2 NAS. +config MACH_NET2BIG_V2 + bool "LaCie 2Big Network v2 NAS Board" + help + Say 'Y' here if you want your kernel to support the + LaCie 2Big Network v2 NAS. + +config MACH_NET5BIG_V2 + bool "LaCie 5Big Network v2 NAS Board" + help + Say 'Y' here if you want your kernel to support the + LaCie 5Big Network v2 NAS. + endmenu endif diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index a5530e36ba3..c0cd5d36200 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -6,10 +6,13 @@ obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o +obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o +obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o +obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index f759ca24392..6072eaa5e66 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -305,6 +305,15 @@ void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, platform_device_register(&kirkwood_nand_flash); } +void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, + int (*dev_ready)(struct mtd_info *)) +{ + kirkwood_clk_ctrl |= CGC_RUNIT; + kirkwood_nand_data.parts = parts; + kirkwood_nand_data.nr_parts = nr_parts; + kirkwood_nand_data.dev_ready = dev_ready; + platform_device_register(&kirkwood_nand_flash); +} /***************************************************************************** * SoC RTC diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index d7de4346435..05e8a8a5692 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -16,6 +16,7 @@ struct mv643xx_eth_platform_data; struct mv_sata_platform_data; struct mvsdio_platform_data; struct mtd_partition; +struct mtd_info; /* * Basic Kirkwood init functions used early by machine-setup. @@ -41,6 +42,7 @@ void kirkwood_i2c_init(void); void kirkwood_uart0_init(void); void kirkwood_uart1_init(void); void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay); +void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *)); extern int kirkwood_tclk; extern struct sys_timer kirkwood_timer; diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c new file mode 100644 index 00000000000..54d07c89d4f --- /dev/null +++ b/arch/arm/mach-kirkwood/guruplug-setup.c @@ -0,0 +1,131 @@ +/* + * arch/arm/mach-kirkwood/guruplug-setup.c + * + * Marvell GuruPlug Reference Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/partitions.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <linux/gpio.h> +#include <linux/leds.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/kirkwood.h> +#include <plat/mvsdio.h> +#include "common.h" +#include "mpp.h" + +static struct mtd_partition guruplug_nand_parts[] = { + { + .name = "u-boot", + .offset = 0, + .size = SZ_1M + }, { + .name = "uImage", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_4M + }, { + .name = "root", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL + }, +}; + +static struct mv643xx_eth_platform_data guruplug_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0), +}; + +static struct mv643xx_eth_platform_data guruplug_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(1), +}; + +static struct mv_sata_platform_data guruplug_sata_data = { + .n_ports = 1, +}; + +static struct mvsdio_platform_data guruplug_mvsdio_data = { + /* unfortunately the CD signal has not been connected */ +}; + +static struct gpio_led guruplug_led_pins[] = { + { + .name = "guruplug:red:health", + .gpio = 46, + .active_low = 1, + }, + { + .name = "guruplug:green:health", + .gpio = 47, + .active_low = 1, + }, + { + .name = "guruplug:red:wmode", + .gpio = 48, + .active_low = 1, + }, + { + .name = "guruplug:green:wmode", + .gpio = 49, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data guruplug_led_data = { + .leds = guruplug_led_pins, + .num_leds = ARRAY_SIZE(guruplug_led_pins), +}; + +static struct platform_device guruplug_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &guruplug_led_data, + } +}; + +static unsigned int guruplug_mpp_config[] __initdata = { + MPP46_GPIO, /* M_RLED */ + MPP47_GPIO, /* M_GLED */ + MPP48_GPIO, /* B_RLED */ + MPP49_GPIO, /* B_GLED */ + 0 +}; + +static void __init guruplug_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + kirkwood_mpp_conf(guruplug_mpp_config); + + kirkwood_uart0_init(); + kirkwood_nand_init(ARRAY_AND_SIZE(guruplug_nand_parts), 25); + + kirkwood_ehci_init(); + kirkwood_ge00_init(&guruplug_ge00_data); + kirkwood_ge01_init(&guruplug_ge01_data); + kirkwood_sata_init(&guruplug_sata_data); + kirkwood_sdio_init(&guruplug_mvsdio_data); + + platform_device_register(&guruplug_leds); +} + +MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board") + /* Maintainer: Siddarth Gore <gores@marvell.com> */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = guruplug_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c new file mode 100644 index 00000000000..8a2bb0228e4 --- /dev/null +++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c @@ -0,0 +1,415 @@ +/* + * arch/arm/mach-kirkwood/netxbig_v2-setup.c + * + * LaCie 2Big and 5Big Network v2 board setup + * + * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/spi/flash.h> +#include <linux/spi/spi.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <linux/i2c.h> +#include <linux/i2c/at24.h> +#include <linux/input.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/leds.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <mach/kirkwood.h> +#include <plat/time.h> +#include "common.h" +#include "mpp.h" + +/***************************************************************************** + * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005) + ****************************************************************************/ + +static struct mtd_partition netxbig_v2_flash_parts[] = { + { + .name = "u-boot", + .size = MTDPART_SIZ_FULL, + .offset = 0, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, +}; + +static const struct flash_platform_data netxbig_v2_flash = { + .type = "mx25l4005a", + .name = "spi_flash", + .parts = netxbig_v2_flash_parts, + .nr_parts = ARRAY_SIZE(netxbig_v2_flash_parts), +}; + +static struct spi_board_info __initdata netxbig_v2_spi_slave_info[] = { + { + .modalias = "m25p80", + .platform_data = &netxbig_v2_flash, + .irq = -1, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data netxbig_v2_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +static struct mv643xx_eth_platform_data netxbig_v2_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0), +}; + +/***************************************************************************** + * I2C devices + ****************************************************************************/ + +static struct at24_platform_data at24c04 = { + .byte_len = SZ_4K / 8, + .page_size = 16, +}; + +/* + * i2c addr | chip | description + * 0x50 | HT24LC04 | eeprom (512B) + */ + +static struct i2c_board_info __initdata netxbig_v2_i2c_info[] = { + { + I2C_BOARD_INFO("24c04", 0x50), + .platform_data = &at24c04, + } +}; + +/***************************************************************************** + * SATA + ****************************************************************************/ + +static struct mv_sata_platform_data netxbig_v2_sata_data = { + .n_ports = 2, +}; + +static int __initdata netxbig_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 }; + +static void __init netxbig_v2_sata_power_init(void) +{ + int i; + int err; + int hdd_nb; + + if (machine_is_net2big_v2()) + hdd_nb = 2; + else + hdd_nb = 5; + + /* Power up all hard disks. */ + for (i = 0; i < hdd_nb; i++) { + err = gpio_request(netxbig_v2_gpio_hdd_power[i], NULL); + if (err == 0) { + err = gpio_direction_output( + netxbig_v2_gpio_hdd_power[i], 1); + /* Free the HDD power GPIOs. This allow user-space to + * configure them via the gpiolib sysfs interface. */ + gpio_free(netxbig_v2_gpio_hdd_power[i]); + } + if (err) + pr_err("netxbig_v2: failed to power up HDD%d\n", i + 1); + } +} + +/***************************************************************************** + * GPIO keys + ****************************************************************************/ + +#define NETXBIG_V2_GPIO_SWITCH_POWER_ON 13 +#define NETXBIG_V2_GPIO_SWITCH_POWER_OFF 15 +#define NETXBIG_V2_GPIO_FUNC_BUTTON 34 + +#define NETXBIG_V2_SWITCH_POWER_ON 0x1 +#define NETXBIG_V2_SWITCH_POWER_OFF 0x2 + +static struct gpio_keys_button netxbig_v2_buttons[] = { + [0] = { + .type = EV_SW, + .code = NETXBIG_V2_SWITCH_POWER_ON, + .gpio = NETXBIG_V2_GPIO_SWITCH_POWER_ON, + .desc = "Back power switch (on|auto)", + .active_low = 1, + }, + [1] = { + .type = EV_SW, + .code = NETXBIG_V2_SWITCH_POWER_OFF, + .gpio = NETXBIG_V2_GPIO_SWITCH_POWER_OFF, + .desc = "Back power switch (auto|off)", + .active_low = 1, + }, + [2] = { + .code = KEY_OPTION, + .gpio = NETXBIG_V2_GPIO_FUNC_BUTTON, + .desc = "Function button", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data netxbig_v2_button_data = { + .buttons = netxbig_v2_buttons, + .nbuttons = ARRAY_SIZE(netxbig_v2_buttons), +}; + +static struct platform_device netxbig_v2_gpio_buttons = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &netxbig_v2_button_data, + }, +}; + +/***************************************************************************** + * GPIO LEDs + ****************************************************************************/ + +/* + * The LEDs are controlled by a CPLD and can be configured through a GPIO + * extension bus: + * + * - address register : bit [0-2] -> GPIO [47-49] + * - data register : bit [0-2] -> GPIO [44-46] + * - enable register : GPIO 29 + * + * Address register selection: + * + * addr | register + * ---------------------------- + * 0 | front LED + * 1 | front LED brightness + * 2 | HDD LED brightness + * 3 | HDD1 LED + * 4 | HDD2 LED + * 5 | HDD3 LED + * 6 | HDD4 LED + * 7 | HDD5 LED + * + * Data register configuration: + * + * data | LED brightness + * ------------------------------------------------- + * 0 | min (off) + * - | - + * 7 | max + * + * data | front LED mode + * ------------------------------------------------- + * 0 | fix off + * 1 | fix blue on + * 2 | fix red on + * 3 | blink blue on=1 sec and blue off=1 sec + * 4 | blink red on=1 sec and red off=1 sec + * 5 | blink blue on=2.5 sec and red on=0.5 sec + * 6 | blink blue on=1 sec and red on=1 sec + * 7 | blink blue on=0.5 sec and blue off=2.5 sec + * + * data | HDD LED mode + * ------------------------------------------------- + * 0 | fix blue on + * 1 | SATA activity blink + * 2 | fix red on + * 3 | blink blue on=1 sec and blue off=1 sec + * 4 | blink red on=1 sec and red off=1 sec + * 5 | blink blue on=2.5 sec and red on=0.5 sec + * 6 | blink blue on=1 sec and red on=1 sec + * 7 | blink blue on=0.5 sec and blue off=2.5 sec + */ + +/***************************************************************************** + * Timer + ****************************************************************************/ + +static void netxbig_v2_timer_init(void) +{ + kirkwood_tclk = 166666667; + orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); +} + +struct sys_timer netxbig_v2_timer = { + .init = netxbig_v2_timer_init, +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +static unsigned int net2big_v2_mpp_config[] __initdata = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Request power-off */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_GPIO, /* Rear power switch (on|auto) */ + MPP14_GPIO, /* USB fuse alarm */ + MPP15_GPIO, /* Rear power switch (auto|off) */ + MPP16_GPIO, /* SATA HDD1 power */ + MPP17_GPIO, /* SATA HDD2 power */ + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP24_GPIO, /* USB mode select */ + MPP26_GPIO, /* USB device vbus */ + MPP28_GPIO, /* USB enable host vbus */ + MPP29_GPIO, /* CPLD extension ALE */ + MPP34_GPIO, /* Rear Push button */ + MPP35_GPIO, /* Inhibit switch power-off */ + MPP36_GPIO, /* SATA HDD1 presence */ + MPP37_GPIO, /* SATA HDD2 presence */ + MPP40_GPIO, /* eSATA presence */ + MPP44_GPIO, /* CPLD extension (data 0) */ + MPP45_GPIO, /* CPLD extension (data 1) */ + MPP46_GPIO, /* CPLD extension (data 2) */ + MPP47_GPIO, /* CPLD extension (addr 0) */ + MPP48_GPIO, /* CPLD extension (addr 1) */ + MPP49_GPIO, /* CPLD extension (addr 2) */ + 0 +}; + +static unsigned int net5big_v2_mpp_config[] __initdata = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Request power-off */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_GPIO, /* Rear power switch (on|auto) */ + MPP14_GPIO, /* USB fuse alarm */ + MPP15_GPIO, /* Rear power switch (auto|off) */ + MPP16_GPIO, /* SATA HDD1 power */ + MPP17_GPIO, /* SATA HDD2 power */ + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, /* USB enable host vbus */ + MPP29_GPIO, /* CPLD extension ALE */ + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, /* Rear Push button */ + MPP35_GPIO, /* Inhibit switch power-off */ + MPP36_GPIO, /* SATA HDD1 presence */ + MPP37_GPIO, /* SATA HDD2 presence */ + MPP38_GPIO, /* SATA HDD3 presence */ + MPP39_GPIO, /* SATA HDD4 presence */ + MPP40_GPIO, /* SATA HDD5 presence */ + MPP41_GPIO, /* SATA HDD3 power */ + MPP42_GPIO, /* SATA HDD4 power */ + MPP43_GPIO, /* SATA HDD5 power */ + MPP44_GPIO, /* CPLD extension (data 0) */ + MPP45_GPIO, /* CPLD extension (data 1) */ + MPP46_GPIO, /* CPLD extension (data 2) */ + MPP47_GPIO, /* CPLD extension (addr 0) */ + MPP48_GPIO, /* CPLD extension (addr 1) */ + MPP49_GPIO, /* CPLD extension (addr 2) */ + 0 +}; + +#define NETXBIG_V2_GPIO_POWER_OFF 7 + +static void netxbig_v2_power_off(void) +{ + gpio_set_value(NETXBIG_V2_GPIO_POWER_OFF, 1); +} + +static void __init netxbig_v2_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + if (machine_is_net2big_v2()) + kirkwood_mpp_conf(net2big_v2_mpp_config); + else + kirkwood_mpp_conf(net5big_v2_mpp_config); + + netxbig_v2_sata_power_init(); + + kirkwood_ehci_init(); + kirkwood_ge00_init(&netxbig_v2_ge00_data); + if (machine_is_net5big_v2()) + kirkwood_ge01_init(&netxbig_v2_ge01_data); + kirkwood_sata_init(&netxbig_v2_sata_data); + kirkwood_uart0_init(); + spi_register_board_info(netxbig_v2_spi_slave_info, + ARRAY_SIZE(netxbig_v2_spi_slave_info)); + kirkwood_spi_init(); + kirkwood_i2c_init(); + i2c_register_board_info(0, netxbig_v2_i2c_info, + ARRAY_SIZE(netxbig_v2_i2c_info)); + + platform_device_register(&netxbig_v2_gpio_buttons); + + if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 && + gpio_direction_output(NETXBIG_V2_GPIO_POWER_OFF, 0) == 0) + pm_power_off = netxbig_v2_power_off; + else + pr_err("netxbig_v2: failed to configure power-off GPIO\n"); +} + +#ifdef CONFIG_MACH_NET2BIG_V2 +MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2") + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = netxbig_v2_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &netxbig_v2_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_NET5BIG_V2 +MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2") + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = netxbig_v2_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &netxbig_v2_timer, +MACHINE_END +#endif diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c index a2d307ec042..244655d323e 100644 --- a/arch/arm/mach-mmp/aspenite.c +++ b/arch/arm/mach-mmp/aspenite.c @@ -59,6 +59,13 @@ static unsigned long common_pin_config[] __initdata = { /* UART1 */ GPIO107_UART1_RXD, GPIO108_UART1_TXD, + + /* SSP1 */ + GPIO113_I2S_MCLK, + GPIO114_I2S_FRM, + GPIO115_I2S_BCLK, + GPIO116_I2S_RXD, + GPIO117_I2S_TXD, }; static struct smc91x_platdata smc91x_info = { @@ -123,12 +130,18 @@ static struct pxa3xx_nand_platform_data aspenite_nand_info = { .nr_parts = ARRAY_SIZE(aspenite_nand_partitions), }; +static struct i2c_board_info aspenite_i2c_info[] __initdata = { + { I2C_BOARD_INFO("wm8753", 0x1b), }, +}; + static void __init common_init(void) { mfp_config(ARRAY_AND_SIZE(common_pin_config)); /* on-chip devices */ pxa168_add_uart(1); + pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info)); + pxa168_add_ssp(1); pxa168_add_nand(&aspenite_nand_info); /* off-chip devices */ diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h index ab26d13295c..ee8b02ed801 100644 --- a/arch/arm/mach-mmp/include/mach/gpio.h +++ b/arch/arm/mach-mmp/include/mach/gpio.h @@ -10,7 +10,7 @@ #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) #define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) -#define NR_BUILTIN_GPIO (128) +#define NR_BUILTIN_GPIO (192) #define gpio_to_bank(gpio) ((gpio) >> 5) #define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio)) diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index 02701196ea0..b379cdec4d3 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h @@ -5,10 +5,10 @@ * Interrupt numbers for PXA168 */ #define IRQ_PXA168_NONE (-1) -#define IRQ_PXA168_SSP3 0 -#define IRQ_PXA168_SSP2 1 -#define IRQ_PXA168_SSP1 2 -#define IRQ_PXA168_SSP0 3 +#define IRQ_PXA168_SSP4 0 +#define IRQ_PXA168_SSP3 1 +#define IRQ_PXA168_SSP2 2 +#define IRQ_PXA168_SSP1 3 #define IRQ_PXA168_PMIC_INT 4 #define IRQ_PXA168_RTC_INT 5 #define IRQ_PXA168_RTC_ALARM 6 @@ -20,7 +20,7 @@ #define IRQ_PXA168_TIMER2 14 #define IRQ_PXA168_TIMER3 15 #define IRQ_PXA168_CMU 16 -#define IRQ_PXA168_SSP4 17 +#define IRQ_PXA168_SSP5 17 #define IRQ_PXA168_MSP_WAKEUP 19 #define IRQ_PXA168_CF_WAKEUP 20 #define IRQ_PXA168_XD_WAKEUP 21 diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h index 9f9f8143e27..761c2dacc07 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h @@ -9,6 +9,175 @@ #define MFP_DRIVE_FAST (0x8 << 13) /* GPIO */ +#define GPIO0_GPIO0 MFP_CFG(GPIO0, AF0) +#define GPIO1_GPIO1 MFP_CFG(GPIO1, AF0) +#define GPIO2_GPIO2 MFP_CFG(GPIO2, AF0) +#define GPIO3_GPIO3 MFP_CFG(GPIO3, AF0) +#define GPIO4_GPIO4 MFP_CFG(GPIO4, AF0) +#define GPIO5_GPIO5 MFP_CFG(GPIO5, AF0) +#define GPIO6_GPIO6 MFP_CFG(GPIO6, AF0) +#define GPIO7_GPIO7 MFP_CFG(GPIO7, AF0) +#define GPIO8_GPIO8 MFP_CFG(GPIO8, AF0) +#define GPIO9_GPIO9 MFP_CFG(GPIO9, AF0) +#define GPIO10_GPIO10 MFP_CFG(GPIO10, AF0) +#define GPIO11_GPIO11 MFP_CFG(GPIO11, AF0) +#define GPIO12_GPIO12 MFP_CFG(GPIO12, AF0) +#define GPIO13_GPIO13 MFP_CFG(GPIO13, AF0) +#define GPIO14_GPIO14 MFP_CFG(GPIO14, AF0) +#define GPIO15_GPIO15 MFP_CFG(GPIO15, AF0) +#define GPIO16_GPIO16 MFP_CFG(GPIO16, AF0) +#define GPIO17_GPIO17 MFP_CFG(GPIO17, AF0) +#define GPIO18_GPIO18 MFP_CFG(GPIO18, AF0) +#define GPIO19_GPIO19 MFP_CFG(GPIO19, AF0) +#define GPIO20_GPIO20 MFP_CFG(GPIO20, AF0) +#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0) +#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0) +#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0) +#define GPIO24_GPIO24 MFP_CFG(GPIO24, AF0) +#define GPIO25_GPIO25 MFP_CFG(GPIO25, AF0) +#define GPIO26_GPIO26 MFP_CFG(GPIO26, AF0) +#define GPIO27_GPIO27 MFP_CFG(GPIO27, AF0) +#define GPIO28_GPIO28 MFP_CFG(GPIO28, AF0) +#define GPIO29_GPIO29 MFP_CFG(GPIO29, AF0) +#define GPIO30_GPIO30 MFP_CFG(GPIO30, AF0) +#define GPIO31_GPIO31 MFP_CFG(GPIO31, AF0) +#define GPIO32_GPIO32 MFP_CFG(GPIO32, AF0) +#define GPIO33_GPIO33 MFP_CFG(GPIO33, AF0) +#define GPIO34_GPIO34 MFP_CFG(GPIO34, AF0) +#define GPIO35_GPIO35 MFP_CFG(GPIO35, AF0) +#define GPIO36_GPIO36 MFP_CFG(GPIO36, AF0) +#define GPIO37_GPIO37 MFP_CFG(GPIO37, AF0) +#define GPIO38_GPIO38 MFP_CFG(GPIO38, AF0) +#define GPIO39_GPIO39 MFP_CFG(GPIO39, AF0) +#define GPIO40_GPIO40 MFP_CFG(GPIO40, AF0) +#define GPIO41_GPIO41 MFP_CFG(GPIO41, AF0) +#define GPIO42_GPIO42 MFP_CFG(GPIO42, AF0) +#define GPIO43_GPIO43 MFP_CFG(GPIO43, AF0) +#define GPIO44_GPIO44 MFP_CFG(GPIO44, AF0) +#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0) +#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0) +#define GPIO47_GPIO47 MFP_CFG(GPIO47, AF0) +#define GPIO48_GPIO48 MFP_CFG(GPIO48, AF0) +#define GPIO49_GPIO49 MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO50 MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO51 MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO52 MFP_CFG(GPIO52, AF0) +#define GPIO53_GPIO53 MFP_CFG(GPIO53, AF0) +#define GPIO54_GPIO54 MFP_CFG(GPIO54, AF0) +#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0) +#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0) +#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0) +#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO59 MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO60 MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO61 MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO62 MFP_CFG(GPIO62, AF0) +#define GPIO63_GPIO63 MFP_CFG(GPIO63, AF0) +#define GPIO64_GPIO64 MFP_CFG(GPIO64, AF0) +#define GPIO65_GPIO65 MFP_CFG(GPIO65, AF0) +#define GPIO66_GPIO66 MFP_CFG(GPIO66, AF0) +#define GPIO67_GPIO67 MFP_CFG(GPIO67, AF0) +#define GPIO68_GPIO68 MFP_CFG(GPIO68, AF0) +#define GPIO69_GPIO69 MFP_CFG(GPIO69, AF0) +#define GPIO70_GPIO70 MFP_CFG(GPIO70, AF0) +#define GPIO71_GPIO71 MFP_CFG(GPIO71, AF0) +#define GPIO72_GPIO72 MFP_CFG(GPIO72, AF0) +#define GPIO73_GPIO73 MFP_CFG(GPIO73, AF0) +#define GPIO74_GPIO74 MFP_CFG(GPIO74, AF0) +#define GPIO75_GPIO75 MFP_CFG(GPIO75, AF0) +#define GPIO76_GPIO76 MFP_CFG(GPIO76, AF0) +#define GPIO77_GPIO77 MFP_CFG(GPIO77, AF0) +#define GPIO78_GPIO78 MFP_CFG(GPIO78, AF0) +#define GPIO79_GPIO79 MFP_CFG(GPIO79, AF0) +#define GPIO80_GPIO80 MFP_CFG(GPIO80, AF0) +#define GPIO81_GPIO81 MFP_CFG(GPIO81, AF0) +#define GPIO82_GPIO82 MFP_CFG(GPIO82, AF0) +#define GPIO83_GPIO83 MFP_CFG(GPIO83, AF0) +#define GPIO84_GPIO84 MFP_CFG(GPIO84, AF0) +#define GPIO85_GPIO85 MFP_CFG(GPIO85, AF0) +#define GPIO86_GPIO86 MFP_CFG(GPIO86, AF0) +#define GPIO87_GPIO87 MFP_CFG(GPIO87, AF0) +#define GPIO88_GPIO88 MFP_CFG(GPIO88, AF0) +#define GPIO89_GPIO89 MFP_CFG(GPIO89, AF0) +#define GPIO90_GPIO90 MFP_CFG(GPIO90, AF0) +#define GPIO91_GPIO91 MFP_CFG(GPIO91, AF0) +#define GPIO92_GPIO92 MFP_CFG(GPIO92, AF0) +#define GPIO93_GPIO93 MFP_CFG(GPIO93, AF0) +#define GPIO94_GPIO94 MFP_CFG(GPIO94, AF0) +#define GPIO95_GPIO95 MFP_CFG(GPIO95, AF0) +#define GPIO96_GPIO96 MFP_CFG(GPIO96, AF0) +#define GPIO97_GPIO97 MFP_CFG(GPIO97, AF0) +#define GPIO98_GPIO98 MFP_CFG(GPIO98, AF0) +#define GPIO99_GPIO99 MFP_CFG(GPIO99, AF0) +#define GPIO100_GPIO100 MFP_CFG(GPIO100, AF0) +#define GPIO101_GPIO101 MFP_CFG(GPIO101, AF0) +#define GPIO102_GPIO102 MFP_CFG(GPIO102, AF1) +#define GPIO103_GPIO103 MFP_CFG(GPIO103, AF1) +#define GPIO104_GPIO104 MFP_CFG(GPIO104, AF1) +#define GPIO105_GPIO105 MFP_CFG(GPIO105, AF1) +#define GPIO106_GPIO106 MFP_CFG(GPIO106, AF1) +#define GPIO107_GPIO107 MFP_CFG(GPIO107, AF1) +#define GPIO108_GPIO108 MFP_CFG(GPIO108, AF1) +#define GPIO109_GPIO109 MFP_CFG(GPIO109, AF1) +#define GPIO110_GPIO110 MFP_CFG(GPIO110, AF1) +#define GPIO111_GPIO111 MFP_CFG(GPIO111, AF1) +#define GPIO112_GPIO112 MFP_CFG(GPIO112, AF1) +#define GPIO113_GPIO113 MFP_CFG(GPIO113, AF1) +#define GPIO114_GPIO114 MFP_CFG(GPIO114, AF0) +#define GPIO115_GPIO115 MFP_CFG(GPIO115, AF0) +#define GPIO116_GPIO116 MFP_CFG(GPIO116, AF0) +#define GPIO117_GPIO117 MFP_CFG(GPIO117, AF0) +#define GPIO118_GPIO118 MFP_CFG(GPIO118, AF0) +#define GPIO119_GPIO119 MFP_CFG(GPIO119, AF0) +#define GPIO120_GPIO120 MFP_CFG(GPIO120, AF0) +#define GPIO121_GPIO121 MFP_CFG(GPIO121, AF0) +#define GPIO122_GPIO122 MFP_CFG(GPIO122, AF0) +#define GPIO123_GPIO123 MFP_CFG(GPIO123, AF0) +#define GPIO124_GPIO124 MFP_CFG(GPIO124, AF0) +#define GPIO125_GPIO125 MFP_CFG(GPIO125, AF0) +#define GPIO126_GPIO126 MFP_CFG(GPIO126, AF0) +#define GPIO127_GPIO127 MFP_CFG(GPIO127, AF0) +#define GPIO128_GPIO128 MFP_CFG(GPIO128, AF0) +#define GPIO129_GPIO129 MFP_CFG(GPIO129, AF0) +#define GPIO130_GPIO130 MFP_CFG(GPIO130, AF0) +#define GPIO131_GPIO131 MFP_CFG(GPIO131, AF0) +#define GPIO132_GPIO132 MFP_CFG(GPIO132, AF0) +#define GPIO133_GPIO133 MFP_CFG(GPIO133, AF0) +#define GPIO134_GPIO134 MFP_CFG(GPIO134, AF0) +#define GPIO135_GPIO135 MFP_CFG(GPIO135, AF0) +#define GPIO136_GPIO136 MFP_CFG(GPIO136, AF0) +#define GPIO137_GPIO137 MFP_CFG(GPIO137, AF0) +#define GPIO138_GPIO138 MFP_CFG(GPIO138, AF0) +#define GPIO139_GPIO139 MFP_CFG(GPIO139, AF0) +#define GPIO140_GPIO140 MFP_CFG(GPIO140, AF0) +#define GPIO141_GPIO141 MFP_CFG(GPIO141, AF0) +#define GPIO142_GPIO142 MFP_CFG(GPIO142, AF1) +#define GPIO143_GPIO143 MFP_CFG(GPIO143, AF1) +#define GPIO144_GPIO144 MFP_CFG(GPIO144, AF1) +#define GPIO145_GPIO145 MFP_CFG(GPIO145, AF1) +#define GPIO146_GPIO146 MFP_CFG(GPIO146, AF1) +#define GPIO147_GPIO147 MFP_CFG(GPIO147, AF1) +#define GPIO148_GPIO148 MFP_CFG(GPIO148, AF1) +#define GPIO149_GPIO149 MFP_CFG(GPIO149, AF1) +#define GPIO150_GPIO150 MFP_CFG(GPIO150, AF1) +#define GPIO151_GPIO151 MFP_CFG(GPIO151, AF1) +#define GPIO152_GPIO152 MFP_CFG(GPIO152, AF1) +#define GPIO153_GPIO153 MFP_CFG(GPIO153, AF1) +#define GPIO154_GPIO154 MFP_CFG(GPIO154, AF1) +#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1) +#define GPIO156_GPIO156 MFP_CFG(GPIO156, AF1) +#define GPIO157_GPIO157 MFP_CFG(GPIO157, AF1) +#define GPIO158_GPIO158 MFP_CFG(GPIO158, AF1) +#define GPIO159_GPIO159 MFP_CFG(GPIO159, AF1) +#define GPIO160_GPIO160 MFP_CFG(GPIO160, AF1) +#define GPIO161_GPIO161 MFP_CFG(GPIO161, AF1) +#define GPIO162_GPIO162 MFP_CFG(GPIO162, AF1) +#define GPIO163_GPIO163 MFP_CFG(GPIO163, AF1) +#define GPIO164_GPIO164 MFP_CFG(GPIO164, AF1) +#define GPIO165_GPIO165 MFP_CFG(GPIO165, AF1) +#define GPIO166_GPIO166 MFP_CFG(GPIO166, AF1) +#define GPIO167_GPIO167 MFP_CFG(GPIO167, AF1) +#define GPIO168_GPIO168 MFP_CFG(GPIO168, AF1) /* DFI */ #define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0) @@ -47,7 +216,6 @@ /* Ethernet */ #define GPIO155_SM_ADVMUX MFP_CFG(GPIO155, AF2) -#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1) /* UART1 */ #define GPIO45_UART1_RXD MFP_CFG(GPIO45, AF1) @@ -159,6 +327,8 @@ #define GPIO44_TWSI2_SDA MFP_CFG_DRV(GPIO44, AF1, SLOW) #define GPIO71_TWSI3_SCL MFP_CFG_DRV(GPIO71, AF1, SLOW) #define GPIO72_TWSI3_SDA MFP_CFG_DRV(GPIO72, AF1, SLOW) +#define TWSI4_SCL MFP_CFG_DRV(TWSI4_SCL, AF0, SLOW) +#define TWSI4_SDA MFP_CFG_DRV(TWSI4_SDA, AF0, SLOW) #define GPIO99_TWSI5_SCL MFP_CFG_DRV(GPIO99, AF4, SLOW) #define GPIO100_TWSI5_SDA MFP_CFG_DRV(GPIO100, AF4, SLOW) #define GPIO97_TWSI6_SCL MFP_CFG_DRV(GPIO97, AF2, SLOW) @@ -218,21 +388,6 @@ #define GPIO69_CAM_MCLK MFP_CFG_DRV(GPIO69, AF1, FAST) #define GPIO70_CAM_PCLK MFP_CFG_DRV(GPIO70, AF1, FAST) -/* Wifi */ -#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0) -#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0) -#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0) -#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0) -#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0) -#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0) -#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0) -#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0) - -/* Codec*/ -#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0) - -#define GPIO101_GPIO101 MFP_CFG(GPIO101, AF0) - /* PMIC */ #define PMIC_PMIC_INT MFP_CFG(PMIC_INT, AF0) diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h index 459f3be9cfb..fec220bd504 100644 --- a/arch/arm/mach-mmp/include/mach/mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mmp2.h @@ -39,17 +39,17 @@ static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data, int ret; switch (id) { - case 0: d = &mmp2_device_twsi1; break; - case 1: d = &mmp2_device_twsi2; break; - case 2: d = &mmp2_device_twsi3; break; - case 3: d = &mmp2_device_twsi4; break; - case 4: d = &mmp2_device_twsi5; break; - case 5: d = &mmp2_device_twsi6; break; + case 1: d = &mmp2_device_twsi1; break; + case 2: d = &mmp2_device_twsi2; break; + case 3: d = &mmp2_device_twsi3; break; + case 4: d = &mmp2_device_twsi4; break; + case 5: d = &mmp2_device_twsi5; break; + case 6: d = &mmp2_device_twsi6; break; default: return -EINVAL; } - ret = i2c_register_board_info(id, info, size); + ret = i2c_register_board_info(id - 1, info, size); if (ret) return ret; diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index 3ad612cbdf0..3b2bd5d5eb0 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -14,6 +14,11 @@ extern struct pxa_device_desc pxa168_device_pwm1; extern struct pxa_device_desc pxa168_device_pwm2; extern struct pxa_device_desc pxa168_device_pwm3; extern struct pxa_device_desc pxa168_device_pwm4; +extern struct pxa_device_desc pxa168_device_ssp1; +extern struct pxa_device_desc pxa168_device_ssp2; +extern struct pxa_device_desc pxa168_device_ssp3; +extern struct pxa_device_desc pxa168_device_ssp4; +extern struct pxa_device_desc pxa168_device_ssp5; extern struct pxa_device_desc pxa168_device_nand; static inline int pxa168_add_uart(int id) @@ -67,6 +72,22 @@ static inline int pxa168_add_pwm(int id) return pxa_register_device(d, NULL, 0); } +static inline int pxa168_add_ssp(int id) +{ + struct pxa_device_desc *d = NULL; + + switch (id) { + case 1: d = &pxa168_device_ssp1; break; + case 2: d = &pxa168_device_ssp2; break; + case 3: d = &pxa168_device_ssp3; break; + case 4: d = &pxa168_device_ssp4; break; + case 5: d = &pxa168_device_ssp5; break; + default: + return -EINVAL; + } + return pxa_register_device(d, NULL, 0); +} + static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info) { return pxa_register_device(&pxa168_device_nand, info, sizeof(*info)); diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index 712af03fd1a..1a96585336b 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -26,8 +26,6 @@ #define APBC_PXA168_PWM2 APBC_REG(0x010) #define APBC_PXA168_PWM3 APBC_REG(0x014) #define APBC_PXA168_PWM4 APBC_REG(0x018) -#define APBC_PXA168_SSP1 APBC_REG(0x01c) -#define APBC_PXA168_SSP2 APBC_REG(0x020) #define APBC_PXA168_RTC APBC_REG(0x028) #define APBC_PXA168_TWSI0 APBC_REG(0x02c) #define APBC_PXA168_KPC APBC_REG(0x030) @@ -35,14 +33,16 @@ #define APBC_PXA168_AIB APBC_REG(0x03c) #define APBC_PXA168_SW_JTAG APBC_REG(0x040) #define APBC_PXA168_ONEWIRE APBC_REG(0x048) -#define APBC_PXA168_SSP3 APBC_REG(0x04c) #define APBC_PXA168_ASFAR APBC_REG(0x050) #define APBC_PXA168_ASSAR APBC_REG(0x054) -#define APBC_PXA168_SSP4 APBC_REG(0x058) -#define APBC_PXA168_SSP5 APBC_REG(0x05c) #define APBC_PXA168_TWSI1 APBC_REG(0x06c) #define APBC_PXA168_UART3 APBC_REG(0x070) #define APBC_PXA168_AC97 APBC_REG(0x084) +#define APBC_PXA168_SSP1 APBC_REG(0x81c) +#define APBC_PXA168_SSP2 APBC_REG(0x820) +#define APBC_PXA168_SSP3 APBC_REG(0x84c) +#define APBC_PXA168_SSP4 APBC_REG(0x858) +#define APBC_PXA168_SSP5 APBC_REG(0x85c) /* * APB Clock register offsets for PXA910 diff --git a/arch/arm/mach-mmp/include/mach/regs-smc.h b/arch/arm/mach-mmp/include/mach/regs-smc.h new file mode 100644 index 00000000000..e484d40d71b --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-smc.h @@ -0,0 +1,37 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/regs-smc.h + * + * Static Memory Controller Registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_REGS_SMC_H +#define __ASM_MACH_REGS_SMC_H + +#include <mach/addr-map.h> + +#define SMC_VIRT_BASE (AXI_VIRT_BASE + 0x83800) +#define SMC_REG(x) (SMC_VIRT_BASE + (x)) + +#define SMC_MSC0 SMC_REG(0x0020) +#define SMC_MSC1 SMC_REG(0x0024) +#define SMC_SXCNFG0 SMC_REG(0x0030) +#define SMC_SXCNFG1 SMC_REG(0x0034) +#define SMC_MEMCLKCFG SMC_REG(0x0068) +#define SMC_CSDFICFG0 SMC_REG(0x0090) +#define SMC_CSDFICFG1 SMC_REG(0x0094) +#define SMC_CLK_RET_DEL SMC_REG(0x00b0) +#define SMC_ADV_RET_DEL SMC_REG(0x00b4) +#define SMC_CSADRMAP0 SMC_REG(0x00c0) +#define SMC_CSADRMAP1 SMC_REG(0x00c4) +#define SMC_WE_AP0 SMC_REG(0x00e0) +#define SMC_WE_AP1 SMC_REG(0x00e4) +#define SMC_OE_AP0 SMC_REG(0x00f0) +#define SMC_OE_AP1 SMC_REG(0x00f4) +#define SMC_ADV_AP0 SMC_REG(0x0100) +#define SMC_ADV_AP1 SMC_REG(0x0104) + +#endif /* __ASM_MACH_REGS_SMC_H */ diff --git a/arch/arm/mach-mmp/include/mach/timex.h b/arch/arm/mach-mmp/include/mach/timex.h index 6cebbd0ca8f..70c9f1d88c0 100644 --- a/arch/arm/mach-mmp/include/mach/timex.h +++ b/arch/arm/mach-mmp/include/mach/timex.h @@ -6,4 +6,8 @@ * published by the Free Software Foundation. */ +#ifdef CONFIG_CPU_MMP2 +#define CLOCK_TICK_RATE 6500000 +#else #define CLOCK_TICK_RATE 3250000 +#endif diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c index cfd4d66ef80..d77dd41d60e 100644 --- a/arch/arm/mach-mmp/jasper.c +++ b/arch/arm/mach-mmp/jasper.c @@ -15,12 +15,16 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/gpio.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/max8649.h> +#include <linux/mfd/max8925.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/addr-map.h> #include <mach/mfp-mmp2.h> #include <mach/mmp2.h> +#include <mach/irqs.h> #include "common.h" @@ -58,6 +62,63 @@ static unsigned long jasper_pin_config[] __initdata = { GPIO149_ND_CLE, GPIO112_ND_RDY0, GPIO160_ND_RDY1, + + /* PMIC */ + PMIC_PMIC_INT | MFP_LPM_EDGE_FALL, +}; + +static struct regulator_consumer_supply max8649_supply[] = { + REGULATOR_SUPPLY("vcc_core", NULL), +}; + +static struct regulator_init_data max8649_init_data = { + .constraints = { + .name = "vcc_core range", + .min_uV = 1150000, + .max_uV = 1280000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8649_supply[0], +}; + +static struct max8649_platform_data jasper_max8649_info = { + .mode = 2, /* VID1 = 1, VID0 = 0 */ + .extclk = 0, + .ramp_timing = MAX8649_RAMP_32MV, + .regulator = &max8649_init_data, +}; + +static struct max8925_backlight_pdata jasper_backlight_data = { + .dual_string = 0, +}; + +static struct max8925_power_pdata jasper_power_data = { + .batt_detect = 0, /* can't detect battery by ID pin */ + .topoff_threshold = MAX8925_TOPOFF_THR_10PER, + .fast_charge = MAX8925_FCHG_1000MA, +}; + +static struct max8925_platform_data jasper_max8925_info = { + .backlight = &jasper_backlight_data, + .power = &jasper_power_data, + .irq_base = IRQ_BOARD_START, +}; + +static struct i2c_board_info jasper_twsi1_info[] = { + [0] = { + .type = "max8649", + .addr = 0x60, + .platform_data = &jasper_max8649_info, + }, + [1] = { + .type = "max8925", + .addr = 0x3c, + .irq = IRQ_MMP2_PMIC, + .platform_data = &jasper_max8925_info, + }, }; static void __init jasper_init(void) @@ -67,6 +128,9 @@ static void __init jasper_init(void) /* on-chip devices */ mmp2_add_uart(1); mmp2_add_uart(3); + mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info)); + + regulator_has_full_constraints(); } MACHINE_START(MARVELL_JASPER, "Jasper Development Platform") diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index 72eb9daeea9..7f5eb059bb0 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c @@ -15,11 +15,14 @@ #include <linux/init.h> #include <linux/io.h> +#include <asm/hardware/cache-tauros2.h> + #include <mach/addr-map.h> #include <mach/regs-apbc.h> #include <mach/regs-apmu.h> #include <mach/cputype.h> #include <mach/irqs.h> +#include <mach/dma.h> #include <mach/mfp.h> #include <mach/gpio.h> #include <mach/devices.h> @@ -32,7 +35,50 @@ #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c) static struct mfp_addr_map mmp2_addr_map[] __initdata = { + + MFP_ADDR_X(GPIO0, GPIO58, 0x54), + MFP_ADDR_X(GPIO59, GPIO73, 0x280), + MFP_ADDR_X(GPIO74, GPIO101, 0x170), + + MFP_ADDR(GPIO102, 0x0), + MFP_ADDR(GPIO103, 0x4), + MFP_ADDR(GPIO104, 0x1fc), + MFP_ADDR(GPIO105, 0x1f8), + MFP_ADDR(GPIO106, 0x1f4), + MFP_ADDR(GPIO107, 0x1f0), + MFP_ADDR(GPIO108, 0x21c), + MFP_ADDR(GPIO109, 0x218), + MFP_ADDR(GPIO110, 0x214), + MFP_ADDR(GPIO111, 0x200), + MFP_ADDR(GPIO112, 0x244), + MFP_ADDR(GPIO113, 0x25c), + MFP_ADDR(GPIO114, 0x164), + MFP_ADDR_X(GPIO115, GPIO122, 0x260), + + MFP_ADDR(GPIO123, 0x148), + MFP_ADDR_X(GPIO124, GPIO141, 0xc), + + MFP_ADDR(GPIO142, 0x8), + MFP_ADDR_X(GPIO143, GPIO151, 0x220), + MFP_ADDR_X(GPIO152, GPIO153, 0x248), + MFP_ADDR_X(GPIO154, GPIO155, 0x254), + MFP_ADDR_X(GPIO156, GPIO159, 0x14c), + + MFP_ADDR(GPIO160, 0x250), + MFP_ADDR(GPIO161, 0x210), + MFP_ADDR(GPIO162, 0x20c), + MFP_ADDR(GPIO163, 0x208), + MFP_ADDR(GPIO164, 0x204), + MFP_ADDR(GPIO165, 0x1ec), + MFP_ADDR(GPIO166, 0x1e8), + MFP_ADDR(GPIO167, 0x1e4), + MFP_ADDR(GPIO168, 0x1e0), + + MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140), + MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc), + MFP_ADDR(PMIC_INT, 0x2c4), + MFP_ADDR(CLK_REQ, 0x160), MFP_ADDR_END, }; @@ -99,9 +145,13 @@ static struct clk_lookup mmp2_clkregs[] = { static int __init mmp2_init(void) { if (cpu_is_mmp2()) { +#ifdef CONFIG_CACHE_TAUROS2 + tauros2_init(); +#endif mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(mmp2_addr_map); - clks_register(ARRAY_AND_SIZE(mmp2_clkregs)); + pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); + clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); } return 0; diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index 1873c821df9..652ae660634 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -72,6 +72,11 @@ static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); +static APBC_CLK(ssp1, PXA168_SSP1, 4, 0); +static APBC_CLK(ssp2, PXA168_SSP2, 4, 0); +static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); +static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); +static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); static APMU_CLK(nand, NAND, 0x01db, 208000000); @@ -85,6 +90,11 @@ static struct clk_lookup pxa168_clkregs[] = { INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), + INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), + INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), + INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), + INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), + INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), }; @@ -132,3 +142,8 @@ PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10); PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10); PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10); PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); +PXA168_DEVICE(ssp1, "pxa168-ssp", 0, SSP1, 0xd401b000, 0x40, 52, 53); +PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55); +PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57); +PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59); +PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61); diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index f780086befd..47264a76eeb 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -1,7 +1,80 @@ if ARCH_MSM -comment "MSM Board Type" +choice + prompt "Qualcomm MSM SoC Type" + default ARCH_MSM7X00A + +config ARCH_MSM7X00A + bool "MSM7x00A / MSM7x01A" + select ARCH_MSM_ARM11 + select MSM_SMD + select MSM_SMD_PKG3 + select CPU_V6 + +config ARCH_MSM7X30 + bool "MSM7x30" + select ARCH_MSM_SCORPION + select MSM_SMD + select MSM_VIC + select CPU_V7 + select MSM_REMOTE_SPINLOCK_DEKKERS + +config ARCH_QSD8X50 + bool "QSD8X50" + select ARCH_MSM_SCORPION + select MSM_SMD + select MSM_VIC + select CPU_V7 + select MSM_REMOTE_SPINLOCK_LDREX +endchoice + +config MSM_SOC_REV_A + bool + +config ARCH_MSM_ARM11 + bool +config ARCH_MSM_SCORPION + bool + +config MSM_VIC + bool + +menu "Qualcomm MSM Board Type" + +config MACH_HALIBUT depends on ARCH_MSM + depends on ARCH_MSM7X00A + bool "Halibut Board (QCT SURF7201A)" + help + Support for the Qualcomm SURF7201A eval board. + +config MACH_TROUT + depends on ARCH_MSM + depends on ARCH_MSM7X00A + bool "HTC Dream (aka trout)" + help + Support for the HTC Dream, T-Mobile G1, Android ADP1 devices. + +config MACH_MSM7X30_SURF + depends on ARCH_MSM7X30 + bool "MSM7x30 SURF" + help + Support for the Qualcomm MSM7x30 SURF eval board. + +config MACH_QSD8X50_SURF + depends on ARCH_QSD8X50 + bool "QSD8x50 SURF" + help + Support for the Qualcomm QSD8x50 SURF eval board. + +config MACH_QSD8X50A_ST1_5 + depends on ARCH_QSD8X50 + select MSM_SOC_REV_A + bool "QSD8x50A ST1.5" + help + Support for the Qualcomm ST1.5. + +endmenu config MSM_DEBUG_UART int @@ -27,17 +100,10 @@ choice bool "UART3" endchoice -config MACH_HALIBUT - depends on ARCH_MSM - default y - bool "Halibut Board (QCT SURF7201A)" - help - Support for the Qualcomm SURF7201A eval board. +config MSM_SMD_PKG3 + bool -config MACH_TROUT - default y - bool "HTC Dream (aka trout)" - help - Support for the HTC Dream, T-Mobile G1, Android ADP1 devices. +config MSM_SMD + bool endif diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 91e6f5c95dc..66677f0acae 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -1,9 +1,22 @@ -obj-y += io.o idle.o irq.o timer.o dma.o -obj-y += devices.o obj-y += proc_comm.o +obj-y += io.o idle.o timer.o dma.o obj-y += vreg.o -obj-y += clock.o clock-7x01a.o +obj-y += acpuclock-arm11.o +obj-y += clock.o clock-pcom.o +obj-y += gpio.o -obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o +ifdef CONFIG_MSM_VIC +obj-y += irq-vic.o +else +obj-y += irq.o +endif + +obj-$(CONFIG_ARCH_QSD8X50) += sirc.o +obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o +obj-$(CONFIG_MSM_SMD) += last_radio_log.o + +obj-$(CONFIG_MACH_TROUT) += board-trout.o devices-msm7x00.o +obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o +obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o +obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o -obj-$(CONFIG_MACH_TROUT) += board-dream.o diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c new file mode 100644 index 00000000000..af5e85b91d0 --- /dev/null +++ b/arch/arm/mach-msm/acpuclock-arm11.c @@ -0,0 +1,526 @@ +/* arch/arm/mach-msm/acpuclock.c + * + * MSM architecture clock driver + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007 QUALCOMM Incorporated + * Author: San Mehat <san@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/version.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/cpufreq.h> +#include <linux/mutex.h> +#include <linux/io.h> +#include <mach/board.h> +#include <mach/msm_iomap.h> + +#include "proc_comm.h" +#include "acpuclock.h" + + +#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) +#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) +#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) + +/* + * ARM11 clock configuration for specific ACPU speeds + */ + +#define ACPU_PLL_TCXO -1 +#define ACPU_PLL_0 0 +#define ACPU_PLL_1 1 +#define ACPU_PLL_2 2 +#define ACPU_PLL_3 3 + +#define PERF_SWITCH_DEBUG 0 +#define PERF_SWITCH_STEP_DEBUG 0 + +struct clock_state +{ + struct clkctl_acpu_speed *current_speed; + struct mutex lock; + uint32_t acpu_switch_time_us; + uint32_t max_speed_delta_khz; + uint32_t vdd_switch_time_us; + unsigned long power_collapse_khz; + unsigned long wait_for_irq_khz; +}; + +static struct clk *ebi1_clk; +static struct clock_state drv_state = { 0 }; + +static void __init acpuclk_init(void); + +/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */ +enum { + VDD_0 = 0, + VDD_1 = 1, + VDD_2 = 2, + VDD_3 = 3, + VDD_4 = 3, + VDD_5 = 3, + VDD_6 = 3, + VDD_7 = 7, + VDD_END +}; + +struct clkctl_acpu_speed { + unsigned int a11clk_khz; + int pll; + unsigned int a11clk_src_sel; + unsigned int a11clk_src_div; + unsigned int ahbclk_khz; + unsigned int ahbclk_div; + int vdd; + unsigned int axiclk_khz; + unsigned long lpj; /* loops_per_jiffy */ +/* Index in acpu_freq_tbl[] for steppings. */ + short down; + short up; +}; + +/* + * ACPU speed table. Complete table is shown but certain speeds are commented + * out to optimized speed switching. Initalize loops_per_jiffy to 0. + * + * Table stepping up/down is optimized for 256mhz jumps while staying on the + * same PLL. + */ +#if (0) +static struct clkctl_acpu_speed acpu_freq_tbl[] = { + { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 }, + { 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 }, + { 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 }, + { 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 }, + { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 }, + { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 }, + { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 }, + { 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 }, + { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 }, + { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 }, + { 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 }, + { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 }, + { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 }, + { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +}; +#else /* Table of freq we currently use. */ +static struct clkctl_acpu_speed acpu_freq_tbl[] = { + { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 }, + { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 }, + { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 }, + { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 }, + { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 }, + { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 }, + { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 }, + { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +}; +#endif + + +#ifdef CONFIG_CPU_FREQ_TABLE +static struct cpufreq_frequency_table freq_table[] = { + { 0, 122880 }, + { 1, 128000 }, + { 2, 245760 }, + { 3, 384000 }, + { 4, 528000 }, + { 5, CPUFREQ_TABLE_END }, +}; +#endif + +static int pc_pll_request(unsigned id, unsigned on) +{ + int res; + on = !!on; + +#if PERF_SWITCH_DEBUG + if (on) + printk(KERN_DEBUG "Enabling PLL %d\n", id); + else + printk(KERN_DEBUG "Disabling PLL %d\n", id); +#endif + + res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on); + if (res < 0) + return res; + +#if PERF_SWITCH_DEBUG + if (on) + printk(KERN_DEBUG "PLL %d enabled\n", id); + else + printk(KERN_DEBUG "PLL %d disabled\n", id); +#endif + return res; +} + + +/*---------------------------------------------------------------------------- + * ARM11 'owned' clock control + *---------------------------------------------------------------------------*/ + +unsigned long acpuclk_power_collapse(void) { + int ret = acpuclk_get_rate(); + ret *= 1000; + if (ret > drv_state.power_collapse_khz) + acpuclk_set_rate(drv_state.power_collapse_khz, 1); + return ret; +} + +unsigned long acpuclk_get_wfi_rate(void) +{ + return drv_state.wait_for_irq_khz; +} + +unsigned long acpuclk_wait_for_irq(void) { + int ret = acpuclk_get_rate(); + ret *= 1000; + if (ret > drv_state.wait_for_irq_khz) + acpuclk_set_rate(drv_state.wait_for_irq_khz, 1); + return ret; +} + +static int acpuclk_set_vdd_level(int vdd) +{ + uint32_t current_vdd; + + current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07; + +#if PERF_SWITCH_DEBUG + printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n", + current_vdd, vdd); +#endif + writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR); + udelay(drv_state.vdd_switch_time_us); + if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) { +#if PERF_SWITCH_DEBUG + printk(KERN_ERR "acpuclock: VDD set failed\n"); +#endif + return -EIO; + } + +#if PERF_SWITCH_DEBUG + printk(KERN_DEBUG "acpuclock: VDD switched\n"); +#endif + return 0; +} + +/* Set proper dividers for the given clock speed. */ +static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { + uint32_t reg_clkctl, reg_clksel, clk_div; + + /* AHB_CLK_DIV */ + clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03; + /* + * If the new clock divider is higher than the previous, then + * program the divider before switching the clock + */ + if (hunt_s->ahbclk_div > clk_div) { + reg_clksel = readl(A11S_CLK_SEL_ADDR); + reg_clksel &= ~(0x3 << 1); + reg_clksel |= (hunt_s->ahbclk_div << 1); + writel(reg_clksel, A11S_CLK_SEL_ADDR); + } + if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) { + /* SRC0 */ + + /* Program clock source */ + reg_clkctl = readl(A11S_CLK_CNTL_ADDR); + reg_clkctl &= ~(0x07 << 4); + reg_clkctl |= (hunt_s->a11clk_src_sel << 4); + writel(reg_clkctl, A11S_CLK_CNTL_ADDR); + + /* Program clock divider */ + reg_clkctl = readl(A11S_CLK_CNTL_ADDR); + reg_clkctl &= ~0xf; + reg_clkctl |= hunt_s->a11clk_src_div; + writel(reg_clkctl, A11S_CLK_CNTL_ADDR); + + /* Program clock source selection */ + reg_clksel = readl(A11S_CLK_SEL_ADDR); + reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */ + writel(reg_clksel, A11S_CLK_SEL_ADDR); + } else { + /* SRC1 */ + + /* Program clock source */ + reg_clkctl = readl(A11S_CLK_CNTL_ADDR); + reg_clkctl &= ~(0x07 << 12); + reg_clkctl |= (hunt_s->a11clk_src_sel << 12); + writel(reg_clkctl, A11S_CLK_CNTL_ADDR); + + /* Program clock divider */ + reg_clkctl = readl(A11S_CLK_CNTL_ADDR); + reg_clkctl &= ~(0xf << 8); + reg_clkctl |= (hunt_s->a11clk_src_div << 8); + writel(reg_clkctl, A11S_CLK_CNTL_ADDR); + + /* Program clock source selection */ + reg_clksel = readl(A11S_CLK_SEL_ADDR); + reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */ + writel(reg_clksel, A11S_CLK_SEL_ADDR); + } + + /* + * If the new clock divider is lower than the previous, then + * program the divider after switching the clock + */ + if (hunt_s->ahbclk_div < clk_div) { + reg_clksel = readl(A11S_CLK_SEL_ADDR); + reg_clksel &= ~(0x3 << 1); + reg_clksel |= (hunt_s->ahbclk_div << 1); + writel(reg_clksel, A11S_CLK_SEL_ADDR); + } +} + +int acpuclk_set_rate(unsigned long rate, int for_power_collapse) +{ + uint32_t reg_clkctl; + struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s; + int rc = 0; + unsigned int plls_enabled = 0, pll; + + strt_s = cur_s = drv_state.current_speed; + + WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n"); + if (cur_s == NULL) + return -ENOENT; + + if (rate == (cur_s->a11clk_khz * 1000)) + return 0; + + for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) { + if (tgt_s->a11clk_khz == (rate / 1000)) + break; + } + + if (tgt_s->a11clk_khz == 0) + return -EINVAL; + + /* Choose the highest speed speed at or below 'rate' with same PLL. */ + if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) { + while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll) + tgt_s--; + } + + if (strt_s->pll != ACPU_PLL_TCXO) + plls_enabled |= 1 << strt_s->pll; + + if (!for_power_collapse) { + mutex_lock(&drv_state.lock); + if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) { + rc = pc_pll_request(tgt_s->pll, 1); + if (rc < 0) { + pr_err("PLL%d enable failed (%d)\n", + tgt_s->pll, rc); + goto out; + } + plls_enabled |= 1 << tgt_s->pll; + } + /* Increase VDD if needed. */ + if (tgt_s->vdd > cur_s->vdd) { + if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) { + printk(KERN_ERR "Unable to switch ACPU vdd\n"); + goto out; + } + } + } + + /* Set wait states for CPU inbetween frequency changes */ + reg_clkctl = readl(A11S_CLK_CNTL_ADDR); + reg_clkctl |= (100 << 16); /* set WT_ST_CNT */ + writel(reg_clkctl, A11S_CLK_CNTL_ADDR); + +#if PERF_SWITCH_DEBUG + printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n", + strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000); +#endif + + while (cur_s != tgt_s) { + /* + * Always jump to target freq if within 256mhz, regulardless of + * PLL. If differnece is greater, use the predefinied + * steppings in the table. + */ + int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz)); + if (d > drv_state.max_speed_delta_khz) { + /* Step up or down depending on target vs current. */ + int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ? + cur_s->up : cur_s->down; + if (clk_index < 0) { /* This should not happen. */ + printk(KERN_ERR "cur:%u target: %u\n", + cur_s->a11clk_khz, tgt_s->a11clk_khz); + rc = -EINVAL; + goto out; + } + cur_s = &acpu_freq_tbl[clk_index]; + } else { + cur_s = tgt_s; + } +#if PERF_SWITCH_STEP_DEBUG + printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n", + __FUNCTION__, cur_s->a11clk_khz, cur_s->pll); +#endif + if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO + && !(plls_enabled & (1 << cur_s->pll))) { + rc = pc_pll_request(cur_s->pll, 1); + if (rc < 0) { + pr_err("PLL%d enable failed (%d)\n", + cur_s->pll, rc); + goto out; + } + plls_enabled |= 1 << cur_s->pll; + } + + acpuclk_set_div(cur_s); + drv_state.current_speed = cur_s; + /* Re-adjust lpj for the new clock speed. */ + loops_per_jiffy = cur_s->lpj; + udelay(drv_state.acpu_switch_time_us); + } + + /* Nothing else to do for power collapse. */ + if (for_power_collapse) + return 0; + + /* Disable PLLs we are not using anymore. */ + plls_enabled &= ~(1 << tgt_s->pll); + for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++) + if (plls_enabled & (1 << pll)) { + rc = pc_pll_request(pll, 0); + if (rc < 0) { + pr_err("PLL%d disable failed (%d)\n", pll, rc); + goto out; + } + } + + /* Change the AXI bus frequency if we can. */ + if (strt_s->axiclk_khz != tgt_s->axiclk_khz) { + rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000); + if (rc < 0) + pr_err("Setting AXI min rate failed!\n"); + } + + /* Drop VDD level if we can. */ + if (tgt_s->vdd < strt_s->vdd) { + if (acpuclk_set_vdd_level(tgt_s->vdd) < 0) + printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n"); + } + +#if PERF_SWITCH_DEBUG + printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__); +#endif +out: + if (!for_power_collapse) + mutex_unlock(&drv_state.lock); + return rc; +} + +static void __init acpuclk_init(void) +{ + struct clkctl_acpu_speed *speed; + uint32_t div, sel; + int rc; + + /* + * Determine the rate of ACPU clock + */ + + if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */ + /* CLK_SRC0_SEL */ + sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7; + /* CLK_SRC0_DIV */ + div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f; + } else { + /* CLK_SRC1_SEL */ + sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07; + /* CLK_SRC1_DIV */ + div = readl(A11S_CLK_CNTL_ADDR) & 0x0f; + } + + for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) { + if (speed->a11clk_src_sel == sel + && (speed->a11clk_src_div == div)) + break; + } + if (speed->a11clk_khz == 0) { + printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n"); + return; + } + + drv_state.current_speed = speed; + + rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000); + if (rc < 0) + pr_err("Setting AXI min rate failed!\n"); + + printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz); +} + +unsigned long acpuclk_get_rate(void) +{ + WARN_ONCE(drv_state.current_speed == NULL, + "acpuclk_get_rate: not initialized\n"); + if (drv_state.current_speed) + return drv_state.current_speed->a11clk_khz; + else + return 0; +} + +uint32_t acpuclk_get_switch_time(void) +{ + return drv_state.acpu_switch_time_us; +} + +/*---------------------------------------------------------------------------- + * Clock driver initialization + *---------------------------------------------------------------------------*/ + +/* Initalize the lpj field in the acpu_freq_tbl. */ +static void __init lpj_init(void) +{ + int i; + const struct clkctl_acpu_speed *base_clk = drv_state.current_speed; + for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) { + acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy, + base_clk->a11clk_khz, + acpu_freq_tbl[i].a11clk_khz); + } +} + +void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata) +{ + pr_info("acpu_clock_init()\n"); + + ebi1_clk = clk_get(NULL, "ebi1_clk"); + + mutex_init(&drv_state.lock); + drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us; + drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz; + drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us; + drv_state.power_collapse_khz = clkdata->power_collapse_khz; + drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz; + acpuclk_init(); + lpj_init(); +#ifdef CONFIG_CPU_FREQ_TABLE + cpufreq_frequency_table_get_attr(freq_table, smp_processor_id()); +#endif +} diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h new file mode 100644 index 00000000000..415de2eb9a5 --- /dev/null +++ b/arch/arm/mach-msm/acpuclock.h @@ -0,0 +1,32 @@ +/* arch/arm/mach-msm/acpuclock.h + * + * MSM architecture clock driver header + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007 QUALCOMM Incorporated + * Author: San Mehat <san@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H +#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H + +int acpuclk_set_rate(unsigned long rate, int for_power_collapse); +unsigned long acpuclk_get_rate(void); +uint32_t acpuclk_get_switch_time(void); +unsigned long acpuclk_wait_for_irq(void); +unsigned long acpuclk_power_collapse(void); +unsigned long acpuclk_get_wfi_rate(void); + + +#endif + diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index e61967dde9a..7bd72e8f127 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c @@ -26,6 +26,7 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> +#include <asm/setup.h> #include <mach/irqs.h> #include <mach/board.h> @@ -77,14 +78,28 @@ static void __init halibut_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); } +static void __init halibut_fixup(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mi->nr_banks=1; + mi->bank[0].start = PHYS_OFFSET; + mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET); + mi->bank[0].size = (101*1024*1024); +} + static void __init halibut_map_io(void) { msm_map_common_io(); - msm_clock_init(); + msm_clock_init(msm_clocks_7x01a, msm_num_clocks_7x01a); } MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif .boot_params = 0x10000100, + .fixup = halibut_fixup, .map_io = halibut_map_io, .init_irq = halibut_init_irq, .init_machine = halibut_init, diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c new file mode 100644 index 00000000000..bcbefdfe7b5 --- /dev/null +++ b/arch/arm/mach-msm/board-mahimahi.c @@ -0,0 +1,87 @@ +/* linux/arch/arm/mach-msm/board-mahimahi.c + * + * Copyright (C) 2009 Google, Inc. + * Copyright (C) 2009 HTC Corporation. + * Author: Dima Zavin <dima@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/input.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/setup.h> + +#include <mach/board.h> +#include <mach/hardware.h> +#include <mach/system.h> + +#include "board-mahimahi.h" +#include "devices.h" +#include "proc_comm.h" + +static uint debug_uart; + +module_param_named(debug_uart, debug_uart, uint, 0); + +static struct platform_device *devices[] __initdata = { +#if !defined(CONFIG_MSM_SERIAL_DEBUGGER) + &msm_device_uart1, +#endif + &msm_device_uart_dm1, + &msm_device_nand, +}; + +static void __init mahimahi_init(void) +{ + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static void __init mahimahi_fixup(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mi->nr_banks = 2; + mi->bank[0].start = PHYS_OFFSET; + mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET); + mi->bank[0].size = (219*1024*1024); + mi->bank[1].start = MSM_HIGHMEM_BASE; + mi->bank[1].node = PHYS_TO_NID(MSM_HIGHMEM_BASE); + mi->bank[1].size = MSM_HIGHMEM_SIZE; +} + +static void __init mahimahi_map_io(void) +{ + msm_map_common_io(); + msm_clock_init(); +} + +extern struct sys_timer msm_timer; + +MACHINE_START(MAHIMAHI, "mahimahi") +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif + .boot_params = 0x20000100, + .fixup = mahimahi_fixup, + .map_io = mahimahi_map_io, + .init_irq = msm_init_irq, + .init_machine = mahimahi_init, + .timer = &msm_timer, +MACHINE_END diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c new file mode 100644 index 00000000000..cccb9f3c9d0 --- /dev/null +++ b/arch/arm/mach-msm/board-msm7x27.c @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/input.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/bootmem.h> +#include <linux/power_supply.h> + +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> +#include <asm/setup.h> +#ifdef CONFIG_CACHE_L2X0 +#include <asm/hardware/cache-l2x0.h> +#endif + +#include <mach/vreg.h> +#include <mach/mpp.h> +#include <mach/gpio.h> +#include <mach/board.h> +#include <mach/msm_iomap.h> + +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> + +#include "devices.h" +#include "socinfo.h" +#include "clock.h" + +static struct resource smc91x_resources[] = { + [0] = { + .start = 0x9C004300, + .end = 0x9C0043ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSM_GPIO_TO_INT(132), + .end = MSM_GPIO_TO_INT(132), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct platform_device *devices[] __initdata = { + &msm_device_uart3, + &msm_device_smd, + &msm_device_dmov, + &msm_device_nand, + &smc91x_device, +}; + +extern struct sys_timer msm_timer; + +static void __init msm7x2x_init_irq(void) +{ + msm_init_irq(); +} + +static void __init msm7x2x_init(void) +{ + if (socinfo_init() < 0) + BUG(); + + if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) { + smc91x_resources[0].start = 0x98000300; + smc91x_resources[0].end = 0x980003ff; + smc91x_resources[1].start = MSM_GPIO_TO_INT(85); + smc91x_resources[1].end = MSM_GPIO_TO_INT(85); + if (gpio_tlmm_config(GPIO_CFG(85, 0, + GPIO_INPUT, + GPIO_PULL_DOWN, + GPIO_2MA), + GPIO_ENABLE)) { + printk(KERN_ERR + "%s: Err: Config GPIO-85 INT\n", + __func__); + } + } + + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static void __init msm7x2x_map_io(void) +{ + msm_map_common_io(); + /* Technically dependent on the SoC but using machine_is + * macros since socinfo is not available this early and there + * are plans to restructure the code which will eliminate the + * need for socinfo. + */ + if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) + msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27); + + if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa()) + msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25); + +#ifdef CONFIG_CACHE_L2X0 + if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) { + /* 7x27 has 256KB L2 cache: + 64Kb/Way and 4-Way Associativity; + R/W latency: 3 cycles; + evmon/parity/share disabled. */ + l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000); + } +#endif +} + +MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .map_io = msm7x2x_map_io, + .init_irq = msm7x2x_init_irq, + .init_machine = msm7x2x_init, + .timer = &msm_timer, +MACHINE_END + +MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .map_io = msm7x2x_map_io, + .init_irq = msm7x2x_init_irq, + .init_machine = msm7x2x_init, + .timer = &msm_timer, +MACHINE_END + +MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .map_io = msm7x2x_map_io, + .init_irq = msm7x2x_init_irq, + .init_machine = msm7x2x_init, + .timer = &msm_timer, +MACHINE_END + +MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .map_io = msm7x2x_map_io, + .init_irq = msm7x2x_init_irq, + .init_machine = msm7x2x_init, + .timer = &msm_timer, +MACHINE_END diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c new file mode 100644 index 00000000000..bac1f3c38a3 --- /dev/null +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -0,0 +1,120 @@ +/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/bootmem.h> +#include <linux/io.h> +#include <linux/smsc911x.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/setup.h> + +#include <mach/gpio.h> +#include <mach/board.h> +#include <mach/memory.h> +#include <mach/msm_iomap.h> +#include <mach/dma.h> + +#include <mach/vreg.h> +#include "devices.h" +#include "proc_comm.h" + +extern struct sys_timer msm_timer; + +#ifdef CONFIG_SERIAL_MSM_CONSOLE +static struct msm_gpio uart2_config_data[] = { + { GPIO_CFG(49, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_RFR"}, + { GPIO_CFG(50, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_CTS"}, + { GPIO_CFG(51, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"}, + { GPIO_CFG(52, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"}, +}; + +static void msm7x30_init_uart2(void) +{ + msm_gpios_request_enable(uart2_config_data, + ARRAY_SIZE(uart2_config_data)); + +} +#endif + +static struct platform_device *devices[] __initdata = { +#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) + &msm_device_uart2, +#endif + +}; + +static void __init msm7x30_init_irq(void) +{ + msm_init_irq(); +} + +static void __init msm7x30_init(void) +{ + platform_add_devices(devices, ARRAY_SIZE(devices)); +#ifdef CONFIG_SERIAL_MSM_CONSOLE + msm7x30_init_uart2(); +#endif + +} + +static void __init msm7x30_map_io(void) +{ + msm_map_msm7x30_io(); + msm_clock_init(msm_clocks_7x30, msm_num_clocks_7x30); +} + +MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .map_io = msm7x30_map_io, + .init_irq = msm7x30_init_irq, + .init_machine = msm7x30_init, + .timer = &msm_timer, +MACHINE_END + +MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .map_io = msm7x30_map_io, + .init_irq = msm7x30_init_irq, + .init_machine = msm7x30_init, + .timer = &msm_timer, +MACHINE_END + +MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .map_io = msm7x30_map_io, + .init_irq = msm7x30_init_irq, + .init_machine = msm7x30_init, + .timer = &msm_timer, +MACHINE_END diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c new file mode 100644 index 00000000000..ec4606643d2 --- /dev/null +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -0,0 +1,94 @@ +/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/bootmem.h> +#include <linux/delay.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/io.h> +#include <asm/setup.h> + +#include <mach/board.h> +#include <mach/irqs.h> +#include <mach/sirc.h> +#include <mach/gpio.h> + +#include "devices.h" + +extern struct sys_timer msm_timer; + +static struct msm_gpio uart3_config_data[] = { + { GPIO_CFG(86, 1, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"}, + { GPIO_CFG(87, 1, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"}, +}; + +static struct platform_device *devices[] __initdata = { + &msm_device_uart3, +}; + +static void msm8x50_init_uart3(void) +{ + msm_gpios_request_enable(uart3_config_data, + ARRAY_SIZE(uart3_config_data)); +} + +static void __init qsd8x50_map_io(void) +{ + msm_map_qsd8x50_io(); + msm_clock_init(msm_clocks_8x50, msm_num_clocks_8x50); +} + +static void __init qsd8x50_init_irq(void) +{ + msm_init_irq(); + msm_init_sirc(); +} + +static void __init qsd8x50_init(void) +{ + msm8x50_init_uart3(); + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .map_io = qsd8x50_map_io, + .init_irq = qsd8x50_init_irq, + .init_machine = qsd8x50_init, + .timer = &msm_timer, +MACHINE_END + +MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .map_io = qsd8x50_map_io, + .init_irq = qsd8x50_init_irq, + .init_machine = qsd8x50_init, + .timer = &msm_timer, +MACHINE_END diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c new file mode 100644 index 00000000000..2bc1b9d5623 --- /dev/null +++ b/arch/arm/mach-msm/board-sapphire.c @@ -0,0 +1,118 @@ +/* linux/arch/arm/mach-msm/board-sapphire.c + * Copyright (C) 2007-2009 HTC Corporation. + * Author: Thomas Tsai <thomas_tsai@htc.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/input.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/sysdev.h> + +#include <linux/delay.h> + +#include <asm/gpio.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> +#include <asm/system.h> +#include <mach/system.h> +#include <mach/vreg.h> +#include <mach/board.h> + +#include <asm/io.h> +#include <asm/delay.h> +#include <asm/setup.h> + +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> + +#include "gpio_chip.h" +#include "board-sapphire.h" +#include "proc_comm.h" +#include "devices.h" + +void msm_init_irq(void); +void msm_init_gpio(void); + +static struct platform_device *devices[] __initdata = { + &msm_device_smd, + &msm_device_dmov, + &msm_device_nand, + &msm_device_uart1, + &msm_device_uart3, +}; + +extern struct sys_timer msm_timer; + +static void __init sapphire_init_irq(void) +{ + msm_init_irq(); +} + +static void __init sapphire_init(void) +{ + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static struct map_desc sapphire_io_desc[] __initdata = { + { + .virtual = SAPPHIRE_CPLD_BASE, + .pfn = __phys_to_pfn(SAPPHIRE_CPLD_START), + .length = SAPPHIRE_CPLD_SIZE, + .type = MT_DEVICE_NONSHARED + } +}; + +static void __init sapphire_fixup(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + int smi_sz = parse_tag_smi((const struct tag *)tags); + + mi->nr_banks = 1; + mi->bank[0].start = PHYS_OFFSET; + mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET); + if (smi_sz == 32) { + mi->bank[0].size = (84*1024*1024); + } else if (smi_sz == 64) { + mi->bank[0].size = (101*1024*1024); + } else { + /* Give a default value when not get smi size */ + smi_sz = 64; + mi->bank[0].size = (101*1024*1024); + } +} + +static void __init sapphire_map_io(void) +{ + msm_map_common_io(); + iotable_init(sapphire_io_desc, ARRAY_SIZE(sapphire_io_desc)); + msm_clock_init(); +} + +MACHINE_START(SAPPHIRE, "sapphire") +/* Maintainer: Brian Swetland <swetland@google.com> */ +#ifdef CONFIG_MSM_DEBUG_UART + .phys_io = MSM_DEBUG_UART_PHYS, + .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .fixup = sapphire_fixup, + .map_io = sapphire_map_io, + .init_irq = sapphire_init_irq, + .init_machine = sapphire_init, + .timer = &msm_timer, +MACHINE_END diff --git a/arch/arm/mach-msm/board-dream.c b/arch/arm/mach-msm/board-trout.c index 21afa851316..dca5a5f062d 100644 --- a/arch/arm/mach-msm/board-dream.c +++ b/arch/arm/mach-msm/board-trout.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-msm/board-dream.c +/* linux/arch/arm/mach-msm/board-trout.c * * Copyright (C) 2009 Google, Inc. * Author: Brian Swetland <swetland@google.com> @@ -28,7 +28,7 @@ #include <mach/msm_iomap.h> #include "devices.h" -#include "board-dream.h" +#include "board-trout.h" static struct platform_device *devices[] __initdata = { &msm_device_uart3, @@ -78,12 +78,14 @@ static void __init trout_map_io(void) writeb(0x80, TROUT_CPLD_BASE + 0x00); #endif - msm_clock_init(); + msm_clock_init(msm_clocks_7x01a, msm_num_clocks_7x01a); } MACHINE_START(TROUT, "HTC Dream") +#ifdef CONFIG_MSM_DEBUG_UART .phys_io = MSM_DEBUG_UART_PHYS, .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc, +#endif .boot_params = 0x10000100, .fixup = trout_fixup, .map_io = trout_map_io, diff --git a/arch/arm/mach-msm/board-dream.h b/arch/arm/mach-msm/board-trout.h index 4f345a5a0a6..4f345a5a0a6 100644 --- a/arch/arm/mach-msm/board-dream.h +++ b/arch/arm/mach-msm/board-trout.h diff --git a/arch/arm/mach-msm/clock-7x01a.c b/arch/arm/mach-msm/clock-7x01a.c deleted file mode 100644 index 62230a3428e..00000000000 --- a/arch/arm/mach-msm/clock-7x01a.c +++ /dev/null @@ -1,126 +0,0 @@ -/* arch/arm/mach-msm/clock-7x01a.c - * - * Clock tables for MSM7X01A - * - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2007 QUALCOMM Incorporated - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include "clock.h" -#include "devices.h" - -/* clock IDs used by the modem processor */ - -#define ACPU_CLK 0 /* Applications processor clock */ -#define ADM_CLK 1 /* Applications data mover clock */ -#define ADSP_CLK 2 /* ADSP clock */ -#define EBI1_CLK 3 /* External bus interface 1 clock */ -#define EBI2_CLK 4 /* External bus interface 2 clock */ -#define ECODEC_CLK 5 /* External CODEC clock */ -#define EMDH_CLK 6 /* External MDDI host clock */ -#define GP_CLK 7 /* General purpose clock */ -#define GRP_CLK 8 /* Graphics clock */ -#define I2C_CLK 9 /* I2C clock */ -#define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */ -#define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */ -#define IMEM_CLK 12 /* Internal graphics memory clock */ -#define MDC_CLK 13 /* MDDI client clock */ -#define MDP_CLK 14 /* Mobile display processor clock */ -#define PBUS_CLK 15 /* Peripheral bus clock */ -#define PCM_CLK 16 /* PCM clock */ -#define PMDH_CLK 17 /* Primary MDDI host clock */ -#define SDAC_CLK 18 /* Stereo DAC clock */ -#define SDC1_CLK 19 /* Secure Digital Card clocks */ -#define SDC1_PCLK 20 -#define SDC2_CLK 21 -#define SDC2_PCLK 22 -#define SDC3_CLK 23 -#define SDC3_PCLK 24 -#define SDC4_CLK 25 -#define SDC4_PCLK 26 -#define TSIF_CLK 27 /* Transport Stream Interface clocks */ -#define TSIF_REF_CLK 28 -#define TV_DAC_CLK 29 /* TV clocks */ -#define TV_ENC_CLK 30 -#define UART1_CLK 31 /* UART clocks */ -#define UART2_CLK 32 -#define UART3_CLK 33 -#define UART1DM_CLK 34 -#define UART2DM_CLK 35 -#define USB_HS_CLK 36 /* High speed USB core clock */ -#define USB_HS_PCLK 37 /* High speed USB pbus clock */ -#define USB_OTG_CLK 38 /* Full speed USB clock */ -#define VDC_CLK 39 /* Video controller clock */ -#define VFE_CLK 40 /* Camera / Video Front End clock */ -#define VFE_MDC_CLK 41 /* VFE MDDI client clock */ - -#define NR_CLKS 42 - -#define CLOCK(clk_name, clk_id, clk_dev, clk_flags) { \ - .name = clk_name, \ - .id = clk_id, \ - .flags = clk_flags, \ - .dev = clk_dev, \ - } - -#define OFF CLKFLAG_AUTO_OFF -#define MINMAX CLKFLAG_USE_MIN_MAX_TO_SET - -struct clk msm_clocks[] = { - CLOCK("adm_clk", ADM_CLK, NULL, 0), - CLOCK("adsp_clk", ADSP_CLK, NULL, 0), - CLOCK("ebi1_clk", EBI1_CLK, NULL, 0), - CLOCK("ebi2_clk", EBI2_CLK, NULL, 0), - CLOCK("ecodec_clk", ECODEC_CLK, NULL, 0), - CLOCK("emdh_clk", EMDH_CLK, NULL, OFF), - CLOCK("gp_clk", GP_CLK, NULL, 0), - CLOCK("grp_clk", GRP_CLK, NULL, OFF), - CLOCK("i2c_clk", I2C_CLK, &msm_device_i2c.dev, 0), - CLOCK("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), - CLOCK("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), - CLOCK("imem_clk", IMEM_CLK, NULL, OFF), - CLOCK("mdc_clk", MDC_CLK, NULL, 0), - CLOCK("mdp_clk", MDP_CLK, NULL, OFF), - CLOCK("pbus_clk", PBUS_CLK, NULL, 0), - CLOCK("pcm_clk", PCM_CLK, NULL, 0), - CLOCK("pmdh_clk", PMDH_CLK, NULL, OFF | MINMAX), - CLOCK("sdac_clk", SDAC_CLK, NULL, OFF), - CLOCK("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), - CLOCK("sdc_pclk", SDC1_PCLK, &msm_device_sdc1.dev, OFF), - CLOCK("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF), - CLOCK("sdc_pclk", SDC2_PCLK, &msm_device_sdc2.dev, OFF), - CLOCK("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF), - CLOCK("sdc_pclk", SDC3_PCLK, &msm_device_sdc3.dev, OFF), - CLOCK("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF), - CLOCK("sdc_pclk", SDC4_PCLK, &msm_device_sdc4.dev, OFF), - CLOCK("tsif_clk", TSIF_CLK, NULL, 0), - CLOCK("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), - CLOCK("tv_dac_clk", TV_DAC_CLK, NULL, 0), - CLOCK("tv_enc_clk", TV_ENC_CLK, NULL, 0), - CLOCK("uart_clk", UART1_CLK, &msm_device_uart1.dev, OFF), - CLOCK("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), - CLOCK("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF), - CLOCK("uart1dm_clk", UART1DM_CLK, NULL, OFF), - CLOCK("uart2dm_clk", UART2DM_CLK, NULL, 0), - CLOCK("usb_hs_clk", USB_HS_CLK, &msm_device_hsusb.dev, OFF), - CLOCK("usb_hs_pclk", USB_HS_PCLK, &msm_device_hsusb.dev, OFF), - CLOCK("usb_otg_clk", USB_OTG_CLK, NULL, 0), - CLOCK("vdc_clk", VDC_CLK, NULL, OFF | MINMAX), - CLOCK("vfe_clk", VFE_CLK, NULL, OFF), - CLOCK("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF), -}; - -unsigned msm_num_clocks = ARRAY_SIZE(msm_clocks); diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h new file mode 100644 index 00000000000..e16f72f3282 --- /dev/null +++ b/arch/arm/mach-msm/clock-7x30.h @@ -0,0 +1,168 @@ +/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H +#define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H + +enum { + L_7X30_NONE_CLK = -1, + L_7X30_ADM_CLK, + L_7X30_I2C_CLK, + L_7X30_I2C_2_CLK, + L_7X30_QUP_I2C_CLK, + L_7X30_UART1DM_CLK, + L_7X30_UART1DM_P_CLK, + L_7X30_UART2DM_CLK, + L_7X30_UART2DM_P_CLK, + L_7X30_EMDH_CLK, + L_7X30_EMDH_P_CLK, + L_7X30_PMDH_CLK, + L_7X30_PMDH_P_CLK, + L_7X30_GRP_2D_CLK, + L_7X30_GRP_2D_P_CLK, + L_7X30_GRP_3D_SRC_CLK, + L_7X30_GRP_3D_CLK, + L_7X30_GRP_3D_P_CLK, + L_7X30_IMEM_CLK, + L_7X30_SDC1_CLK, + L_7X30_SDC1_P_CLK, + L_7X30_SDC2_CLK, + L_7X30_SDC2_P_CLK, + L_7X30_SDC3_CLK, + L_7X30_SDC3_P_CLK, + L_7X30_SDC4_CLK, + L_7X30_SDC4_P_CLK, + L_7X30_MDP_CLK, + L_7X30_MDP_P_CLK, + L_7X30_MDP_LCDC_PCLK_CLK, + L_7X30_MDP_LCDC_PAD_PCLK_CLK, + L_7X30_MDP_VSYNC_CLK, + L_7X30_MI2S_CODEC_RX_M_CLK, + L_7X30_MI2S_CODEC_RX_S_CLK, + L_7X30_MI2S_CODEC_TX_M_CLK, + L_7X30_MI2S_CODEC_TX_S_CLK, + L_7X30_MI2S_M_CLK, + L_7X30_MI2S_S_CLK, + L_7X30_LPA_CODEC_CLK, + L_7X30_LPA_CORE_CLK, + L_7X30_LPA_P_CLK, + L_7X30_MIDI_CLK, + L_7X30_MDC_CLK, + L_7X30_ROTATOR_IMEM_CLK, + L_7X30_ROTATOR_P_CLK, + L_7X30_SDAC_M_CLK, + L_7X30_SDAC_CLK, + L_7X30_UART1_CLK, + L_7X30_UART2_CLK, + L_7X30_UART3_CLK, + L_7X30_TV_CLK, + L_7X30_TV_DAC_CLK, + L_7X30_TV_ENC_CLK, + L_7X30_HDMI_CLK, + L_7X30_TSIF_REF_CLK, + L_7X30_TSIF_P_CLK, + L_7X30_USB_HS_SRC_CLK, + L_7X30_USB_HS_CLK, + L_7X30_USB_HS_CORE_CLK, + L_7X30_USB_HS_P_CLK, + L_7X30_USB_HS2_CLK, + L_7X30_USB_HS2_CORE_CLK, + L_7X30_USB_HS2_P_CLK, + L_7X30_USB_HS3_CLK, + L_7X30_USB_HS3_CORE_CLK, + L_7X30_USB_HS3_P_CLK, + L_7X30_VFE_CLK, + L_7X30_VFE_P_CLK, + L_7X30_VFE_MDC_CLK, + L_7X30_VFE_CAMIF_CLK, + L_7X30_CAMIF_PAD_P_CLK, + L_7X30_CAM_M_CLK, + L_7X30_JPEG_CLK, + L_7X30_JPEG_P_CLK, + L_7X30_VPE_CLK, + L_7X30_MFC_CLK, + L_7X30_MFC_DIV2_CLK, + L_7X30_MFC_P_CLK, + L_7X30_SPI_CLK, + L_7X30_SPI_P_CLK, + L_7X30_CSI0_CLK, + L_7X30_CSI0_VFE_CLK, + L_7X30_CSI0_P_CLK, + L_7X30_CSI1_CLK, + L_7X30_CSI1_VFE_CLK, + L_7X30_CSI1_P_CLK, + L_7X30_GLBL_ROOT_CLK, + + L_7X30_AXI_LI_VG_CLK, + L_7X30_AXI_LI_GRP_CLK, + L_7X30_AXI_LI_JPEG_CLK, + L_7X30_AXI_GRP_2D_CLK, + L_7X30_AXI_MFC_CLK, + L_7X30_AXI_VPE_CLK, + L_7X30_AXI_LI_VFE_CLK, + L_7X30_AXI_LI_APPS_CLK, + L_7X30_AXI_MDP_CLK, + L_7X30_AXI_IMEM_CLK, + L_7X30_AXI_LI_ADSP_A_CLK, + L_7X30_AXI_ROTATOR_CLK, + + L_7X30_NR_CLKS +}; + +struct clk_ops; +extern struct clk_ops clk_ops_7x30; + +struct clk_ops *clk_7x30_is_local(uint32_t id); +int clk_7x30_init(void); + +void pll_enable(uint32_t pll); +void pll_disable(uint32_t pll); + +extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable); + +#define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) { \ + .name = clk_name, \ + .id = L_7X30_##clk_id, \ + .remote_id = P_##clk_id, \ + .flags = clk_flags, \ + .dev = clk_dev, \ + .dbg_name = #clk_id, \ + } + +#define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) { \ + .name = clk_name, \ + .id = L_7X30_##l_id, \ + .remote_id = P_##r_id, \ + .flags = clk_flags, \ + .dev = clk_dev, \ + .dbg_name = #l_id, \ + } + +#endif + diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c new file mode 100644 index 00000000000..a3b45627eb4 --- /dev/null +++ b/arch/arm/mach-msm/clock-pcom.c @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/err.h> +#include <linux/ctype.h> +#include <linux/stddef.h> +#include <mach/clk.h> + +#include "proc_comm.h" +#include "clock.h" + +/* + * glue for the proc_comm interface + */ +int pc_clk_enable(unsigned id) +{ + int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL); + if (rc < 0) + return rc; + else + return (int)id < 0 ? -EINVAL : 0; +} + +void pc_clk_disable(unsigned id) +{ + msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL); +} + +int pc_clk_reset(unsigned id, enum clk_reset_action action) +{ + int rc; + + if (action == CLK_RESET_ASSERT) + rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL); + else + rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_DEASSERT, &id, NULL); + + if (rc < 0) + return rc; + else + return (int)id < 0 ? -EINVAL : 0; +} + +int pc_clk_set_rate(unsigned id, unsigned rate) +{ + /* The rate _might_ be rounded off to the nearest KHz value by the + * remote function. So a return value of 0 doesn't necessarily mean + * that the exact rate was set successfully. + */ + int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate); + if (rc < 0) + return rc; + else + return (int)id < 0 ? -EINVAL : 0; +} + +int pc_clk_set_min_rate(unsigned id, unsigned rate) +{ + int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate); + if (rc < 0) + return rc; + else + return (int)id < 0 ? -EINVAL : 0; +} + +int pc_clk_set_max_rate(unsigned id, unsigned rate) +{ + int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate); + if (rc < 0) + return rc; + else + return (int)id < 0 ? -EINVAL : 0; +} + +int pc_clk_set_flags(unsigned id, unsigned flags) +{ + int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags); + if (rc < 0) + return rc; + else + return (int)id < 0 ? -EINVAL : 0; +} + +unsigned pc_clk_get_rate(unsigned id) +{ + if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL)) + return 0; + else + return id; +} + +unsigned pc_clk_is_enabled(unsigned id) +{ + if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL)) + return 0; + else + return id; +} + +long pc_clk_round_rate(unsigned id, unsigned rate) +{ + + /* Not really supported; pc_clk_set_rate() does rounding on it's own. */ + return rate; +} + +struct clk_ops clk_ops_pcom = { + .enable = pc_clk_enable, + .disable = pc_clk_disable, + .auto_off = pc_clk_disable, + .reset = pc_clk_reset, + .set_rate = pc_clk_set_rate, + .set_min_rate = pc_clk_set_min_rate, + .set_max_rate = pc_clk_set_max_rate, + .set_flags = pc_clk_set_flags, + .get_rate = pc_clk_get_rate, + .is_enabled = pc_clk_is_enabled, + .round_rate = pc_clk_round_rate, +}; diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h new file mode 100644 index 00000000000..17d027b2350 --- /dev/null +++ b/arch/arm/mach-msm/clock-pcom.h @@ -0,0 +1,153 @@ +/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H +#define __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H + +/* clock IDs used by the modem processor */ + +#define P_ACPU_CLK 0 /* Applications processor clock */ +#define P_ADM_CLK 1 /* Applications data mover clock */ +#define P_ADSP_CLK 2 /* ADSP clock */ +#define P_EBI1_CLK 3 /* External bus interface 1 clock */ +#define P_EBI2_CLK 4 /* External bus interface 2 clock */ +#define P_ECODEC_CLK 5 /* External CODEC clock */ +#define P_EMDH_CLK 6 /* External MDDI host clock */ +#define P_GP_CLK 7 /* General purpose clock */ +#define P_GRP_3D_CLK 8 /* Graphics clock */ +#define P_I2C_CLK 9 /* I2C clock */ +#define P_ICODEC_RX_CLK 10 /* Internal CODEX RX clock */ +#define P_ICODEC_TX_CLK 11 /* Internal CODEX TX clock */ +#define P_IMEM_CLK 12 /* Internal graphics memory clock */ +#define P_MDC_CLK 13 /* MDDI client clock */ +#define P_MDP_CLK 14 /* Mobile display processor clock */ +#define P_PBUS_CLK 15 /* Peripheral bus clock */ +#define P_PCM_CLK 16 /* PCM clock */ +#define P_PMDH_CLK 17 /* Primary MDDI host clock */ +#define P_SDAC_CLK 18 /* Stereo DAC clock */ +#define P_SDC1_CLK 19 /* Secure Digital Card clocks */ +#define P_SDC1_P_CLK 20 +#define P_SDC2_CLK 21 +#define P_SDC2_P_CLK 22 +#define P_SDC3_CLK 23 +#define P_SDC3_P_CLK 24 +#define P_SDC4_CLK 25 +#define P_SDC4_P_CLK 26 +#define P_TSIF_CLK 27 /* Transport Stream Interface clocks */ +#define P_TSIF_REF_CLK 28 +#define P_TV_DAC_CLK 29 /* TV clocks */ +#define P_TV_ENC_CLK 30 +#define P_UART1_CLK 31 /* UART clocks */ +#define P_UART2_CLK 32 +#define P_UART3_CLK 33 +#define P_UART1DM_CLK 34 +#define P_UART2DM_CLK 35 +#define P_USB_HS_CLK 36 /* High speed USB core clock */ +#define P_USB_HS_P_CLK 37 /* High speed USB pbus clock */ +#define P_USB_OTG_CLK 38 /* Full speed USB clock */ +#define P_VDC_CLK 39 /* Video controller clock */ +#define P_VFE_MDC_CLK 40 /* Camera / Video Front End clock */ +#define P_VFE_CLK 41 /* VFE MDDI client clock */ +#define P_MDP_LCDC_PCLK_CLK 42 +#define P_MDP_LCDC_PAD_PCLK_CLK 43 +#define P_MDP_VSYNC_CLK 44 +#define P_SPI_CLK 45 +#define P_VFE_AXI_CLK 46 +#define P_USB_HS2_CLK 47 /* High speed USB 2 core clock */ +#define P_USB_HS2_P_CLK 48 /* High speed USB 2 pbus clock */ +#define P_USB_HS3_CLK 49 /* High speed USB 3 core clock */ +#define P_USB_HS3_P_CLK 50 /* High speed USB 3 pbus clock */ +#define P_GRP_3D_P_CLK 51 /* Graphics pbus clock */ +#define P_USB_PHY_CLK 52 /* USB PHY clock */ +#define P_USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */ +#define P_USB_HS2_CORE_CLK 54 /* High speed USB 2 core clock */ +#define P_USB_HS3_CORE_CLK 55 /* High speed USB 3 core clock */ +#define P_CAM_M_CLK 56 +#define P_CAMIF_PAD_P_CLK 57 +#define P_GRP_2D_CLK 58 +#define P_GRP_2D_P_CLK 59 +#define P_I2S_CLK 60 +#define P_JPEG_CLK 61 +#define P_JPEG_P_CLK 62 +#define P_LPA_CODEC_CLK 63 +#define P_LPA_CORE_CLK 64 +#define P_LPA_P_CLK 65 +#define P_MDC_IO_CLK 66 +#define P_MDC_P_CLK 67 +#define P_MFC_CLK 68 +#define P_MFC_DIV2_CLK 69 +#define P_MFC_P_CLK 70 +#define P_QUP_I2C_CLK 71 +#define P_ROTATOR_IMEM_CLK 72 +#define P_ROTATOR_P_CLK 73 +#define P_VFE_CAMIF_CLK 74 +#define P_VFE_P_CLK 75 +#define P_VPE_CLK 76 +#define P_I2C_2_CLK 77 +#define P_MI2S_CODEC_RX_S_CLK 78 +#define P_MI2S_CODEC_RX_M_CLK 79 +#define P_MI2S_CODEC_TX_S_CLK 80 +#define P_MI2S_CODEC_TX_M_CLK 81 +#define P_PMDH_P_CLK 82 +#define P_EMDH_P_CLK 83 +#define P_SPI_P_CLK 84 +#define P_TSIF_P_CLK 85 +#define P_MDP_P_CLK 86 +#define P_SDAC_M_CLK 87 +#define P_MI2S_S_CLK 88 +#define P_MI2S_M_CLK 89 +#define P_AXI_ROTATOR_CLK 90 +#define P_HDMI_CLK 91 +#define P_CSI0_CLK 92 +#define P_CSI0_VFE_CLK 93 +#define P_CSI0_P_CLK 94 +#define P_CSI1_CLK 95 +#define P_CSI1_VFE_CLK 96 +#define P_CSI1_P_CLK 97 +#define P_GSBI_CLK 98 +#define P_GSBI_P_CLK 99 + +#define P_NR_CLKS 100 + +struct clk_ops; +extern struct clk_ops clk_ops_pcom; + +int pc_clk_reset(unsigned id, enum clk_reset_action action); + +#define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \ + .name = clk_name, \ + .id = P_##clk_id, \ + .remote_id = P_##clk_id, \ + .ops = &clk_ops_pcom, \ + .flags = clk_flags, \ + .dev = clk_dev, \ + .dbg_name = #clk_id, \ + } + +#endif diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index 3b1ce36f103..9cb1276ab74 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c @@ -1,7 +1,7 @@ /* arch/arm/mach-msm/clock.c * * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2007 QUALCOMM Incorporated + * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -22,68 +22,27 @@ #include <linux/err.h> #include <linux/clk.h> #include <linux/spinlock.h> +#include <linux/debugfs.h> +#include <linux/ctype.h> +#include <linux/pm_qos_params.h> +#include <mach/clk.h> #include "clock.h" #include "proc_comm.h" +#include "clock-7x30.h" static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clocks_lock); static LIST_HEAD(clocks); +struct clk *msm_clocks; +unsigned msm_num_clocks; /* - * glue for the proc_comm interface + * Bitmap of enabled clocks, excluding ACPU which is always + * enabled */ -static inline int pc_clk_enable(unsigned id) -{ - return msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL); -} - -static inline void pc_clk_disable(unsigned id) -{ - msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL); -} - -static inline int pc_clk_set_rate(unsigned id, unsigned rate) -{ - return msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate); -} - -static inline int pc_clk_set_min_rate(unsigned id, unsigned rate) -{ - return msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate); -} - -static inline int pc_clk_set_max_rate(unsigned id, unsigned rate) -{ - return msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate); -} - -static inline int pc_clk_set_flags(unsigned id, unsigned flags) -{ - return msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags); -} - -static inline unsigned pc_clk_get_rate(unsigned id) -{ - if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL)) - return 0; - else - return id; -} - -static inline unsigned pc_clk_is_enabled(unsigned id) -{ - if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL)) - return 0; - else - return id; -} - -static inline int pc_pll_request(unsigned id, unsigned on) -{ - on = !!on; - return msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on); -} +static DECLARE_BITMAP(clock_map_enabled, NR_CLKS); +static DEFINE_SPINLOCK(clock_map_lock); /* * Standard clock functions defined in include/linux/clk.h @@ -119,8 +78,12 @@ int clk_enable(struct clk *clk) unsigned long flags; spin_lock_irqsave(&clocks_lock, flags); clk->count++; - if (clk->count == 1) - pc_clk_enable(clk->id); + if (clk->count == 1) { + clk->ops->enable(clk->id); + spin_lock(&clock_map_lock); + clock_map_enabled[BIT_WORD(clk->id)] |= BIT_MASK(clk->id); + spin_unlock(&clock_map_lock); + } spin_unlock_irqrestore(&clocks_lock, flags); return 0; } @@ -132,31 +95,54 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clocks_lock, flags); BUG_ON(clk->count == 0); clk->count--; - if (clk->count == 0) - pc_clk_disable(clk->id); + if (clk->count == 0) { + clk->ops->disable(clk->id); + spin_lock(&clock_map_lock); + clock_map_enabled[BIT_WORD(clk->id)] &= ~BIT_MASK(clk->id); + spin_unlock(&clock_map_lock); + } spin_unlock_irqrestore(&clocks_lock, flags); } EXPORT_SYMBOL(clk_disable); +int clk_reset(struct clk *clk, enum clk_reset_action action) +{ + if (!clk->ops->reset) + clk->ops->reset = &pc_clk_reset; + return clk->ops->reset(clk->remote_id, action); +} +EXPORT_SYMBOL(clk_reset); + unsigned long clk_get_rate(struct clk *clk) { - return pc_clk_get_rate(clk->id); + return clk->ops->get_rate(clk->id); } EXPORT_SYMBOL(clk_get_rate); int clk_set_rate(struct clk *clk, unsigned long rate) { - int ret; - if (clk->flags & CLKFLAG_USE_MIN_MAX_TO_SET) { - ret = pc_clk_set_max_rate(clk->id, rate); - if (ret) - return ret; - return pc_clk_set_min_rate(clk->id, rate); - } - return pc_clk_set_rate(clk->id, rate); + return clk->ops->set_rate(clk->id, rate); } EXPORT_SYMBOL(clk_set_rate); +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + return clk->ops->round_rate(clk->id, rate); +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_min_rate(struct clk *clk, unsigned long rate) +{ + return clk->ops->set_min_rate(clk->id, rate); +} +EXPORT_SYMBOL(clk_set_min_rate); + +int clk_set_max_rate(struct clk *clk, unsigned long rate) +{ + return clk->ops->set_max_rate(clk->id, rate); +} +EXPORT_SYMBOL(clk_set_max_rate); + int clk_set_parent(struct clk *clk, struct clk *parent) { return -ENOSYS; @@ -173,22 +159,153 @@ int clk_set_flags(struct clk *clk, unsigned long flags) { if (clk == NULL || IS_ERR(clk)) return -EINVAL; - return pc_clk_set_flags(clk->id, flags); + return clk->ops->set_flags(clk->id, flags); } EXPORT_SYMBOL(clk_set_flags); +/* EBI1 is the only shared clock that several clients want to vote on as of + * this commit. If this changes in the future, then it might be better to + * make clk_min_rate handle the voting or make ebi1_clk_set_min_rate more + * generic to support different clocks. + */ +static struct clk *ebi1_clk; -void __init msm_clock_init(void) +static void __init set_clock_ops(struct clk *clk) +{ + if (!clk->ops) { + clk->ops = &clk_ops_pcom; + clk->id = clk->remote_id; + } +} + +void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks) { unsigned n; spin_lock_init(&clocks_lock); mutex_lock(&clocks_mutex); - for (n = 0; n < msm_num_clocks; n++) + msm_clocks = clock_tbl; + msm_num_clocks = num_clocks; + for (n = 0; n < msm_num_clocks; n++) { + set_clock_ops(&msm_clocks[n]); list_add_tail(&msm_clocks[n].list, &clocks); + } mutex_unlock(&clocks_mutex); + + ebi1_clk = clk_get(NULL, "ebi1_clk"); + BUG_ON(ebi1_clk == NULL); + +} + +#if defined(CONFIG_DEBUG_FS) +static struct clk *msm_clock_get_nth(unsigned index) +{ + if (index < msm_num_clocks) + return msm_clocks + index; + else + return 0; +} + +static int clock_debug_rate_set(void *data, u64 val) +{ + struct clk *clock = data; + int ret; + + /* Only increases to max rate will succeed, but that's actually good + * for debugging purposes. So we don't check for error. */ + if (clock->flags & CLK_MAX) + clk_set_max_rate(clock, val); + if (clock->flags & CLK_MIN) + ret = clk_set_min_rate(clock, val); + else + ret = clk_set_rate(clock, val); + if (ret != 0) + printk(KERN_ERR "clk_set%s_rate failed (%d)\n", + (clock->flags & CLK_MIN) ? "_min" : "", ret); + return ret; +} + +static int clock_debug_rate_get(void *data, u64 *val) +{ + struct clk *clock = data; + *val = clk_get_rate(clock); + return 0; +} + +static int clock_debug_enable_set(void *data, u64 val) +{ + struct clk *clock = data; + int rc = 0; + + if (val) + rc = clock->ops->enable(clock->id); + else + clock->ops->disable(clock->id); + + return rc; } +static int clock_debug_enable_get(void *data, u64 *val) +{ + struct clk *clock = data; + + *val = clock->ops->is_enabled(clock->id); + + return 0; +} + +static int clock_debug_local_get(void *data, u64 *val) +{ + struct clk *clock = data; + + *val = clock->ops != &clk_ops_pcom; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get, + clock_debug_rate_set, "%llu\n"); +DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get, + clock_debug_enable_set, "%llu\n"); +DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get, + NULL, "%llu\n"); + +static int __init clock_debug_init(void) +{ + struct dentry *dent_rate, *dent_enable, *dent_local; + struct clk *clock; + unsigned n = 0; + char temp[50], *ptr; + + dent_rate = debugfs_create_dir("clk_rate", 0); + if (IS_ERR(dent_rate)) + return PTR_ERR(dent_rate); + + dent_enable = debugfs_create_dir("clk_enable", 0); + if (IS_ERR(dent_enable)) + return PTR_ERR(dent_enable); + + dent_local = debugfs_create_dir("clk_local", NULL); + if (IS_ERR(dent_local)) + return PTR_ERR(dent_local); + + while ((clock = msm_clock_get_nth(n++)) != 0) { + strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1); + for (ptr = temp; *ptr; ptr++) + *ptr = tolower(*ptr); + debugfs_create_file(temp, 0644, dent_rate, + clock, &clock_rate_fops); + debugfs_create_file(temp, 0644, dent_enable, + clock, &clock_enable_fops); + debugfs_create_file(temp, S_IRUGO, dent_local, + clock, &clock_local_fops); + } + return 0; +} + +device_initcall(clock_debug_init); +#endif + /* The bootloader and/or AMSS may have left various clocks enabled. * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have * not been explicitly enabled by a clk_enable() call. @@ -205,7 +322,7 @@ static int __init clock_late_init(void) spin_lock_irqsave(&clocks_lock, flags); if (!clk->count) { count++; - pc_clk_disable(clk->id); + clk->ops->auto_off(clk->id); } spin_unlock_irqrestore(&clocks_lock, flags); } @@ -216,3 +333,4 @@ static int __init clock_late_init(void) } late_initcall(clock_late_init); + diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h index f875e1544e5..c270b552ed1 100644 --- a/arch/arm/mach-msm/clock.h +++ b/arch/arm/mach-msm/clock.h @@ -1,7 +1,7 @@ /* arch/arm/mach-msm/clock.h * * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2007 QUALCOMM Incorporated + * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -18,6 +18,10 @@ #define __ARCH_ARM_MACH_MSM_CLOCK_H #include <linux/list.h> +#include <mach/clk.h> + +#include "clock-pcom.h" +#include "clock-7x30.h" #define CLKFLAG_INVERT 0x00000001 #define CLKFLAG_NOINVERT 0x00000002 @@ -25,14 +29,32 @@ #define CLKFLAG_NORESET 0x00000008 #define CLK_FIRST_AVAILABLE_FLAG 0x00000100 -#define CLKFLAG_USE_MIN_MAX_TO_SET 0x00000200 -#define CLKFLAG_AUTO_OFF 0x00000400 +#define CLKFLAG_AUTO_OFF 0x00000200 +#define CLKFLAG_MIN 0x00000400 +#define CLKFLAG_MAX 0x00000800 + +struct clk_ops { + int (*enable)(unsigned id); + void (*disable)(unsigned id); + void (*auto_off)(unsigned id); + int (*reset)(unsigned id, enum clk_reset_action action); + int (*set_rate)(unsigned id, unsigned rate); + int (*set_min_rate)(unsigned id, unsigned rate); + int (*set_max_rate)(unsigned id, unsigned rate); + int (*set_flags)(unsigned id, unsigned flags); + unsigned (*get_rate)(unsigned id); + unsigned (*is_enabled)(unsigned id); + long (*round_rate)(unsigned id, unsigned rate); +}; struct clk { uint32_t id; + uint32_t remote_id; uint32_t count; uint32_t flags; const char *name; + struct clk_ops *ops; + const char *dbg_name; struct list_head list; struct device *dev; }; @@ -41,8 +63,47 @@ struct clk { #define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) #define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) -extern struct clk msm_clocks[]; -extern unsigned msm_num_clocks; +#ifdef CONFIG_DEBUG_FS +#define CLOCK_DBG_NAME(x) .dbg_name = x, +#else +#define CLOCK_DBG_NAME(x) +#endif + +#define CLOCK(clk_name, clk_id, clk_dev, clk_flags) { \ + .name = clk_name, \ + .id = clk_id, \ + .flags = clk_flags, \ + .dev = clk_dev, \ + CLOCK_DBG_NAME(#clk_id) \ + } + +#define OFF CLKFLAG_AUTO_OFF +#define CLK_MIN CLKFLAG_MIN +#define CLK_MAX CLKFLAG_MAX +#define CLK_MINMAX (CLK_MIN | CLK_MAX) +#define NR_CLKS P_NR_CLKS + +enum { + PLL_0 = 0, + PLL_1, + PLL_2, + PLL_3, + PLL_4, + PLL_5, + PLL_6, + NUM_PLL +}; + +enum clkvote_client { + CLKVOTE_ACPUCLK = 0, + CLKVOTE_PMQOS, + CLKVOTE_MAX, +}; + +int msm_clock_require_tcxo(unsigned long *reason, int nbits); +int msm_clock_get_name(uint32_t id, char *name, uint32_t size); +int ebi1_clk_set_min_rate(enum clkvote_client client, unsigned long rate); +unsigned long clk_get_max_axi_khz(void); #endif diff --git a/arch/arm/mach-msm/devices.c b/arch/arm/mach-msm/devices-msm7x00.c index 31b6b30e98b..fde9d8f69f1 100644 --- a/arch/arm/mach-msm/devices.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -24,6 +24,10 @@ #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> + +#include "clock.h" +#include <mach/mmc.h> + static struct resource resources_uart1[] = { { .start = INT_UART1, @@ -163,8 +167,19 @@ static struct resource resources_sdc1[] = { }, { .start = INT_SDC1_0, + .end = INT_SDC1_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC1_1, .end = INT_SDC1_1, .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" }, { .start = 8, @@ -181,8 +196,19 @@ static struct resource resources_sdc2[] = { }, { .start = INT_SDC2_0, + .end = INT_SDC2_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC2_1, .end = INT_SDC2_1, .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" }, { .start = 8, @@ -199,8 +225,19 @@ static struct resource resources_sdc3[] = { }, { .start = INT_SDC3_0, + .end = INT_SDC3_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC3_1, .end = INT_SDC3_1, .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" }, { .start = 8, @@ -217,8 +254,19 @@ static struct resource resources_sdc4[] = { }, { .start = INT_SDC4_0, + .end = INT_SDC4_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC4_1, .end = INT_SDC4_1, .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" }, { .start = 8, @@ -266,3 +314,80 @@ struct platform_device msm_device_sdc4 = { .coherent_dma_mask = 0xffffffff, }, }; + +static struct platform_device *msm_sdcc_devices[] __initdata = { + &msm_device_sdc1, + &msm_device_sdc2, + &msm_device_sdc3, + &msm_device_sdc4, +}; + +int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat, + unsigned int stat_irq, unsigned long stat_irq_flags) +{ + struct platform_device *pdev; + struct resource *res; + + if (controller < 1 || controller > 4) + return -EINVAL; + + pdev = msm_sdcc_devices[controller-1]; + pdev->dev.platform_data = plat; + + res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq"); + if (!res) + return -EINVAL; + else if (stat_irq) { + res->start = res->end = stat_irq; + res->flags &= ~IORESOURCE_DISABLED; + res->flags |= stat_irq_flags; + } + + return platform_device_register(pdev); +} + +struct clk msm_clocks_7x01a[] = { + CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), + CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), + CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0), + CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0), + CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), + CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF), + CLK_PCOM("gp_clk", GP_CLK, NULL, 0), + CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, OFF), + CLK_PCOM("i2c_clk", I2C_CLK, &msm_device_i2c.dev, 0), + CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), + CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), + CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), + CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0), + CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF), + CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0), + CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), + CLK_PCOM("pmdh_clk", PMDH_CLK, NULL, OFF ), + CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), + CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), + CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF), + CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF), + CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF), + CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF), + CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF), + CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF), + CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF), + CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), + CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), + CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), + CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), + CLK_PCOM("uart_clk", UART1_CLK, &msm_device_uart1.dev, OFF), + CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), + CLK_PCOM("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF), + CLK_PCOM("uart1dm_clk", UART1DM_CLK, NULL, OFF), + CLK_PCOM("uart2dm_clk", UART2DM_CLK, NULL, 0), + CLK_PCOM("usb_hs_clk", USB_HS_CLK, &msm_device_hsusb.dev, OFF), + CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, &msm_device_hsusb.dev, OFF), + CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), + CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF ), + CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF), + CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF), +}; + +unsigned msm_num_clocks_7x01a = ARRAY_SIZE(msm_clocks_7x01a); diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c new file mode 100644 index 00000000000..b449e8ad290 --- /dev/null +++ b/arch/arm/mach-msm/devices-msm7x30.c @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2008 Google, Inc. + * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <linux/dma-mapping.h> +#include <mach/irqs.h> +#include <mach/msm_iomap.h> +#include <mach/dma.h> +#include <mach/board.h> + +#include "devices.h" +#include "smd_private.h" + +#include <asm/mach/flash.h> + +#include "clock-pcom.h" + +#include <mach/mmc.h> + +static struct resource resources_uart2[] = { + { + .start = INT_UART2, + .end = INT_UART2, + .flags = IORESOURCE_IRQ, + }, + { + .start = MSM_UART2_PHYS, + .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device msm_device_uart2 = { + .name = "msm_serial", + .id = 1, + .num_resources = ARRAY_SIZE(resources_uart2), + .resource = resources_uart2, +}; + +struct clk msm_clocks_7x30[] = { + CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), + CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), + CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0), + CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF), + CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), + CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), + CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), + CLK_PCOM("emdh_pclk", EMDH_P_CLK, NULL, OFF), + CLK_PCOM("gp_clk", GP_CLK, NULL, 0), + CLK_PCOM("grp_2d_clk", GRP_2D_CLK, NULL, 0), + CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK, NULL, 0), + CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0), + CLK_PCOM("grp_pclk", GRP_3D_P_CLK, NULL, 0), + CLK_7X30S("grp_src_clk", GRP_3D_SRC_CLK, GRP_3D_CLK, NULL, 0), + CLK_PCOM("hdmi_clk", HDMI_CLK, NULL, 0), + CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), + CLK_PCOM("jpeg_clk", JPEG_CLK, NULL, OFF), + CLK_PCOM("jpeg_pclk", JPEG_P_CLK, NULL, OFF), + CLK_PCOM("lpa_codec_clk", LPA_CODEC_CLK, NULL, 0), + CLK_PCOM("lpa_core_clk", LPA_CORE_CLK, NULL, 0), + CLK_PCOM("lpa_pclk", LPA_P_CLK, NULL, 0), + CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0), + CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), + CLK_PCOM("mddi_pclk", PMDH_P_CLK, NULL, 0), + CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF), + CLK_PCOM("mdp_pclk", MDP_P_CLK, NULL, 0), + CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0), + CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0), + CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0), + CLK_PCOM("mfc_clk", MFC_CLK, NULL, 0), + CLK_PCOM("mfc_div2_clk", MFC_DIV2_CLK, NULL, 0), + CLK_PCOM("mfc_pclk", MFC_P_CLK, NULL, 0), + CLK_PCOM("mi2s_m_clk", MI2S_M_CLK, NULL, 0), + CLK_PCOM("mi2s_s_clk", MI2S_S_CLK, NULL, 0), + CLK_PCOM("mi2s_codec_rx_m_clk", MI2S_CODEC_RX_M_CLK, NULL, 0), + CLK_PCOM("mi2s_codec_rx_s_clk", MI2S_CODEC_RX_S_CLK, NULL, 0), + CLK_PCOM("mi2s_codec_tx_m_clk", MI2S_CODEC_TX_M_CLK, NULL, 0), + CLK_PCOM("mi2s_codec_tx_s_clk", MI2S_CODEC_TX_S_CLK, NULL, 0), + CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), + CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), + CLK_PCOM("rotator_clk", AXI_ROTATOR_CLK, NULL, 0), + CLK_PCOM("rotator_imem_clk", ROTATOR_IMEM_CLK, NULL, OFF), + CLK_PCOM("rotator_pclk", ROTATOR_P_CLK, NULL, OFF), + CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), + CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), + CLK_PCOM("spi_pclk", SPI_P_CLK, NULL, 0), + CLK_7X30S("tv_src_clk", TV_CLK, TV_ENC_CLK, NULL, 0), + CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), + CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), + CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), + CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), + CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), + CLK_PCOM("usb_hs_core_clk", USB_HS_CORE_CLK, NULL, OFF), + CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF), + CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF), + CLK_PCOM("usb_hs2_core_clk", USB_HS2_CORE_CLK, NULL, OFF), + CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF), + CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF), + CLK_PCOM("usb_hs3_core_clk", USB_HS3_CORE_CLK, NULL, OFF), + CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN), + CLK_PCOM("vfe_camif_clk", VFE_CAMIF_CLK, NULL, 0), + CLK_PCOM("vfe_clk", VFE_CLK, NULL, 0), + CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, 0), + CLK_PCOM("vfe_pclk", VFE_P_CLK, NULL, OFF), + CLK_PCOM("vpe_clk", VPE_CLK, NULL, 0), + + /* 7x30 v2 hardware only. */ + CLK_PCOM("csi_clk", CSI0_CLK, NULL, 0), + CLK_PCOM("csi_pclk", CSI0_P_CLK, NULL, 0), + CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK, NULL, 0), +}; + +unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30); + diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c new file mode 100644 index 00000000000..4d4a50785e3 --- /dev/null +++ b/arch/arm/mach-msm/devices-qsd8x50.c @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2008 Google, Inc. + * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <linux/dma-mapping.h> +#include <mach/irqs.h> +#include <mach/msm_iomap.h> +#include <mach/dma.h> +#include <mach/board.h> + +#include "devices.h" + +#include <asm/mach/flash.h> + +#include <mach/mmc.h> + +static struct resource resources_uart3[] = { + { + .start = INT_UART3, + .end = INT_UART3, + .flags = IORESOURCE_IRQ, + }, + { + .start = MSM_UART3_PHYS, + .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device msm_device_uart3 = { + .name = "msm_serial", + .id = 2, + .num_resources = ARRAY_SIZE(resources_uart3), + .resource = resources_uart3, +}; + +struct clk msm_clocks_8x50[] = { + CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), + CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), + CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0), + CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), + CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), + CLK_PCOM("gp_clk", GP_CLK, NULL, 0), + CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0), + CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), + CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), + CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), + CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0), + CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), + CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF), + CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0), + CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0), + CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0), + CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), + CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), + CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), + CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), + CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), + CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), + CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), + CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), + CLK_PCOM("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF), + CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), + CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), + CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), + CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN), + CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF), + CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF), + CLK_PCOM("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF), + CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF), + CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF), + CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF), + CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF), + CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0), +}; + +unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50); + diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h index 0744c4a27d6..568443e7642 100644 --- a/arch/arm/mach-msm/devices.h +++ b/arch/arm/mach-msm/devices.h @@ -16,6 +16,8 @@ #ifndef __ARCH_ARM_MACH_MSM_DEVICES_H #define __ARCH_ARM_MACH_MSM_DEVICES_H +#include "clock.h" + extern struct platform_device msm_device_uart1; extern struct platform_device msm_device_uart2; extern struct platform_device msm_device_uart3; @@ -33,4 +35,13 @@ extern struct platform_device msm_device_smd; extern struct platform_device msm_device_nand; +extern struct clk msm_clocks_7x01a[]; +extern unsigned msm_num_clocks_7x01a; + +extern struct clk msm_clocks_7x30[]; +extern unsigned msm_num_clocks_7x30; + +extern struct clk msm_clocks_8x50[]; +extern unsigned msm_num_clocks_8x50; + #endif diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c index f5420f9585c..d029d1f5f9e 100644 --- a/arch/arm/mach-msm/dma.c +++ b/arch/arm/mach-msm/dma.c @@ -13,6 +13,8 @@ * */ +#include <linux/clk.h> +#include <linux/err.h> #include <linux/io.h> #include <linux/interrupt.h> #include <mach/dma.h> @@ -26,6 +28,7 @@ enum { }; static DEFINE_SPINLOCK(msm_dmov_lock); +static struct clk *msm_dmov_clk; static unsigned int channel_active; static struct list_head ready_commands[MSM_DMOV_CHANNEL_COUNT]; static struct list_head active_commands[MSM_DMOV_CHANNEL_COUNT]; @@ -54,6 +57,9 @@ void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) unsigned int status; spin_lock_irqsave(&msm_dmov_lock, irq_flags); + if (!channel_active) + clk_enable(msm_dmov_clk); + dsb(); status = readl(DMOV_STATUS(id)); if (list_empty(&ready_commands[id]) && (status & DMOV_STATUS_CMD_PTR_RDY)) { @@ -63,6 +69,8 @@ void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) writel(DMOV_CONFIG_IRQ_EN, DMOV_CONFIG(id)); } #endif + if (cmd->execute_func) + cmd->execute_func(cmd); PRINT_IO("msm_dmov_enqueue_cmd(%d), start command, status %x\n", id, status); list_add_tail(&cmd->list, &active_commands[id]); if (!channel_active) @@ -70,6 +78,8 @@ void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) channel_active |= 1U << id; writel(cmd->cmdptr, DMOV_CMD_PTR(id)); } else { + if (!channel_active) + clk_disable(msm_dmov_clk); if (list_empty(&active_commands[id])) PRINT_ERROR("msm_dmov_enqueue_cmd(%d), error datamover stalled, status %x\n", id, status); @@ -108,6 +118,7 @@ int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) cmd.dmov_cmd.cmdptr = cmdptr; cmd.dmov_cmd.complete_func = dmov_exec_cmdptr_complete_func; + cmd.dmov_cmd.execute_func = NULL; cmd.id = id; init_completion(&cmd.complete); @@ -165,6 +176,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) "for %p, result %x\n", id, cmd, ch_result); if (cmd) { list_del(&cmd->list); + dsb(); cmd->complete_func(cmd, ch_result, NULL); } } @@ -181,6 +193,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) PRINT_FLOW("msm_datamover_irq_handler id %d, flush, result %x, flush0 %x\n", id, ch_result, errdata.flush[0]); if (cmd) { list_del(&cmd->list); + dsb(); cmd->complete_func(cmd, ch_result, &errdata); } } @@ -198,6 +211,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) PRINT_ERROR("msm_datamover_irq_handler id %d, error, result %x, flush0 %x\n", id, ch_result, errdata.flush[0]); if (cmd) { list_del(&cmd->list); + dsb(); cmd->complete_func(cmd, ch_result, &errdata); } /* this does not seem to work, once we get an error */ @@ -210,6 +224,8 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) cmd = list_entry(ready_commands[id].next, typeof(*cmd), list); list_del(&cmd->list); list_add_tail(&cmd->list, &active_commands[id]); + if (cmd->execute_func) + cmd->execute_func(cmd); PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id); writel(cmd->cmdptr, DMOV_CMD_PTR(id)); } @@ -219,8 +235,10 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); } - if (!channel_active) - disable_irq(INT_ADM_AARM); + if (!channel_active) { + disable_irq_nosync(INT_ADM_AARM); + clk_disable(msm_dmov_clk); + } spin_unlock_irqrestore(&msm_dmov_lock, irq_flags); return IRQ_HANDLED; @@ -230,11 +248,17 @@ static int __init msm_init_datamover(void) { int i; int ret; + struct clk *clk; + for (i = 0; i < MSM_DMOV_CHANNEL_COUNT; i++) { INIT_LIST_HEAD(&ready_commands[i]); INIT_LIST_HEAD(&active_commands[i]); writel(DMOV_CONFIG_IRQ_EN | DMOV_CONFIG_FORCE_TOP_PTR_RSLT | DMOV_CONFIG_FORCE_FLUSH_RSLT, DMOV_CONFIG(i)); } + clk = clk_get(NULL, "adm_clk"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + msm_dmov_clk = clk; ret = request_irq(INT_ADM_AARM, msm_datamover_irq_handler, 0, "msmdatamover", NULL); if (ret) return ret; diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c new file mode 100644 index 00000000000..bc32c845c7b --- /dev/null +++ b/arch/arm/mach-msm/gpio.c @@ -0,0 +1,85 @@ +/* linux/arch/arm/mach-msm/gpio.c + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2009, Code Aurora Forum. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/module.h> +#include <mach/gpio.h> +#include "proc_comm.h" + +int gpio_tlmm_config(unsigned config, unsigned disable) +{ + return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable); +} +EXPORT_SYMBOL(gpio_tlmm_config); + +int msm_gpios_enable(const struct msm_gpio *table, int size) +{ + int rc; + int i; + const struct msm_gpio *g; + for (i = 0; i < size; i++) { + g = table + i; + rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE); + if (rc) { + pr_err("gpio_tlmm_config(0x%08x, GPIO_ENABLE)" + " <%s> failed: %d\n", + g->gpio_cfg, g->label ?: "?", rc); + pr_err("pin %d func %d dir %d pull %d drvstr %d\n", + GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg), + GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg), + GPIO_DRVSTR(g->gpio_cfg)); + goto err; + } + } + return 0; +err: + msm_gpios_disable(table, i); + return rc; +} +EXPORT_SYMBOL(msm_gpios_enable); + +void msm_gpios_disable(const struct msm_gpio *table, int size) +{ + int rc; + int i; + const struct msm_gpio *g; + for (i = size-1; i >= 0; i--) { + g = table + i; + rc = gpio_tlmm_config(g->gpio_cfg, GPIO_DISABLE); + if (rc) { + pr_err("gpio_tlmm_config(0x%08x, GPIO_DISABLE)" + " <%s> failed: %d\n", + g->gpio_cfg, g->label ?: "?", rc); + pr_err("pin %d func %d dir %d pull %d drvstr %d\n", + GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg), + GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg), + GPIO_DRVSTR(g->gpio_cfg)); + } + } +} +EXPORT_SYMBOL(msm_gpios_disable); + +int msm_gpios_request_enable(const struct msm_gpio *table, int size) +{ + int rc = msm_gpios_enable(table, size); + return rc; +} +EXPORT_SYMBOL(msm_gpios_request_enable); + +void msm_gpios_disable_free(const struct msm_gpio *table, int size) +{ + msm_gpios_disable(table, size); +} +EXPORT_SYMBOL(msm_gpios_disable_free); diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h index 264d62e519f..e302fbdc439 100644 --- a/arch/arm/mach-msm/include/mach/board.h +++ b/arch/arm/mach-msm/include/mach/board.h @@ -21,18 +21,24 @@ /* platform device data structures */ -struct msm_mddi_platform_data +struct msm_acpu_clock_platform_data { - void (*panel_power)(int on); - unsigned has_vsync_irq:1; + uint32_t acpu_switch_time_us; + uint32_t max_speed_delta_khz; + uint32_t vdd_switch_time_us; + unsigned long power_collapse_khz; + unsigned long wait_for_irq_khz; }; +struct clk; + /* common init routines for use by arch/arm/mach-msm/board-*.c */ void __init msm_add_devices(void); void __init msm_map_common_io(void); void __init msm_init_irq(void); void __init msm_init_gpio(void); -void __init msm_clock_init(void); +void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks); +void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *); #endif diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h new file mode 100644 index 00000000000..c05ca40478c --- /dev/null +++ b/arch/arm/mach-msm/include/mach/clk.h @@ -0,0 +1,57 @@ +/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef __MACH_CLK_H +#define __MACH_CLK_H + +/* Magic rate value for use with PM QOS to request the board's maximum + * supported AXI rate. PM QOS will only pass positive s32 rate values + * through to the clock driver, so INT_MAX is used. + */ +#define MSM_AXI_MAX_FREQ LONG_MAX + +enum clk_reset_action { + CLK_RESET_DEASSERT = 0, + CLK_RESET_ASSERT = 1 +}; + +struct clk; + +/* Rate is minimum clock rate in Hz */ +int clk_set_min_rate(struct clk *clk, unsigned long rate); + +/* Rate is maximum clock rate in Hz */ +int clk_set_max_rate(struct clk *clk, unsigned long rate); + +/* Assert/Deassert reset to a hardware block associated with a clock */ +int clk_reset(struct clk *clk, enum clk_reset_action action); + +/* Set clock-specific configuration parameters */ +int clk_set_flags(struct clk *clk, unsigned long flags); + +#endif diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h index 5ab5bdffab0..00f9bbfadbe 100644 --- a/arch/arm/mach-msm/include/mach/dma.h +++ b/arch/arm/mach-msm/include/mach/dma.h @@ -28,6 +28,8 @@ struct msm_dmov_cmd { void (*complete_func)(struct msm_dmov_cmd *cmd, unsigned int result, struct msm_dmov_errdata *err); + void (*execute_func)(struct msm_dmov_cmd *cmd); + void *data; }; void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd); @@ -41,40 +43,42 @@ int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr); #define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2)) #define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2)) -/* only security domain 3 is available to the ARM11 - * SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM - */ +#if defined(CONFIG_ARCH_MSM7X30) +#define DMOV_SD_AARM DMOV_SD2 +#else +#define DMOV_SD_AARM DMOV_SD3 +#endif -#define DMOV_CMD_PTR(ch) DMOV_SD3(0x000, ch) +#define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch) #define DMOV_CMD_LIST (0 << 29) /* does not work */ #define DMOV_CMD_PTR_LIST (1 << 29) /* works */ #define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */ #define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */ #define DMOV_CMD_ADDR(addr) ((addr) >> 3) -#define DMOV_RSLT(ch) DMOV_SD3(0x040, ch) +#define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch) #define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */ #define DMOV_RSLT_ERROR (1 << 3) #define DMOV_RSLT_FLUSH (1 << 2) #define DMOV_RSLT_DONE (1 << 1) /* top pointer done */ #define DMOV_RSLT_USER (1 << 0) /* command with FR force result */ -#define DMOV_FLUSH0(ch) DMOV_SD3(0x080, ch) -#define DMOV_FLUSH1(ch) DMOV_SD3(0x0C0, ch) -#define DMOV_FLUSH2(ch) DMOV_SD3(0x100, ch) -#define DMOV_FLUSH3(ch) DMOV_SD3(0x140, ch) -#define DMOV_FLUSH4(ch) DMOV_SD3(0x180, ch) -#define DMOV_FLUSH5(ch) DMOV_SD3(0x1C0, ch) +#define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch) +#define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch) +#define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch) +#define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch) +#define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch) +#define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch) -#define DMOV_STATUS(ch) DMOV_SD3(0x200, ch) +#define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch) #define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29)) #define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3) #define DMOV_STATUS_RSLT_VALID (1 << 1) #define DMOV_STATUS_CMD_PTR_RDY (1 << 0) -#define DMOV_ISR DMOV_SD3(0x380, 0) - -#define DMOV_CONFIG(ch) DMOV_SD3(0x300, ch) +#define DMOV_ISR DMOV_SD_AARM(0x380, 0) + +#define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch) #define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2) #define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1) #define DMOV_CONFIG_IRQ_EN (1 << 0) diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h new file mode 100644 index 00000000000..262b441b437 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/gpio.h @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * Author: Mike Lockwood <lockwood@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __ASM_ARCH_MSM_GPIO_H +#define __ASM_ARCH_MSM_GPIO_H + +/** + * struct msm_gpio - GPIO pin description + * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config() + * @label - textual label + * + * Usually, GPIO's are operated by sets. + * This struct accumulate all GPIO information in single source + * and facilitete group operations provided by msm_gpios_xxx() + */ +struct msm_gpio { + u32 gpio_cfg; + const char *label; +}; + +/** + * msm_gpios_request_enable() - request and enable set of GPIOs + * + * Request and configure set of GPIO's + * In case of error, all operations rolled back. + * Return error code. + * + * @table: GPIO table + * @size: number of entries in @table + */ +int msm_gpios_request_enable(const struct msm_gpio *table, int size); + +/** + * msm_gpios_disable_free() - disable and free set of GPIOs + * + * @table: GPIO table + * @size: number of entries in @table + */ +void msm_gpios_disable_free(const struct msm_gpio *table, int size); + +/** + * msm_gpios_request() - request set of GPIOs + * In case of error, all operations rolled back. + * Return error code. + * + * @table: GPIO table + * @size: number of entries in @table + */ +int msm_gpios_request(const struct msm_gpio *table, int size); + +/** + * msm_gpios_free() - free set of GPIOs + * + * @table: GPIO table + * @size: number of entries in @table + */ +void msm_gpios_free(const struct msm_gpio *table, int size); + +/** + * msm_gpios_enable() - enable set of GPIOs + * In case of error, all operations rolled back. + * Return error code. + * + * @table: GPIO table + * @size: number of entries in @table + */ +int msm_gpios_enable(const struct msm_gpio *table, int size); + +/** + * msm_gpios_disable() - disable set of GPIOs + * + * @table: GPIO table + * @size: number of entries in @table + */ +void msm_gpios_disable(const struct msm_gpio *table, int size); + +/* GPIO TLMM (Top Level Multiplexing) Definitions */ + +/* GPIO TLMM: Function -- GPIO specific */ + +/* GPIO TLMM: Direction */ +enum { + GPIO_INPUT, + GPIO_OUTPUT, +}; + +/* GPIO TLMM: Pullup/Pulldown */ +enum { + GPIO_NO_PULL, + GPIO_PULL_DOWN, + GPIO_KEEPER, + GPIO_PULL_UP, +}; + +/* GPIO TLMM: Drive Strength */ +enum { + GPIO_2MA, + GPIO_4MA, + GPIO_6MA, + GPIO_8MA, + GPIO_10MA, + GPIO_12MA, + GPIO_14MA, + GPIO_16MA, +}; + +enum { + GPIO_ENABLE, + GPIO_DISABLE, +}; + +#define GPIO_CFG(gpio, func, dir, pull, drvstr) \ + ((((gpio) & 0x3FF) << 4) | \ + ((func) & 0xf) | \ + (((dir) & 0x1) << 14) | \ + (((pull) & 0x3) << 15) | \ + (((drvstr) & 0xF) << 17)) + +/** + * extract GPIO pin from bit-field used for gpio_tlmm_config + */ +#define GPIO_PIN(gpio_cfg) (((gpio_cfg) >> 4) & 0x3ff) +#define GPIO_FUNC(gpio_cfg) (((gpio_cfg) >> 0) & 0xf) +#define GPIO_DIR(gpio_cfg) (((gpio_cfg) >> 14) & 0x1) +#define GPIO_PULL(gpio_cfg) (((gpio_cfg) >> 15) & 0x3) +#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg) >> 17) & 0xf) + +int gpio_tlmm_config(unsigned config, unsigned disable); + +#endif /* __ASM_ARCH_MSM_GPIO_H */ diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h index aab964591db..c35b29f9ac0 100644 --- a/arch/arm/mach-msm/include/mach/io.h +++ b/arch/arm/mach-msm/include/mach/io.h @@ -26,4 +26,9 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m #define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) +void msm_map_qsd8x50_io(void); +void msm_map_msm7x30_io(void); + +extern unsigned int msm_shared_ram_phys; + #endif diff --git a/arch/arm/mach-msm/include/mach/irqs-7x00.h b/arch/arm/mach-msm/include/mach/irqs-7x00.h new file mode 100644 index 00000000000..f1fe70612fe --- /dev/null +++ b/arch/arm/mach-msm/include/mach/irqs-7x00.h @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2009, Code Aurora Forum. All rights reserved. + * Author: Brian Swetland <swetland@google.com> + */ + +#ifndef __ASM_ARCH_MSM_IRQS_7X00_H +#define __ASM_ARCH_MSM_IRQS_7X00_H + +/* MSM ARM11 Interrupt Numbers */ +/* See 80-VE113-1 A, pp219-221 */ + +#define INT_A9_M2A_0 0 +#define INT_A9_M2A_1 1 +#define INT_A9_M2A_2 2 +#define INT_A9_M2A_3 3 +#define INT_A9_M2A_4 4 +#define INT_A9_M2A_5 5 +#define INT_A9_M2A_6 6 +#define INT_GP_TIMER_EXP 7 +#define INT_DEBUG_TIMER_EXP 8 +#define INT_UART1 9 +#define INT_UART2 10 +#define INT_UART3 11 +#define INT_UART1_RX 12 +#define INT_UART2_RX 13 +#define INT_UART3_RX 14 +#define INT_USB_OTG 15 +#define INT_MDDI_PRI 16 +#define INT_MDDI_EXT 17 +#define INT_MDDI_CLIENT 18 +#define INT_MDP 19 +#define INT_GRAPHICS 20 +#define INT_ADM_AARM 21 +#define INT_ADSP_A11 22 +#define INT_ADSP_A9_A11 23 +#define INT_SDC1_0 24 +#define INT_SDC1_1 25 +#define INT_SDC2_0 26 +#define INT_SDC2_1 27 +#define INT_KEYSENSE 28 +#define INT_TCHSCRN_SSBI 29 +#define INT_TCHSCRN1 30 +#define INT_TCHSCRN2 31 + +#define INT_GPIO_GROUP1 (32 + 0) +#define INT_GPIO_GROUP2 (32 + 1) +#define INT_PWB_I2C (32 + 2) +#define INT_SOFTRESET (32 + 3) +#define INT_NAND_WR_ER_DONE (32 + 4) +#define INT_NAND_OP_DONE (32 + 5) +#define INT_PBUS_ARM11 (32 + 6) +#define INT_AXI_MPU_SMI (32 + 7) +#define INT_AXI_MPU_EBI1 (32 + 8) +#define INT_AD_HSSD (32 + 9) +#define INT_ARM11_PMU (32 + 10) +#define INT_ARM11_DMA (32 + 11) +#define INT_TSIF_IRQ (32 + 12) +#define INT_UART1DM_IRQ (32 + 13) +#define INT_UART1DM_RX (32 + 14) +#define INT_USB_HS (32 + 15) +#define INT_SDC3_0 (32 + 16) +#define INT_SDC3_1 (32 + 17) +#define INT_SDC4_0 (32 + 18) +#define INT_SDC4_1 (32 + 19) +#define INT_UART2DM_RX (32 + 20) +#define INT_UART2DM_IRQ (32 + 21) + +/* 22-31 are reserved */ + +#define NR_MSM_IRQS 64 +#define NR_GPIO_IRQS 122 +#define NR_BOARD_IRQS 64 + +#endif diff --git a/arch/arm/mach-msm/include/mach/irqs-7x30.h b/arch/arm/mach-msm/include/mach/irqs-7x30.h new file mode 100644 index 00000000000..67c5396514f --- /dev/null +++ b/arch/arm/mach-msm/include/mach/irqs-7x30.h @@ -0,0 +1,170 @@ +/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ASM_ARCH_MSM_IRQS_7X30_H +#define __ASM_ARCH_MSM_IRQS_7X30_H + +/* MSM ACPU Interrupt Numbers */ + +#define INT_DEBUG_TIMER_EXP 0 +#define INT_GPT0_TIMER_EXP 1 +#define INT_GPT1_TIMER_EXP 2 +#define INT_WDT0_ACCSCSSBARK 3 +#define INT_WDT1_ACCSCSSBARK 4 +#define INT_AVS_SVIC 5 +#define INT_AVS_SVIC_SW_DONE 6 +#define INT_SC_DBG_RX_FULL 7 +#define INT_SC_DBG_TX_EMPTY 8 +#define INT_ARM11_PM 9 +#define INT_AVS_REQ_DOWN 10 +#define INT_AVS_REQ_UP 11 +#define INT_SC_ACG 12 +/* SCSS_VICFIQSTS0[13:15] are RESERVED */ +#define INT_L2_SVICCPUIRPTREQ 16 +#define INT_L2_SVICDMANSIRPTREQ 17 +#define INT_L2_SVICDMASIRPTREQ 18 +#define INT_L2_SVICSLVIRPTREQ 19 +#define INT_AD5A_MPROC_APPS_0 20 +#define INT_AD5A_MPROC_APPS_1 21 +#define INT_A9_M2A_0 22 +#define INT_A9_M2A_1 23 +#define INT_A9_M2A_2 24 +#define INT_A9_M2A_3 25 +#define INT_A9_M2A_4 26 +#define INT_A9_M2A_5 27 +#define INT_A9_M2A_6 28 +#define INT_A9_M2A_7 29 +#define INT_A9_M2A_8 30 +#define INT_A9_M2A_9 31 + +#define INT_AXI_EBI1_SC (32 + 0) +#define INT_IMEM_ERR (32 + 1) +#define INT_AXI_EBI0_SC (32 + 2) +#define INT_PBUS_SC_IRQC (32 + 3) +#define INT_PERPH_BUS_BPM (32 + 4) +#define INT_CC_TEMP_SENSE (32 + 5) +#define INT_UXMC_EBI0 (32 + 6) +#define INT_UXMC_EBI1 (32 + 7) +#define INT_EBI2_OP_DONE (32 + 8) +#define INT_EBI2_WR_ER_DONE (32 + 9) +#define INT_TCSR_SPSS_CE (32 + 10) +#define INT_EMDH (32 + 11) +#define INT_PMDH (32 + 12) +#define INT_MDC (32 + 13) +#define INT_MIDI_TO_SUPSS (32 + 14) +#define INT_LPA_2 (32 + 15) +#define INT_GPIO_GROUP1_SECURE (32 + 16) +#define INT_GPIO_GROUP2_SECURE (32 + 17) +#define INT_GPIO_GROUP1 (32 + 18) +#define INT_GPIO_GROUP2 (32 + 19) +#define INT_MPRPH_SOFTRESET (32 + 20) +#define INT_PWB_I2C (32 + 21) +#define INT_PWB_I2C_2 (32 + 22) +#define INT_TSSC_SAMPLE (32 + 23) +#define INT_TSSC_PENUP (32 + 24) +#define INT_TCHSCRN_SSBI (32 + 25) +#define INT_FM_RDS (32 + 26) +#define INT_KEYSENSE (32 + 27) +#define INT_USB_OTG_HS (32 + 28) +#define INT_USB_OTG_HS2 (32 + 29) +#define INT_USB_OTG_HS3 (32 + 30) +#define INT_CSI (32 + 31) + +#define INT_SPI_OUTPUT (64 + 0) +#define INT_SPI_INPUT (64 + 1) +#define INT_SPI_ERROR (64 + 2) +#define INT_UART1 (64 + 3) +#define INT_UART1_RX (64 + 4) +#define INT_UART2 (64 + 5) +#define INT_UART2_RX (64 + 6) +#define INT_UART3 (64 + 7) +#define INT_UART3_RX (64 + 8) +#define INT_UART1DM_IRQ (64 + 9) +#define INT_UART1DM_RX (64 + 10) +#define INT_UART2DM_IRQ (64 + 11) +#define INT_UART2DM_RX (64 + 12) +#define INT_TSIF (64 + 13) +#define INT_ADM_SC1 (64 + 14) +#define INT_ADM_SC2 (64 + 15) +#define INT_MDP (64 + 16) +#define INT_VPE (64 + 17) +#define INT_GRP_2D (64 + 18) +#define INT_GRP_3D (64 + 19) +#define INT_ROTATOR (64 + 20) +#define INT_MFC720 (64 + 21) +#define INT_JPEG (64 + 22) +#define INT_VFE (64 + 23) +#define INT_TV_ENC (64 + 24) +#define INT_PMIC_SSBI (64 + 25) +#define INT_MPM_1 (64 + 26) +#define INT_TCSR_SPSS_SAMPLE (64 + 27) +#define INT_TCSR_SPSS_PENUP (64 + 28) +#define INT_MPM_2 (64 + 29) +#define INT_SDC1_0 (64 + 30) +#define INT_SDC1_1 (64 + 31) + +#define INT_SDC3_0 (96 + 0) +#define INT_SDC3_1 (96 + 1) +#define INT_SDC2_0 (96 + 2) +#define INT_SDC2_1 (96 + 3) +#define INT_SDC4_0 (96 + 4) +#define INT_SDC4_1 (96 + 5) +#define INT_PWB_QUP_IN (96 + 6) +#define INT_PWB_QUP_OUT (96 + 7) +#define INT_PWB_QUP_ERR (96 + 8) +#define INT_SCSS_WDT0_BITE (96 + 9) +/* SCSS_VICFIQSTS3[10:31] are RESERVED */ + +/* Retrofit universal macro names */ +#define INT_ADM_AARM INT_ADM_SC2 +#define INT_USB_HS INT_USB_OTG_HS +#define INT_USB_OTG INT_USB_OTG_HS +#define INT_TCHSCRN1 INT_TSSC_SAMPLE +#define INT_TCHSCRN2 INT_TSSC_PENUP +#define INT_GP_TIMER_EXP INT_GPT0_TIMER_EXP +#define INT_ADSP_A11 INT_AD5A_MPROC_APPS_0 +#define INT_ADSP_A9_A11 INT_AD5A_MPROC_APPS_1 +#define INT_MDDI_EXT INT_EMDH +#define INT_MDDI_PRI INT_PMDH +#define INT_MDDI_CLIENT INT_MDC +#define INT_NAND_WR_ER_DONE INT_EBI2_WR_ER_DONE +#define INT_NAND_OP_DONE INT_EBI2_OP_DONE + +#define NR_MSM_IRQS 128 +#define NR_GPIO_IRQS 182 +#define PMIC8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS) +#define NR_PMIC8058_GPIO_IRQS 40 +#define NR_PMIC8058_MPP_IRQS 12 +#define NR_PMIC8058_MISC_IRQS 8 +#define NR_PMIC8058_IRQS (NR_PMIC8058_GPIO_IRQS +\ + NR_PMIC8058_MPP_IRQS +\ + NR_PMIC8058_MISC_IRQS) +#define NR_BOARD_IRQS NR_PMIC8058_IRQS + +#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */ diff --git a/arch/arm/mach-msm/include/mach/irqs-8x50.h b/arch/arm/mach-msm/include/mach/irqs-8x50.h new file mode 100644 index 00000000000..de3d8fe24e4 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/irqs-8x50.h @@ -0,0 +1,105 @@ +/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ASM_ARCH_MSM_IRQS_8XXX_H +#define __ASM_ARCH_MSM_IRQS_8XXX_H + +/* MSM ACPU Interrupt Numbers */ + +#define INT_A9_M2A_0 0 +#define INT_A9_M2A_1 1 +#define INT_A9_M2A_2 2 +#define INT_A9_M2A_3 3 +#define INT_A9_M2A_4 4 +#define INT_A9_M2A_5 5 +#define INT_A9_M2A_6 6 +#define INT_GP_TIMER_EXP 7 +#define INT_DEBUG_TIMER_EXP 8 +#define INT_SIRC_0 9 +#define INT_SDC3_0 10 +#define INT_SDC3_1 11 +#define INT_SDC4_0 12 +#define INT_SDC4_1 13 +#define INT_AD6_EXT_VFR 14 +#define INT_USB_OTG 15 +#define INT_MDDI_PRI 16 +#define INT_MDDI_EXT 17 +#define INT_MDDI_CLIENT 18 +#define INT_MDP 19 +#define INT_GRAPHICS 20 +#define INT_ADM_AARM 21 +#define INT_ADSP_A11 22 +#define INT_ADSP_A9_A11 23 +#define INT_SDC1_0 24 +#define INT_SDC1_1 25 +#define INT_SDC2_0 26 +#define INT_SDC2_1 27 +#define INT_KEYSENSE 28 +#define INT_TCHSCRN_SSBI 29 +#define INT_TCHSCRN1 30 +#define INT_TCHSCRN2 31 + +#define INT_TCSR_MPRPH_SC1 (32 + 0) +#define INT_USB_FS2 (32 + 1) +#define INT_PWB_I2C (32 + 2) +#define INT_SOFTRESET (32 + 3) +#define INT_NAND_WR_ER_DONE (32 + 4) +#define INT_NAND_OP_DONE (32 + 5) +#define INT_TCSR_MPRPH_SC2 (32 + 6) +#define INT_OP_PEN (32 + 7) +#define INT_AD_HSSD (32 + 8) +#define INT_ARM11_PM (32 + 9) +#define INT_SDMA_NON_SECURE (32 + 10) +#define INT_TSIF_IRQ (32 + 11) +#define INT_UART1DM_IRQ (32 + 12) +#define INT_UART1DM_RX (32 + 13) +#define INT_SDMA_SECURE (32 + 14) +#define INT_SI2S_SLAVE (32 + 15) +#define INT_SC_I2CPU (32 + 16) +#define INT_SC_DBG_RDTRFULL (32 + 17) +#define INT_SC_DBG_WDTRFULL (32 + 18) +#define INT_SCPLL_CTL_DONE (32 + 19) +#define INT_UART2DM_IRQ (32 + 20) +#define INT_UART2DM_RX (32 + 21) +#define INT_VDC_MEC (32 + 22) +#define INT_VDC_DB (32 + 23) +#define INT_VDC_AXI (32 + 24) +#define INT_VFE (32 + 25) +#define INT_USB_HS (32 + 26) +#define INT_AUDIO_OUT0 (32 + 27) +#define INT_AUDIO_OUT1 (32 + 28) +#define INT_CRYPTO (32 + 29) +#define INT_AD6M_IDLE (32 + 30) +#define INT_SIRC_1 (32 + 31) + +#define NR_GPIO_IRQS 165 +#define NR_MSM_IRQS 64 +#define NR_BOARD_IRQS 64 + +#endif diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h index 9dd4cf8a269..164d355c96e 100644 --- a/arch/arm/mach-msm/include/mach/irqs.h +++ b/arch/arm/mach-msm/include/mach/irqs.h @@ -1,6 +1,6 @@ -/* arch/arm/mach-msm/include/mach/irqs.h - * +/* * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -17,74 +17,21 @@ #ifndef __ASM_ARCH_MSM_IRQS_H #define __ASM_ARCH_MSM_IRQS_H -/* MSM ARM11 Interrupt Numbers */ -/* See 80-VE113-1 A, pp219-221 */ - -#define INT_A9_M2A_0 0 -#define INT_A9_M2A_1 1 -#define INT_A9_M2A_2 2 -#define INT_A9_M2A_3 3 -#define INT_A9_M2A_4 4 -#define INT_A9_M2A_5 5 -#define INT_A9_M2A_6 6 -#define INT_GP_TIMER_EXP 7 -#define INT_DEBUG_TIMER_EXP 8 -#define INT_UART1 9 -#define INT_UART2 10 -#define INT_UART3 11 -#define INT_UART1_RX 12 -#define INT_UART2_RX 13 -#define INT_UART3_RX 14 -#define INT_USB_OTG 15 -#define INT_MDDI_PRI 16 -#define INT_MDDI_EXT 17 -#define INT_MDDI_CLIENT 18 -#define INT_MDP 19 -#define INT_GRAPHICS 20 -#define INT_ADM_AARM 21 -#define INT_ADSP_A11 22 -#define INT_ADSP_A9_A11 23 -#define INT_SDC1_0 24 -#define INT_SDC1_1 25 -#define INT_SDC2_0 26 -#define INT_SDC2_1 27 -#define INT_KEYSENSE 28 -#define INT_TCHSCRN_SSBI 29 -#define INT_TCHSCRN1 30 -#define INT_TCHSCRN2 31 - -#define INT_GPIO_GROUP1 (32 + 0) -#define INT_GPIO_GROUP2 (32 + 1) -#define INT_PWB_I2C (32 + 2) -#define INT_SOFTRESET (32 + 3) -#define INT_NAND_WR_ER_DONE (32 + 4) -#define INT_NAND_OP_DONE (32 + 5) -#define INT_PBUS_ARM11 (32 + 6) -#define INT_AXI_MPU_SMI (32 + 7) -#define INT_AXI_MPU_EBI1 (32 + 8) -#define INT_AD_HSSD (32 + 9) -#define INT_ARM11_PMU (32 + 10) -#define INT_ARM11_DMA (32 + 11) -#define INT_TSIF_IRQ (32 + 12) -#define INT_UART1DM_IRQ (32 + 13) -#define INT_UART1DM_RX (32 + 14) -#define INT_USB_HS (32 + 15) -#define INT_SDC3_0 (32 + 16) -#define INT_SDC3_1 (32 + 17) -#define INT_SDC4_0 (32 + 18) -#define INT_SDC4_1 (32 + 19) -#define INT_UART2DM_RX (32 + 20) -#define INT_UART2DM_IRQ (32 + 21) - -/* 22-31 are reserved */ - #define MSM_IRQ_BIT(irq) (1 << ((irq) & 31)) -#define NR_MSM_IRQS 64 -#define NR_GPIO_IRQS 122 -#define NR_BOARD_IRQS 64 -#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS) +#if defined(CONFIG_ARCH_MSM7X30) +#include "irqs-7x30.h" +#elif defined(CONFIG_ARCH_QSD8X50) +#include "irqs-8x50.h" +#include "sirc.h" +#elif defined(CONFIG_ARCH_MSM_ARM11) +#include "irqs-7x00.h" +#else +#error "Unknown architecture specification" +#endif +#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS) #define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n)) +#define MSM_INT_TO_REG(base, irq) (base + irq / 32) #endif diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h index f4698baec97..50c7847e600 100644 --- a/arch/arm/mach-msm/include/mach/memory.h +++ b/arch/arm/mach-msm/include/mach/memory.h @@ -17,7 +17,15 @@ #define __ASM_ARCH_MEMORY_H /* physical offset of RAM */ +#if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A) +#define PHYS_OFFSET UL(0x00000000) +#elif defined(CONFIG_ARCH_QSD8X50) +#define PHYS_OFFSET UL(0x20000000) +#elif defined(CONFIG_ARCH_MSM7X30) +#define PHYS_OFFSET UL(0x00200000) +#else #define PHYS_OFFSET UL(0x10000000) +#endif #endif diff --git a/arch/arm/mach-msm/include/mach/msm_fb.h b/arch/arm/mach-msm/include/mach/msm_fb.h new file mode 100644 index 00000000000..1f4fc81b3d8 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/msm_fb.h @@ -0,0 +1,147 @@ +/* arch/arm/mach-msm/include/mach/msm_fb.h + * + * Internal shared definitions for various MSM framebuffer parts. + * + * Copyright (C) 2007 Google Incorporated + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MSM_FB_H_ +#define _MSM_FB_H_ + +#include <linux/device.h> + +struct mddi_info; + +struct msm_fb_data { + int xres; /* x resolution in pixels */ + int yres; /* y resolution in pixels */ + int width; /* disply width in mm */ + int height; /* display height in mm */ + unsigned output_format; +}; + +struct msmfb_callback { + void (*func)(struct msmfb_callback *); +}; + +enum { + MSM_MDDI_PMDH_INTERFACE, + MSM_MDDI_EMDH_INTERFACE, + MSM_EBI2_INTERFACE, +}; + +#define MSMFB_CAP_PARTIAL_UPDATES (1 << 0) + +struct msm_panel_data { + /* turns off the fb memory */ + int (*suspend)(struct msm_panel_data *); + /* turns on the fb memory */ + int (*resume)(struct msm_panel_data *); + /* turns off the panel */ + int (*blank)(struct msm_panel_data *); + /* turns on the panel */ + int (*unblank)(struct msm_panel_data *); + void (*wait_vsync)(struct msm_panel_data *); + void (*request_vsync)(struct msm_panel_data *, struct msmfb_callback *); + void (*clear_vsync)(struct msm_panel_data *); + /* from the enum above */ + unsigned interface_type; + /* data to be passed to the fb driver */ + struct msm_fb_data *fb_data; + + /* capabilities supported by the panel */ + uint32_t caps; +}; + +struct msm_mddi_client_data { + void (*suspend)(struct msm_mddi_client_data *); + void (*resume)(struct msm_mddi_client_data *); + void (*activate_link)(struct msm_mddi_client_data *); + void (*remote_write)(struct msm_mddi_client_data *, uint32_t val, + uint32_t reg); + uint32_t (*remote_read)(struct msm_mddi_client_data *, uint32_t reg); + void (*auto_hibernate)(struct msm_mddi_client_data *, int); + /* custom data that needs to be passed from the board file to a + * particular client */ + void *private_client_data; + struct resource *fb_resource; + /* from the list above */ + unsigned interface_type; +}; + +struct msm_mddi_platform_data { + unsigned int clk_rate; + void (*power_client)(struct msm_mddi_client_data *, int on); + + /* fixup the mfr name, product id */ + void (*fixup)(uint16_t *mfr_name, uint16_t *product_id); + + struct resource *fb_resource; /*optional*/ + /* number of clients in the list that follows */ + int num_clients; + /* array of client information of clients */ + struct { + unsigned product_id; /* mfr id in top 16 bits, product id + * in lower 16 bits + */ + char *name; /* the device name will be the platform + * device name registered for the client, + * it should match the name of the associated + * driver + */ + unsigned id; /* id for mddi client device node, will also + * be used as device id of panel devices, if + * the client device will have multiple panels + * space must be left here for them + */ + void *client_data; /* required private client data */ + unsigned int clk_rate; /* optional: if the client requires a + * different mddi clk rate + */ + } client_platform_data[]; +}; + +struct mdp_blit_req; +struct fb_info; +struct mdp_device { + struct device dev; + void (*dma)(struct mdp_device *mpd, uint32_t addr, + uint32_t stride, uint32_t w, uint32_t h, uint32_t x, + uint32_t y, struct msmfb_callback *callback, int interface); + void (*dma_wait)(struct mdp_device *mdp); + int (*blit)(struct mdp_device *mdp, struct fb_info *fb, + struct mdp_blit_req *req); + void (*set_grp_disp)(struct mdp_device *mdp, uint32_t disp_id); +}; + +struct class_interface; +int register_mdp_client(struct class_interface *class_intf); + +/**** private client data structs go below this line ***/ + +struct msm_mddi_bridge_platform_data { + /* from board file */ + int (*init)(struct msm_mddi_bridge_platform_data *, + struct msm_mddi_client_data *); + int (*uninit)(struct msm_mddi_bridge_platform_data *, + struct msm_mddi_client_data *); + /* passed to panel for use by the fb driver */ + int (*blank)(struct msm_mddi_bridge_platform_data *, + struct msm_mddi_client_data *); + int (*unblank)(struct msm_mddi_bridge_platform_data *, + struct msm_mddi_client_data *); + struct msm_fb_data fb_data; +}; + + + +#endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h new file mode 100644 index 00000000000..cfff0e74f12 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h @@ -0,0 +1,139 @@ +/* arch/arm/mach-msm/include/mach/msm_iomap.h + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * The MSM peripherals are spread all over across 768MB of physical + * space, which makes just having a simple IO_ADDRESS macro to slide + * them into the right virtual location rough. Instead, we will + * provide a master phys->virt mapping for peripherals here. + * + */ + +#ifndef __ASM_ARCH_MSM_IOMAP_7X00_H +#define __ASM_ARCH_MSM_IOMAP_7X00_H + +#include <asm/sizes.h> + +/* Physical base address and size of peripherals. + * Ordered by the virtual base addresses they will be mapped at. + * + * MSM_VIC_BASE must be an value that can be loaded via a "mov" + * instruction, otherwise entry-macro.S will not compile. + * + * If you add or remove entries here, you'll want to edit the + * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your + * changes. + * + */ + +#ifdef __ASSEMBLY__ +#define IOMEM(x) x +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + +#define MSM_VIC_BASE IOMEM(0xE0000000) +#define MSM_VIC_PHYS 0xC0000000 +#define MSM_VIC_SIZE SZ_4K + +#define MSM_CSR_BASE IOMEM(0xE0001000) +#define MSM_CSR_PHYS 0xC0100000 +#define MSM_CSR_SIZE SZ_4K + +#define MSM_GPT_PHYS MSM_CSR_PHYS +#define MSM_GPT_BASE MSM_CSR_BASE +#define MSM_GPT_SIZE SZ_4K + +#define MSM_DMOV_BASE IOMEM(0xE0002000) +#define MSM_DMOV_PHYS 0xA9700000 +#define MSM_DMOV_SIZE SZ_4K + +#define MSM_GPIO1_BASE IOMEM(0xE0003000) +#define MSM_GPIO1_PHYS 0xA9200000 +#define MSM_GPIO1_SIZE SZ_4K + +#define MSM_GPIO2_BASE IOMEM(0xE0004000) +#define MSM_GPIO2_PHYS 0xA9300000 +#define MSM_GPIO2_SIZE SZ_4K + +#define MSM_CLK_CTL_BASE IOMEM(0xE0005000) +#define MSM_CLK_CTL_PHYS 0xA8600000 +#define MSM_CLK_CTL_SIZE SZ_4K + +#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000) +#define MSM_SHARED_RAM_PHYS 0x01F00000 +#define MSM_SHARED_RAM_SIZE SZ_1M + +#define MSM_UART1_PHYS 0xA9A00000 +#define MSM_UART1_SIZE SZ_4K + +#define MSM_UART2_PHYS 0xA9B00000 +#define MSM_UART2_SIZE SZ_4K + +#define MSM_UART3_PHYS 0xA9C00000 +#define MSM_UART3_SIZE SZ_4K + +#ifdef CONFIG_MSM_DEBUG_UART +#define MSM_DEBUG_UART_BASE 0xE1000000 +#if CONFIG_MSM_DEBUG_UART == 1 +#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS +#elif CONFIG_MSM_DEBUG_UART == 2 +#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS +#elif CONFIG_MSM_DEBUG_UART == 3 +#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS +#endif +#define MSM_DEBUG_UART_SIZE SZ_4K +#endif + +#define MSM_SDC1_PHYS 0xA0400000 +#define MSM_SDC1_SIZE SZ_4K + +#define MSM_SDC2_PHYS 0xA0500000 +#define MSM_SDC2_SIZE SZ_4K + +#define MSM_SDC3_PHYS 0xA0600000 +#define MSM_SDC3_SIZE SZ_4K + +#define MSM_SDC4_PHYS 0xA0700000 +#define MSM_SDC4_SIZE SZ_4K + +#define MSM_I2C_PHYS 0xA9900000 +#define MSM_I2C_SIZE SZ_4K + +#define MSM_HSUSB_PHYS 0xA0800000 +#define MSM_HSUSB_SIZE SZ_4K + +#define MSM_PMDH_PHYS 0xAA600000 +#define MSM_PMDH_SIZE SZ_4K + +#define MSM_EMDH_PHYS 0xAA700000 +#define MSM_EMDH_SIZE SZ_4K + +#define MSM_MDP_PHYS 0xAA200000 +#define MSM_MDP_SIZE 0x000F0000 + +#define MSM_MDC_PHYS 0xAA500000 +#define MSM_MDC_SIZE SZ_1M + +#define MSM_AD5_PHYS 0xAC000000 +#define MSM_AD5_SIZE (SZ_1M*13) + + +#if defined(CONFIG_ARCH_MSM7X30) +#define MSM_GCC_BASE IOMEM(0xF8009000) +#define MSM_GCC_PHYS 0xC0182000 +#define MSM_GCC_SIZE SZ_4K +#endif + +#endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h new file mode 100644 index 00000000000..8a00c2defbc --- /dev/null +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * The MSM peripherals are spread all over across 768MB of physical + * space, which makes just having a simple IO_ADDRESS macro to slide + * them into the right virtual location rough. Instead, we will + * provide a master phys->virt mapping for peripherals here. + * + */ + +#ifndef __ASM_ARCH_MSM_IOMAP_7X30_H +#define __ASM_ARCH_MSM_IOMAP_7X30_H + +/* Physical base address and size of peripherals. + * Ordered by the virtual base addresses they will be mapped at. + * + * MSM_VIC_BASE must be an value that can be loaded via a "mov" + * instruction, otherwise entry-macro.S will not compile. + * + * If you add or remove entries here, you'll want to edit the + * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your + * changes. + * + */ + +#define MSM_VIC_BASE IOMEM(0xE0000000) +#define MSM_VIC_PHYS 0xC0080000 +#define MSM_VIC_SIZE SZ_4K + +#define MSM_CSR_BASE IOMEM(0xE0001000) +#define MSM_CSR_PHYS 0xC0100000 +#define MSM_CSR_SIZE SZ_4K + +#define MSM_TMR_PHYS MSM_CSR_PHYS +#define MSM_TMR_BASE MSM_CSR_BASE +#define MSM_TMR_SIZE SZ_4K + +#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) +#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) + +#define MSM_DMOV_BASE IOMEM(0xE0002000) +#define MSM_DMOV_PHYS 0xAC400000 +#define MSM_DMOV_SIZE SZ_4K + +#define MSM_GPIO1_BASE IOMEM(0xE0003000) +#define MSM_GPIO1_PHYS 0xAC001000 +#define MSM_GPIO1_SIZE SZ_4K + +#define MSM_GPIO2_BASE IOMEM(0xE0004000) +#define MSM_GPIO2_PHYS 0xAC101000 +#define MSM_GPIO2_SIZE SZ_4K + +#define MSM_CLK_CTL_BASE IOMEM(0xE0005000) +#define MSM_CLK_CTL_PHYS 0xAB800000 +#define MSM_CLK_CTL_SIZE SZ_4K + +#define MSM_CLK_CTL_SH2_BASE IOMEM(0xE0006000) +#define MSM_CLK_CTL_SH2_PHYS 0xABA01000 +#define MSM_CLK_CTL_SH2_SIZE SZ_4K + +#define MSM_ACC_BASE IOMEM(0xE0007000) +#define MSM_ACC_PHYS 0xC0101000 +#define MSM_ACC_SIZE SZ_4K + +#define MSM_SAW_BASE IOMEM(0xE0008000) +#define MSM_SAW_PHYS 0xC0102000 +#define MSM_SAW_SIZE SZ_4K + +#define MSM_GCC_BASE IOMEM(0xE0009000) +#define MSM_GCC_PHYS 0xC0182000 +#define MSM_GCC_SIZE SZ_4K + +#define MSM_TCSR_BASE IOMEM(0xE000A000) +#define MSM_TCSR_PHYS 0xAB600000 +#define MSM_TCSR_SIZE SZ_4K + +#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000) +#define MSM_SHARED_RAM_PHYS 0x00100000 +#define MSM_SHARED_RAM_SIZE SZ_1M + +#define MSM_UART1_PHYS 0xACA00000 +#define MSM_UART1_SIZE SZ_4K + +#define MSM_UART2_PHYS 0xACB00000 +#define MSM_UART2_SIZE SZ_4K + +#define MSM_UART3_PHYS 0xACC00000 +#define MSM_UART3_SIZE SZ_4K + +#ifdef CONFIG_MSM_DEBUG_UART +#define MSM_DEBUG_UART_BASE 0xE1000000 +#if CONFIG_MSM_DEBUG_UART == 1 +#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS +#elif CONFIG_MSM_DEBUG_UART == 2 +#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS +#elif CONFIG_MSM_DEBUG_UART == 3 +#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS +#endif +#define MSM_DEBUG_UART_SIZE SZ_4K +#endif + +#define MSM_MDC_BASE IOMEM(0xE0200000) +#define MSM_MDC_PHYS 0xAA500000 +#define MSM_MDC_SIZE SZ_1M + +#define MSM_AD5_BASE IOMEM(0xE0300000) +#define MSM_AD5_PHYS 0xA7000000 +#define MSM_AD5_SIZE (SZ_1M*13) + +#endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h new file mode 100644 index 00000000000..acc819eb76e --- /dev/null +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * The MSM peripherals are spread all over across 768MB of physical + * space, which makes just having a simple IO_ADDRESS macro to slide + * them into the right virtual location rough. Instead, we will + * provide a master phys->virt mapping for peripherals here. + * + */ + +#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H +#define __ASM_ARCH_MSM_IOMAP_8X50_H + +/* Physical base address and size of peripherals. + * Ordered by the virtual base addresses they will be mapped at. + * + * MSM_VIC_BASE must be an value that can be loaded via a "mov" + * instruction, otherwise entry-macro.S will not compile. + * + * If you add or remove entries here, you'll want to edit the + * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your + * changes. + * + */ + +#define MSM_VIC_BASE IOMEM(0xE0000000) +#define MSM_VIC_PHYS 0xAC000000 +#define MSM_VIC_SIZE SZ_4K + +#define MSM_CSR_BASE IOMEM(0xE0001000) +#define MSM_CSR_PHYS 0xAC100000 +#define MSM_CSR_SIZE SZ_4K + +#define MSM_TMR_PHYS MSM_CSR_PHYS +#define MSM_TMR_BASE MSM_CSR_BASE +#define MSM_TMR_SIZE SZ_4K + +#define MSM_GPT_BASE MSM_TMR_BASE +#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10) + +#define MSM_DMOV_BASE IOMEM(0xE0002000) +#define MSM_DMOV_PHYS 0xA9700000 +#define MSM_DMOV_SIZE SZ_4K + +#define MSM_GPIO1_BASE IOMEM(0xE0003000) +#define MSM_GPIO1_PHYS 0xA9000000 +#define MSM_GPIO1_SIZE SZ_4K + +#define MSM_GPIO2_BASE IOMEM(0xE0004000) +#define MSM_GPIO2_PHYS 0xA9100000 +#define MSM_GPIO2_SIZE SZ_4K + +#define MSM_CLK_CTL_BASE IOMEM(0xE0005000) +#define MSM_CLK_CTL_PHYS 0xA8600000 +#define MSM_CLK_CTL_SIZE SZ_4K + +#define MSM_SIRC_BASE IOMEM(0xE1006000) +#define MSM_SIRC_PHYS 0xAC200000 +#define MSM_SIRC_SIZE SZ_4K + +#define MSM_SCPLL_BASE IOMEM(0xE1007000) +#define MSM_SCPLL_PHYS 0xA8800000 +#define MSM_SCPLL_SIZE SZ_4K + +#ifdef CONFIG_MSM_SOC_REV_A +#define MSM_SMI_BASE 0xE0000000 +#else +#define MSM_SMI_BASE 0x00000000 +#endif + +#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000) +#define MSM_SHARED_RAM_PHYS (MSM_SMI_BASE + 0x00100000) +#define MSM_SHARED_RAM_SIZE SZ_1M + +#define MSM_UART1_PHYS 0xA9A00000 +#define MSM_UART1_SIZE SZ_4K + +#define MSM_UART2_PHYS 0xA9B00000 +#define MSM_UART2_SIZE SZ_4K + +#define MSM_UART3_PHYS 0xA9C00000 +#define MSM_UART3_SIZE SZ_4K + +#ifdef CONFIG_MSM_DEBUG_UART +#define MSM_DEBUG_UART_BASE 0xE1000000 +#if CONFIG_MSM_DEBUG_UART == 1 +#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS +#elif CONFIG_MSM_DEBUG_UART == 2 +#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS +#elif CONFIG_MSM_DEBUG_UART == 3 +#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS +#endif +#define MSM_DEBUG_UART_SIZE SZ_4K +#endif + +#define MSM_MDC_BASE IOMEM(0xE0200000) +#define MSM_MDC_PHYS 0xAA500000 +#define MSM_MDC_SIZE SZ_1M + +#define MSM_AD5_BASE IOMEM(0xE0300000) +#define MSM_AD5_PHYS 0xAC000000 +#define MSM_AD5_SIZE (SZ_1M*13) + + +#define MSM_I2C_SIZE SZ_4K +#define MSM_I2C_PHYS 0xA9900000 + +#define MSM_HSUSB_PHYS 0xA0800000 +#define MSM_HSUSB_SIZE SZ_1K + +#define MSM_NAND_PHYS 0xA0A00000 + + +#define MSM_TSIF_PHYS (0xa0100000) +#define MSM_TSIF_SIZE (0x200) + +#define MSM_TSSC_PHYS 0xAA300000 + +#define MSM_UART1DM_PHYS 0xA0200000 +#define MSM_UART2DM_PHYS 0xA0900000 + + +#define MSM_SDC1_PHYS 0xA0400000 +#define MSM_SDC1_SIZE SZ_4K + +#define MSM_SDC2_PHYS 0xA0500000 +#define MSM_SDC2_SIZE SZ_4K + +#define MSM_SDC3_PHYS 0xA0600000 +#define MSM_SDC3_SIZE SZ_4K + +#define MSM_SDC4_PHYS 0xA0700000 +#define MSM_SDC4_SIZE SZ_4K + +#endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 9dae1a98c77..e6b1821cc4e 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -1,6 +1,6 @@ -/* arch/arm/mach-msm/include/mach/msm_iomap.h - * +/* * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -43,91 +43,12 @@ #define IOMEM(x) ((void __force __iomem *)(x)) #endif -#define MSM_VIC_BASE IOMEM(0xE0000000) -#define MSM_VIC_PHYS 0xC0000000 -#define MSM_VIC_SIZE SZ_4K - -#define MSM_CSR_BASE IOMEM(0xE0001000) -#define MSM_CSR_PHYS 0xC0100000 -#define MSM_CSR_SIZE SZ_4K - -#define MSM_GPT_PHYS MSM_CSR_PHYS -#define MSM_GPT_BASE MSM_CSR_BASE -#define MSM_GPT_SIZE SZ_4K - -#define MSM_DMOV_BASE IOMEM(0xE0002000) -#define MSM_DMOV_PHYS 0xA9700000 -#define MSM_DMOV_SIZE SZ_4K - -#define MSM_GPIO1_BASE IOMEM(0xE0003000) -#define MSM_GPIO1_PHYS 0xA9200000 -#define MSM_GPIO1_SIZE SZ_4K - -#define MSM_GPIO2_BASE IOMEM(0xE0004000) -#define MSM_GPIO2_PHYS 0xA9300000 -#define MSM_GPIO2_SIZE SZ_4K - -#define MSM_CLK_CTL_BASE IOMEM(0xE0005000) -#define MSM_CLK_CTL_PHYS 0xA8600000 -#define MSM_CLK_CTL_SIZE SZ_4K - -#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000) -#define MSM_SHARED_RAM_PHYS 0x01F00000 -#define MSM_SHARED_RAM_SIZE SZ_1M - -#define MSM_UART1_PHYS 0xA9A00000 -#define MSM_UART1_SIZE SZ_4K - -#define MSM_UART2_PHYS 0xA9B00000 -#define MSM_UART2_SIZE SZ_4K - -#define MSM_UART3_PHYS 0xA9C00000 -#define MSM_UART3_SIZE SZ_4K - -#ifdef CONFIG_MSM_DEBUG_UART -#define MSM_DEBUG_UART_BASE 0xE1000000 -#if CONFIG_MSM_DEBUG_UART == 1 -#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS -#elif CONFIG_MSM_DEBUG_UART == 2 -#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS -#elif CONFIG_MSM_DEBUG_UART == 3 -#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS -#endif -#define MSM_DEBUG_UART_SIZE SZ_4K +#if defined(CONFIG_ARCH_MSM7X30) +#include "msm_iomap-7x30.h" +#elif defined(CONFIG_ARCH_QSD8X50) +#include "msm_iomap-8x50.h" +#else +#include "msm_iomap-7x00.h" #endif -#define MSM_SDC1_PHYS 0xA0400000 -#define MSM_SDC1_SIZE SZ_4K - -#define MSM_SDC2_PHYS 0xA0500000 -#define MSM_SDC2_SIZE SZ_4K - -#define MSM_SDC3_PHYS 0xA0600000 -#define MSM_SDC3_SIZE SZ_4K - -#define MSM_SDC4_PHYS 0xA0700000 -#define MSM_SDC4_SIZE SZ_4K - -#define MSM_I2C_PHYS 0xA9900000 -#define MSM_I2C_SIZE SZ_4K - -#define MSM_HSUSB_PHYS 0xA0800000 -#define MSM_HSUSB_SIZE SZ_4K - -#define MSM_PMDH_PHYS 0xAA600000 -#define MSM_PMDH_SIZE SZ_4K - -#define MSM_EMDH_PHYS 0xAA700000 -#define MSM_EMDH_SIZE SZ_4K - -#define MSM_MDP_PHYS 0xAA200000 -#define MSM_MDP_SIZE 0x000F0000 - -#define MSM_MDC_PHYS 0xAA500000 -#define MSM_MDC_SIZE SZ_1M - -#define MSM_AD5_PHYS 0xAC000000 -#define MSM_AD5_SIZE (SZ_1M*13) - - #endif diff --git a/arch/arm/mach-msm/include/mach/msm_smd.h b/arch/arm/mach-msm/include/mach/msm_smd.h new file mode 100644 index 00000000000..029463ec875 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/msm_smd.h @@ -0,0 +1,109 @@ +/* linux/include/asm-arm/arch-msm/msm_smd.h + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_SMD_H +#define __ASM_ARCH_MSM_SMD_H + +typedef struct smd_channel smd_channel_t; + +extern int (*msm_check_for_modem_crash)(void); + +/* warning: notify() may be called before open returns */ +int smd_open(const char *name, smd_channel_t **ch, void *priv, + void (*notify)(void *priv, unsigned event)); + +#define SMD_EVENT_DATA 1 +#define SMD_EVENT_OPEN 2 +#define SMD_EVENT_CLOSE 3 + +int smd_close(smd_channel_t *ch); + +/* passing a null pointer for data reads and discards */ +int smd_read(smd_channel_t *ch, void *data, int len); + +/* Write to stream channels may do a partial write and return +** the length actually written. +** Write to packet channels will never do a partial write -- +** it will return the requested length written or an error. +*/ +int smd_write(smd_channel_t *ch, const void *data, int len); +int smd_write_atomic(smd_channel_t *ch, const void *data, int len); + +int smd_write_avail(smd_channel_t *ch); +int smd_read_avail(smd_channel_t *ch); + +/* Returns the total size of the current packet being read. +** Returns 0 if no packets available or a stream channel. +*/ +int smd_cur_packet_size(smd_channel_t *ch); + +/* used for tty unthrottling and the like -- causes the notify() +** callback to be called from the same lock context as is used +** when it is called from channel updates +*/ +void smd_kick(smd_channel_t *ch); + + +#if 0 +/* these are interruptable waits which will block you until the specified +** number of bytes are readable or writable. +*/ +int smd_wait_until_readable(smd_channel_t *ch, int bytes); +int smd_wait_until_writable(smd_channel_t *ch, int bytes); +#endif + +typedef enum { + SMD_PORT_DS = 0, + SMD_PORT_DIAG, + SMD_PORT_RPC_CALL, + SMD_PORT_RPC_REPLY, + SMD_PORT_BT, + SMD_PORT_CONTROL, + SMD_PORT_MEMCPY_SPARE1, + SMD_PORT_DATA1, + SMD_PORT_DATA2, + SMD_PORT_DATA3, + SMD_PORT_DATA4, + SMD_PORT_DATA5, + SMD_PORT_DATA6, + SMD_PORT_DATA7, + SMD_PORT_DATA8, + SMD_PORT_DATA9, + SMD_PORT_DATA10, + SMD_PORT_DATA11, + SMD_PORT_DATA12, + SMD_PORT_DATA13, + SMD_PORT_DATA14, + SMD_PORT_DATA15, + SMD_PORT_DATA16, + SMD_PORT_DATA17, + SMD_PORT_DATA18, + SMD_PORT_DATA19, + SMD_PORT_DATA20, + SMD_PORT_GPS_NMEA, + SMD_PORT_BRIDGE_1, + SMD_PORT_BRIDGE_2, + SMD_PORT_BRIDGE_3, + SMD_PORT_BRIDGE_4, + SMD_PORT_BRIDGE_5, + SMD_PORT_LOOPBACK, + SMD_PORT_CS_APPS_MODEM, + SMD_PORT_CS_APPS_DSP, + SMD_PORT_CS_MODEM_DSP, + SMD_NUM_PORTS, +} smd_port_id_type; + +#endif diff --git a/arch/arm/mach-msm/include/mach/sirc.h b/arch/arm/mach-msm/include/mach/sirc.h new file mode 100644 index 00000000000..7281337ee28 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/sirc.h @@ -0,0 +1,115 @@ +/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ASM_ARCH_MSM_SIRC_H +#define __ASM_ARCH_MSM_SIRC_H + +struct sirc_regs_t { + void *int_enable; + void *int_enable_clear; + void *int_enable_set; + void *int_type; + void *int_polarity; + void *int_clear; +}; + +struct sirc_cascade_regs { + void *int_status; + unsigned int cascade_irq; +}; + +void msm_init_sirc(void); +void msm_sirc_enter_sleep(void); +void msm_sirc_exit_sleep(void); + +#if defined(CONFIG_ARCH_MSM_SCORPION) + +#include <mach/msm_iomap.h> + +/* + * Secondary interrupt controller interrupts + */ + +#define FIRST_SIRC_IRQ (NR_MSM_IRQS + NR_GPIO_IRQS) + +#define INT_UART1 (FIRST_SIRC_IRQ + 0) +#define INT_UART2 (FIRST_SIRC_IRQ + 1) +#define INT_UART3 (FIRST_SIRC_IRQ + 2) +#define INT_UART1_RX (FIRST_SIRC_IRQ + 3) +#define INT_UART2_RX (FIRST_SIRC_IRQ + 4) +#define INT_UART3_RX (FIRST_SIRC_IRQ + 5) +#define INT_SPI_INPUT (FIRST_SIRC_IRQ + 6) +#define INT_SPI_OUTPUT (FIRST_SIRC_IRQ + 7) +#define INT_SPI_ERROR (FIRST_SIRC_IRQ + 8) +#define INT_GPIO_GROUP1 (FIRST_SIRC_IRQ + 9) +#define INT_GPIO_GROUP2 (FIRST_SIRC_IRQ + 10) +#define INT_GPIO_GROUP1_SECURE (FIRST_SIRC_IRQ + 11) +#define INT_GPIO_GROUP2_SECURE (FIRST_SIRC_IRQ + 12) +#define INT_AVS_SVIC (FIRST_SIRC_IRQ + 13) +#define INT_AVS_REQ_UP (FIRST_SIRC_IRQ + 14) +#define INT_AVS_REQ_DOWN (FIRST_SIRC_IRQ + 15) +#define INT_PBUS_ERR (FIRST_SIRC_IRQ + 16) +#define INT_AXI_ERR (FIRST_SIRC_IRQ + 17) +#define INT_SMI_ERR (FIRST_SIRC_IRQ + 18) +#define INT_EBI1_ERR (FIRST_SIRC_IRQ + 19) +#define INT_IMEM_ERR (FIRST_SIRC_IRQ + 20) +#define INT_TEMP_SENSOR (FIRST_SIRC_IRQ + 21) +#define INT_TV_ENC (FIRST_SIRC_IRQ + 22) +#define INT_GRP2D (FIRST_SIRC_IRQ + 23) +#define INT_GSBI_QUP (FIRST_SIRC_IRQ + 24) +#define INT_SC_ACG (FIRST_SIRC_IRQ + 25) +#define INT_WDT0 (FIRST_SIRC_IRQ + 26) +#define INT_WDT1 (FIRST_SIRC_IRQ + 27) + +#if defined(CONFIG_MSM_SOC_REV_A) +#define NR_SIRC_IRQS 28 +#define SIRC_MASK 0x0FFFFFFF +#else +#define NR_SIRC_IRQS 23 +#define SIRC_MASK 0x007FFFFF +#endif + +#define LAST_SIRC_IRQ (FIRST_SIRC_IRQ + NR_SIRC_IRQS - 1) + +#define SPSS_SIRC_INT_SELECT (MSM_SIRC_BASE + 0x00) +#define SPSS_SIRC_INT_ENABLE (MSM_SIRC_BASE + 0x04) +#define SPSS_SIRC_INT_ENABLE_CLEAR (MSM_SIRC_BASE + 0x08) +#define SPSS_SIRC_INT_ENABLE_SET (MSM_SIRC_BASE + 0x0C) +#define SPSS_SIRC_INT_TYPE (MSM_SIRC_BASE + 0x10) +#define SPSS_SIRC_INT_POLARITY (MSM_SIRC_BASE + 0x14) +#define SPSS_SIRC_SECURITY (MSM_SIRC_BASE + 0x18) +#define SPSS_SIRC_IRQ_STATUS (MSM_SIRC_BASE + 0x1C) +#define SPSS_SIRC_IRQ1_STATUS (MSM_SIRC_BASE + 0x20) +#define SPSS_SIRC_RAW_STATUS (MSM_SIRC_BASE + 0x24) +#define SPSS_SIRC_INT_CLEAR (MSM_SIRC_BASE + 0x28) +#define SPSS_SIRC_SOFT_INT (MSM_SIRC_BASE + 0x2C) + +#endif + +#endif diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h index 574ccc493da..d2e83f42ba1 100644 --- a/arch/arm/mach-msm/include/mach/system.h +++ b/arch/arm/mach-msm/include/mach/system.h @@ -21,3 +21,8 @@ static inline void arch_reset(char mode, const char *cmd) { for (;;) ; /* depends on IPC w/ other core */ } + +/* low level hardware reset hook -- for example, hitting the + * PSHOLD line on the PMIC to hard reset the system + */ +extern void (*msm_hw_reset_hook)(void); diff --git a/arch/arm/mach-msm/include/mach/vreg.h b/arch/arm/mach-msm/include/mach/vreg.h index 9f9e25cb718..6626e7864e2 100644 --- a/arch/arm/mach-msm/include/mach/vreg.h +++ b/arch/arm/mach-msm/include/mach/vreg.h @@ -23,7 +23,7 @@ struct vreg *vreg_get(struct device *dev, const char *id); void vreg_put(struct vreg *vreg); int vreg_enable(struct vreg *vreg); -void vreg_disable(struct vreg *vreg); +int vreg_disable(struct vreg *vreg); int vreg_set_level(struct vreg *vreg, unsigned mv); #endif diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index 05f96b780aa..1c05060b5f3 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -1,8 +1,9 @@ /* arch/arm/mach-msm/io.c * - * MSM7K io support + * MSM7K, QSD io support * * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -34,6 +35,8 @@ .type = MT_DEVICE_NONSHARED, \ } +#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ + || defined(CONFIG_ARCH_MSM7X25) static struct map_desc msm_io_desc[] __initdata = { MSM_DEVICE(VIC), MSM_DEVICE(CSR), @@ -45,9 +48,12 @@ static struct map_desc msm_io_desc[] __initdata = { #ifdef CONFIG_MSM_DEBUG_UART MSM_DEVICE(DEBUG_UART), #endif +#ifdef CONFIG_ARCH_MSM7X30 + MSM_DEVICE(GCC), +#endif { .virtual = (unsigned long) MSM_SHARED_RAM_BASE, - .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), + .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), .length = MSM_SHARED_RAM_SIZE, .type = MT_DEVICE, }, @@ -60,9 +66,72 @@ void __init msm_map_common_io(void) * pages are peripheral interface or not. */ asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0)); - iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc)); } +#endif + +#ifdef CONFIG_ARCH_QSD8X50 +static struct map_desc qsd8x50_io_desc[] __initdata = { + MSM_DEVICE(VIC), + MSM_DEVICE(CSR), + MSM_DEVICE(TMR), + MSM_DEVICE(DMOV), + MSM_DEVICE(GPIO1), + MSM_DEVICE(GPIO2), + MSM_DEVICE(CLK_CTL), + MSM_DEVICE(SIRC), + MSM_DEVICE(SCPLL), + MSM_DEVICE(AD5), + MSM_DEVICE(MDC), +#ifdef CONFIG_MSM_DEBUG_UART + MSM_DEVICE(DEBUG_UART), +#endif + { + .virtual = (unsigned long) MSM_SHARED_RAM_BASE, + .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), + .length = MSM_SHARED_RAM_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init msm_map_qsd8x50_io(void) +{ + iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc)); +} +#endif /* CONFIG_ARCH_QSD8X50 */ + +#ifdef CONFIG_ARCH_MSM7X30 +static struct map_desc msm7x30_io_desc[] __initdata = { + MSM_DEVICE(VIC), + MSM_DEVICE(CSR), + MSM_DEVICE(TMR), + MSM_DEVICE(DMOV), + MSM_DEVICE(GPIO1), + MSM_DEVICE(GPIO2), + MSM_DEVICE(CLK_CTL), + MSM_DEVICE(CLK_CTL_SH2), + MSM_DEVICE(AD5), + MSM_DEVICE(MDC), + MSM_DEVICE(ACC), + MSM_DEVICE(SAW), + MSM_DEVICE(GCC), + MSM_DEVICE(TCSR), +#ifdef CONFIG_MSM_DEBUG_UART + MSM_DEVICE(DEBUG_UART), +#endif + { + .virtual = (unsigned long) MSM_SHARED_RAM_BASE, + .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), + .length = MSM_SHARED_RAM_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init msm_map_msm7x30_io(void) +{ + iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc)); +} +#endif /* CONFIG_ARCH_MSM7X30 */ void __iomem * __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c new file mode 100644 index 00000000000..99f2c347303 --- /dev/null +++ b/arch/arm/mach-msm/irq-vic.c @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2009, Code Aurora Forum. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/ptrace.h> +#include <linux/timer.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <asm/cacheflush.h> + +#include <mach/hardware.h> + +#include <mach/msm_iomap.h> + +#include "smd_private.h" + +enum { + IRQ_DEBUG_SLEEP_INT_TRIGGER = 1U << 0, + IRQ_DEBUG_SLEEP_INT = 1U << 1, + IRQ_DEBUG_SLEEP_ABORT = 1U << 2, + IRQ_DEBUG_SLEEP = 1U << 3, + IRQ_DEBUG_SLEEP_REQUEST = 1U << 4, +}; +static int msm_irq_debug_mask; +module_param_named(debug_mask, msm_irq_debug_mask, int, + S_IRUGO | S_IWUSR | S_IWGRP); + +#define VIC_REG(off) (MSM_VIC_BASE + (off)) +#define VIC_INT_TO_REG_ADDR(base, irq) (base + (irq / 32) * 4) +#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 3) + +#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */ +#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */ +#define VIC_INT_SELECT2 VIC_REG(0x0008) /* 1: FIQ, 0: IRQ */ +#define VIC_INT_SELECT3 VIC_REG(0x000C) /* 1: FIQ, 0: IRQ */ +#define VIC_INT_EN0 VIC_REG(0x0010) +#define VIC_INT_EN1 VIC_REG(0x0014) +#define VIC_INT_EN2 VIC_REG(0x0018) +#define VIC_INT_EN3 VIC_REG(0x001C) +#define VIC_INT_ENCLEAR0 VIC_REG(0x0020) +#define VIC_INT_ENCLEAR1 VIC_REG(0x0024) +#define VIC_INT_ENCLEAR2 VIC_REG(0x0028) +#define VIC_INT_ENCLEAR3 VIC_REG(0x002C) +#define VIC_INT_ENSET0 VIC_REG(0x0030) +#define VIC_INT_ENSET1 VIC_REG(0x0034) +#define VIC_INT_ENSET2 VIC_REG(0x0038) +#define VIC_INT_ENSET3 VIC_REG(0x003C) +#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */ +#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */ +#define VIC_INT_TYPE2 VIC_REG(0x0048) /* 1: EDGE, 0: LEVEL */ +#define VIC_INT_TYPE3 VIC_REG(0x004C) /* 1: EDGE, 0: LEVEL */ +#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */ +#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */ +#define VIC_INT_POLARITY2 VIC_REG(0x0058) /* 1: NEG, 0: POS */ +#define VIC_INT_POLARITY3 VIC_REG(0x005C) /* 1: NEG, 0: POS */ +#define VIC_NO_PEND_VAL VIC_REG(0x0060) + +#if defined(CONFIG_ARCH_MSM_SCORPION) +#define VIC_NO_PEND_VAL_FIQ VIC_REG(0x0064) +#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */ +#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE SC VIC */ +#else +#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */ +#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */ +#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */ +#endif + +#define VIC_IRQ_STATUS0 VIC_REG(0x0080) +#define VIC_IRQ_STATUS1 VIC_REG(0x0084) +#define VIC_IRQ_STATUS2 VIC_REG(0x0088) +#define VIC_IRQ_STATUS3 VIC_REG(0x008C) +#define VIC_FIQ_STATUS0 VIC_REG(0x0090) +#define VIC_FIQ_STATUS1 VIC_REG(0x0094) +#define VIC_FIQ_STATUS2 VIC_REG(0x0098) +#define VIC_FIQ_STATUS3 VIC_REG(0x009C) +#define VIC_RAW_STATUS0 VIC_REG(0x00A0) +#define VIC_RAW_STATUS1 VIC_REG(0x00A4) +#define VIC_RAW_STATUS2 VIC_REG(0x00A8) +#define VIC_RAW_STATUS3 VIC_REG(0x00AC) +#define VIC_INT_CLEAR0 VIC_REG(0x00B0) +#define VIC_INT_CLEAR1 VIC_REG(0x00B4) +#define VIC_INT_CLEAR2 VIC_REG(0x00B8) +#define VIC_INT_CLEAR3 VIC_REG(0x00BC) +#define VIC_SOFTINT0 VIC_REG(0x00C0) +#define VIC_SOFTINT1 VIC_REG(0x00C4) +#define VIC_SOFTINT2 VIC_REG(0x00C8) +#define VIC_SOFTINT3 VIC_REG(0x00CC) +#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */ +#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */ +#define VIC_IRQ_VEC_WR VIC_REG(0x00D8) + +#if defined(CONFIG_ARCH_MSM_SCORPION) +#define VIC_FIQ_VEC_RD VIC_REG(0x00DC) +#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0) +#define VIC_FIQ_VEC_WR VIC_REG(0x00E4) +#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E8) +#define VIC_IRQ_IN_STACK VIC_REG(0x00EC) +#define VIC_FIQ_IN_SERVICE VIC_REG(0x00F0) +#define VIC_FIQ_IN_STACK VIC_REG(0x00F4) +#define VIC_TEST_BUS_SEL VIC_REG(0x00F8) +#define VIC_IRQ_CTRL_CONFIG VIC_REG(0x00FC) +#else +#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0) +#define VIC_IRQ_IN_STACK VIC_REG(0x00E4) +#define VIC_TEST_BUS_SEL VIC_REG(0x00E8) +#endif + +#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4)) +#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4)) + +#if defined(CONFIG_ARCH_MSM7X30) +#define VIC_NUM_REGS 4 +#else +#define VIC_NUM_REGS 2 +#endif + +#if VIC_NUM_REGS == 2 +#define DPRINT_REGS(base_reg, format, ...) \ + printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \ + readl(base_reg ## 0), readl(base_reg ## 1)) +#define DPRINT_ARRAY(array, format, ...) \ + printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \ + array[0], array[1]) +#elif VIC_NUM_REGS == 4 +#define DPRINT_REGS(base_reg, format, ...) \ + printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \ + readl(base_reg ## 0), readl(base_reg ## 1), \ + readl(base_reg ## 2), readl(base_reg ## 3)) +#define DPRINT_ARRAY(array, format, ...) \ + printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \ + array[0], array[1], \ + array[2], array[3]) +#else +#error "VIC_NUM_REGS set to illegal value" +#endif + +static uint32_t msm_irq_smsm_wake_enable[2]; +static struct { + uint32_t int_en[2]; + uint32_t int_type; + uint32_t int_polarity; + uint32_t int_select; +} msm_irq_shadow_reg[VIC_NUM_REGS]; +static uint32_t msm_irq_idle_disable[VIC_NUM_REGS]; + +#define SMSM_FAKE_IRQ (0xff) +static uint8_t msm_irq_to_smsm[NR_IRQS] = { + [INT_MDDI_EXT] = 1, + [INT_MDDI_PRI] = 2, + [INT_MDDI_CLIENT] = 3, + [INT_USB_OTG] = 4, + + [INT_PWB_I2C] = 5, + [INT_SDC1_0] = 6, + [INT_SDC1_1] = 7, + [INT_SDC2_0] = 8, + + [INT_SDC2_1] = 9, + [INT_ADSP_A9_A11] = 10, + [INT_UART1] = 11, + [INT_UART2] = 12, + + [INT_UART3] = 13, + [INT_UART1_RX] = 14, + [INT_UART2_RX] = 15, + [INT_UART3_RX] = 16, + + [INT_UART1DM_IRQ] = 17, + [INT_UART1DM_RX] = 18, + [INT_KEYSENSE] = 19, +#if !defined(CONFIG_ARCH_MSM7X30) + [INT_AD_HSSD] = 20, +#endif + + [INT_NAND_WR_ER_DONE] = 21, + [INT_NAND_OP_DONE] = 22, + [INT_TCHSCRN1] = 23, + [INT_TCHSCRN2] = 24, + + [INT_TCHSCRN_SSBI] = 25, + [INT_USB_HS] = 26, + [INT_UART2DM_RX] = 27, + [INT_UART2DM_IRQ] = 28, + + [INT_SDC4_1] = 29, + [INT_SDC4_0] = 30, + [INT_SDC3_1] = 31, + [INT_SDC3_0] = 32, + + /* fake wakeup interrupts */ + [INT_GPIO_GROUP1] = SMSM_FAKE_IRQ, + [INT_GPIO_GROUP2] = SMSM_FAKE_IRQ, + [INT_A9_M2A_0] = SMSM_FAKE_IRQ, + [INT_A9_M2A_1] = SMSM_FAKE_IRQ, + [INT_A9_M2A_5] = SMSM_FAKE_IRQ, + [INT_GP_TIMER_EXP] = SMSM_FAKE_IRQ, + [INT_DEBUG_TIMER_EXP] = SMSM_FAKE_IRQ, + [INT_ADSP_A11] = SMSM_FAKE_IRQ, +#ifdef CONFIG_ARCH_QSD8X50 + [INT_SIRC_0] = SMSM_FAKE_IRQ, + [INT_SIRC_1] = SMSM_FAKE_IRQ, +#endif +}; + +static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val) +{ + int i; + + for (i = 0; i < VIC_NUM_REGS; i++) + writel(val, base + (i * 4)); +} + +static void msm_irq_ack(unsigned int irq) +{ + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, irq); + irq = 1 << (irq & 31); + writel(irq, reg); +} + +static void msm_irq_mask(unsigned int irq) +{ + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, irq); + unsigned index = VIC_INT_TO_REG_INDEX(irq); + uint32_t mask = 1UL << (irq & 31); + int smsm_irq = msm_irq_to_smsm[irq]; + + msm_irq_shadow_reg[index].int_en[0] &= ~mask; + writel(mask, reg); + if (smsm_irq == 0) + msm_irq_idle_disable[index] &= ~mask; + else { + mask = 1UL << (smsm_irq - 1); + msm_irq_smsm_wake_enable[0] &= ~mask; + } +} + +static void msm_irq_unmask(unsigned int irq) +{ + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, irq); + unsigned index = VIC_INT_TO_REG_INDEX(irq); + uint32_t mask = 1UL << (irq & 31); + int smsm_irq = msm_irq_to_smsm[irq]; + + msm_irq_shadow_reg[index].int_en[0] |= mask; + writel(mask, reg); + + if (smsm_irq == 0) + msm_irq_idle_disable[index] |= mask; + else { + mask = 1UL << (smsm_irq - 1); + msm_irq_smsm_wake_enable[0] |= mask; + } +} + +static int msm_irq_set_wake(unsigned int irq, unsigned int on) +{ + unsigned index = VIC_INT_TO_REG_INDEX(irq); + uint32_t mask = 1UL << (irq & 31); + int smsm_irq = msm_irq_to_smsm[irq]; + + if (smsm_irq == 0) { + printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", irq); + return -EINVAL; + } + if (on) + msm_irq_shadow_reg[index].int_en[1] |= mask; + else + msm_irq_shadow_reg[index].int_en[1] &= ~mask; + + if (smsm_irq == SMSM_FAKE_IRQ) + return 0; + + mask = 1UL << (smsm_irq - 1); + if (on) + msm_irq_smsm_wake_enable[1] |= mask; + else + msm_irq_smsm_wake_enable[1] &= ~mask; + return 0; +} + +static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) +{ + void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, irq); + void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, irq); + unsigned index = VIC_INT_TO_REG_INDEX(irq); + int b = 1 << (irq & 31); + uint32_t polarity; + uint32_t type; + + polarity = msm_irq_shadow_reg[index].int_polarity; + if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW)) + polarity |= b; + if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) + polarity &= ~b; + writel(polarity, preg); + msm_irq_shadow_reg[index].int_polarity = polarity; + + type = msm_irq_shadow_reg[index].int_type; + if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { + type |= b; + irq_desc[irq].handle_irq = handle_edge_irq; + } + if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { + type &= ~b; + irq_desc[irq].handle_irq = handle_level_irq; + } + writel(type, treg); + msm_irq_shadow_reg[index].int_type = type; + return 0; +} + +static struct irq_chip msm_irq_chip = { + .name = "msm", + .disable = msm_irq_mask, + .ack = msm_irq_ack, + .mask = msm_irq_mask, + .unmask = msm_irq_unmask, + .set_wake = msm_irq_set_wake, + .set_type = msm_irq_set_type, +}; + +void __init msm_init_irq(void) +{ + unsigned n; + + /* select level interrupts */ + msm_irq_write_all_regs(VIC_INT_TYPE0, 0); + + /* select highlevel interrupts */ + msm_irq_write_all_regs(VIC_INT_POLARITY0, 0); + + /* select IRQ for all INTs */ + msm_irq_write_all_regs(VIC_INT_SELECT0, 0); + + /* disable all INTs */ + msm_irq_write_all_regs(VIC_INT_EN0, 0); + + /* don't use vic */ + writel(0, VIC_CONFIG); + + /* enable interrupt controller */ + writel(3, VIC_INT_MASTEREN); + + for (n = 0; n < NR_MSM_IRQS; n++) { + set_irq_chip(n, &msm_irq_chip); + set_irq_handler(n, handle_level_irq); + set_irq_flags(n, IRQF_VALID); + } +} diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c index 69ca0dd79bd..6c8d5f8caef 100644 --- a/arch/arm/mach-msm/irq.c +++ b/arch/arm/mach-msm/irq.c @@ -101,11 +101,11 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { writel(readl(treg) | b, treg); - set_irq_handler(irq, handle_edge_irq); + irq_desc[irq].handle_irq = handle_edge_irq; } if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { writel(readl(treg) & (~b), treg); - set_irq_handler(irq, handle_level_irq); + irq_desc[irq].handle_irq = handle_level_irq; } return 0; } diff --git a/arch/arm/mach-msm/last_radio_log.c b/arch/arm/mach-msm/last_radio_log.c new file mode 100644 index 00000000000..b64ba5a9868 --- /dev/null +++ b/arch/arm/mach-msm/last_radio_log.c @@ -0,0 +1,82 @@ +/* arch/arm/mach-msm/last_radio_log.c + * + * Extract the log from a modem crash though SMEM + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/proc_fs.h> +#include <linux/uaccess.h> + +#include "smd_private.h" + +static void *radio_log_base; +static size_t radio_log_size; + +extern void *smem_item(unsigned id, unsigned *size); + +static ssize_t last_radio_log_read(struct file *file, char __user *buf, + size_t len, loff_t *offset) +{ + loff_t pos = *offset; + ssize_t count; + + if (pos >= radio_log_size) + return 0; + + count = min(len, (size_t)(radio_log_size - pos)); + if (copy_to_user(buf, radio_log_base + pos, count)) { + pr_err("%s: copy to user failed\n", __func__); + return -EFAULT; + } + + *offset += count; + return count; +} + +static struct file_operations last_radio_log_fops = { + .read = last_radio_log_read +}; + +void msm_init_last_radio_log(struct module *owner) +{ + struct proc_dir_entry *entry; + + if (last_radio_log_fops.owner) { + pr_err("%s: already claimed\n", __func__); + return; + } + + radio_log_base = smem_item(SMEM_CLKREGIM_BSP, &radio_log_size); + if (!radio_log_base) { + pr_err("%s: could not retrieve SMEM_CLKREGIM_BSP\n", __func__); + return; + } + + entry = create_proc_entry("last_radio_log", S_IFREG | S_IRUGO, NULL); + if (!entry) { + pr_err("%s: could not create proc entry for radio log\n", + __func__); + return; + } + + pr_err("%s: last radio log is %d bytes long\n", __func__, + radio_log_size); + last_radio_log_fops.owner = owner; + entry->proc_fops = &last_radio_log_fops; + entry->size = radio_log_size; +} +EXPORT_SYMBOL(msm_init_last_radio_log); diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c index 915ee704ed3..67e701c7f18 100644 --- a/arch/arm/mach-msm/proc_comm.c +++ b/arch/arm/mach-msm/proc_comm.c @@ -23,11 +23,18 @@ #include "proc_comm.h" -#define MSM_A2M_INT(n) (MSM_CSR_BASE + 0x400 + (n) * 4) +static inline void msm_a2m_int(uint32_t irq) +{ +#if defined(CONFIG_ARCH_MSM7X30) + writel(1 << irq, MSM_GCC_BASE + 0x8); +#else + writel(1, MSM_CSR_BASE + 0x400 + (irq * 4)); +#endif +} static inline void notify_other_proc_comm(void) { - writel(1, MSM_A2M_INT(6)); + msm_a2m_int(6); } #define APP_COMMAND 0x00 @@ -107,4 +114,17 @@ int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2) return ret; } - +/* + * We need to wait for the ARM9 to at least partially boot + * up before we can continue. Since the ARM9 does resource + * allocation, if we dont' wait we could end up crashing or in + * and unknown state. This function should be called early to + * wait on the ARM9. + */ +void __init proc_comm_boot_wait(void) +{ + void __iomem *base = MSM_SHARED_RAM_BASE; + + proc_comm_wait_for(base + MDM_STATUS, PCOM_READY); + +} diff --git a/arch/arm/mach-msm/proc_comm.h b/arch/arm/mach-msm/proc_comm.h index 834760f2569..12da4cacd4a 100644 --- a/arch/arm/mach-msm/proc_comm.h +++ b/arch/arm/mach-msm/proc_comm.h @@ -16,6 +16,8 @@ #ifndef _ARCH_ARM_MACH_MSM_PROC_COMM_H_ #define _ARCH_ARM_MACH_MSM_PROC_COMM_H_ +#include <linux/init.h> + enum { PCOM_CMD_IDLE = 0x0, PCOM_CMD_DONE, @@ -62,19 +64,104 @@ enum { PCOM_RESET_CHIP_IMM, PCOM_PM_VID_EN, PCOM_VREG_PULLDOWN, + PCOM_GET_MODEM_VERSION, + PCOM_CLK_REGIME_SEC_RESET, + PCOM_CLK_REGIME_SEC_RESET_ASSERT, + PCOM_CLK_REGIME_SEC_RESET_DEASSERT, + PCOM_CLK_REGIME_SEC_PLL_REQUEST_WRP, + PCOM_CLK_REGIME_SEC_ENABLE, + PCOM_CLK_REGIME_SEC_DISABLE, + PCOM_CLK_REGIME_SEC_IS_ON, + PCOM_CLK_REGIME_SEC_SEL_CLK_INV, + PCOM_CLK_REGIME_SEC_SEL_CLK_SRC, + PCOM_CLK_REGIME_SEC_SEL_CLK_DIV, + PCOM_CLK_REGIME_SEC_ICODEC_CLK_ENABLE, + PCOM_CLK_REGIME_SEC_ICODEC_CLK_DISABLE, + PCOM_CLK_REGIME_SEC_SEL_SPEED, + PCOM_CLK_REGIME_SEC_CONFIG_GP_CLK_WRP, + PCOM_CLK_REGIME_SEC_CONFIG_MDH_CLK_WRP, + PCOM_CLK_REGIME_SEC_USB_XTAL_ON, + PCOM_CLK_REGIME_SEC_USB_XTAL_OFF, + PCOM_CLK_REGIME_SEC_SET_QDSP_DME_MODE, + PCOM_CLK_REGIME_SEC_SWITCH_ADSP_CLK, + PCOM_CLK_REGIME_SEC_GET_MAX_ADSP_CLK_KHZ, + PCOM_CLK_REGIME_SEC_GET_I2C_CLK_KHZ, + PCOM_CLK_REGIME_SEC_MSM_GET_CLK_FREQ_KHZ, + PCOM_CLK_REGIME_SEC_SEL_VFE_SRC, + PCOM_CLK_REGIME_SEC_MSM_SEL_CAMCLK, + PCOM_CLK_REGIME_SEC_MSM_SEL_LCDCLK, + PCOM_CLK_REGIME_SEC_VFE_RAIL_OFF, + PCOM_CLK_REGIME_SEC_VFE_RAIL_ON, + PCOM_CLK_REGIME_SEC_GRP_RAIL_OFF, + PCOM_CLK_REGIME_SEC_GRP_RAIL_ON, + PCOM_CLK_REGIME_SEC_VDC_RAIL_OFF, + PCOM_CLK_REGIME_SEC_VDC_RAIL_ON, + PCOM_CLK_REGIME_SEC_LCD_CTRL, + PCOM_CLK_REGIME_SEC_REGISTER_FOR_CPU_RESOURCE, + PCOM_CLK_REGIME_SEC_DEREGISTER_FOR_CPU_RESOURCE, + PCOM_CLK_REGIME_SEC_RESOURCE_REQUEST_WRP, + PCOM_CLK_REGIME_MSM_SEC_SEL_CLK_OWNER, + PCOM_CLK_REGIME_SEC_DEVMAN_REQUEST_WRP, + PCOM_GPIO_CONFIG, + PCOM_GPIO_CONFIGURE_GROUP, + PCOM_GPIO_TLMM_SET_PORT, + PCOM_GPIO_TLMM_CONFIG_EX, + PCOM_SET_FTM_BOOT_COUNT, + PCOM_RESERVED0, + PCOM_RESERVED1, + PCOM_CUSTOMER_CMD1, + PCOM_CUSTOMER_CMD2, + PCOM_CUSTOMER_CMD3, + PCOM_CLK_REGIME_ENTER_APPSBL_CHG_MODE, + PCOM_CLK_REGIME_EXIT_APPSBL_CHG_MODE, + PCOM_CLK_REGIME_SEC_RAIL_DISABLE, + PCOM_CLK_REGIME_SEC_RAIL_ENABLE, + PCOM_CLK_REGIME_SEC_RAIL_CONTROL, + PCOM_SET_SW_WATCHDOG_STATE, + PCOM_PM_MPP_CONFIG_DIGITAL_INPUT, + PCOM_PM_MPP_CONFIG_I_SINK, + PCOM_RESERVED_101, + PCOM_MSM_HSUSB_PHY_RESET, + PCOM_GET_BATT_MV_LEVEL, + PCOM_CHG_USB_IS_PC_CONNECTED, + PCOM_CHG_USB_IS_CHARGER_CONNECTED, + PCOM_CHG_USB_IS_DISCONNECTED, + PCOM_CHG_USB_IS_AVAILABLE, + PCOM_CLK_REGIME_SEC_MSM_SEL_FREQ, + PCOM_CLK_REGIME_SEC_SET_PCLK_AXI_POLICY, + PCOM_CLKCTL_RPC_RESET_ASSERT, + PCOM_CLKCTL_RPC_RESET_DEASSERT, + PCOM_CLKCTL_RPC_RAIL_ON, + PCOM_CLKCTL_RPC_RAIL_OFF, + PCOM_CLKCTL_RPC_RAIL_ENABLE, + PCOM_CLKCTL_RPC_RAIL_DISABLE, + PCOM_CLKCTL_RPC_RAIL_CONTROL, + PCOM_CLKCTL_RPC_MIN_MSMC1, PCOM_NUM_CMDS, }; enum { - PCOM_INVALID_STATUS = 0x0, - PCOM_READY, - PCOM_CMD_RUNNING, - PCOM_CMD_SUCCESS, - PCOM_CMD_FAIL, + PCOM_INVALID_STATUS = 0x0, + PCOM_READY, + PCOM_CMD_RUNNING, + PCOM_CMD_SUCCESS, + PCOM_CMD_FAIL, + PCOM_CMD_FAIL_FALSE_RETURNED, + PCOM_CMD_FAIL_CMD_OUT_OF_BOUNDS_SERVER, + PCOM_CMD_FAIL_CMD_OUT_OF_BOUNDS_CLIENT, + PCOM_CMD_FAIL_CMD_UNREGISTERED, + PCOM_CMD_FAIL_CMD_LOCKED, + PCOM_CMD_FAIL_SERVER_NOT_YET_READY, + PCOM_CMD_FAIL_BAD_DESTINATION, + PCOM_CMD_FAIL_SERVER_RESET, + PCOM_CMD_FAIL_SMSM_NOT_INIT, + PCOM_CMD_FAIL_PROC_COMM_BUSY, + PCOM_CMD_FAIL_PROC_COMM_NOT_INIT, + }; /* List of VREGs that support the Pull Down Resistor setting. */ -enum { +enum vreg_pdown_id { PM_VREG_PDOWN_MSMA_ID, PM_VREG_PDOWN_MSMP_ID, PM_VREG_PDOWN_MSME1_ID, /* Not supported in Panoramix */ @@ -131,6 +218,11 @@ enum { PM_VREG_PDOWN_XO_ID = PM_VREG_PDOWN_TCXO_ID }; +enum { + PCOM_CLKRGM_APPS_RESET_USB_PHY = 34, + PCOM_CLKRGM_APPS_RESET_USBH = 37, +}; + /* gpio info for PCOM_RPC_GPIO_TLMM_CONFIG_EX */ #define GPIO_ENABLE 0 @@ -161,5 +253,6 @@ enum { (((drvstr) & 0xF) << 17)) int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2); +void __init proc_comm_boot_wait(void); #endif diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c new file mode 100644 index 00000000000..b0794524ba6 --- /dev/null +++ b/arch/arm/mach-msm/sirc.c @@ -0,0 +1,177 @@ +/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <asm/irq.h> + +static unsigned int int_enable; +static unsigned int wake_enable; + +static struct sirc_regs_t sirc_regs = { + .int_enable = SPSS_SIRC_INT_ENABLE, + .int_enable_clear = SPSS_SIRC_INT_ENABLE_CLEAR, + .int_enable_set = SPSS_SIRC_INT_ENABLE_SET, + .int_type = SPSS_SIRC_INT_TYPE, + .int_polarity = SPSS_SIRC_INT_POLARITY, + .int_clear = SPSS_SIRC_INT_CLEAR, +}; + +static struct sirc_cascade_regs sirc_reg_table[] = { + { + .int_status = SPSS_SIRC_IRQ_STATUS, + .cascade_irq = INT_SIRC_0, + } +}; + +static unsigned int save_type; +static unsigned int save_polarity; + +/* Mask off the given interrupt. Keep the int_enable mask in sync with + the enable reg, so it can be restored after power collapse. */ +static void sirc_irq_mask(unsigned int irq) +{ + unsigned int mask; + + + mask = 1 << (irq - FIRST_SIRC_IRQ); + writel(mask, sirc_regs.int_enable_clear); + int_enable &= ~mask; + return; +} + +/* Unmask the given interrupt. Keep the int_enable mask in sync with + the enable reg, so it can be restored after power collapse. */ +static void sirc_irq_unmask(unsigned int irq) +{ + unsigned int mask; + + mask = 1 << (irq - FIRST_SIRC_IRQ); + writel(mask, sirc_regs.int_enable_set); + int_enable |= mask; + return; +} + +static void sirc_irq_ack(unsigned int irq) +{ + unsigned int mask; + + mask = 1 << (irq - FIRST_SIRC_IRQ); + writel(mask, sirc_regs.int_clear); + return; +} + +static int sirc_irq_set_wake(unsigned int irq, unsigned int on) +{ + unsigned int mask; + + /* Used to set the interrupt enable mask during power collapse. */ + mask = 1 << (irq - FIRST_SIRC_IRQ); + if (on) + wake_enable |= mask; + else + wake_enable &= ~mask; + + return 0; +} + +static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type) +{ + unsigned int mask; + unsigned int val; + + mask = 1 << (irq - FIRST_SIRC_IRQ); + val = readl(sirc_regs.int_polarity); + + if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING)) + val |= mask; + else + val &= ~mask; + + writel(val, sirc_regs.int_polarity); + + val = readl(sirc_regs.int_type); + if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { + val |= mask; + irq_desc[irq].handle_irq = handle_edge_irq; + } else { + val &= ~mask; + irq_desc[irq].handle_irq = handle_level_irq; + } + + writel(val, sirc_regs.int_type); + + return 0; +} + +/* Finds the pending interrupt on the passed cascade irq and redrives it */ +static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + unsigned int reg = 0; + unsigned int sirq; + unsigned int status; + + while ((reg < ARRAY_SIZE(sirc_reg_table)) && + (sirc_reg_table[reg].cascade_irq != irq)) + reg++; + + status = readl(sirc_reg_table[reg].int_status); + status &= SIRC_MASK; + if (status == 0) + return; + + for (sirq = 0; + (sirq < NR_SIRC_IRQS) && ((status & (1U << sirq)) == 0); + sirq++) + ; + generic_handle_irq(sirq+FIRST_SIRC_IRQ); + + desc->chip->ack(irq); +} + +static struct irq_chip sirc_irq_chip = { + .name = "sirc", + .ack = sirc_irq_ack, + .mask = sirc_irq_mask, + .unmask = sirc_irq_unmask, + .set_wake = sirc_irq_set_wake, + .set_type = sirc_irq_set_type, +}; + +void __init msm_init_sirc(void) +{ + int i; + + int_enable = 0; + wake_enable = 0; + + for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { + set_irq_chip(i, &sirc_irq_chip); + set_irq_handler(i, handle_edge_irq); + set_irq_flags(i, IRQF_VALID); + } + + for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) { + set_irq_chained_handler(sirc_reg_table[i].cascade_irq, + sirc_irq_handler); + set_irq_wake(sirc_reg_table[i].cascade_irq, 1); + } + return; +} + diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c new file mode 100644 index 00000000000..cf11d414b42 --- /dev/null +++ b/arch/arm/mach-msm/smd.c @@ -0,0 +1,1046 @@ +/* arch/arm/mach-msm/smd.c + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/cdev.h> +#include <linux/device.h> +#include <linux/wait.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/list.h> +#include <linux/slab.h> +#include <linux/debugfs.h> +#include <linux/delay.h> + +#include <mach/msm_smd.h> +#include <mach/system.h> + +#include "smd_private.h" +#include "proc_comm.h" + +#if defined(CONFIG_ARCH_QSD8X50) +#define CONFIG_QDSP6 1 +#endif + +void (*msm_hw_reset_hook)(void); + +#define MODULE_NAME "msm_smd" + +enum { + MSM_SMD_DEBUG = 1U << 0, + MSM_SMSM_DEBUG = 1U << 0, +}; + +static int msm_smd_debug_mask; + +struct shared_info { + int ready; + unsigned state; +}; + +static unsigned dummy_state[SMSM_STATE_COUNT]; + +static struct shared_info smd_info = { + .state = (unsigned) &dummy_state, +}; + +module_param_named(debug_mask, msm_smd_debug_mask, + int, S_IRUGO | S_IWUSR | S_IWGRP); + +static unsigned last_heap_free = 0xffffffff; + +static inline void notify_other_smsm(void) +{ + msm_a2m_int(5); +#ifdef CONFIG_QDSP6 + msm_a2m_int(8); +#endif +} + +static inline void notify_modem_smd(void) +{ + msm_a2m_int(0); +} + +static inline void notify_dsp_smd(void) +{ + msm_a2m_int(8); +} + +static void smd_diag(void) +{ + char *x; + + x = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG); + if (x != 0) { + x[SZ_DIAG_ERR_MSG - 1] = 0; + pr_info("smem: DIAG '%s'\n", x); + } +} + +/* call when SMSM_RESET flag is set in the A9's smsm_state */ +static void handle_modem_crash(void) +{ + pr_err("ARM9 has CRASHED\n"); + smd_diag(); + + /* hard reboot if possible */ + if (msm_hw_reset_hook) + msm_hw_reset_hook(); + + /* in this case the modem or watchdog should reboot us */ + for (;;) + ; +} + +uint32_t raw_smsm_get_state(enum smsm_state_item item) +{ + return readl(smd_info.state + item * 4); +} + +static int check_for_modem_crash(void) +{ + if (raw_smsm_get_state(SMSM_STATE_MODEM) & SMSM_RESET) { + handle_modem_crash(); + return -1; + } + return 0; +} + +/* the spinlock is used to synchronize between the + * irq handler and code that mutates the channel + * list or fiddles with channel state + */ +DEFINE_SPINLOCK(smd_lock); +DEFINE_SPINLOCK(smem_lock); + +/* the mutex is used during open() and close() + * operations to avoid races while creating or + * destroying smd_channel structures + */ +static DEFINE_MUTEX(smd_creation_mutex); + +static int smd_initialized; + +LIST_HEAD(smd_ch_closed_list); +LIST_HEAD(smd_ch_list_modem); +LIST_HEAD(smd_ch_list_dsp); + +static unsigned char smd_ch_allocated[64]; +static struct work_struct probe_work; + +/* how many bytes are available for reading */ +static int smd_stream_read_avail(struct smd_channel *ch) +{ + return (ch->recv->head - ch->recv->tail) & ch->fifo_mask; +} + +/* how many bytes we are free to write */ +static int smd_stream_write_avail(struct smd_channel *ch) +{ + return ch->fifo_mask - + ((ch->send->head - ch->send->tail) & ch->fifo_mask); +} + +static int smd_packet_read_avail(struct smd_channel *ch) +{ + if (ch->current_packet) { + int n = smd_stream_read_avail(ch); + if (n > ch->current_packet) + n = ch->current_packet; + return n; + } else { + return 0; + } +} + +static int smd_packet_write_avail(struct smd_channel *ch) +{ + int n = smd_stream_write_avail(ch); + return n > SMD_HEADER_SIZE ? n - SMD_HEADER_SIZE : 0; +} + +static int ch_is_open(struct smd_channel *ch) +{ + return (ch->recv->state == SMD_SS_OPENED) && + (ch->send->state == SMD_SS_OPENED); +} + +/* provide a pointer and length to readable data in the fifo */ +static unsigned ch_read_buffer(struct smd_channel *ch, void **ptr) +{ + unsigned head = ch->recv->head; + unsigned tail = ch->recv->tail; + *ptr = (void *) (ch->recv_data + tail); + + if (tail <= head) + return head - tail; + else + return ch->fifo_size - tail; +} + +/* advance the fifo read pointer after data from ch_read_buffer is consumed */ +static void ch_read_done(struct smd_channel *ch, unsigned count) +{ + BUG_ON(count > smd_stream_read_avail(ch)); + ch->recv->tail = (ch->recv->tail + count) & ch->fifo_mask; + ch->send->fTAIL = 1; +} + +/* basic read interface to ch_read_{buffer,done} used + * by smd_*_read() and update_packet_state() + * will read-and-discard if the _data pointer is null + */ +static int ch_read(struct smd_channel *ch, void *_data, int len) +{ + void *ptr; + unsigned n; + unsigned char *data = _data; + int orig_len = len; + + while (len > 0) { + n = ch_read_buffer(ch, &ptr); + if (n == 0) + break; + + if (n > len) + n = len; + if (_data) + memcpy(data, ptr, n); + + data += n; + len -= n; + ch_read_done(ch, n); + } + + return orig_len - len; +} + +static void update_stream_state(struct smd_channel *ch) +{ + /* streams have no special state requiring updating */ +} + +static void update_packet_state(struct smd_channel *ch) +{ + unsigned hdr[5]; + int r; + + /* can't do anything if we're in the middle of a packet */ + if (ch->current_packet != 0) + return; + + /* don't bother unless we can get the full header */ + if (smd_stream_read_avail(ch) < SMD_HEADER_SIZE) + return; + + r = ch_read(ch, hdr, SMD_HEADER_SIZE); + BUG_ON(r != SMD_HEADER_SIZE); + + ch->current_packet = hdr[0]; +} + +/* provide a pointer and length to next free space in the fifo */ +static unsigned ch_write_buffer(struct smd_channel *ch, void **ptr) +{ + unsigned head = ch->send->head; + unsigned tail = ch->send->tail; + *ptr = (void *) (ch->send_data + head); + + if (head < tail) { + return tail - head - 1; + } else { + if (tail == 0) + return ch->fifo_size - head - 1; + else + return ch->fifo_size - head; + } +} + +/* advace the fifo write pointer after freespace + * from ch_write_buffer is filled + */ +static void ch_write_done(struct smd_channel *ch, unsigned count) +{ + BUG_ON(count > smd_stream_write_avail(ch)); + ch->send->head = (ch->send->head + count) & ch->fifo_mask; + ch->send->fHEAD = 1; +} + +static void ch_set_state(struct smd_channel *ch, unsigned n) +{ + if (n == SMD_SS_OPENED) { + ch->send->fDSR = 1; + ch->send->fCTS = 1; + ch->send->fCD = 1; + } else { + ch->send->fDSR = 0; + ch->send->fCTS = 0; + ch->send->fCD = 0; + } + ch->send->state = n; + ch->send->fSTATE = 1; + ch->notify_other_cpu(); +} + +static void do_smd_probe(void) +{ + struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE; + if (shared->heap_info.free_offset != last_heap_free) { + last_heap_free = shared->heap_info.free_offset; + schedule_work(&probe_work); + } +} + +static void smd_state_change(struct smd_channel *ch, + unsigned last, unsigned next) +{ + ch->last_state = next; + + pr_info("SMD: ch %d %d -> %d\n", ch->n, last, next); + + switch (next) { + case SMD_SS_OPENING: + ch->recv->tail = 0; + case SMD_SS_OPENED: + if (ch->send->state != SMD_SS_OPENED) + ch_set_state(ch, SMD_SS_OPENED); + ch->notify(ch->priv, SMD_EVENT_OPEN); + break; + case SMD_SS_FLUSHING: + case SMD_SS_RESET: + /* we should force them to close? */ + default: + ch->notify(ch->priv, SMD_EVENT_CLOSE); + } +} + +static void handle_smd_irq(struct list_head *list, void (*notify)(void)) +{ + unsigned long flags; + struct smd_channel *ch; + int do_notify = 0; + unsigned ch_flags; + unsigned tmp; + + spin_lock_irqsave(&smd_lock, flags); + list_for_each_entry(ch, list, ch_list) { + ch_flags = 0; + if (ch_is_open(ch)) { + if (ch->recv->fHEAD) { + ch->recv->fHEAD = 0; + ch_flags |= 1; + do_notify |= 1; + } + if (ch->recv->fTAIL) { + ch->recv->fTAIL = 0; + ch_flags |= 2; + do_notify |= 1; + } + if (ch->recv->fSTATE) { + ch->recv->fSTATE = 0; + ch_flags |= 4; + do_notify |= 1; + } + } + tmp = ch->recv->state; + if (tmp != ch->last_state) + smd_state_change(ch, ch->last_state, tmp); + if (ch_flags) { + ch->update_state(ch); + ch->notify(ch->priv, SMD_EVENT_DATA); + } + } + if (do_notify) + notify(); + spin_unlock_irqrestore(&smd_lock, flags); + do_smd_probe(); +} + +static irqreturn_t smd_modem_irq_handler(int irq, void *data) +{ + handle_smd_irq(&smd_ch_list_modem, notify_modem_smd); + return IRQ_HANDLED; +} + +#if defined(CONFIG_QDSP6) +static irqreturn_t smd_dsp_irq_handler(int irq, void *data) +{ + handle_smd_irq(&smd_ch_list_dsp, notify_dsp_smd); + return IRQ_HANDLED; +} +#endif + +static void smd_fake_irq_handler(unsigned long arg) +{ + handle_smd_irq(&smd_ch_list_modem, notify_modem_smd); + handle_smd_irq(&smd_ch_list_dsp, notify_dsp_smd); +} + +static DECLARE_TASKLET(smd_fake_irq_tasklet, smd_fake_irq_handler, 0); + +static inline int smd_need_int(struct smd_channel *ch) +{ + if (ch_is_open(ch)) { + if (ch->recv->fHEAD || ch->recv->fTAIL || ch->recv->fSTATE) + return 1; + if (ch->recv->state != ch->last_state) + return 1; + } + return 0; +} + +void smd_sleep_exit(void) +{ + unsigned long flags; + struct smd_channel *ch; + int need_int = 0; + + spin_lock_irqsave(&smd_lock, flags); + list_for_each_entry(ch, &smd_ch_list_modem, ch_list) { + if (smd_need_int(ch)) { + need_int = 1; + break; + } + } + list_for_each_entry(ch, &smd_ch_list_dsp, ch_list) { + if (smd_need_int(ch)) { + need_int = 1; + break; + } + } + spin_unlock_irqrestore(&smd_lock, flags); + do_smd_probe(); + + if (need_int) { + if (msm_smd_debug_mask & MSM_SMD_DEBUG) + pr_info("smd_sleep_exit need interrupt\n"); + tasklet_schedule(&smd_fake_irq_tasklet); + } +} + + +void smd_kick(smd_channel_t *ch) +{ + unsigned long flags; + unsigned tmp; + + spin_lock_irqsave(&smd_lock, flags); + ch->update_state(ch); + tmp = ch->recv->state; + if (tmp != ch->last_state) { + ch->last_state = tmp; + if (tmp == SMD_SS_OPENED) + ch->notify(ch->priv, SMD_EVENT_OPEN); + else + ch->notify(ch->priv, SMD_EVENT_CLOSE); + } + ch->notify(ch->priv, SMD_EVENT_DATA); + ch->notify_other_cpu(); + spin_unlock_irqrestore(&smd_lock, flags); +} + +static int smd_is_packet(int chn, unsigned type) +{ + type &= SMD_KIND_MASK; + if (type == SMD_KIND_PACKET) + return 1; + if (type == SMD_KIND_STREAM) + return 0; + + /* older AMSS reports SMD_KIND_UNKNOWN always */ + if ((chn > 4) || (chn == 1)) + return 1; + else + return 0; +} + +static int smd_stream_write(smd_channel_t *ch, const void *_data, int len) +{ + void *ptr; + const unsigned char *buf = _data; + unsigned xfer; + int orig_len = len; + + if (len < 0) + return -EINVAL; + + while ((xfer = ch_write_buffer(ch, &ptr)) != 0) { + if (!ch_is_open(ch)) + break; + if (xfer > len) + xfer = len; + memcpy(ptr, buf, xfer); + ch_write_done(ch, xfer); + len -= xfer; + buf += xfer; + if (len == 0) + break; + } + + ch->notify_other_cpu(); + + return orig_len - len; +} + +static int smd_packet_write(smd_channel_t *ch, const void *_data, int len) +{ + unsigned hdr[5]; + + if (len < 0) + return -EINVAL; + + if (smd_stream_write_avail(ch) < (len + SMD_HEADER_SIZE)) + return -ENOMEM; + + hdr[0] = len; + hdr[1] = hdr[2] = hdr[3] = hdr[4] = 0; + + smd_stream_write(ch, hdr, sizeof(hdr)); + smd_stream_write(ch, _data, len); + + return len; +} + +static int smd_stream_read(smd_channel_t *ch, void *data, int len) +{ + int r; + + if (len < 0) + return -EINVAL; + + r = ch_read(ch, data, len); + if (r > 0) + ch->notify_other_cpu(); + + return r; +} + +static int smd_packet_read(smd_channel_t *ch, void *data, int len) +{ + unsigned long flags; + int r; + + if (len < 0) + return -EINVAL; + + if (len > ch->current_packet) + len = ch->current_packet; + + r = ch_read(ch, data, len); + if (r > 0) + ch->notify_other_cpu(); + + spin_lock_irqsave(&smd_lock, flags); + ch->current_packet -= r; + update_packet_state(ch); + spin_unlock_irqrestore(&smd_lock, flags); + + return r; +} + +static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type) +{ + struct smd_channel *ch; + + ch = kzalloc(sizeof(struct smd_channel), GFP_KERNEL); + if (ch == 0) { + pr_err("smd_alloc_channel() out of memory\n"); + return -1; + } + ch->n = cid; + + if (_smd_alloc_channel(ch)) { + kfree(ch); + return -1; + } + + ch->fifo_mask = ch->fifo_size - 1; + ch->type = type; + + if ((type & SMD_TYPE_MASK) == SMD_TYPE_APPS_MODEM) + ch->notify_other_cpu = notify_modem_smd; + else + ch->notify_other_cpu = notify_dsp_smd; + + if (smd_is_packet(cid, type)) { + ch->read = smd_packet_read; + ch->write = smd_packet_write; + ch->read_avail = smd_packet_read_avail; + ch->write_avail = smd_packet_write_avail; + ch->update_state = update_packet_state; + } else { + ch->read = smd_stream_read; + ch->write = smd_stream_write; + ch->read_avail = smd_stream_read_avail; + ch->write_avail = smd_stream_write_avail; + ch->update_state = update_stream_state; + } + + if ((type & 0xff) == 0) + memcpy(ch->name, "SMD_", 4); + else + memcpy(ch->name, "DSP_", 4); + memcpy(ch->name + 4, name, 20); + ch->name[23] = 0; + ch->pdev.name = ch->name; + ch->pdev.id = -1; + + pr_info("smd_alloc_channel() cid=%02d size=%05d '%s'\n", + ch->n, ch->fifo_size, ch->name); + + mutex_lock(&smd_creation_mutex); + list_add(&ch->ch_list, &smd_ch_closed_list); + mutex_unlock(&smd_creation_mutex); + + platform_device_register(&ch->pdev); + return 0; +} + +static void smd_channel_probe_worker(struct work_struct *work) +{ + struct smd_alloc_elm *shared; + unsigned ctype; + unsigned type; + unsigned n; + + shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64); + if (!shared) { + pr_err("smd: cannot find allocation table\n"); + return; + } + for (n = 0; n < 64; n++) { + if (smd_ch_allocated[n]) + continue; + if (!shared[n].ref_count) + continue; + if (!shared[n].name[0]) + continue; + ctype = shared[n].ctype; + type = ctype & SMD_TYPE_MASK; + + /* DAL channels are stream but neither the modem, + * nor the DSP correctly indicate this. Fixup manually. + */ + if (!memcmp(shared[n].name, "DAL", 3)) + ctype = (ctype & (~SMD_KIND_MASK)) | SMD_KIND_STREAM; + + type = shared[n].ctype & SMD_TYPE_MASK; + if ((type == SMD_TYPE_APPS_MODEM) || + (type == SMD_TYPE_APPS_DSP)) + if (!smd_alloc_channel(shared[n].name, shared[n].cid, ctype)) + smd_ch_allocated[n] = 1; + } +} + +static void do_nothing_notify(void *priv, unsigned flags) +{ +} + +struct smd_channel *smd_get_channel(const char *name) +{ + struct smd_channel *ch; + + mutex_lock(&smd_creation_mutex); + list_for_each_entry(ch, &smd_ch_closed_list, ch_list) { + if (!strcmp(name, ch->name)) { + list_del(&ch->ch_list); + mutex_unlock(&smd_creation_mutex); + return ch; + } + } + mutex_unlock(&smd_creation_mutex); + + return NULL; +} + +int smd_open(const char *name, smd_channel_t **_ch, + void *priv, void (*notify)(void *, unsigned)) +{ + struct smd_channel *ch; + unsigned long flags; + + if (smd_initialized == 0) { + pr_info("smd_open() before smd_init()\n"); + return -ENODEV; + } + + ch = smd_get_channel(name); + if (!ch) + return -ENODEV; + + if (notify == 0) + notify = do_nothing_notify; + + ch->notify = notify; + ch->current_packet = 0; + ch->last_state = SMD_SS_CLOSED; + ch->priv = priv; + + *_ch = ch; + + spin_lock_irqsave(&smd_lock, flags); + + if ((ch->type & SMD_TYPE_MASK) == SMD_TYPE_APPS_MODEM) + list_add(&ch->ch_list, &smd_ch_list_modem); + else + list_add(&ch->ch_list, &smd_ch_list_dsp); + + /* If the remote side is CLOSING, we need to get it to + * move to OPENING (which we'll do by moving from CLOSED to + * OPENING) and then get it to move from OPENING to + * OPENED (by doing the same state change ourselves). + * + * Otherwise, it should be OPENING and we can move directly + * to OPENED so that it will follow. + */ + if (ch->recv->state == SMD_SS_CLOSING) { + ch->send->head = 0; + ch_set_state(ch, SMD_SS_OPENING); + } else { + ch_set_state(ch, SMD_SS_OPENED); + } + spin_unlock_irqrestore(&smd_lock, flags); + smd_kick(ch); + + return 0; +} + +int smd_close(smd_channel_t *ch) +{ + unsigned long flags; + + pr_info("smd_close(%p)\n", ch); + + if (ch == 0) + return -1; + + spin_lock_irqsave(&smd_lock, flags); + ch->notify = do_nothing_notify; + list_del(&ch->ch_list); + ch_set_state(ch, SMD_SS_CLOSED); + spin_unlock_irqrestore(&smd_lock, flags); + + mutex_lock(&smd_creation_mutex); + list_add(&ch->ch_list, &smd_ch_closed_list); + mutex_unlock(&smd_creation_mutex); + + return 0; +} + +int smd_read(smd_channel_t *ch, void *data, int len) +{ + return ch->read(ch, data, len); +} + +int smd_write(smd_channel_t *ch, const void *data, int len) +{ + return ch->write(ch, data, len); +} + +int smd_write_atomic(smd_channel_t *ch, const void *data, int len) +{ + unsigned long flags; + int res; + spin_lock_irqsave(&smd_lock, flags); + res = ch->write(ch, data, len); + spin_unlock_irqrestore(&smd_lock, flags); + return res; +} + +int smd_read_avail(smd_channel_t *ch) +{ + return ch->read_avail(ch); +} + +int smd_write_avail(smd_channel_t *ch) +{ + return ch->write_avail(ch); +} + +int smd_wait_until_readable(smd_channel_t *ch, int bytes) +{ + return -1; +} + +int smd_wait_until_writable(smd_channel_t *ch, int bytes) +{ + return -1; +} + +int smd_cur_packet_size(smd_channel_t *ch) +{ + return ch->current_packet; +} + + +/* ------------------------------------------------------------------------- */ + +void *smem_alloc(unsigned id, unsigned size) +{ + return smem_find(id, size); +} + +void *smem_item(unsigned id, unsigned *size) +{ + struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE; + struct smem_heap_entry *toc = shared->heap_toc; + + if (id >= SMEM_NUM_ITEMS) + return 0; + + if (toc[id].allocated) { + *size = toc[id].size; + return (void *) (MSM_SHARED_RAM_BASE + toc[id].offset); + } else { + *size = 0; + } + + return 0; +} + +void *smem_find(unsigned id, unsigned size_in) +{ + unsigned size; + void *ptr; + + ptr = smem_item(id, &size); + if (!ptr) + return 0; + + size_in = ALIGN(size_in, 8); + if (size_in != size) { + pr_err("smem_find(%d, %d): wrong size %d\n", + id, size_in, size); + return 0; + } + + return ptr; +} + +static irqreturn_t smsm_irq_handler(int irq, void *data) +{ + unsigned long flags; + unsigned apps, modm; + + spin_lock_irqsave(&smem_lock, flags); + + apps = raw_smsm_get_state(SMSM_STATE_APPS); + modm = raw_smsm_get_state(SMSM_STATE_MODEM); + + if (msm_smd_debug_mask & MSM_SMSM_DEBUG) + pr_info("<SM %08x %08x>\n", apps, modm); + if (modm & SMSM_RESET) + handle_modem_crash(); + + do_smd_probe(); + + spin_unlock_irqrestore(&smem_lock, flags); + return IRQ_HANDLED; +} + +int smsm_change_state(enum smsm_state_item item, + uint32_t clear_mask, uint32_t set_mask) +{ + unsigned long addr = smd_info.state + item * 4; + unsigned long flags; + unsigned state; + + if (!smd_info.ready) + return -EIO; + + spin_lock_irqsave(&smem_lock, flags); + + if (raw_smsm_get_state(SMSM_STATE_MODEM) & SMSM_RESET) + handle_modem_crash(); + + state = (readl(addr) & ~clear_mask) | set_mask; + writel(state, addr); + + if (msm_smd_debug_mask & MSM_SMSM_DEBUG) + pr_info("smsm_change_state %d %x\n", item, state); + notify_other_smsm(); + + spin_unlock_irqrestore(&smem_lock, flags); + + return 0; +} + +uint32_t smsm_get_state(enum smsm_state_item item) +{ + unsigned long flags; + uint32_t rv; + + spin_lock_irqsave(&smem_lock, flags); + + rv = readl(smd_info.state + item * 4); + + if (item == SMSM_STATE_MODEM && (rv & SMSM_RESET)) + handle_modem_crash(); + + spin_unlock_irqrestore(&smem_lock, flags); + + return rv; +} + +#ifdef CONFIG_ARCH_MSM_SCORPION + +int smsm_set_sleep_duration(uint32_t delay) +{ + struct msm_dem_slave_data *ptr; + + ptr = smem_find(SMEM_APPS_DEM_SLAVE_DATA, sizeof(*ptr)); + if (ptr == NULL) { + pr_err("smsm_set_sleep_duration <SM NO APPS_DEM_SLAVE_DATA>\n"); + return -EIO; + } + if (msm_smd_debug_mask & MSM_SMSM_DEBUG) + pr_info("smsm_set_sleep_duration %d -> %d\n", + ptr->sleep_time, delay); + ptr->sleep_time = delay; + return 0; +} + +#else + +int smsm_set_sleep_duration(uint32_t delay) +{ + uint32_t *ptr; + + ptr = smem_find(SMEM_SMSM_SLEEP_DELAY, sizeof(*ptr)); + if (ptr == NULL) { + pr_err("smsm_set_sleep_duration <SM NO SLEEP_DELAY>\n"); + return -EIO; + } + if (msm_smd_debug_mask & MSM_SMSM_DEBUG) + pr_info("smsm_set_sleep_duration %d -> %d\n", + *ptr, delay); + *ptr = delay; + return 0; +} + +#endif + +int smd_core_init(void) +{ + int r; + pr_info("smd_core_init()\n"); + + /* wait for essential items to be initialized */ + for (;;) { + unsigned size; + void *state; + state = smem_item(SMEM_SMSM_SHARED_STATE, &size); + if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) { + smd_info.state = (unsigned)state; + break; + } + } + + smd_info.ready = 1; + + r = request_irq(INT_A9_M2A_0, smd_modem_irq_handler, + IRQF_TRIGGER_RISING, "smd_dev", 0); + if (r < 0) + return r; + r = enable_irq_wake(INT_A9_M2A_0); + if (r < 0) + pr_err("smd_core_init: enable_irq_wake failed for A9_M2A_0\n"); + + r = request_irq(INT_A9_M2A_5, smsm_irq_handler, + IRQF_TRIGGER_RISING, "smsm_dev", 0); + if (r < 0) { + free_irq(INT_A9_M2A_0, 0); + return r; + } + r = enable_irq_wake(INT_A9_M2A_5); + if (r < 0) + pr_err("smd_core_init: enable_irq_wake failed for A9_M2A_5\n"); + +#if defined(CONFIG_QDSP6) + r = request_irq(INT_ADSP_A11, smd_dsp_irq_handler, + IRQF_TRIGGER_RISING, "smd_dsp", 0); + if (r < 0) { + free_irq(INT_A9_M2A_0, 0); + free_irq(INT_A9_M2A_5, 0); + return r; + } +#endif + + /* check for any SMD channels that may already exist */ + do_smd_probe(); + + /* indicate that we're up and running */ + smsm_change_state(SMSM_STATE_APPS, + ~0, SMSM_INIT | SMSM_SMDINIT | SMSM_RPCINIT | SMSM_RUN); +#ifdef CONFIG_ARCH_MSM_SCORPION + smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0); +#endif + + pr_info("smd_core_init() done\n"); + + return 0; +} + +static int __init msm_smd_probe(struct platform_device *pdev) +{ + pr_info("smd_init()\n"); + + /* + * If we haven't waited for the ARM9 to boot up till now, + * then we need to wait here. Otherwise this should just + * return immediately. + */ + proc_comm_boot_wait(); + + INIT_WORK(&probe_work, smd_channel_probe_worker); + + if (smd_core_init()) { + pr_err("smd_core_init() failed\n"); + return -1; + } + + do_smd_probe(); + + msm_check_for_modem_crash = check_for_modem_crash; + + msm_init_last_radio_log(THIS_MODULE); + + smd_initialized = 1; + + return 0; +} + +static struct platform_driver msm_smd_driver = { + .probe = msm_smd_probe, + .driver = { + .name = MODULE_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init msm_smd_init(void) +{ + return platform_driver_register(&msm_smd_driver); +} + +module_init(msm_smd_init); + +MODULE_DESCRIPTION("MSM Shared Memory Core"); +MODULE_AUTHOR("Brian Swetland <swetland@google.com>"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c new file mode 100644 index 00000000000..3b2dd717b78 --- /dev/null +++ b/arch/arm/mach-msm/smd_debug.c @@ -0,0 +1,315 @@ +/* arch/arm/mach-msm/smd_debug.c + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/debugfs.h> +#include <linux/list.h> + +#include <mach/msm_iomap.h> + +#include "smd_private.h" + +#if defined(CONFIG_DEBUG_FS) + +static char *chstate(unsigned n) +{ + switch (n) { + case SMD_SS_CLOSED: + return "CLOSED"; + case SMD_SS_OPENING: + return "OPENING"; + case SMD_SS_OPENED: + return "OPENED"; + case SMD_SS_FLUSHING: + return "FLUSHING"; + case SMD_SS_CLOSING: + return "CLOSING"; + case SMD_SS_RESET: + return "RESET"; + case SMD_SS_RESET_OPENING: + return "ROPENING"; + default: + return "UNKNOWN"; + } +} + + +static int dump_ch(char *buf, int max, struct smd_channel *ch) +{ + volatile struct smd_half_channel *s = ch->send; + volatile struct smd_half_channel *r = ch->recv; + + return scnprintf( + buf, max, + "ch%02d:" + " %8s(%05d/%05d) %c%c%c%c%c%c%c <->" + " %8s(%05d/%05d) %c%c%c%c%c%c%c '%s'\n", ch->n, + chstate(s->state), s->tail, s->head, + s->fDSR ? 'D' : 'd', + s->fCTS ? 'C' : 'c', + s->fCD ? 'C' : 'c', + s->fRI ? 'I' : 'i', + s->fHEAD ? 'W' : 'w', + s->fTAIL ? 'R' : 'r', + s->fSTATE ? 'S' : 's', + chstate(r->state), r->tail, r->head, + r->fDSR ? 'D' : 'd', + r->fCTS ? 'R' : 'r', + r->fCD ? 'C' : 'c', + r->fRI ? 'I' : 'i', + r->fHEAD ? 'W' : 'w', + r->fTAIL ? 'R' : 'r', + r->fSTATE ? 'S' : 's', + ch->name + ); +} + +static int debug_read_stat(char *buf, int max) +{ + char *msg; + int i = 0; + + msg = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG); + + if (raw_smsm_get_state(SMSM_STATE_MODEM) & SMSM_RESET) + i += scnprintf(buf + i, max - i, + "smsm: ARM9 HAS CRASHED\n"); + + i += scnprintf(buf + i, max - i, "smsm: a9: %08x a11: %08x\n", + raw_smsm_get_state(SMSM_STATE_MODEM), + raw_smsm_get_state(SMSM_STATE_APPS)); +#ifdef CONFIG_ARCH_MSM_SCORPION + i += scnprintf(buf + i, max - i, "smsm dem: apps: %08x modem: %08x " + "qdsp6: %08x power: %08x time: %08x\n", + raw_smsm_get_state(SMSM_STATE_APPS_DEM), + raw_smsm_get_state(SMSM_STATE_MODEM_DEM), + raw_smsm_get_state(SMSM_STATE_QDSP6_DEM), + raw_smsm_get_state(SMSM_STATE_POWER_MASTER_DEM), + raw_smsm_get_state(SMSM_STATE_TIME_MASTER_DEM)); +#endif + if (msg) { + msg[SZ_DIAG_ERR_MSG - 1] = 0; + i += scnprintf(buf + i, max - i, "diag: '%s'\n", msg); + } + return i; +} + +static int debug_read_mem(char *buf, int max) +{ + unsigned n; + struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE; + struct smem_heap_entry *toc = shared->heap_toc; + int i = 0; + + i += scnprintf(buf + i, max - i, + "heap: init=%d free=%d remain=%d\n", + shared->heap_info.initialized, + shared->heap_info.free_offset, + shared->heap_info.heap_remaining); + + for (n = 0; n < SMEM_NUM_ITEMS; n++) { + if (toc[n].allocated == 0) + continue; + i += scnprintf(buf + i, max - i, + "%04d: offset %08x size %08x\n", + n, toc[n].offset, toc[n].size); + } + return i; +} + +static int debug_read_ch(char *buf, int max) +{ + struct smd_channel *ch; + unsigned long flags; + int i = 0; + + spin_lock_irqsave(&smd_lock, flags); + list_for_each_entry(ch, &smd_ch_list_dsp, ch_list) + i += dump_ch(buf + i, max - i, ch); + list_for_each_entry(ch, &smd_ch_list_modem, ch_list) + i += dump_ch(buf + i, max - i, ch); + list_for_each_entry(ch, &smd_ch_closed_list, ch_list) + i += dump_ch(buf + i, max - i, ch); + spin_unlock_irqrestore(&smd_lock, flags); + + return i; +} + +static int debug_read_version(char *buf, int max) +{ + struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE; + unsigned version = shared->version[VERSION_MODEM]; + return sprintf(buf, "%d.%d\n", version >> 16, version & 0xffff); +} + +static int debug_read_build_id(char *buf, int max) +{ + unsigned size; + void *data; + + data = smem_item(SMEM_HW_SW_BUILD_ID, &size); + if (!data) + return 0; + + if (size >= max) + size = max; + memcpy(buf, data, size); + + return size; +} + +static int debug_read_alloc_tbl(char *buf, int max) +{ + struct smd_alloc_elm *shared; + int n, i = 0; + + shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64); + + for (n = 0; n < 64; n++) { + if (shared[n].ref_count == 0) + continue; + i += scnprintf(buf + i, max - i, + "%03d: %-20s cid=%02d type=%03d " + "kind=%02d ref_count=%d\n", + n, shared[n].name, shared[n].cid, + shared[n].ctype & 0xff, + (shared[n].ctype >> 8) & 0xf, + shared[n].ref_count); + } + + return i; +} + +#define DEBUG_BUFMAX 4096 +static char debug_buffer[DEBUG_BUFMAX]; + +static ssize_t debug_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + int (*fill)(char *buf, int max) = file->private_data; + int bsize = fill(debug_buffer, DEBUG_BUFMAX); + return simple_read_from_buffer(buf, count, ppos, debug_buffer, bsize); +} + +static int debug_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static const struct file_operations debug_ops = { + .read = debug_read, + .open = debug_open, +}; + +static void debug_create(const char *name, mode_t mode, + struct dentry *dent, + int (*fill)(char *buf, int max)) +{ + debugfs_create_file(name, mode, dent, fill, &debug_ops); +} + +static int smd_debugfs_init(void) +{ + struct dentry *dent; + + dent = debugfs_create_dir("smd", 0); + if (IS_ERR(dent)) + return 1; + + debug_create("ch", 0444, dent, debug_read_ch); + debug_create("stat", 0444, dent, debug_read_stat); + debug_create("mem", 0444, dent, debug_read_mem); + debug_create("version", 0444, dent, debug_read_version); + debug_create("tbl", 0444, dent, debug_read_alloc_tbl); + debug_create("build", 0444, dent, debug_read_build_id); + + return 0; +} + +late_initcall(smd_debugfs_init); +#endif + + +#define MAX_NUM_SLEEP_CLIENTS 64 +#define MAX_SLEEP_NAME_LEN 8 + +#define NUM_GPIO_INT_REGISTERS 6 +#define GPIO_SMEM_NUM_GROUPS 2 +#define GPIO_SMEM_MAX_PC_INTERRUPTS 8 + +struct tramp_gpio_save { + unsigned int enable; + unsigned int detect; + unsigned int polarity; +}; + +struct tramp_gpio_smem { + uint16_t num_fired[GPIO_SMEM_NUM_GROUPS]; + uint16_t fired[GPIO_SMEM_NUM_GROUPS][GPIO_SMEM_MAX_PC_INTERRUPTS]; + uint32_t enabled[NUM_GPIO_INT_REGISTERS]; + uint32_t detection[NUM_GPIO_INT_REGISTERS]; + uint32_t polarity[NUM_GPIO_INT_REGISTERS]; +}; + + +void smsm_print_sleep_info(void) +{ + unsigned long flags; + uint32_t *ptr; + struct tramp_gpio_smem *gpio; + struct smsm_interrupt_info *int_info; + + + spin_lock_irqsave(&smem_lock, flags); + + ptr = smem_alloc(SMEM_SMSM_SLEEP_DELAY, sizeof(*ptr)); + if (ptr) + pr_info("SMEM_SMSM_SLEEP_DELAY: %x\n", *ptr); + + ptr = smem_alloc(SMEM_SMSM_LIMIT_SLEEP, sizeof(*ptr)); + if (ptr) + pr_info("SMEM_SMSM_LIMIT_SLEEP: %x\n", *ptr); + + ptr = smem_alloc(SMEM_SLEEP_POWER_COLLAPSE_DISABLED, sizeof(*ptr)); + if (ptr) + pr_info("SMEM_SLEEP_POWER_COLLAPSE_DISABLED: %x\n", *ptr); + +#ifndef CONFIG_ARCH_MSM_SCORPION + int_info = smem_alloc(SMEM_SMSM_INT_INFO, sizeof(*int_info)); + if (int_info) + pr_info("SMEM_SMSM_INT_INFO %x %x %x\n", + int_info->interrupt_mask, + int_info->pending_interrupts, + int_info->wakeup_reason); + + gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*gpio)); + if (gpio) { + int i; + for (i = 0; i < NUM_GPIO_INT_REGISTERS; i++) + pr_info("SMEM_GPIO_INT: %d: e %x d %x p %x\n", + i, gpio->enabled[i], gpio->detection[i], + gpio->polarity[i]); + + for (i = 0; i < GPIO_SMEM_NUM_GROUPS; i++) + pr_info("SMEM_GPIO_INT: %d: f %d: %d %d...\n", + i, gpio->num_fired[i], gpio->fired[i][0], + gpio->fired[i][1]); + } +#else +#endif + spin_unlock_irqrestore(&smem_lock, flags); +} + diff --git a/arch/arm/mach-msm/smd_private.h b/arch/arm/mach-msm/smd_private.h new file mode 100644 index 00000000000..727bfe68aa9 --- /dev/null +++ b/arch/arm/mach-msm/smd_private.h @@ -0,0 +1,403 @@ +/* arch/arm/mach-msm/smd_private.h + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007 QUALCOMM Incorporated + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_ +#define _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_ + +#include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <linux/list.h> +#include <linux/io.h> + +#include <mach/msm_iomap.h> + +struct smem_heap_info { + unsigned initialized; + unsigned free_offset; + unsigned heap_remaining; + unsigned reserved; +}; + +struct smem_heap_entry { + unsigned allocated; + unsigned offset; + unsigned size; + unsigned reserved; +}; + +struct smem_proc_comm { + unsigned command; + unsigned status; + unsigned data1; + unsigned data2; +}; + +#define PC_APPS 0 +#define PC_MODEM 1 + +#define VERSION_SMD 0 +#define VERSION_QDSP6 4 +#define VERSION_APPS_SBL 6 +#define VERSION_MODEM_SBL 7 +#define VERSION_APPS 8 +#define VERSION_MODEM 9 + +struct smem_shared { + struct smem_proc_comm proc_comm[4]; + unsigned version[32]; + struct smem_heap_info heap_info; + struct smem_heap_entry heap_toc[512]; +}; + +#define SMSM_V1_SIZE (sizeof(unsigned) * 8) +#define SMSM_V2_SIZE (sizeof(unsigned) * 4) + +#ifdef CONFIG_MSM_SMD_PKG3 +struct smsm_interrupt_info { + uint32_t interrupt_mask; + uint32_t pending_interrupts; + uint32_t wakeup_reason; +}; +#else +#define DEM_MAX_PORT_NAME_LEN (20) +struct msm_dem_slave_data { + uint32_t sleep_time; + uint32_t interrupt_mask; + uint32_t resources_used; + uint32_t reserved1; + + uint32_t wakeup_reason; + uint32_t pending_interrupts; + uint32_t rpc_prog; + uint32_t rpc_proc; + char smd_port_name[DEM_MAX_PORT_NAME_LEN]; + uint32_t reserved2; +}; +#endif + +#define SZ_DIAG_ERR_MSG 0xC8 +#define ID_DIAG_ERR_MSG SMEM_DIAG_ERR_MESSAGE +#define ID_SMD_CHANNELS SMEM_SMD_BASE_ID +#define ID_SHARED_STATE SMEM_SMSM_SHARED_STATE +#define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL + +#define SMSM_INIT 0x00000001 +#define SMSM_SMDINIT 0x00000008 +#define SMSM_RPCINIT 0x00000020 +#define SMSM_RESET 0x00000040 +#define SMSM_RSA 0x00000080 +#define SMSM_RUN 0x00000100 +#define SMSM_PWRC 0x00000200 +#define SMSM_TIMEWAIT 0x00000400 +#define SMSM_TIMEINIT 0x00000800 +#define SMSM_PWRC_EARLY_EXIT 0x00001000 +#define SMSM_WFPI 0x00002000 +#define SMSM_SLEEP 0x00004000 +#define SMSM_SLEEPEXIT 0x00008000 +#define SMSM_APPS_REBOOT 0x00020000 +#define SMSM_SYSTEM_POWER_DOWN 0x00040000 +#define SMSM_SYSTEM_REBOOT 0x00080000 +#define SMSM_SYSTEM_DOWNLOAD 0x00100000 +#define SMSM_PWRC_SUSPEND 0x00200000 +#define SMSM_APPS_SHUTDOWN 0x00400000 +#define SMSM_SMD_LOOPBACK 0x00800000 +#define SMSM_RUN_QUIET 0x01000000 +#define SMSM_MODEM_WAIT 0x02000000 +#define SMSM_MODEM_BREAK 0x04000000 +#define SMSM_MODEM_CONTINUE 0x08000000 +#define SMSM_UNKNOWN 0x80000000 + +#define SMSM_WKUP_REASON_RPC 0x00000001 +#define SMSM_WKUP_REASON_INT 0x00000002 +#define SMSM_WKUP_REASON_GPIO 0x00000004 +#define SMSM_WKUP_REASON_TIMER 0x00000008 +#define SMSM_WKUP_REASON_ALARM 0x00000010 +#define SMSM_WKUP_REASON_RESET 0x00000020 + +#ifdef CONFIG_ARCH_MSM7X00A +enum smsm_state_item { + SMSM_STATE_APPS = 1, + SMSM_STATE_MODEM = 3, + SMSM_STATE_COUNT, +}; +#else +enum smsm_state_item { + SMSM_STATE_APPS, + SMSM_STATE_MODEM, + SMSM_STATE_HEXAGON, + SMSM_STATE_APPS_DEM, + SMSM_STATE_MODEM_DEM, + SMSM_STATE_QDSP6_DEM, + SMSM_STATE_POWER_MASTER_DEM, + SMSM_STATE_TIME_MASTER_DEM, + SMSM_STATE_COUNT, +}; +#endif + +void *smem_alloc(unsigned id, unsigned size); +int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask); +uint32_t smsm_get_state(enum smsm_state_item item); +int smsm_set_sleep_duration(uint32_t delay); +void smsm_print_sleep_info(void); + +#define SMEM_NUM_SMD_CHANNELS 64 + +typedef enum { + /* fixed items */ + SMEM_PROC_COMM = 0, + SMEM_HEAP_INFO, + SMEM_ALLOCATION_TABLE, + SMEM_VERSION_INFO, + SMEM_HW_RESET_DETECT, + SMEM_AARM_WARM_BOOT, + SMEM_DIAG_ERR_MESSAGE, + SMEM_SPINLOCK_ARRAY, + SMEM_MEMORY_BARRIER_LOCATION, + + /* dynamic items */ + SMEM_AARM_PARTITION_TABLE, + SMEM_AARM_BAD_BLOCK_TABLE, + SMEM_RESERVE_BAD_BLOCKS, + SMEM_WM_UUID, + SMEM_CHANNEL_ALLOC_TBL, + SMEM_SMD_BASE_ID, + SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_CHANNELS, + SMEM_SMEM_LOG_EVENTS, + SMEM_SMEM_STATIC_LOG_IDX, + SMEM_SMEM_STATIC_LOG_EVENTS, + SMEM_SMEM_SLOW_CLOCK_SYNC, + SMEM_SMEM_SLOW_CLOCK_VALUE, + SMEM_BIO_LED_BUF, + SMEM_SMSM_SHARED_STATE, + SMEM_SMSM_INT_INFO, + SMEM_SMSM_SLEEP_DELAY, + SMEM_SMSM_LIMIT_SLEEP, + SMEM_SLEEP_POWER_COLLAPSE_DISABLED, + SMEM_KEYPAD_KEYS_PRESSED, + SMEM_KEYPAD_STATE_UPDATED, + SMEM_KEYPAD_STATE_IDX, + SMEM_GPIO_INT, + SMEM_MDDI_LCD_IDX, + SMEM_MDDI_HOST_DRIVER_STATE, + SMEM_MDDI_LCD_DISP_STATE, + SMEM_LCD_CUR_PANEL, + SMEM_MARM_BOOT_SEGMENT_INFO, + SMEM_AARM_BOOT_SEGMENT_INFO, + SMEM_SLEEP_STATIC, + SMEM_SCORPION_FREQUENCY, + SMEM_SMD_PROFILES, + SMEM_TSSC_BUSY, + SMEM_HS_SUSPEND_FILTER_INFO, + SMEM_BATT_INFO, + SMEM_APPS_BOOT_MODE, + SMEM_VERSION_FIRST, + SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24, + SMEM_OSS_RRCASN1_BUF1, + SMEM_OSS_RRCASN1_BUF2, + SMEM_ID_VENDOR0, + SMEM_ID_VENDOR1, + SMEM_ID_VENDOR2, + SMEM_HW_SW_BUILD_ID, + SMEM_SMD_BLOCK_PORT_BASE_ID, + SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + SMEM_NUM_SMD_CHANNELS, + SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + SMEM_NUM_SMD_CHANNELS, + SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + SMEM_NUM_SMD_CHANNELS, + SMEM_SCLK_CONVERSION, + SMEM_SMD_SMSM_INTR_MUX, + SMEM_SMSM_CPU_INTR_MASK, + SMEM_APPS_DEM_SLAVE_DATA, + SMEM_QDSP6_DEM_SLAVE_DATA, + SMEM_CLKREGIM_BSP, + SMEM_CLKREGIM_SOURCES, + SMEM_SMD_FIFO_BASE_ID, + SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + SMEM_NUM_SMD_CHANNELS, + SMEM_POWER_ON_STATUS_INFO, + SMEM_DAL_AREA, + SMEM_SMEM_LOG_POWER_IDX, + SMEM_SMEM_LOG_POWER_WRAP, + SMEM_SMEM_LOG_POWER_EVENTS, + SMEM_ERR_CRASH_LOG, + SMEM_ERR_F3_TRACE_LOG, + SMEM_NUM_ITEMS, +} smem_mem_type; + + +#define SMD_SS_CLOSED 0x00000000 +#define SMD_SS_OPENING 0x00000001 +#define SMD_SS_OPENED 0x00000002 +#define SMD_SS_FLUSHING 0x00000003 +#define SMD_SS_CLOSING 0x00000004 +#define SMD_SS_RESET 0x00000005 +#define SMD_SS_RESET_OPENING 0x00000006 + +#define SMD_BUF_SIZE 8192 +#define SMD_CHANNELS 64 + +#define SMD_HEADER_SIZE 20 + +struct smd_alloc_elm { + char name[20]; + uint32_t cid; + uint32_t ctype; + uint32_t ref_count; +}; + +struct smd_half_channel { + unsigned state; + unsigned char fDSR; + unsigned char fCTS; + unsigned char fCD; + unsigned char fRI; + unsigned char fHEAD; + unsigned char fTAIL; + unsigned char fSTATE; + unsigned char fUNUSED; + unsigned tail; + unsigned head; +} __attribute__(( aligned(4), packed )); + +/* Only used on SMD package v3 on msm7201a */ +struct smd_shared_v1 { + struct smd_half_channel ch0; + unsigned char data0[SMD_BUF_SIZE]; + struct smd_half_channel ch1; + unsigned char data1[SMD_BUF_SIZE]; +}; + +/* Used on SMD package v4 */ +struct smd_shared_v2 { + struct smd_half_channel ch0; + struct smd_half_channel ch1; +}; + +struct smd_channel { + volatile struct smd_half_channel *send; + volatile struct smd_half_channel *recv; + unsigned char *send_data; + unsigned char *recv_data; + + unsigned fifo_mask; + unsigned fifo_size; + unsigned current_packet; + unsigned n; + + struct list_head ch_list; + + void *priv; + void (*notify)(void *priv, unsigned flags); + + int (*read)(struct smd_channel *ch, void *data, int len); + int (*write)(struct smd_channel *ch, const void *data, int len); + int (*read_avail)(struct smd_channel *ch); + int (*write_avail)(struct smd_channel *ch); + + void (*update_state)(struct smd_channel *ch); + unsigned last_state; + void (*notify_other_cpu)(void); + unsigned type; + + char name[32]; + struct platform_device pdev; +}; + +#define SMD_TYPE_MASK 0x0FF +#define SMD_TYPE_APPS_MODEM 0x000 +#define SMD_TYPE_APPS_DSP 0x001 +#define SMD_TYPE_MODEM_DSP 0x002 + +#define SMD_KIND_MASK 0xF00 +#define SMD_KIND_UNKNOWN 0x000 +#define SMD_KIND_STREAM 0x100 +#define SMD_KIND_PACKET 0x200 + +extern struct list_head smd_ch_closed_list; +extern struct list_head smd_ch_list_modem; +extern struct list_head smd_ch_list_dsp; + +extern spinlock_t smd_lock; +extern spinlock_t smem_lock; + +void *smem_find(unsigned id, unsigned size); +void *smem_item(unsigned id, unsigned *size); +uint32_t raw_smsm_get_state(enum smsm_state_item item); + +extern void msm_init_last_radio_log(struct module *); + +#ifdef CONFIG_MSM_SMD_PKG3 +/* + * This allocator assumes an SMD Package v3 which only exists on + * MSM7x00 SoC's. + */ +static inline int _smd_alloc_channel(struct smd_channel *ch) +{ + struct smd_shared_v1 *shared1; + + shared1 = smem_alloc(ID_SMD_CHANNELS + ch->n, sizeof(*shared1)); + if (!shared1) { + pr_err("smd_alloc_channel() cid %d does not exist\n", ch->n); + return -1; + } + ch->send = &shared1->ch0; + ch->recv = &shared1->ch1; + ch->send_data = shared1->data0; + ch->recv_data = shared1->data1; + ch->fifo_size = SMD_BUF_SIZE; + return 0; +} +#else +/* + * This allocator assumes an SMD Package v4, the most common + * and the default. + */ +static inline int _smd_alloc_channel(struct smd_channel *ch) +{ + struct smd_shared_v2 *shared2; + void *buffer; + unsigned buffer_sz; + + shared2 = smem_alloc(SMEM_SMD_BASE_ID + ch->n, sizeof(*shared2)); + buffer = smem_item(SMEM_SMD_FIFO_BASE_ID + ch->n, &buffer_sz); + + if (!buffer) + return -1; + + /* buffer must be a power-of-two size */ + if (buffer_sz & (buffer_sz - 1)) + return -1; + + buffer_sz /= 2; + ch->send = &shared2->ch0; + ch->recv = &shared2->ch1; + ch->send_data = buffer; + ch->recv_data = buffer + buffer_sz; + ch->fifo_size = buffer_sz; + return 0; +} +#endif /* CONFIG_MSM_SMD_PKG3 */ + +#if defined(CONFIG_ARCH_MSM7X30) +static inline void msm_a2m_int(uint32_t irq) +{ + writel(1 << irq, MSM_GCC_BASE + 0x8); +} +#else +static inline void msm_a2m_int(uint32_t irq) +{ + writel(1, MSM_CSR_BASE + 0x400 + (irq * 4)); +} +#endif /* CONFIG_ARCH_MSM7X30 */ + + +#endif diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 4855b8ca510..dec5ca622d7 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -25,7 +25,9 @@ #include <asm/mach/time.h> #include <mach/msm_iomap.h> +#ifndef MSM_DGT_BASE #define MSM_DGT_BASE (MSM_GPT_BASE + 0x10) +#endif #define MSM_DGT_SHIFT (5) #define TIMER_MATCH_VAL 0x0000 diff --git a/arch/arm/mach-msm/vreg.c b/arch/arm/mach-msm/vreg.c index fcb0b9f2568..a9103bc6615 100644 --- a/arch/arm/mach-msm/vreg.c +++ b/arch/arm/mach-msm/vreg.c @@ -1,6 +1,7 @@ /* arch/arm/mach-msm/vreg.c * * Copyright (C) 2008 Google, Inc. + * Copyright (c) 2009, Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -18,6 +19,7 @@ #include <linux/device.h> #include <linux/init.h> #include <linux/debugfs.h> +#include <linux/string.h> #include <mach/vreg.h> #include "proc_comm.h" @@ -25,42 +27,62 @@ struct vreg { const char *name; unsigned id; + int status; + unsigned refcnt; }; -#define VREG(_name, _id) { .name = _name, .id = _id, } +#define VREG(_name, _id, _status, _refcnt) \ + { .name = _name, .id = _id, .status = _status, .refcnt = _refcnt } static struct vreg vregs[] = { - VREG("msma", 0), - VREG("msmp", 1), - VREG("msme1", 2), - VREG("msmc1", 3), - VREG("msmc2", 4), - VREG("gp3", 5), - VREG("msme2", 6), - VREG("gp4", 7), - VREG("gp1", 8), - VREG("tcxo", 9), - VREG("pa", 10), - VREG("rftx", 11), - VREG("rfrx1", 12), - VREG("rfrx2", 13), - VREG("synt", 14), - VREG("wlan", 15), - VREG("usb", 16), - VREG("boost", 17), - VREG("mmc", 18), - VREG("ruim", 19), - VREG("msmc0", 20), - VREG("gp2", 21), - VREG("gp5", 22), - VREG("gp6", 23), - VREG("rf", 24), - VREG("rf_vco", 26), - VREG("mpll", 27), - VREG("s2", 28), - VREG("s3", 29), - VREG("rfubm", 30), - VREG("ncp", 31), + VREG("msma", 0, 0, 0), + VREG("msmp", 1, 0, 0), + VREG("msme1", 2, 0, 0), + VREG("msmc1", 3, 0, 0), + VREG("msmc2", 4, 0, 0), + VREG("gp3", 5, 0, 0), + VREG("msme2", 6, 0, 0), + VREG("gp4", 7, 0, 0), + VREG("gp1", 8, 0, 0), + VREG("tcxo", 9, 0, 0), + VREG("pa", 10, 0, 0), + VREG("rftx", 11, 0, 0), + VREG("rfrx1", 12, 0, 0), + VREG("rfrx2", 13, 0, 0), + VREG("synt", 14, 0, 0), + VREG("wlan", 15, 0, 0), + VREG("usb", 16, 0, 0), + VREG("boost", 17, 0, 0), + VREG("mmc", 18, 0, 0), + VREG("ruim", 19, 0, 0), + VREG("msmc0", 20, 0, 0), + VREG("gp2", 21, 0, 0), + VREG("gp5", 22, 0, 0), + VREG("gp6", 23, 0, 0), + VREG("rf", 24, 0, 0), + VREG("rf_vco", 26, 0, 0), + VREG("mpll", 27, 0, 0), + VREG("s2", 28, 0, 0), + VREG("s3", 29, 0, 0), + VREG("rfubm", 30, 0, 0), + VREG("ncp", 31, 0, 0), + VREG("gp7", 32, 0, 0), + VREG("gp8", 33, 0, 0), + VREG("gp9", 34, 0, 0), + VREG("gp10", 35, 0, 0), + VREG("gp11", 36, 0, 0), + VREG("gp12", 37, 0, 0), + VREG("gp13", 38, 0, 0), + VREG("gp14", 39, 0, 0), + VREG("gp15", 40, 0, 0), + VREG("gp16", 41, 0, 0), + VREG("gp17", 42, 0, 0), + VREG("s4", 43, 0, 0), + VREG("usb2", 44, 0, 0), + VREG("wlan2", 45, 0, 0), + VREG("xo_out", 46, 0, 0), + VREG("lvsw0", 47, 0, 0), + VREG("lvsw1", 48, 0, 0), }; struct vreg *vreg_get(struct device *dev, const char *id) @@ -70,7 +92,7 @@ struct vreg *vreg_get(struct device *dev, const char *id) if (!strcmp(vregs[n].name, id)) return vregs + n; } - return 0; + return ERR_PTR(-ENOENT); } void vreg_put(struct vreg *vreg) @@ -81,20 +103,39 @@ int vreg_enable(struct vreg *vreg) { unsigned id = vreg->id; unsigned enable = 1; - return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable); + + if (vreg->refcnt == 0) + vreg->status = msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable); + + if ((vreg->refcnt < UINT_MAX) && (!vreg->status)) + vreg->refcnt++; + + return vreg->status; } -void vreg_disable(struct vreg *vreg) +int vreg_disable(struct vreg *vreg) { unsigned id = vreg->id; unsigned enable = 0; - msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable); + + if (!vreg->refcnt) + return 0; + + if (vreg->refcnt == 1) + vreg->status = msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable); + + if (!vreg->status) + vreg->refcnt--; + + return vreg->status; } int vreg_set_level(struct vreg *vreg, unsigned mv) { unsigned id = vreg->id; - return msm_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv); + + vreg->status = msm_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv); + return vreg->status; } #if defined(CONFIG_DEBUG_FS) @@ -118,24 +159,59 @@ static int vreg_debug_set(void *data, u64 val) static int vreg_debug_get(void *data, u64 *val) { - return -ENOSYS; + struct vreg *vreg = data; + + if (!vreg->status) + *val = 0; + else + *val = 1; + + return 0; +} + +static int vreg_debug_count_set(void *data, u64 val) +{ + struct vreg *vreg = data; + if (val > UINT_MAX) + val = UINT_MAX; + vreg->refcnt = val; + return 0; +} + +static int vreg_debug_count_get(void *data, u64 *val) +{ + struct vreg *vreg = data; + + *val = vreg->refcnt; + + return 0; } DEFINE_SIMPLE_ATTRIBUTE(vreg_fops, vreg_debug_get, vreg_debug_set, "%llu\n"); +DEFINE_SIMPLE_ATTRIBUTE(vreg_count_fops, vreg_debug_count_get, + vreg_debug_count_set, "%llu\n"); static int __init vreg_debug_init(void) { struct dentry *dent; int n; + char name[32]; + const char *refcnt_name = "_refcnt"; dent = debugfs_create_dir("vreg", 0); if (IS_ERR(dent)) return 0; - for (n = 0; n < ARRAY_SIZE(vregs); n++) + for (n = 0; n < ARRAY_SIZE(vregs); n++) { (void) debugfs_create_file(vregs[n].name, 0644, dent, vregs + n, &vreg_fops); + strlcpy(name, vregs[n].name, sizeof(name)); + strlcat(name, refcnt_name, sizeof(name)); + (void) debugfs_create_file(name, 0644, + dent, vregs + n, &vreg_count_fops); + } + return 0; } diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c index 4aafd5b8b85..f490a406d57 100644 --- a/arch/arm/mach-mx2/pcm970-baseboard.c +++ b/arch/arm/mach-mx2/pcm970-baseboard.c @@ -201,9 +201,9 @@ static struct resource pcm970_sja1000_resources[] = { }; struct sja1000_platform_data pcm970_sja1000_platform_data = { - .clock = 16000000 / 2, - .ocr = 0x40 | 0x18, - .cdr = 0x40, + .osc_freq = 16000000, + .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL, + .cdr = CDR_CBP, }; static struct platform_device pcm970_sja1000 = { diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 2df1ec55a97..78ecd751549 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -530,9 +530,9 @@ static struct resource pcm970_sja1000_resources[] = { }; struct sja1000_platform_data pcm970_sja1000_platform_data = { - .clock = 16000000 / 2, - .ocr = 0x40 | 0x18, - .cdr = 0x40, + .osc_freq = 16000000, + .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL, + .cdr = CDR_CBP, }; static struct platform_device pcm970_sja1000 = { diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig index 3c5e0f522e9..71f3ea62397 100644 --- a/arch/arm/mach-nomadik/Kconfig +++ b/arch/arm/mach-nomadik/Kconfig @@ -6,6 +6,7 @@ config MACH_NOMADIK_8815NHK bool "ST 8815 Nomadik Hardware Kit (evaluation board)" select NOMADIK_8815 select HAS_MTU + select NOMADIK_GPIO endmenu diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile index 36f67fb207d..a6bbd1a7b4e 100644 --- a/arch/arm/mach-nomadik/Makefile +++ b/arch/arm/mach-nomadik/Makefile @@ -7,7 +7,7 @@ # Object file lists. -obj-y += clock.o gpio.o +obj-y += clock.o # Cpu revision obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c index ab3712c86d2..841d459ad59 100644 --- a/arch/arm/mach-nomadik/board-nhk8815.c +++ b/arch/arm/mach-nomadik/board-nhk8815.c @@ -32,7 +32,6 @@ #include <mach/setup.h> #include <mach/nand.h> #include <mach/fsmc.h> -#include "clock.h" /* Initial value for SRC control register: all timers use MXTAL/8 source */ #define SRC_CR_INIT_MASK 0x00007fff @@ -202,11 +201,6 @@ static struct amba_device *amba_devs[] __initdata = { &uart1_device, }; -/* We have a fixed clock alone, by now */ -static struct clk nhk8815_clk_48 = { - .rate = 48*1000*1000, -}; - static struct resource nhk8815_eth_resources[] = { { .name = "smc91x-regs", @@ -276,10 +270,8 @@ static void __init nhk8815_platform_init(void) platform_add_devices(nhk8815_platform_devices, ARRAY_SIZE(nhk8815_platform_devices)); - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { - nmdk_clk_create(&nhk8815_clk_48, amba_devs[i]->dev.init_name); + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) amba_device_register(amba_devs[i], &iomem_resource); - } } MACHINE_START(NOMADIK, "NHK8815") diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c index 9f92502a008..60f5bee09f2 100644 --- a/arch/arm/mach-nomadik/clock.c +++ b/arch/arm/mach-nomadik/clock.c @@ -32,14 +32,36 @@ void clk_disable(struct clk *clk) } EXPORT_SYMBOL(clk_disable); -/* Create a clock structure with the given name */ -int nmdk_clk_create(struct clk *clk, const char *dev_id) -{ - struct clk_lookup *clkdev; +/* We have a fixed clock alone, for now */ +static struct clk clk_48 = { + .rate = 48 * 1000 * 1000, +}; + +/* + * Catch-all default clock to satisfy drivers using the clk API. We don't + * model the actual hardware clocks yet. + */ +static struct clk clk_default; - clkdev = clkdev_alloc(clk, NULL, dev_id); - if (!clkdev) - return -ENOMEM; - clkdev_add(clkdev); +#define CLK(_clk, dev) \ + { \ + .clk = _clk, \ + .dev_id = dev, \ + } + +static struct clk_lookup lookups[] = { + CLK(&clk_48, "uart0"), + CLK(&clk_48, "uart1"), + CLK(&clk_default, "gpio.0"), + CLK(&clk_default, "gpio.1"), + CLK(&clk_default, "gpio.2"), + CLK(&clk_default, "gpio.3"), +}; + +static int __init clk_init(void) +{ + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); return 0; } + +arch_initcall(clk_init); diff --git a/arch/arm/mach-nomadik/clock.h b/arch/arm/mach-nomadik/clock.h index 235faec7f62..5563985a2cc 100644 --- a/arch/arm/mach-nomadik/clock.h +++ b/arch/arm/mach-nomadik/clock.h @@ -11,4 +11,3 @@ struct clk { unsigned long rate; }; -extern int nmdk_clk_create(struct clk *clk, const char *dev_id); diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 9bf33b30a02..91c3c901b46 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -20,6 +20,7 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/amba/bus.h> +#include <linux/platform_device.h> #include <linux/gpio.h> #include <mach/hardware.h> @@ -30,60 +31,66 @@ #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> +#define __MEM_4K_RESOURCE(x) \ + .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM} + /* The 8815 has 4 GPIO blocks, let's register them immediately */ + +#define GPIO_RESOURCE(block) \ + { \ + .start = NOMADIK_GPIO##block##_BASE, \ + .end = NOMADIK_GPIO##block##_BASE + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = IRQ_GPIO##block, \ + .end = IRQ_GPIO##block, \ + .flags = IORESOURCE_IRQ, \ + } + +#define GPIO_DEVICE(block) \ + { \ + .name = "gpio", \ + .id = block, \ + .num_resources = 2, \ + .resource = &cpu8815_gpio_resources[block * 2], \ + .dev = { \ + .platform_data = &cpu8815_gpio[block], \ + }, \ + } + static struct nmk_gpio_platform_data cpu8815_gpio[] = { { .name = "GPIO-0-31", .first_gpio = 0, .first_irq = NOMADIK_GPIO_TO_IRQ(0), - .parent_irq = IRQ_GPIO0, }, { .name = "GPIO-32-63", .first_gpio = 32, .first_irq = NOMADIK_GPIO_TO_IRQ(32), - .parent_irq = IRQ_GPIO1, }, { .name = "GPIO-64-95", .first_gpio = 64, .first_irq = NOMADIK_GPIO_TO_IRQ(64), - .parent_irq = IRQ_GPIO2, }, { .name = "GPIO-96-127", /* 124..127 not routed to pin */ .first_gpio = 96, .first_irq = NOMADIK_GPIO_TO_IRQ(96), - .parent_irq = IRQ_GPIO3, } }; -#define __MEM_4K_RESOURCE(x) \ - .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM} +static struct resource cpu8815_gpio_resources[] = { + GPIO_RESOURCE(0), + GPIO_RESOURCE(1), + GPIO_RESOURCE(2), + GPIO_RESOURCE(3), +}; -static struct amba_device cpu8815_amba_gpio[] = { - { - .dev = { - .init_name = "gpio0", - .platform_data = cpu8815_gpio + 0, - }, - __MEM_4K_RESOURCE(NOMADIK_GPIO0_BASE), - }, { - .dev = { - .init_name = "gpio1", - .platform_data = cpu8815_gpio + 1, - }, - __MEM_4K_RESOURCE(NOMADIK_GPIO1_BASE), - }, { - .dev = { - .init_name = "gpio2", - .platform_data = cpu8815_gpio + 2, - }, - __MEM_4K_RESOURCE(NOMADIK_GPIO2_BASE), - }, { - .dev = { - .init_name = "gpio3", - .platform_data = cpu8815_gpio + 3, - }, - __MEM_4K_RESOURCE(NOMADIK_GPIO3_BASE), - }, +static struct platform_device cpu8815_platform_gpio[] = { + GPIO_DEVICE(0), + GPIO_DEVICE(1), + GPIO_DEVICE(2), + GPIO_DEVICE(3), }; static struct amba_device cpu8815_amba_rng = { @@ -93,11 +100,14 @@ static struct amba_device cpu8815_amba_rng = { __MEM_4K_RESOURCE(NOMADIK_RNG_BASE), }; +static struct platform_device *platform_devs[] __initdata = { + cpu8815_platform_gpio + 0, + cpu8815_platform_gpio + 1, + cpu8815_platform_gpio + 2, + cpu8815_platform_gpio + 3, +}; + static struct amba_device *amba_devs[] __initdata = { - cpu8815_amba_gpio + 0, - cpu8815_amba_gpio + 1, - cpu8815_amba_gpio + 2, - cpu8815_amba_gpio + 3, &cpu8815_amba_rng }; @@ -105,6 +115,7 @@ static int __init cpu8815_init(void) { int i; + platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) amba_device_register(amba_devs[i], &iomem_resource); return 0; diff --git a/arch/arm/mach-nomadik/include/mach/gpio.h b/arch/arm/mach-nomadik/include/mach/gpio.h index 61577c9f9a7..7a81a042034 100644 --- a/arch/arm/mach-nomadik/include/mach/gpio.h +++ b/arch/arm/mach-nomadik/include/mach/gpio.h @@ -1,71 +1,6 @@ -/* - * Structures and registers for GPIO access in the Nomadik SoC - * - * Copyright (C) 2008 STMicroelectronics - * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com> - * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ #ifndef __ASM_ARCH_GPIO_H #define __ASM_ARCH_GPIO_H -#include <asm-generic/gpio.h> - -/* - * These currently cause a function call to happen, they may be optimized - * if needed by adding cpu-specific defines to identify blocks - * (see mach-pxa/include/mach/gpio.h as an example using GPLR etc) - */ -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value -#define gpio_cansleep __gpio_cansleep -#define gpio_to_irq __gpio_to_irq - -/* - * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving - * the "gpio" namespace for generic and cross-machine functions - */ - -/* Register in the logic block */ -#define NMK_GPIO_DAT 0x00 -#define NMK_GPIO_DATS 0x04 -#define NMK_GPIO_DATC 0x08 -#define NMK_GPIO_PDIS 0x0c -#define NMK_GPIO_DIR 0x10 -#define NMK_GPIO_DIRS 0x14 -#define NMK_GPIO_DIRC 0x18 -#define NMK_GPIO_SLPC 0x1c -#define NMK_GPIO_AFSLA 0x20 -#define NMK_GPIO_AFSLB 0x24 - -#define NMK_GPIO_RIMSC 0x40 -#define NMK_GPIO_FIMSC 0x44 -#define NMK_GPIO_IS 0x48 -#define NMK_GPIO_IC 0x4c -#define NMK_GPIO_RWIMSC 0x50 -#define NMK_GPIO_FWIMSC 0x54 -#define NMK_GPIO_WKS 0x58 - -/* Alternate functions: function C is set in hw by setting both A and B */ -#define NMK_GPIO_ALT_GPIO 0 -#define NMK_GPIO_ALT_A 1 -#define NMK_GPIO_ALT_B 2 -#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) - -extern int nmk_gpio_set_mode(int gpio, int gpio_mode); -extern int nmk_gpio_get_mode(int gpio); - -/* - * Platform data to register a block: only the initial gpio/irq number. - */ -struct nmk_gpio_platform_data { - char *name; - int first_gpio; - int first_irq; - int parent_irq; -}; +#include <plat/gpio.h> #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 27f489747bb..b18d7c28ab7 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -152,6 +152,16 @@ config MACH_AMS_DELTA Support for the Amstrad E3 (codename Delta) videophone. Say Y here if you have such a device. +config AMS_DELTA_FIQ + bool "Fast Interrupt Request (FIQ) support for the E3" + depends on MACH_AMS_DELTA + select FIQ + help + Provide a FIQ handler for the E3. + This allows for fast handling of interrupts generated + by the clock line of the E3 mailboard (or a PS/2 keyboard) + connected to the GPIO based external keyboard port. + config MACH_OMAP_GENERIC bool "Generic OMAP board" depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX) diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index b6a537c875b..ea231c7a550 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o +obj-$(CONFIG_AMS_DELTA_FIQ) += ams-delta-fiq.o ams-delta-fiq-handler.o obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o obj-$(CONFIG_MACH_HERALD) += board-htcherald.o diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S new file mode 100644 index 00000000000..927d5a18176 --- /dev/null +++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S @@ -0,0 +1,278 @@ +/* + * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S + * + * Based on linux/arch/arm/lib/floppydma.S + * Renamed and modified to work with 2.6 kernel by Matt Callow + * Copyright (C) 1995, 1996 Russell King + * Copyright (C) 2004 Pete Trapps + * Copyright (C) 2006 Matt Callow + * Copyright (C) 2010 Janusz Krzysztofik + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#include <linux/linkage.h> + +#include <plat/io.h> +#include <plat/board-ams-delta.h> + +#include <mach/ams-delta-fiq.h> + +/* + * GPIO related definitions, copied from arch/arm/plat-omap/gpio.c. + * Unfortunately, those were not placed in a separate header file. + */ +#define OMAP1510_GPIO_BASE 0xFFFCE000 +#define OMAP1510_GPIO_DATA_INPUT 0x00 +#define OMAP1510_GPIO_DATA_OUTPUT 0x04 +#define OMAP1510_GPIO_DIR_CONTROL 0x08 +#define OMAP1510_GPIO_INT_CONTROL 0x0c +#define OMAP1510_GPIO_INT_MASK 0x10 +#define OMAP1510_GPIO_INT_STATUS 0x14 +#define OMAP1510_GPIO_PIN_CONTROL 0x18 + +/* GPIO register bitmasks */ +#define KEYBRD_DATA_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_DATA) +#define KEYBRD_CLK_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_CLK) +#define MODEM_IRQ_MASK (0x1 << AMS_DELTA_GPIO_PIN_MODEM_IRQ) +#define HOOK_SWITCH_MASK (0x1 << AMS_DELTA_GPIO_PIN_HOOK_SWITCH) +#define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK) + +/* IRQ handler register bitmasks */ +#define DEFERRED_FIQ_MASK (0x1 << (INT_DEFERRED_FIQ % IH2_BASE)) +#define GPIO_BANK1_MASK (0x1 << INT_GPIO_BANK1) + +/* Driver buffer byte offsets */ +#define BUF_MASK (FIQ_MASK * 4) +#define BUF_STATE (FIQ_STATE * 4) +#define BUF_KEYS_CNT (FIQ_KEYS_CNT * 4) +#define BUF_TAIL_OFFSET (FIQ_TAIL_OFFSET * 4) +#define BUF_HEAD_OFFSET (FIQ_HEAD_OFFSET * 4) +#define BUF_BUF_LEN (FIQ_BUF_LEN * 4) +#define BUF_KEY (FIQ_KEY * 4) +#define BUF_MISSED_KEYS (FIQ_MISSED_KEYS * 4) +#define BUF_BUFFER_START (FIQ_BUFFER_START * 4) +#define BUF_GPIO_INT_MASK (FIQ_GPIO_INT_MASK * 4) +#define BUF_KEYS_HICNT (FIQ_KEYS_HICNT * 4) +#define BUF_IRQ_PEND (FIQ_IRQ_PEND * 4) +#define BUF_SIR_CODE_L1 (FIQ_SIR_CODE_L1 * 4) +#define BUF_SIR_CODE_L2 (IRQ_SIR_CODE_L2 * 4) +#define BUF_CNT_INT_00 (FIQ_CNT_INT_00 * 4) +#define BUF_CNT_INT_KEY (FIQ_CNT_INT_KEY * 4) +#define BUF_CNT_INT_MDM (FIQ_CNT_INT_MDM * 4) +#define BUF_CNT_INT_03 (FIQ_CNT_INT_03 * 4) +#define BUF_CNT_INT_HSW (FIQ_CNT_INT_HSW * 4) +#define BUF_CNT_INT_05 (FIQ_CNT_INT_05 * 4) +#define BUF_CNT_INT_06 (FIQ_CNT_INT_06 * 4) +#define BUF_CNT_INT_07 (FIQ_CNT_INT_07 * 4) +#define BUF_CNT_INT_08 (FIQ_CNT_INT_08 * 4) +#define BUF_CNT_INT_09 (FIQ_CNT_INT_09 * 4) +#define BUF_CNT_INT_10 (FIQ_CNT_INT_10 * 4) +#define BUF_CNT_INT_11 (FIQ_CNT_INT_11 * 4) +#define BUF_CNT_INT_12 (FIQ_CNT_INT_12 * 4) +#define BUF_CNT_INT_13 (FIQ_CNT_INT_13 * 4) +#define BUF_CNT_INT_14 (FIQ_CNT_INT_14 * 4) +#define BUF_CNT_INT_15 (FIQ_CNT_INT_15 * 4) +#define BUF_CIRC_BUFF (FIQ_CIRC_BUFF * 4) + + +/* + * Register useage + * r8 - temporary + * r9 - the driver buffer + * r10 - temporary + * r11 - interrupts mask + * r12 - base pointers + * r13 - interrupts status + */ + + .text + + .global qwerty_fiqin_end + +ENTRY(qwerty_fiqin_start) + @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + @ FIQ intrrupt handler + ldr r12, omap_ih1_base @ set pointer to level1 handler + + ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask + + ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status + bics r13, r13, r11 @ clear masked - any left? + beq exit @ none - spurious FIQ? exit + + ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number + + mov r8, #2 @ reset FIQ agreement + str r8, [r12, #IRQ_CONTROL_REG_OFFSET] + + cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt? + beq gpio @ yes - process it + + mov r8, #1 + orr r8, r11, r8, lsl r10 @ mask spurious interrupt + str r8, [r12, #IRQ_MIR_REG_OFFSET] +exit: + subs pc, lr, #4 @ return from FIQ + @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + + + @@@@@@@@@@@@@@@@@@@@@@@@@@@ +gpio: @ GPIO bank interrupt handler + ldr r12, omap1510_gpio_base @ set base pointer to GPIO bank + + ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask +restart: + ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits + bics r13, r13, r11 @ clear masked - any left? + beq exit @ no - spurious interrupt? exit + + orr r11, r11, r13 @ mask all requested interrupts + str r11, [r12, #OMAP1510_GPIO_INT_MASK] + + ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set? + beq hksw @ no - try next source + + + @@@@@@@@@@@@@@@@@@@@@@ + @ Keyboard clock FIQ mode interrupt handler + @ r10 now contains KEYBRD_CLK_MASK, use it + str r10, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack the interrupt + bic r11, r11, r10 @ unmask it + str r11, [r12, #OMAP1510_GPIO_INT_MASK] + + @ Process keyboard data + ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input + + ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state + cmp r10, #0 @ are we expecting start bit? + bne data @ no - go to data processing + + ands r8, r8, #KEYBRD_DATA_MASK @ check start bit - detected? + beq hksw @ no - try next source + + @ r8 contains KEYBRD_DATA_MASK, use it + str r8, [r9, #BUF_STATE] @ enter data processing state + @ r10 already contains 0, reuse it + str r10, [r9, #BUF_KEY] @ clear keycode + mov r10, #2 @ reset input bit mask + str r10, [r9, #BUF_MASK] + + @ Mask other GPIO line interrupts till key done + str r11, [r9, #BUF_GPIO_INT_MASK] @ save mask for later restore + mvn r11, #KEYBRD_CLK_MASK @ prepare all except kbd mask + str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ store into the mask register + + b restart @ restart + +data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask + + @ r8 still contains GPIO input bits + ands r8, r8, #KEYBRD_DATA_MASK @ is keyboard data line low? + ldreq r8, [r9, #BUF_KEY] @ yes - fetch collected so far, + orreq r8, r8, r10 @ set 1 at current mask position + streq r8, [r9, #BUF_KEY] @ and save back + + mov r10, r10, lsl #1 @ shift mask left + bics r10, r10, #0x800 @ have we got all the bits? + strne r10, [r9, #BUF_MASK] @ not yet - store the mask + bne restart @ and restart + + @ r10 already contains 0, reuse it + str r10, [r9, #BUF_STATE] @ reset state to start + + @ Key done - restore interrupt mask + ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask + and r11, r11, r10 @ unmask all saved as unmasked + str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ restore into the mask register + + @ Try appending the keycode to the circular buffer + ldr r10, [r9, #BUF_KEYS_CNT] @ get saved keystrokes count + ldr r8, [r9, #BUF_BUF_LEN] @ get buffer size + cmp r10, r8 @ is buffer full? + beq hksw @ yes - key lost, next source + + add r10, r10, #1 @ incremet keystrokes counter + str r10, [r9, #BUF_KEYS_CNT] + + ldr r10, [r9, #BUF_TAIL_OFFSET] @ get buffer tail offset + @ r8 already contains buffer size + cmp r10, r8 @ end of buffer? + moveq r10, #0 @ yes - rewind to buffer start + + ldr r12, [r9, #BUF_BUFFER_START] @ get buffer start address + add r12, r12, r10, LSL #2 @ calculate buffer tail address + ldr r8, [r9, #BUF_KEY] @ get last keycode + str r8, [r12] @ append it to the buffer tail + + add r10, r10, #1 @ increment buffer tail offset + str r10, [r9, #BUF_TAIL_OFFSET] + + ldr r10, [r9, #BUF_CNT_INT_KEY] @ increment interrupts counter + add r10, r10, #1 + str r10, [r9, #BUF_CNT_INT_KEY] + @@@@@@@@@@@@@@@@@@@@@@@@ + + +hksw: @Is hook switch interrupt requested? + tst r13, #HOOK_SWITCH_MASK @ is hook switch status bit set? + beq mdm @ no - try next source + + + @@@@@@@@@@@@@@@@@@@@@@@@ + @ Hook switch interrupt FIQ mode simple handler + + @ Don't toggle active edge, the switch always bounces + + @ Increment hook switch interrupt counter + ldr r10, [r9, #BUF_CNT_INT_HSW] + add r10, r10, #1 + str r10, [r9, #BUF_CNT_INT_HSW] + @@@@@@@@@@@@@@@@@@@@@@@@ + + +mdm: @Is it a modem interrupt? + tst r13, #MODEM_IRQ_MASK @ is modem status bit set? + beq irq @ no - check for next interrupt + + + @@@@@@@@@@@@@@@@@@@@@@@@ + @ Modem FIQ mode interrupt handler stub + + @ Increment modem interrupt counter + ldr r10, [r9, #BUF_CNT_INT_MDM] + add r10, r10, #1 + str r10, [r9, #BUF_CNT_INT_MDM] + @@@@@@@@@@@@@@@@@@@@@@@@ + + +irq: @ Place deferred_fiq interrupt request + ldr r12, deferred_fiq_ih_base @ set pointer to IRQ handler + mov r10, #DEFERRED_FIQ_MASK @ set deferred_fiq bit + str r10, [r12, #IRQ_ISR_REG_OFFSET] @ place it in the ISR register + + ldr r12, omap1510_gpio_base @ set pointer back to GPIO bank + b restart @ check for next GPIO interrupt + @@@@@@@@@@@@@@@@@@@@@@@@@@@ + + +/* + * Virtual addresses for IO + */ +omap_ih1_base: + .word OMAP1_IO_ADDRESS(OMAP_IH1_BASE) +deferred_fiq_ih_base: + .word OMAP1_IO_ADDRESS(DEFERRED_FIQ_IH_BASE) +omap1510_gpio_base: + .word OMAP1_IO_ADDRESS(OMAP1510_GPIO_BASE) +qwerty_fiqin_end: + +/* + * Check the size of the FIQ, + * it cannot go beyond 0xffff0200, and is copied to 0xffff001c + */ +.if (qwerty_fiqin_end - qwerty_fiqin_start) > (0x200 - 0x1c) + .err +.endif diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c new file mode 100644 index 00000000000..6c994e2d887 --- /dev/null +++ b/arch/arm/mach-omap1/ams-delta-fiq.c @@ -0,0 +1,155 @@ +/* + * Amstrad E3 FIQ handling + * + * Copyright (C) 2009 Janusz Krzysztofik + * Copyright (c) 2006 Matt Callow + * Copyright (c) 2004 Amstrad Plc + * Copyright (C) 2001 RidgeRun, Inc. + * + * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c + * in the MontaVista 2.4 kernel (and the Amstrad changes therein) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/module.h> +#include <linux/io.h> + +#include <plat/board-ams-delta.h> + +#include <asm/fiq.h> +#include <mach/ams-delta-fiq.h> + +static struct fiq_handler fh = { + .name = "ams-delta-fiq" +}; + +/* + * This buffer is shared between FIQ and IRQ contexts. + * The FIQ and IRQ isrs can both read and write it. + * It is structured as a header section several 32bit slots, + * followed by the circular buffer where the FIQ isr stores + * keystrokes received from the qwerty keyboard. + * See ams-delta-fiq.h for details of offsets. + */ +unsigned int fiq_buffer[1024]; +EXPORT_SYMBOL(fiq_buffer); + +static unsigned int irq_counter[16]; + +static irqreturn_t deferred_fiq(int irq, void *dev_id) +{ + struct irq_desc *irq_desc; + struct irq_chip *irq_chip = NULL; + int gpio, irq_num, fiq_count; + + irq_desc = irq_to_desc(IH_GPIO_BASE); + if (irq_desc) + irq_chip = irq_desc->chip; + + /* + * For each handled GPIO interrupt, keep calling its interrupt handler + * until the IRQ counter catches the FIQ incremented interrupt counter. + */ + for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK; + gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) { + irq_num = gpio_to_irq(gpio); + fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio]; + + while (irq_counter[gpio] < fiq_count) { + if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) { + /* + * It looks like handle_edge_irq() that + * OMAP GPIO edge interrupts default to, + * expects interrupt already unmasked. + */ + if (irq_chip && irq_chip->unmask) + irq_chip->unmask(irq_num); + } + generic_handle_irq(irq_num); + + irq_counter[gpio]++; + } + } + return IRQ_HANDLED; +} + +void __init ams_delta_init_fiq(void) +{ + void *fiqhandler_start; + unsigned int fiqhandler_length; + struct pt_regs FIQ_regs; + unsigned long val, offset; + int i, retval; + + fiqhandler_start = &qwerty_fiqin_start; + fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start; + pr_info("Installing fiq handler from %p, length 0x%x\n", + fiqhandler_start, fiqhandler_length); + + retval = claim_fiq(&fh); + if (retval) { + pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n", + retval); + return; + } + + retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq, + IRQ_TYPE_EDGE_RISING, "deferred_fiq", 0); + if (retval < 0) { + pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval); + release_fiq(&fh); + return; + } + /* + * Since no set_type() method is provided by OMAP irq chip, + * switch to edge triggered interrupt type manually. + */ + offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4; + val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1); + omap_writel(val, DEFERRED_FIQ_IH_BASE + offset); + + set_fiq_handler(fiqhandler_start, fiqhandler_length); + + /* + * Initialise the buffer which is shared + * between FIQ mode and IRQ mode + */ + fiq_buffer[FIQ_GPIO_INT_MASK] = 0; + fiq_buffer[FIQ_MASK] = 0; + fiq_buffer[FIQ_STATE] = 0; + fiq_buffer[FIQ_KEY] = 0; + fiq_buffer[FIQ_KEYS_CNT] = 0; + fiq_buffer[FIQ_KEYS_HICNT] = 0; + fiq_buffer[FIQ_TAIL_OFFSET] = 0; + fiq_buffer[FIQ_HEAD_OFFSET] = 0; + fiq_buffer[FIQ_BUF_LEN] = 256; + fiq_buffer[FIQ_MISSED_KEYS] = 0; + fiq_buffer[FIQ_BUFFER_START] = + (unsigned int) &fiq_buffer[FIQ_CIRC_BUFF]; + + for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++) + fiq_buffer[i] = 0; + + /* + * FIQ mode r9 always points to the fiq_buffer, becauses the FIQ isr + * will run in an unpredictable context. The fiq_buffer is the FIQ isr's + * only means of communication with the IRQ level and other kernel + * context code. + */ + FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer; + set_fiq_regs(&FIQ_regs); + + pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer); + + /* + * Redirect GPIO interrupts to FIQ + */ + offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4; + val = omap_readl(OMAP_IH1_BASE + offset) | 1; + omap_writel(val, OMAP_IH1_BASE + offset); +} diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 7fc11c34b69..fdd1dd53fa9 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -33,6 +33,8 @@ #include <plat/board.h> #include <plat/common.h> +#include <mach/ams-delta-fiq.h> + static u8 ams_delta_latch1_reg; static u16 ams_delta_latch2_reg; @@ -236,6 +238,10 @@ static void __init ams_delta_init(void) omap_usb_init(&ams_delta_usb_config); platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); +#ifdef CONFIG_AMS_DELTA_FIQ + ams_delta_init_fiq(); +#endif + omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1); } @@ -263,8 +269,18 @@ static struct platform_device ams_delta_modem_device = { static int __init ams_delta_modem_init(void) { + int err; + omap_cfg_reg(M14_1510_GPIO2); - ams_delta_modem_ports[0].irq = gpio_to_irq(2); + ams_delta_modem_ports[0].irq = + gpio_to_irq(AMS_DELTA_GPIO_PIN_MODEM_IRQ); + + err = gpio_request(AMS_DELTA_GPIO_PIN_MODEM_IRQ, "modem"); + if (err) { + pr_err("Couldn't request gpio pin for modem\n"); + return err; + } + gpio_direction_input(AMS_DELTA_GPIO_PIN_MODEM_IRQ); ams_delta_latch2_write( AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC, diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index e36639f6615..8e313b4b99a 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -28,7 +28,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/input.h> -#include <linux/bootmem.h> #include <linux/io.h> #include <linux/gpio.h> diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index e0aec1007a0..6bbb1b8b829 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -578,7 +578,7 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate) #ifdef CONFIG_OMAP_RESET_CLOCKS -void __init omap1_clk_disable_unused(struct clk *clk) +void omap1_clk_disable_unused(struct clk *clk) { __u32 regval32; diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index a4190afb861..75d0d7d90bf 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -39,7 +39,7 @@ extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); extern unsigned long omap1_watchdog_recalc(struct clk *clk); #ifdef CONFIG_OMAP_RESET_CLOCKS -extern void __init omap1_clk_disable_unused(struct clk *clk); +extern void omap1_clk_disable_unused(struct clk *clk); #else #define omap1_clk_disable_unused NULL #endif diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h new file mode 100644 index 00000000000..7a2df29400c --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h @@ -0,0 +1,79 @@ +/* + * arch/arm/mach-omap1/include/ams-delta-fiq.h + * + * Taken from the original Amstrad modifications to fiq.h + * + * Copyright (c) 2004 Amstrad Plc + * Copyright (c) 2006 Matt Callow + * Copyright (c) 2010 Janusz Krzysztofik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __AMS_DELTA_FIQ_H +#define __AMS_DELTA_FIQ_H + +#include <plat/irqs.h> + +/* + * Interrupt number used for passing control from FIQ to IRQ. + * IRQ12, described as reserved, has been selected. + */ +#define INT_DEFERRED_FIQ INT_1510_RES12 +/* + * Base address of an interrupt handler that the INT_DEFERRED_FIQ belongs to. + */ +#if (INT_DEFERRED_FIQ < IH2_BASE) +#define DEFERRED_FIQ_IH_BASE OMAP_IH1_BASE +#else +#define DEFERRED_FIQ_IH_BASE OMAP_IH2_BASE +#endif + +/* + * These are the offsets from the begining of the fiq_buffer. They are put here + * since the buffer and header need to be accessed by drivers servicing devices + * which generate GPIO interrupts - e.g. keyboard, modem, hook switch. + */ +#define FIQ_MASK 0 +#define FIQ_STATE 1 +#define FIQ_KEYS_CNT 2 +#define FIQ_TAIL_OFFSET 3 +#define FIQ_HEAD_OFFSET 4 +#define FIQ_BUF_LEN 5 +#define FIQ_KEY 6 +#define FIQ_MISSED_KEYS 7 +#define FIQ_BUFFER_START 8 +#define FIQ_GPIO_INT_MASK 9 +#define FIQ_KEYS_HICNT 10 +#define FIQ_IRQ_PEND 11 +#define FIQ_SIR_CODE_L1 12 +#define IRQ_SIR_CODE_L2 13 + +#define FIQ_CNT_INT_00 14 +#define FIQ_CNT_INT_KEY 15 +#define FIQ_CNT_INT_MDM 16 +#define FIQ_CNT_INT_03 17 +#define FIQ_CNT_INT_HSW 18 +#define FIQ_CNT_INT_05 19 +#define FIQ_CNT_INT_06 20 +#define FIQ_CNT_INT_07 21 +#define FIQ_CNT_INT_08 22 +#define FIQ_CNT_INT_09 23 +#define FIQ_CNT_INT_10 24 +#define FIQ_CNT_INT_11 25 +#define FIQ_CNT_INT_12 26 +#define FIQ_CNT_INT_13 27 +#define FIQ_CNT_INT_14 28 +#define FIQ_CNT_INT_15 29 + +#define FIQ_CIRC_BUFF 30 /*Start of circular buffer */ + +#ifndef __ASSEMBLER__ +extern unsigned int fiq_buffer[]; +extern unsigned char qwerty_fiqin_start, qwerty_fiqin_end; + +extern void __init ams_delta_init_fiq(void); +#endif + +#endif diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S index b6d9584544b..e8a8cf36b7f 100644 --- a/arch/arm/mach-omap1/include/mach/debug-macro.S +++ b/arch/arm/mach-omap1/include/mach/debug-macro.S @@ -13,6 +13,8 @@ #include <linux/serial_reg.h> +#include <asm/memory.h> + #include <plat/serial.h> .pushsection .data @@ -37,23 +39,12 @@ omap_uart_virt: .word 0x0 cmp \rx, #0 @ is port configured? bne 99f @ already configured - /* Check 7XX UART1 scratchpad register for uart to use */ + /* Check the debug UART configuration set in uncompress.h */ mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - moveq \rx, #0xff000000 @ physical base address - movne \rx, #0xfe000000 @ virtual base - orr \rx, \rx, #0x00fb0000 @ OMAP1UART1 - ldrb \rx, [\rx, #(UART_SCR << OMAP7XX_PORT_SHIFT)] - cmp \rx, #0 @ anything in 7XX scratchpad? - bne 10f @ found 7XX uart - - /* Check 15xx/16xx UART1 scratchpad register for uart to use */ - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - moveq \rx, #0xff000000 @ physical base address - movne \rx, #0xfe000000 @ virtual base - orr \rx, \rx, #0x00fb0000 @ OMAP1UART1 - ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)] + ldreq \rx, =OMAP_UART_INFO + ldrne \rx, =__phys_to_virt(OMAP_UART_INFO) + ldr \rx, [\rx, #0] /* Select the UART to use based on the UART1 scratchpad value */ 10: cmp \rx, #0 @ no port configured? diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 2455dcc744a..b31b6f12312 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -10,6 +10,7 @@ config ARCH_OMAP2420 config ARCH_OMAP2430 bool "OMAP2430 support" depends on ARCH_OMAP2 + select ARCH_OMAP_OTG config ARCH_OMAP3430 bool "OMAP3430 support" @@ -141,6 +142,12 @@ config MACH_IGEP0020 depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB +config MACH_SBC3530 + bool "OMAP3 SBC STALKER board" + depends on ARCH_OMAP3 + select OMAP_PACKAGE_CUS + select OMAP_MUX + config MACH_OMAP_3630SDP bool "OMAP3630 SDP board" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 4b9fc57770d..ea52b034e96 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -22,7 +22,7 @@ obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o # SMP support ONLY available for OMAP4 obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o -obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o +obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a @@ -89,10 +89,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o -iommu-y += iommu2.o -iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o - -obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y) +obj-$(CONFIG_OMAP_IOMMU) := iommu2.o omap-iommu.o i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o obj-y += $(i2c-omap-m) $(i2c-omap-y) @@ -122,6 +119,7 @@ obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ board-rx51-sdram.o \ board-rx51-peripherals.o \ + board-rx51-video.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ board-zoom-peripherals.o \ @@ -140,10 +138,13 @@ obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o -obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o +obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ + hsmmc.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o +obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ + hsmmc.o # Platform specific device init code obj-y += usb-musb.o obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 01d113ff9fc..a11a575745e 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -174,9 +174,18 @@ static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = { }, }; +static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = { + { + I2C_BOARD_INFO("isp1301_omap", 0x2D), + .flags = I2C_CLIENT_WAKE, + .irq = OMAP_GPIO_IRQ(78), + }, +}; + static int __init omap2430_i2c_init(void) { - omap_register_i2c_bus(1, 400, NULL, 0); + omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo, + ARRAY_SIZE(sdp2430_i2c1_boardinfo)); omap_register_i2c_bus(2, 2600, sdp2430_i2c_boardinfo, ARRAY_SIZE(sdp2430_i2c_boardinfo)); return 0; @@ -198,6 +207,15 @@ static struct omap_musb_board_data musb_board_data = { .mode = MUSB_OTG, .power = 100, }; +static struct omap_usb_config sdp2430_usb_config __initdata = { + .otg = 1, +#ifdef CONFIG_USB_GADGET_OMAP + .hmc_mode = 0x0, +#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) + .hmc_mode = 0x1, +#endif + .pins[0] = 3, +}; static void __init omap_2430sdp_init(void) { @@ -208,6 +226,7 @@ static void __init omap_2430sdp_init(void) platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); omap_serial_init(); omap2_hsmmc_init(mmc); + omap_usb_init(&sdp2430_usb_config); usb_musb_init(&musb_board_data); board_smc91x_init(); diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 5822bcf7b15..e7d629b3c76 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -150,6 +150,7 @@ static int ads7846_get_pendown_state(void) static struct ads7846_platform_data tsc2046_config __initdata = { .get_pendown_state = ads7846_get_pendown_state, .keep_vref_on = 1, + .wakeup = true, }; diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index b88f28c5814..e4a5d66b83b 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -18,8 +18,12 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/usb/otg.h> +#include <linux/spi/spi.h> +#include <linux/i2c/twl.h> +#include <linux/regulator/machine.h> #include <mach/hardware.h> +#include <mach/omap4-common.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -29,8 +33,77 @@ #include <plat/control.h> #include <plat/timer-gp.h> #include <plat/usb.h> -#include <asm/hardware/gic.h> -#include <asm/hardware/cache-l2x0.h> +#include <plat/mmc.h> +#include "hsmmc.h" + +#define ETH_KS8851_IRQ 34 +#define ETH_KS8851_POWER_ON 48 +#define ETH_KS8851_QUART 138 + +static struct spi_board_info sdp4430_spi_board_info[] __initdata = { + { + .modalias = "ks8851", + .bus_num = 1, + .chip_select = 0, + .max_speed_hz = 24000000, + .irq = ETH_KS8851_IRQ, + }, +}; + +static int omap_ethernet_init(void) +{ + int status; + + /* Request of GPIO lines */ + + status = gpio_request(ETH_KS8851_POWER_ON, "eth_power"); + if (status) { + pr_err("Cannot request GPIO %d\n", ETH_KS8851_POWER_ON); + return status; + } + + status = gpio_request(ETH_KS8851_QUART, "quart"); + if (status) { + pr_err("Cannot request GPIO %d\n", ETH_KS8851_QUART); + goto error1; + } + + status = gpio_request(ETH_KS8851_IRQ, "eth_irq"); + if (status) { + pr_err("Cannot request GPIO %d\n", ETH_KS8851_IRQ); + goto error2; + } + + /* Configuration of requested GPIO lines */ + + status = gpio_direction_output(ETH_KS8851_POWER_ON, 1); + if (status) { + pr_err("Cannot set output GPIO %d\n", ETH_KS8851_IRQ); + goto error3; + } + + status = gpio_direction_output(ETH_KS8851_QUART, 1); + if (status) { + pr_err("Cannot set output GPIO %d\n", ETH_KS8851_QUART); + goto error3; + } + + status = gpio_direction_input(ETH_KS8851_IRQ); + if (status) { + pr_err("Cannot set input GPIO %d\n", ETH_KS8851_IRQ); + goto error3; + } + + return 0; + +error3: + gpio_free(ETH_KS8851_IRQ); +error2: + gpio_free(ETH_KS8851_QUART); +error1: + gpio_free(ETH_KS8851_POWER_ON); + return status; +} static struct platform_device sdp4430_lcd_device = { .name = "sdp4430_lcd", @@ -49,50 +122,6 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = { { OMAP_TAG_LCD, &sdp4430_lcd_config }, }; -#ifdef CONFIG_CACHE_L2X0 -static int __init omap_l2_cache_init(void) -{ - extern void omap_smc1(u32 fn, u32 arg); - void __iomem *l2cache_base; - - /* To avoid code running on other OMAPs in - * multi-omap builds - */ - if (!cpu_is_omap44xx()) - return -ENODEV; - - /* Static mapping, never released */ - l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); - BUG_ON(!l2cache_base); - - /* Enable PL310 L2 Cache controller */ - omap_smc1(0x102, 0x1); - - /* 32KB way size, 16-way associativity, - * parity disabled - */ - l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); - - return 0; -} -early_initcall(omap_l2_cache_init); -#endif - -static void __init gic_init_irq(void) -{ - void __iomem *base; - - /* Static mapping, never released */ - base = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); - BUG_ON(!base); - gic_dist_init(0, base, 29); - - /* Static mapping, never released */ - gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); - BUG_ON(!gic_cpu_base_addr); - gic_cpu_init(0, gic_cpu_base_addr); -} - static void __init omap_4430sdp_init_irq(void) { omap_board_config = sdp4430_config; @@ -111,15 +140,254 @@ static struct omap_musb_board_data musb_board_data = { .power = 100, }; +static struct omap2_hsmmc_info mmc[] = { + { + .mmc = 1, + .wires = 8, + .gpio_wp = -EINVAL, + }, + { + .mmc = 2, + .wires = 8, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + .nonremovable = true, + }, + {} /* Terminator */ +}; + +static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { + { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.0", + }, + { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.1", + }, +}; + +static int omap4_twl6030_hsmmc_late_init(struct device *dev) +{ + int ret = 0; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + struct omap_mmc_platform_data *pdata = dev->platform_data; + + /* Setting MMC1 Card detect Irq */ + if (pdev->id == 0) + pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE + + MMCDETECT_INTR_OFFSET; + return ret; +} + +static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) +{ + struct omap_mmc_platform_data *pdata = dev->platform_data; + + pdata->init = omap4_twl6030_hsmmc_late_init; +} + +static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) +{ + struct omap2_hsmmc_info *c; + + omap2_hsmmc_init(controllers); + for (c = controllers; c->mmc; c++) + omap4_twl6030_hsmmc_set_late_init(c->dev); + + return 0; +} + +static struct regulator_init_data sdp4430_vaux1 = { + .constraints = { + .min_uV = 1000000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data sdp4430_vaux2 = { + .constraints = { + .min_uV = 1200000, + .max_uV = 2800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data sdp4430_vaux3 = { + .constraints = { + .min_uV = 1000000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +/* VMMC1 for MMC1 card */ +static struct regulator_init_data sdp4430_vmmc = { + .constraints = { + .min_uV = 1200000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 2, + .consumer_supplies = sdp4430_vmmc_supply, +}; + +static struct regulator_init_data sdp4430_vpp = { + .constraints = { + .min_uV = 1800000, + .max_uV = 2500000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data sdp4430_vusim = { + .constraints = { + .min_uV = 1200000, + .max_uV = 2900000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data sdp4430_vana = { + .constraints = { + .min_uV = 2100000, + .max_uV = 2100000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data sdp4430_vcxio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data sdp4430_vdac = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data sdp4430_vusb = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct twl4030_platform_data sdp4430_twldata = { + .irq_base = TWL6030_IRQ_BASE, + .irq_end = TWL6030_IRQ_END, + + /* Regulators */ + .vmmc = &sdp4430_vmmc, + .vpp = &sdp4430_vpp, + .vusim = &sdp4430_vusim, + .vana = &sdp4430_vana, + .vcxio = &sdp4430_vcxio, + .vdac = &sdp4430_vdac, + .vusb = &sdp4430_vusb, + .vaux1 = &sdp4430_vaux1, + .vaux2 = &sdp4430_vaux2, + .vaux3 = &sdp4430_vaux3, +}; + +static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl6030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = OMAP44XX_IRQ_SYS_1N, + .platform_data = &sdp4430_twldata, + }, +}; +static int __init omap4_i2c_init(void) +{ + /* + * Phoenix Audio IC needs I2C1 to + * start with 400 KHz or less + */ + omap_register_i2c_bus(1, 400, sdp4430_i2c_boardinfo, + ARRAY_SIZE(sdp4430_i2c_boardinfo)); + omap_register_i2c_bus(2, 400, NULL, 0); + omap_register_i2c_bus(3, 400, NULL, 0); + omap_register_i2c_bus(4, 400, NULL, 0); + return 0; +} static void __init omap_4430sdp_init(void) { + int status; + + omap4_i2c_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); omap_serial_init(); + omap4_twl6030_hsmmc_init(mmc); /* OMAP4 SDP uses internal transceiver so register nop transceiver */ usb_nop_xceiv_register(); /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ if (!cpu_is_omap44xx()) usb_musb_init(&musb_board_data); + + status = omap_ethernet_init(); + if (status) { + pr_err("Ethernet initialization failed: %d\n", status); + } else { + sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ); + spi_register_board_info(sdp4430_spi_board_info, + ARRAY_SIZE(sdp4430_spi_board_info)); + } } static void __init omap_4430sdp_map_io(void) diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index c1c4389fbd8..af383a87694 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -21,6 +21,8 @@ #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/i2c/pca953x.h> +#include <linux/can/platform/ti_hecc.h> +#include <linux/davinci_emac.h> #include <mach/hardware.h> #include <mach/am35xx.h> @@ -30,16 +32,111 @@ #include <plat/board.h> #include <plat/common.h> +#include <plat/control.h> #include <plat/usb.h> #include <plat/display.h> #include "mux.h" +#define AM35XX_EVM_PHY_MASK (0xF) +#define AM35XX_EVM_MDIO_FREQUENCY (1000000) + +static struct emac_platform_data am3517_evm_emac_pdata = { + .phy_mask = AM35XX_EVM_PHY_MASK, + .mdio_max_freq = AM35XX_EVM_MDIO_FREQUENCY, + .rmii_en = 1, +}; + +static struct resource am3517_emac_resources[] = { + { + .start = AM35XX_IPSS_EMAC_BASE, + .end = AM35XX_IPSS_EMAC_BASE + 0x3FFFF, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_35XX_EMAC_C0_RXTHRESH_IRQ, + .end = INT_35XX_EMAC_C0_RXTHRESH_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = INT_35XX_EMAC_C0_RX_PULSE_IRQ, + .end = INT_35XX_EMAC_C0_RX_PULSE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = INT_35XX_EMAC_C0_TX_PULSE_IRQ, + .end = INT_35XX_EMAC_C0_TX_PULSE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = INT_35XX_EMAC_C0_MISC_PULSE_IRQ, + .end = INT_35XX_EMAC_C0_MISC_PULSE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device am3517_emac_device = { + .name = "davinci_emac", + .id = -1, + .num_resources = ARRAY_SIZE(am3517_emac_resources), + .resource = am3517_emac_resources, +}; + +static void am3517_enable_ethernet_int(void) +{ + u32 regval; + + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | + AM35XX_CPGMAC_C0_TX_PULSE_CLR | + AM35XX_CPGMAC_C0_MISC_PULSE_CLR | + AM35XX_CPGMAC_C0_RX_THRESH_CLR); + omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); +} + +static void am3517_disable_ethernet_int(void) +{ + u32 regval; + + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | + AM35XX_CPGMAC_C0_TX_PULSE_CLR); + omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); +} + +void am3517_evm_ethernet_init(struct emac_platform_data *pdata) +{ + unsigned int regval; + + pdata->ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET; + pdata->ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET; + pdata->ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET; + pdata->mdio_reg_offset = AM35XX_EMAC_MDIO_OFFSET; + pdata->ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE; + pdata->version = EMAC_VERSION_2; + pdata->hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR; + pdata->interrupt_enable = am3517_enable_ethernet_int; + pdata->interrupt_disable = am3517_disable_ethernet_int; + am3517_emac_device.dev.platform_data = pdata; + platform_device_register(&am3517_emac_device); + + regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + regval = regval & (~(AM35XX_CPGMACSS_SW_RST)); + omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); + regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + + return ; +} + + + #define LCD_PANEL_PWR 176 #define LCD_PANEL_BKLIGHT_PWR 182 #define LCD_PANEL_PWM 181 -static struct i2c_board_info __initdata am3517evm_i2c_boardinfo[] = { +static struct i2c_board_info __initdata am3517evm_i2c1_boardinfo[] = { { I2C_BOARD_INFO("s35390a", 0x30), .type = "s35390a", @@ -69,7 +166,7 @@ static void __init am3517_evm_rtc_init(void) gpio_free(GPIO_RTCS35390A_IRQ); return; } - am3517evm_i2c_boardinfo[0].irq = gpio_to_irq(GPIO_RTCS35390A_IRQ); + am3517evm_i2c1_boardinfo[0].irq = gpio_to_irq(GPIO_RTCS35390A_IRQ); } /* @@ -80,7 +177,7 @@ static void __init am3517_evm_rtc_init(void) static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = { .gpio_base = OMAP_MAX_GPIO_LINES, }; -static struct i2c_board_info __initdata am3517evm_tca6416_info_0[] = { +static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = { { I2C_BOARD_INFO("tca6416", 0x21), .platform_data = &am3517evm_gpio_expander_info_0, @@ -94,7 +191,7 @@ static struct pca953x_platform_data am3517evm_ui_gpio_expander_info_1 = { static struct pca953x_platform_data am3517evm_ui_gpio_expander_info_2 = { .gpio_base = OMAP_MAX_GPIO_LINES + 32, }; -static struct i2c_board_info __initdata am3517evm_ui_tca6416_info[] = { +static struct i2c_board_info __initdata am3517evm_i2c3_boardinfo[] = { { I2C_BOARD_INFO("tca6416", 0x20), .platform_data = &am3517evm_ui_gpio_expander_info_1, @@ -108,10 +205,10 @@ static struct i2c_board_info __initdata am3517evm_ui_tca6416_info[] = { static int __init am3517_evm_i2c_init(void) { omap_register_i2c_bus(1, 400, NULL, 0); - omap_register_i2c_bus(2, 400, am3517evm_tca6416_info_0, - ARRAY_SIZE(am3517evm_tca6416_info_0)); - omap_register_i2c_bus(3, 400, am3517evm_ui_tca6416_info, - ARRAY_SIZE(am3517evm_ui_tca6416_info)); + omap_register_i2c_bus(2, 400, am3517evm_i2c2_boardinfo, + ARRAY_SIZE(am3517evm_i2c2_boardinfo)); + omap_register_i2c_bus(3, 400, am3517evm_i2c3_boardinfo, + ARRAY_SIZE(am3517evm_i2c3_boardinfo)); return 0; } @@ -119,6 +216,8 @@ static int __init am3517_evm_i2c_init(void) static int lcd_enabled; static int dvi_enabled; +#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \ + defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE) static void __init am3517_evm_display_init(void) { int r; @@ -162,6 +261,9 @@ err_2: err_1: gpio_free(LCD_PANEL_BKLIGHT_PWR); } +#else +static void __init am3517_evm_display_init(void) {} +#endif static int am3517_evm_panel_enable_lcd(struct omap_dss_device *dssdev) { @@ -275,7 +377,12 @@ static void __init am3517_evm_init_irq(void) static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, +#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \ + defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE) + .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, +#else .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, +#endif .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, .phy_reset = true, @@ -292,6 +399,42 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif + +static struct resource am3517_hecc_resources[] = { + { + .start = AM35XX_IPSS_HECC_BASE, + .end = AM35XX_IPSS_HECC_BASE + 0x3FFF, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_35XX_HECC0_IRQ, + .end = INT_35XX_HECC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device am3517_hecc_device = { + .name = "ti_hecc", + .id = -1, + .num_resources = ARRAY_SIZE(am3517_hecc_resources), + .resource = am3517_hecc_resources, +}; + +static struct ti_hecc_platform_data am3517_evm_hecc_pdata = { + .scc_hecc_offset = AM35XX_HECC_SCC_HECC_OFFSET, + .scc_ram_offset = AM35XX_HECC_SCC_RAM_OFFSET, + .hecc_ram_offset = AM35XX_HECC_RAM_OFFSET, + .mbx_offset = AM35XX_HECC_MBOX_OFFSET, + .int_line = AM35XX_HECC_INT_LINE, + .version = AM35XX_HECC_VERSION, +}; + +static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata) +{ + am3517_hecc_device.dev.platform_data = pdata; + platform_device_register(&am3517_hecc_device); +} + static void __init am3517_evm_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); @@ -305,14 +448,17 @@ static void __init am3517_evm_init(void) /* Configure GPIO for EHCI port */ omap_mux_init_gpio(57, OMAP_PIN_OUTPUT); usb_ehci_init(&ehci_pdata); + am3517_evm_hecc_init(&am3517_evm_hecc_pdata); /* DSS */ am3517_evm_display_init(); /* RTC - S35390A */ am3517_evm_rtc_init(); - i2c_register_board_info(1, am3517evm_i2c_boardinfo, - ARRAY_SIZE(am3517evm_i2c_boardinfo)); + i2c_register_board_info(1, am3517evm_i2c1_boardinfo, + ARRAY_SIZE(am3517evm_i2c1_boardinfo)); + /*Ethernet*/ + am3517_evm_ethernet_init(&am3517_evm_emac_pdata); } static void __init am3517_evm_map_io(void) diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 2de4f79f03a..e679a2cc86c 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -45,6 +45,7 @@ #include <plat/gpmc.h> #include <plat/usb.h> #include <plat/display.h> +#include <plat/mcspi.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 47e3af2166d..77022b58881 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -633,8 +633,163 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .reset_gpio_port[2] = -EINVAL }; +static struct omap_board_mux board_mux[] __initdata = { + /* nCS and IRQ for Devkit8000 ethernet */ + OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE0), + OMAP3_MUX(ETK_D11, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), + + /* McSPI 2*/ + OMAP3_MUX(MCSPI2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(MCSPI2_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(MCSPI2_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(MCSPI2_CS0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(MCSPI2_CS1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + + /* PENDOWN GPIO */ + OMAP3_MUX(ETK_D13, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + + /* mUSB */ + OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + + /* USB 1 */ + OMAP3_MUX(ETK_CTL, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), + OMAP3_MUX(ETK_D8, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + OMAP3_MUX(ETK_D9, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + OMAP3_MUX(ETK_D0, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + OMAP3_MUX(ETK_D1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + OMAP3_MUX(ETK_D2, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + OMAP3_MUX(ETK_D3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + OMAP3_MUX(ETK_D4, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + OMAP3_MUX(ETK_D5, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + OMAP3_MUX(ETK_D6, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + OMAP3_MUX(ETK_D7, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + + /* MMC 1 */ + OMAP3_MUX(SDMMC1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(SDMMC1_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(SDMMC1_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(SDMMC1_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(SDMMC1_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(SDMMC1_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(SDMMC1_DAT4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(SDMMC1_DAT5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(SDMMC1_DAT6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(SDMMC1_DAT7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + + /* McBSP 2 */ + OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + + /* I2C 1 */ + OMAP3_MUX(I2C1_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(I2C1_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + + /* I2C 2 */ + OMAP3_MUX(I2C2_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(I2C2_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + + /* I2C 3 */ + OMAP3_MUX(I2C3_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(I2C3_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + + /* I2C 4 */ + OMAP3_MUX(I2C4_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(I2C4_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + + /* serial ports */ + OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), + OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + + /* DSS */ + OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + + /* expansion port */ + /* McSPI 1 */ + OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + OMAP3_MUX(MCSPI1_CS3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + + /* HDQ */ + OMAP3_MUX(HDQ_SIO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + + /* McSPI4 */ + OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP), + + /* MMC 2 */ + OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), + OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), + OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), + OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + + /* I2C3 */ + OMAP3_MUX(I2C3_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP3_MUX(I2C3_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + + OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + + OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + + /* TPS IRQ */ + OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \ + OMAP_PIN_INPUT_PULLUP), + + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + static void __init devkit8000_init(void) { + omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); omap_serial_init(); omap_dm9000_init(); diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 962d377970e..69b154cdc75 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -39,6 +39,7 @@ #include <plat/board.h> #include <plat/common.h> +#include <plat/display.h> #include <plat/gpmc.h> #include <plat/nand.h> #include <plat/usb.h> @@ -106,6 +107,77 @@ static struct platform_device omap3beagle_nand_device = { .resource = &omap3beagle_nand_resource, }; +/* DSS */ + +static int beagle_enable_dvi(struct omap_dss_device *dssdev) +{ + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 1); + + return 0; +} + +static void beagle_disable_dvi(struct omap_dss_device *dssdev) +{ + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 0); +} + +static struct omap_dss_device beagle_dvi_device = { + .type = OMAP_DISPLAY_TYPE_DPI, + .name = "dvi", + .driver_name = "generic_panel", + .phy.dpi.data_lines = 24, + .reset_gpio = 170, + .platform_enable = beagle_enable_dvi, + .platform_disable = beagle_disable_dvi, +}; + +static struct omap_dss_device beagle_tv_device = { + .name = "tv", + .driver_name = "venc", + .type = OMAP_DISPLAY_TYPE_VENC, + .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +}; + +static struct omap_dss_device *beagle_dss_devices[] = { + &beagle_dvi_device, + &beagle_tv_device, +}; + +static struct omap_dss_board_info beagle_dss_data = { + .num_devices = ARRAY_SIZE(beagle_dss_devices), + .devices = beagle_dss_devices, + .default_device = &beagle_dvi_device, +}; + +static struct platform_device beagle_dss_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = &beagle_dss_data, + }, +}; + +static struct regulator_consumer_supply beagle_vdac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss"); + +static struct regulator_consumer_supply beagle_vdvi_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); + +static void __init beagle_display_init(void) +{ + int r; + + r = gpio_request(beagle_dvi_device.reset_gpio, "DVI reset"); + if (r < 0) { + printk(KERN_ERR "Unable to get DVI reset GPIO\n"); + return; + } + + gpio_direction_output(beagle_dvi_device.reset_gpio, 0); +} + #include "sdram-micron-mt46h32m32lf-6.h" static struct omap2_hsmmc_info mmc[] = { @@ -117,15 +189,6 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct platform_device omap3_beagle_lcd_device = { - .name = "omap3beagle_lcd", - .id = -1, -}; - -static struct omap_lcd_config omap3_beagle_lcd_config __initdata = { - .ctrl_name = "internal", -}; - static struct regulator_consumer_supply beagle_vmmc1_supply = { .supply = "vmmc", }; @@ -181,16 +244,6 @@ static struct twl4030_gpio_platform_data beagle_gpio_data = { .setup = beagle_twl_gpio_setup, }; -static struct regulator_consumer_supply beagle_vdac_supply = { - .supply = "vdac", - .dev = &omap3_beagle_lcd_device.dev, -}; - -static struct regulator_consumer_supply beagle_vdvi_supply = { - .supply = "vdvi", - .dev = &omap3_beagle_lcd_device.dev, -}; - /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ static struct regulator_init_data beagle_vmmc1 = { .constraints = { @@ -349,14 +402,8 @@ static struct platform_device keys_gpio = { }, }; -static struct omap_board_config_kernel omap3_beagle_config[] __initdata = { - { OMAP_TAG_LCD, &omap3_beagle_lcd_config }, -}; - static void __init omap3_beagle_init_irq(void) { - omap_board_config = omap3_beagle_config; - omap_board_config_size = ARRAY_SIZE(omap3_beagle_config); omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); @@ -367,9 +414,9 @@ static void __init omap3_beagle_init_irq(void) } static struct platform_device *omap3_beagle_devices[] __initdata = { - &omap3_beagle_lcd_device, &leds_gpio, &keys_gpio, + &beagle_dss_device, }; static void __init omap3beagle_flash_init(void) @@ -456,6 +503,8 @@ static void __init omap3_beagle_init(void) /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); + + beagle_display_init(); } static void __init omap3_beagle_map_io(void) diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 017bb2f4f7d..81bba194b03 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -600,6 +600,7 @@ struct ads7846_platform_data ads7846_config = { .get_pendown_state = ads7846_get_pendown_state, .keep_vref_on = 1, .settle_delay_usecs = 150, + .wakeup = true, }; static struct omap2_mcspi_device_config ads7846_mcspi_config = { @@ -651,11 +652,10 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | - OMAP_PIN_OFF_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | OMAP_PIN_OFF_WAKEUPENABLE), OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | - OMAP_PIN_OFF_INPUT_PULLUP | - OMAP_PIN_OFF_WAKEUPENABLE), + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else @@ -702,6 +702,9 @@ static void __init omap3_evm_init(void) omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP); ehci_pdata.reset_gpio_port[1] = 21; + /* EVM REV >= E can supply 500mA with EXTVBUS programming */ + musb_board_data.power = 500; + musb_board_data.extvbus = 1; } else { /* setup EHCI phy reset on MDC */ omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c new file mode 100644 index 00000000000..f848ba8dbc1 --- /dev/null +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -0,0 +1,672 @@ +/* + * linux/arch/arm/mach-omap2/board-omap3evm.c + * + * Copyright (C) 2008 Guangzhou EMA-Tech + * + * Modified from mach-omap2/board-omap3evm.c + * + * Initial code: Syed Mohammed Khasim + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/input.h> +#include <linux/gpio_keys.h> + +#include <linux/regulator/machine.h> +#include <linux/i2c/twl.h> + +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> + +#include <plat/board.h> +#include <plat/common.h> +#include <plat/gpmc.h> +#include <plat/nand.h> +#include <plat/usb.h> +#include <plat/timer-gp.h> +#include <plat/display.h> + +#include <plat/mcspi.h> +#include <linux/input/matrix_keypad.h> +#include <linux/spi/spi.h> +#include <linux/spi/ads7846.h> +#include <linux/interrupt.h> +#include <linux/smsc911x.h> +#include <linux/i2c/at24.h> + +#include "sdram-micron-mt46h32m32lf-6.h" +#include "mux.h" +#include "hsmmc.h" + +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) +#define OMAP3STALKER_ETHR_START 0x2c000000 +#define OMAP3STALKER_ETHR_SIZE 1024 +#define OMAP3STALKER_ETHR_GPIO_IRQ 19 +#define OMAP3STALKER_SMC911X_CS 5 + +static struct resource omap3stalker_smsc911x_resources[] = { + [0] = { + .start = OMAP3STALKER_ETHR_START, + .end = + (OMAP3STALKER_ETHR_START + OMAP3STALKER_ETHR_SIZE - 1), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = OMAP_GPIO_IRQ(OMAP3STALKER_ETHR_GPIO_IRQ), + .end = OMAP_GPIO_IRQ(OMAP3STALKER_ETHR_GPIO_IRQ), + .flags = (IORESOURCE_IRQ | IRQF_TRIGGER_LOW), + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = (SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS), +}; + +static struct platform_device omap3stalker_smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(omap3stalker_smsc911x_resources), + .resource = &omap3stalker_smsc911x_resources[0], + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static inline void __init omap3stalker_init_eth(void) +{ + int eth_cs; + struct clk *l3ck; + unsigned int rate; + + eth_cs = OMAP3STALKER_SMC911X_CS; + + l3ck = clk_get(NULL, "l3_ck"); + if (IS_ERR(l3ck)) + rate = 100000000; + else + rate = clk_get_rate(l3ck); + + omap_mux_init_gpio(19, OMAP_PIN_INPUT_PULLUP); + if (gpio_request(OMAP3STALKER_ETHR_GPIO_IRQ, "SMC911x irq") < 0) { + printk(KERN_ERR + "Failed to request GPIO%d for smc911x IRQ\n", + OMAP3STALKER_ETHR_GPIO_IRQ); + return; + } + + gpio_direction_input(OMAP3STALKER_ETHR_GPIO_IRQ); + + platform_device_register(&omap3stalker_smsc911x_device); +} + +#else +static inline void __init omap3stalker_init_eth(void) +{ + return; +} +#endif + +/* + * OMAP3 DSS control signals + */ + +#define DSS_ENABLE_GPIO 199 +#define LCD_PANEL_BKLIGHT_GPIO 210 +#define ENABLE_VPLL2_DEV_GRP 0xE0 + +static int lcd_enabled; +static int dvi_enabled; + +static void __init omap3_stalker_display_init(void) +{ + return; +} + +static int omap3_stalker_enable_lcd(struct omap_dss_device *dssdev) +{ + if (dvi_enabled) { + printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); + return -EINVAL; + } + gpio_set_value(DSS_ENABLE_GPIO, 1); + gpio_set_value(LCD_PANEL_BKLIGHT_GPIO, 1); + lcd_enabled = 1; + return 0; +} + +static void omap3_stalker_disable_lcd(struct omap_dss_device *dssdev) +{ + gpio_set_value(DSS_ENABLE_GPIO, 0); + gpio_set_value(LCD_PANEL_BKLIGHT_GPIO, 0); + lcd_enabled = 0; +} + +static struct omap_dss_device omap3_stalker_lcd_device = { + .name = "lcd", + .driver_name = "generic_panel", + .phy.dpi.data_lines = 24, + .type = OMAP_DISPLAY_TYPE_DPI, + .platform_enable = omap3_stalker_enable_lcd, + .platform_disable = omap3_stalker_disable_lcd, +}; + +static int omap3_stalker_enable_tv(struct omap_dss_device *dssdev) +{ + return 0; +} + +static void omap3_stalker_disable_tv(struct omap_dss_device *dssdev) +{ +} + +static struct omap_dss_device omap3_stalker_tv_device = { + .name = "tv", + .driver_name = "venc", + .type = OMAP_DISPLAY_TYPE_VENC, +#if defined(CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO) + .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE) + .u.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE, +#endif + .platform_enable = omap3_stalker_enable_tv, + .platform_disable = omap3_stalker_disable_tv, +}; + +static int omap3_stalker_enable_dvi(struct omap_dss_device *dssdev) +{ + if (lcd_enabled) { + printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); + return -EINVAL; + } + gpio_set_value(DSS_ENABLE_GPIO, 1); + dvi_enabled = 1; + return 0; +} + +static void omap3_stalker_disable_dvi(struct omap_dss_device *dssdev) +{ + gpio_set_value(DSS_ENABLE_GPIO, 0); + dvi_enabled = 0; +} + +static struct omap_dss_device omap3_stalker_dvi_device = { + .name = "dvi", + .driver_name = "generic_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 24, + .platform_enable = omap3_stalker_enable_dvi, + .platform_disable = omap3_stalker_disable_dvi, +}; + +static struct omap_dss_device *omap3_stalker_dss_devices[] = { + &omap3_stalker_lcd_device, + &omap3_stalker_tv_device, + &omap3_stalker_dvi_device, +}; + +static struct omap_dss_board_info omap3_stalker_dss_data = { + .num_devices = ARRAY_SIZE(omap3_stalker_dss_devices), + .devices = omap3_stalker_dss_devices, + .default_device = &omap3_stalker_dvi_device, +}; + +static struct platform_device omap3_stalker_dss_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = &omap3_stalker_dss_data, + }, +}; + +static struct regulator_consumer_supply omap3stalker_vmmc1_supply = { + .supply = "vmmc", +}; + +static struct regulator_consumer_supply omap3stalker_vsim_supply = { + .supply = "vmmc_aux", +}; + +/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ +static struct regulator_init_data omap3stalker_vmmc1 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &omap3stalker_vmmc1_supply, +}; + +/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ +static struct regulator_init_data omap3stalker_vsim = { + .constraints = { + .min_uV = 1800000, + .max_uV = 3000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &omap3stalker_vsim_supply, +}; + +static struct omap2_hsmmc_info mmc[] = { + { + .mmc = 1, + .wires = 4, + .gpio_cd = -EINVAL, + .gpio_wp = 23, + }, + {} /* Terminator */ +}; + +static struct gpio_keys_button gpio_buttons[] = { + { + .code = BTN_EXTRA, + .gpio = 18, + .desc = "user", + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data gpio_key_info = { + .buttons = gpio_buttons, + .nbuttons = ARRAY_SIZE(gpio_buttons), +}; + +static struct platform_device keys_gpio = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &gpio_key_info, + }, +}; + +static struct gpio_led gpio_leds[] = { + { + .name = "stalker:D8:usr0", + .default_trigger = "default-on", + .gpio = 126, + }, + { + .name = "stalker:D9:usr1", + .default_trigger = "default-on", + .gpio = 127, + }, + { + .name = "stalker:D3:mmc0", + .gpio = -EINVAL, /* gets replaced */ + .active_low = true, + .default_trigger = "mmc0", + }, + { + .name = "stalker:D4:heartbeat", + .gpio = -EINVAL, /* gets replaced */ + .active_low = true, + .default_trigger = "heartbeat", + }, +}; + +static struct gpio_led_platform_data gpio_led_info = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpio_led_info, + }, +}; + +static int +omap3stalker_twl_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) +{ + /* gpio + 0 is "mmc0_cd" (input/IRQ) */ + omap_mux_init_gpio(23, OMAP_PIN_INPUT); + mmc[0].gpio_cd = gpio + 0; + omap2_hsmmc_init(mmc); + + /* link regulators to MMC adapters */ + omap3stalker_vmmc1_supply.dev = mmc[0].dev; + omap3stalker_vsim_supply.dev = mmc[0].dev; + + /* + * Most GPIOs are for USB OTG. Some are mostly sent to + * the P2 connector; notably LEDA for the LCD backlight. + */ + + /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */ + gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); + gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); + + /* gpio + 7 == DVI Enable */ + gpio_request(gpio + 7, "EN_DVI"); + gpio_direction_output(gpio + 7, 0); + + /* TWL4030_GPIO_MAX + 1 == ledB (out, mmc0) */ + gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; + /* GPIO + 13 == ledsync (out, heartbeat) */ + gpio_leds[3].gpio = gpio + 13; + + platform_device_register(&leds_gpio); + return 0; +} + +static struct twl4030_gpio_platform_data omap3stalker_gpio_data = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, + .use_leds = true, + .setup = omap3stalker_twl_gpio_setup, +}; + +static struct twl4030_usb_data omap3stalker_usb_data = { + .usb_mode = T2_USB_MODE_ULPI, +}; + +static int board_keymap[] = { + KEY(0, 0, KEY_LEFT), + KEY(0, 1, KEY_DOWN), + KEY(0, 2, KEY_ENTER), + KEY(0, 3, KEY_M), + + KEY(1, 0, KEY_RIGHT), + KEY(1, 1, KEY_UP), + KEY(1, 2, KEY_I), + KEY(1, 3, KEY_N), + + KEY(2, 0, KEY_A), + KEY(2, 1, KEY_E), + KEY(2, 2, KEY_J), + KEY(2, 3, KEY_O), + + KEY(3, 0, KEY_B), + KEY(3, 1, KEY_F), + KEY(3, 2, KEY_K), + KEY(3, 3, KEY_P) +}; + +static struct matrix_keymap_data board_map_data = { + .keymap = board_keymap, + .keymap_size = ARRAY_SIZE(board_keymap), +}; + +static struct twl4030_keypad_data omap3stalker_kp_data = { + .keymap_data = &board_map_data, + .rows = 4, + .cols = 4, + .rep = 1, +}; + +static struct twl4030_madc_platform_data omap3stalker_madc_data = { + .irq_line = 1, +}; + +static struct twl4030_codec_audio_data omap3stalker_audio_data = { + .audio_mclk = 26000000, +}; + +static struct twl4030_codec_data omap3stalker_codec_data = { + .audio_mclk = 26000000, + .audio = &omap3stalker_audio_data, +}; + +static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = { + .supply = "vdda_dac", + .dev = &omap3_stalker_dss_device.dev, +}; + +/* VDAC for DSS driving S-Video */ +static struct regulator_init_data omap3_stalker_vdac = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &omap3_stalker_vdda_dac_supply, +}; + +/* VPLL2 for digital video outputs */ +static struct regulator_consumer_supply omap3_stalker_vpll2_supply = { + .supply = "vdds_dsi", + .dev = &omap3_stalker_lcd_device.dev, +}; + +static struct regulator_init_data omap3_stalker_vpll2 = { + .constraints = { + .name = "VDVI", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &omap3_stalker_vpll2_supply, +}; + +static struct twl4030_platform_data omap3stalker_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + + /* platform_data for children goes here */ + .keypad = &omap3stalker_kp_data, + .madc = &omap3stalker_madc_data, + .usb = &omap3stalker_usb_data, + .gpio = &omap3stalker_gpio_data, + .codec = &omap3stalker_codec_data, + .vdac = &omap3_stalker_vdac, + .vpll2 = &omap3_stalker_vpll2, +}; + +static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &omap3stalker_twldata, + }, +}; + +static struct at24_platform_data fram_info = { + .byte_len = (64 * 1024) / 8, + .page_size = 8192, + .flags = AT24_FLAG_ADDR16 | AT24_FLAG_IRUGO, +}; + +static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo3[] = { + { + I2C_BOARD_INFO("24c64", 0x50), + .flags = I2C_CLIENT_WAKE, + .platform_data = &fram_info, + }, +}; + +static int __init omap3_stalker_i2c_init(void) +{ + /* + * REVISIT: These entries can be set in omap3evm_twl_data + * after a merge with MFD tree + */ + omap3stalker_twldata.vmmc1 = &omap3stalker_vmmc1; + omap3stalker_twldata.vsim = &omap3stalker_vsim; + + omap_register_i2c_bus(1, 2600, omap3stalker_i2c_boardinfo, + ARRAY_SIZE(omap3stalker_i2c_boardinfo)); + omap_register_i2c_bus(2, 400, NULL, 0); + omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3, + ARRAY_SIZE(omap3stalker_i2c_boardinfo3)); + return 0; +} + +#define OMAP3_STALKER_TS_GPIO 175 +static void ads7846_dev_init(void) +{ + if (gpio_request(OMAP3_STALKER_TS_GPIO, "ADS7846 pendown") < 0) + printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); + + gpio_direction_input(OMAP3_STALKER_TS_GPIO); + + omap_set_gpio_debounce(OMAP3_STALKER_TS_GPIO, 1); + omap_set_gpio_debounce_time(OMAP3_STALKER_TS_GPIO, 0xa); +} + +static int ads7846_get_pendown_state(void) +{ + return !gpio_get_value(OMAP3_STALKER_TS_GPIO); +} + +static struct ads7846_platform_data ads7846_config = { + .x_max = 0x0fff, + .y_max = 0x0fff, + .x_plate_ohms = 180, + .pressure_max = 255, + .debounce_max = 10, + .debounce_tol = 3, + .debounce_rep = 1, + .get_pendown_state = ads7846_get_pendown_state, + .keep_vref_on = 1, + .settle_delay_usecs = 150, +}; + +static struct omap2_mcspi_device_config ads7846_mcspi_config = { + .turbo_mode = 0, + .single_channel = 1, /* 0: slave, 1: master */ +}; + +struct spi_board_info omap3stalker_spi_board_info[] = { + [0] = { + .modalias = "ads7846", + .bus_num = 1, + .chip_select = 0, + .max_speed_hz = 1500000, + .controller_data = &ads7846_mcspi_config, + .irq = OMAP_GPIO_IRQ(OMAP3_STALKER_TS_GPIO), + .platform_data = &ads7846_config, + }, +}; + +static struct omap_board_config_kernel omap3_stalker_config[] __initdata = { +}; + +static void __init omap3_stalker_init_irq(void) +{ + omap_board_config = omap3_stalker_config; + omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); + omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL); + omap_init_irq(); +#ifdef CONFIG_OMAP_32K_TIMER + omap2_gp_clockevent_set_gptimer(12); +#endif + omap_gpio_init(); +} + +static struct platform_device *omap3_stalker_devices[] __initdata = { + &omap3_stalker_dss_device, + &keys_gpio, +}; + +static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { + .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = 21, + .reset_gpio_port[2] = -EINVAL, +}; + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), + {.reg_offset = OMAP_MUX_TERMINATOR}, +}; +#else +#define board_mux NULL +#endif + +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_ULPI, + .mode = MUSB_OTG, + .power = 100, +}; + +static void __init omap3_stalker_init(void) +{ + omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); + + omap3_stalker_i2c_init(); + + platform_add_devices(omap3_stalker_devices, + ARRAY_SIZE(omap3_stalker_devices)); + + spi_register_board_info(omap3stalker_spi_board_info, + ARRAY_SIZE(omap3stalker_spi_board_info)); + + omap_serial_init(); + usb_musb_init(&musb_board_data); + usb_ehci_init(&ehci_pdata); + ads7846_dev_init(); + + omap_mux_init_gpio(21, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(18, OMAP_PIN_INPUT_PULLUP); + + omap3stalker_init_eth(); + omap3_stalker_display_init(); +/* Ensure SDRC pins are mux'd for self-refresh */ + omap_mux_init_signal("sdr_cke0", OMAP_PIN_OUTPUT); + omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT); +} + +static void __init omap3_stalker_map_io(void) +{ + omap2_set_globals_343x(); + omap34xx_map_common_io(); +} + +MACHINE_START(SBC3530, "OMAP3 STALKER") + /* Maintainer: Jason Lam -lzg@ema-tech.com */ + .phys_io = 0x48000000, + .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = omap3_stalker_map_io, + .init_irq = omap3_stalker_init_irq, + .init_machine = omap3_stalker_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 8848c7c5ce4..79ac41400c2 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -63,6 +63,8 @@ #define OVERO_SMSC911X_CS 5 #define OVERO_SMSC911X_GPIO 176 +#define OVERO_SMSC911X2_CS 4 +#define OVERO_SMSC911X2_GPIO 65 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) @@ -137,6 +139,16 @@ static struct resource overo_smsc911x_resources[] = { }, }; +static struct resource overo_smsc911x2_resources[] = { + { + .name = "smsc911x2-memory", + .flags = IORESOURCE_MEM, + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, + }, +}; + static struct smsc911x_platform_config overo_smsc911x_config = { .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, @@ -146,7 +158,7 @@ static struct smsc911x_platform_config overo_smsc911x_config = { static struct platform_device overo_smsc911x_device = { .name = "smsc911x", - .id = -1, + .id = 0, .num_resources = ARRAY_SIZE(overo_smsc911x_resources), .resource = overo_smsc911x_resources, .dev = { diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 4377a4cf36e..abdf321c2d4 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -45,6 +45,8 @@ /* list all spi devices here */ enum { RX51_SPI_WL1251, + RX51_SPI_MIPID, /* LCD panel */ + RX51_SPI_TSC2005, /* Touch Controller */ }; static struct wl12xx_platform_data wl1251_pdata; @@ -54,6 +56,16 @@ static struct omap2_mcspi_device_config wl1251_mcspi_config = { .single_channel = 1, }; +static struct omap2_mcspi_device_config mipid_mcspi_config = { + .turbo_mode = 0, + .single_channel = 1, +}; + +static struct omap2_mcspi_device_config tsc2005_mcspi_config = { + .turbo_mode = 0, + .single_channel = 1, +}; + static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = { [RX51_SPI_WL1251] = { .modalias = "wl1251", @@ -64,6 +76,22 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = { .controller_data = &wl1251_mcspi_config, .platform_data = &wl1251_pdata, }, + [RX51_SPI_MIPID] = { + .modalias = "acx565akm", + .bus_num = 1, + .chip_select = 2, + .max_speed_hz = 6000000, + .controller_data = &mipid_mcspi_config, + }, + [RX51_SPI_TSC2005] = { + .modalias = "tsc2005", + .bus_num = 1, + .chip_select = 0, + /* .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),*/ + .max_speed_hz = 6000000, + .controller_data = &tsc2005_mcspi_config, + /* .platform_data = &tsc2005_config,*/ + }, }; #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) @@ -277,7 +305,7 @@ static struct regulator_consumer_supply rx51_vmmc1_supply = { .dev_name = "mmci-omap-hs.0", }; -static struct regulator_consumer_supply rx51_vmmc2_supply = { +static struct regulator_consumer_supply rx51_vaux3_supply = { .supply = "vmmc", .dev_name = "mmci-omap-hs.1", }; @@ -287,6 +315,48 @@ static struct regulator_consumer_supply rx51_vsim_supply = { .dev_name = "mmci-omap-hs.1", }; +static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { + /* tlv320aic3x analog supplies */ + { + .supply = "AVDD", + .dev_name = "2-0018", + }, + { + .supply = "DRVDD", + .dev_name = "2-0018", + }, + /* Keep vmmc as last item. It is not iterated for newer boards */ + { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.1", + }, +}; + +static struct regulator_consumer_supply rx51_vio_supplies[] = { + /* tlv320aic3x digital supplies */ + { + .supply = "IOVDD", + .dev_name = "2-0018" + }, + { + .supply = "DVDD", + .dev_name = "2-0018" + }, +}; + +#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) +extern struct platform_device rx51_display_device; +#endif + +static struct regulator_consumer_supply rx51_vaux1_consumers[] = { +#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) + { + .supply = "vdds_sdi", + .dev = &rx51_display_device.dev, + }, +#endif +}; + static struct regulator_init_data rx51_vaux1 = { .constraints = { .name = "V28", @@ -297,6 +367,8 @@ static struct regulator_init_data rx51_vaux1 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, + .num_consumer_supplies = ARRAY_SIZE(rx51_vaux1_consumers), + .consumer_supplies = rx51_vaux1_consumers, }; static struct regulator_init_data rx51_vaux2 = { @@ -338,7 +410,7 @@ static struct regulator_init_data rx51_vaux3_mmc = { | REGULATOR_CHANGE_STATUS, }, .num_consumer_supplies = 1, - .consumer_supplies = &rx51_vmmc2_supply, + .consumer_supplies = &rx51_vaux3_supply, }; static struct regulator_init_data rx51_vaux4 = { @@ -370,9 +442,9 @@ static struct regulator_init_data rx51_vmmc1 = { static struct regulator_init_data rx51_vmmc2 = { .constraints = { - .name = "VMMC2_30", - .min_uV = 1850000, - .max_uV = 3150000, + .name = "V28_A", + .min_uV = 2800000, + .max_uV = 3000000, .apply_uV = true, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, @@ -380,8 +452,8 @@ static struct regulator_init_data rx51_vmmc2 = { | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &rx51_vmmc2_supply, + .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc2_supplies), + .consumer_supplies = rx51_vmmc2_supplies, }; static struct regulator_init_data rx51_vsim = { @@ -411,6 +483,20 @@ static struct regulator_init_data rx51_vdac = { }, }; +static struct regulator_init_data rx51_vio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(rx51_vio_supplies), + .consumer_supplies = rx51_vio_supplies, +}; + static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) { /* FIXME this gpio setup is just a placeholder for now */ @@ -618,6 +704,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = { .vmmc1 = &rx51_vmmc1, .vsim = &rx51_vsim, .vdac = &rx51_vdac, + .vio = &rx51_vio, }; static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { @@ -629,18 +716,27 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { }, }; +static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { + { + I2C_BOARD_INFO("tlv320aic3x", 0x18), + }, +}; + static int __init rx51_i2c_init(void) { if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) || - system_rev >= SYSTEM_REV_B_USES_VAUX3) + system_rev >= SYSTEM_REV_B_USES_VAUX3) { rx51_twldata.vaux3 = &rx51_vaux3_mmc; - else { + /* Only older boards use VMMC2 for internal MMC */ + rx51_vmmc2.num_consumer_supplies--; + } else { rx51_twldata.vaux3 = &rx51_vaux3_cam; - rx51_twldata.vmmc2 = &rx51_vmmc2; } + rx51_twldata.vmmc2 = &rx51_vmmc2; omap_register_i2c_bus(1, 2200, rx51_peripherals_i2c_board_info_1, - ARRAY_SIZE(rx51_peripherals_i2c_board_info_1)); - omap_register_i2c_bus(2, 100, NULL, 0); + ARRAY_SIZE(rx51_peripherals_i2c_board_info_1)); + omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2, + ARRAY_SIZE(rx51_peripherals_i2c_board_info_2)); omap_register_i2c_bus(3, 400, NULL, 0); return 0; } diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c new file mode 100644 index 00000000000..b743a4f4264 --- /dev/null +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -0,0 +1,109 @@ +/* + * linux/arch/arm/mach-omap2/board-rx51-video.c + * + * Copyright (C) 2010 Nokia + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/spi/spi.h> +#include <linux/mm.h> + +#include <asm/mach-types.h> +#include <plat/mux.h> +#include <plat/display.h> +#include <plat/vram.h> +#include <plat/mcspi.h> + +#include "mux.h" + +#define RX51_LCD_RESET_GPIO 90 + +#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) + +static int rx51_lcd_enable(struct omap_dss_device *dssdev) +{ + gpio_set_value(dssdev->reset_gpio, 1); + return 0; +} + +static void rx51_lcd_disable(struct omap_dss_device *dssdev) +{ + gpio_set_value(dssdev->reset_gpio, 0); +} + +static struct omap_dss_device rx51_lcd_device = { + .name = "lcd", + .driver_name = "panel-acx565akm", + .type = OMAP_DISPLAY_TYPE_SDI, + .phy.sdi.datapairs = 2, + .reset_gpio = RX51_LCD_RESET_GPIO, + .platform_enable = rx51_lcd_enable, + .platform_disable = rx51_lcd_disable, +}; + +static struct omap_dss_device *rx51_dss_devices[] = { + &rx51_lcd_device, +}; + +static struct omap_dss_board_info rx51_dss_board_info = { + .num_devices = ARRAY_SIZE(rx51_dss_devices), + .devices = rx51_dss_devices, + .default_device = &rx51_lcd_device, +}; + +struct platform_device rx51_display_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = &rx51_dss_board_info, + }, +}; + +static struct platform_device *rx51_video_devices[] __initdata = { + &rx51_display_device, +}; + +static int __init rx51_video_init(void) +{ + if (!machine_is_nokia_rx51()) + return 0; + + if (omap_mux_init_gpio(RX51_LCD_RESET_GPIO, OMAP_PIN_OUTPUT)) { + pr_err("%s cannot configure MUX for LCD RESET\n", __func__); + return 0; + } + + if (gpio_request(RX51_LCD_RESET_GPIO, "LCD ACX565AKM reset")) { + pr_err("%s failed to get LCD Reset GPIO\n", __func__); + return 0; + } + + gpio_direction_output(RX51_LCD_RESET_GPIO, 1); + + platform_add_devices(rx51_video_devices, + ARRAY_SIZE(rx51_video_devices)); + return 0; +} + +subsys_initcall(rx51_video_init); + +void __init rx51_video_mem_init(void) +{ + /* + * GFX 864x480x32bpp + * VID1/2 1280x720x32bpp double buffered + */ + omap_vram_set_sdram_vram(PAGE_ALIGN(864 * 480 * 4) + + 2 * PAGE_ALIGN(1280 * 720 * 4 * 2), 0); +} + +#else +void __init rx51_video_mem_init(void) { } +#endif /* defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) */ diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index b155c366c65..1b86b5bb87a 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -36,6 +36,7 @@ #define RX51_GPIO_SLEEP_IND 162 struct omap_sdrc_params *rx51_get_sdram_timings(void); +extern void rx51_video_mem_init(void); static struct gpio_led gpio_leds[] = { { @@ -143,6 +144,7 @@ static void __init rx51_init(void) static void __init rx51_map_io(void) { omap2_set_globals_343x(); + rx51_video_mem_init(); omap34xx_map_common_io(); } diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c index e15d2e87cfc..1d7f827b040 100644 --- a/arch/arm/mach-omap2/board-zoom-debugboard.c +++ b/arch/arm/mach-omap2/board-zoom-debugboard.c @@ -82,7 +82,7 @@ static inline void __init zoom_init_smsc911x(void) static struct plat_serial8250_port serial_platform_data[] = { { - .mapbase = 0x10000000, + .mapbase = ZOOM_UART_BASE, .irq = OMAP_GPIO_IRQ(102), .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ, .irqflags = IRQF_SHARED | IRQF_TRIGGER_RISING, diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 9a26f84b114..803ef14cbf2 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -91,8 +91,8 @@ static void __init omap_zoom2_map_io(void) } MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") - .phys_io = 0x48000000, - .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, + .phys_io = ZOOM_UART_BASE, + .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_zoom2_map_io, .init_irq = omap_zoom2_init_irq, diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index cd3e40cf3ac..33147042485 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -73,8 +73,8 @@ static void __init omap_zoom_init(void) } MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") - .phys_io = 0x48000000, - .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, + .phys_io = ZOOM_UART_BASE, + .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_zoom_map_io, .init_irq = omap_zoom_init_irq, diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index 43d7246ce33..66e01acfd58 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -70,12 +70,12 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) static int omap2_clk_apll96_enable(struct clk *clk) { - return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL); + return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK); } static int omap2_clk_apll54_enable(struct clk *clk) { - return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL); + return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK); } /* Stop APLL */ diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index e60ca4e47bb..aef62918aaf 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -68,16 +68,13 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) { const struct prcm_config *ptr; long highest_rate; - long sys_ck_rate; - - sys_ck_rate = clk_get_rate(sclk); highest_rate = -EINVAL; for (ptr = rate_table; ptr->mpu_speed; ptr++) { if (!(ptr->flags & cpu_mask)) continue; - if (ptr->xtal_speed != sys_ck_rate) + if (ptr->xtal_speed != sclk->rate) continue; highest_rate = ptr->mpu_speed; @@ -96,15 +93,12 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) const struct prcm_config *prcm; unsigned long found_speed = 0; unsigned long flags; - long sys_ck_rate; - - sys_ck_rate = clk_get_rate(sclk); for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; - if (prcm->xtal_speed != sys_ck_rate) + if (prcm->xtal_speed != sclk->rate) continue; if (prcm->mpu_speed <= rate) { @@ -181,19 +175,16 @@ static struct cpufreq_frequency_table *freq_table; void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) { const struct prcm_config *prcm; - long sys_ck_rate; int i = 0; int tbl_sz = 0; if (!cpu_is_omap24xx()) return; - sys_ck_rate = clk_get_rate(sclk); - for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; - if (prcm->xtal_speed != sys_ck_rate) + if (prcm->xtal_speed != sclk->rate) continue; /* don't put bypass rates in table */ @@ -226,7 +217,7 @@ void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; - if (prcm->xtal_speed != sys_ck_rate) + if (prcm->xtal_speed != sclk->rate) continue; /* don't put bypass rates in table */ diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index e50812dd03f..a781cd6795a 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -12,8 +12,26 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * XXX At some point these clksel clocks should be split into - * "divider" clocks and "mux" clocks to better match the hardware. + * + * clksel clocks are clocks that do not have a fixed parent, or that + * can divide their parent's rate, or possibly both at the same time, based + * on the contents of a hardware register bitfield. + * + * All of the various mux and divider settings can be encoded into + * struct clksel* data structures, and then these can be autogenerated + * from some hardware database for each new chip generation. This + * should avoid the need to write, review, and validate a lot of new + * clock code for each new chip, since it can be exported from the SoC + * design flow. This is now done on OMAP4. + * + * The fusion of mux and divider clocks is a software creation. In + * hardware reality, the multiplexer (parent selection) and the + * divider exist separately. XXX At some point these clksel clocks + * should be split into "divider" clocks and "mux" clocks to better + * match the hardware. + * + * (The name "clksel" comes from the name of the corresponding + * register field in the OMAP2/3 family of SoCs.) * * XXX Currently these clocks are only used in the OMAP2/3/4 code, but * many of the OMAP1 clocks should be convertible to use this @@ -29,14 +47,11 @@ #include <plat/clock.h> #include "clock.h" -#include "cm.h" -#include "cm-regbits-24xx.h" -#include "cm-regbits-34xx.h" /* Private functions */ /** - * _omap2_get_clksel_by_parent - return clksel struct for a given clk & parent + * _get_clksel_by_parent() - return clksel struct for a given clk & parent * @clk: OMAP struct clk ptr to inspect * @src_clk: OMAP struct clk ptr of the parent clk to search for * @@ -44,141 +59,217 @@ * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ -static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk, - struct clk *src_clk) +static const struct clksel *_get_clksel_by_parent(struct clk *clk, + struct clk *src_clk) { const struct clksel *clks; - if (!clk->clksel) - return NULL; - - for (clks = clk->clksel; clks->parent; clks++) { + for (clks = clk->clksel; clks->parent; clks++) if (clks->parent == src_clk) break; /* Found the requested parent */ - } if (!clks->parent) { - printk(KERN_ERR "clock: Could not find parent clock %s in " - "clksel array of clock %s\n", src_clk->name, - clk->name); + /* This indicates a data problem */ + WARN(1, "clock: Could not find parent clock %s in clksel array " + "of clock %s\n", src_clk->name, clk->name); return NULL; } return clks; } -/* - * Converts encoded control register address into a full address - * On error, the return value (parent_div) will be 0. +/** + * _get_div_and_fieldval() - find the new clksel divisor and field value to use + * @src_clk: planned new parent struct clk * + * @clk: struct clk * that is being reparented + * @field_val: pointer to a u32 to contain the register data for the divisor + * + * Given an intended new parent struct clk * @src_clk, and the struct + * clk * @clk to the clock that is being reparented, find the + * appropriate rate divisor for the new clock (returned as the return + * value), and the corresponding register bitfield data to program to + * reach that divisor (returned in the u32 pointed to by @field_val). + * Returns 0 on error, or returns the newly-selected divisor upon + * success (in this latter case, the corresponding register bitfield + * value is passed back in the variable pointed to by @field_val) */ -static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, - u32 *field_val) +static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, + u32 *field_val) { const struct clksel *clks; - const struct clksel_rate *clkr; + const struct clksel_rate *clkr, *max_clkr; + u8 max_div = 0; - clks = _omap2_get_clksel_by_parent(clk, src_clk); + clks = _get_clksel_by_parent(clk, src_clk); if (!clks) return 0; + /* + * Find the highest divisor (e.g., the one resulting in the + * lowest rate) to use as the default. This should avoid + * clock rates that are too high for the device. XXX A better + * solution here would be to try to determine if there is a + * divisor matching the original clock rate before the parent + * switch, and if it cannot be found, to fall back to the + * highest divisor. + */ for (clkr = clks->rates; clkr->div; clkr++) { - if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) - break; /* Found the default rate for this platform */ + if (!(clkr->flags & cpu_mask)) + continue; + + if (clkr->div > max_div) { + max_div = clkr->div; + max_clkr = clkr; + } } - if (!clkr->div) { - printk(KERN_ERR "clock: Could not find default rate for " - "clock %s parent %s\n", clk->name, - src_clk->parent->name); + if (max_div == 0) { + /* This indicates an error in the clksel data */ + WARN(1, "clock: Could not find divisor for clock %s parent %s" + "\n", clk->name, src_clk->parent->name); return 0; } - /* Should never happen. Add a clksel mask to the struct clk. */ - WARN_ON(clk->clksel_mask == 0); + *field_val = max_clkr->val; - *field_val = clkr->val; - - return clkr->div; + return max_div; } +/** + * _write_clksel_reg() - program a clock's clksel register in hardware + * @clk: struct clk * to program + * @v: clksel bitfield value to program (with LSB at bit 0) + * + * Shift the clksel register bitfield value @v to its appropriate + * location in the clksel register and write it in. This function + * will ensure that the write to the clksel_reg reaches its + * destination before returning -- important since PRM and CM register + * accesses can be quite slow compared to ARM cycles -- but does not + * take into account any time the hardware might take to switch the + * clock source. + */ +static void _write_clksel_reg(struct clk *clk, u32 field_val) +{ + u32 v; -/* Public functions */ + v = __raw_readl(clk->clksel_reg); + v &= ~clk->clksel_mask; + v |= field_val << __ffs(clk->clksel_mask); + __raw_writel(v, clk->clksel_reg); + + v = __raw_readl(clk->clksel_reg); /* OCP barrier */ +} /** - * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware - * @clk: OMAP clock struct ptr to use + * _clksel_to_divisor() - turn clksel field value into integer divider + * @clk: OMAP struct clk to use + * @field_val: register field value to find * - * Given a pointer to a source-selectable struct clk, read the hardware - * register and determine what its parent is currently set to. Update the - * clk->parent field with the appropriate clk ptr. + * Given a struct clk of a rate-selectable clksel clock, and a register field + * value to search for, find the corresponding clock divisor. The register + * field value should be pre-masked and shifted down so the LSB is at bit 0 + * before calling. Returns 0 on error or returns the actual integer divisor + * upon success. */ -void omap2_init_clksel_parent(struct clk *clk) +static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) { const struct clksel *clks; const struct clksel_rate *clkr; - u32 r, found = 0; - if (!clk->clksel) - return; + clks = _get_clksel_by_parent(clk, clk->parent); + if (!clks) + return 0; - r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; - r >>= __ffs(clk->clksel_mask); + for (clkr = clks->rates; clkr->div; clkr++) { + if (!(clkr->flags & cpu_mask)) + continue; - for (clks = clk->clksel; clks->parent && !found; clks++) { - for (clkr = clks->rates; clkr->div && !found; clkr++) { - if ((clkr->flags & cpu_mask) && (clkr->val == r)) { - if (clk->parent != clks->parent) { - pr_debug("clock: inited %s parent " - "to %s (was %s)\n", - clk->name, clks->parent->name, - ((clk->parent) ? - clk->parent->name : "NULL")); - clk_reparent(clk, clks->parent); - }; - found = 1; - } - } + if (clkr->val == field_val) + break; } - if (!found) - printk(KERN_ERR "clock: init parent: could not find " - "regval %0x for clock %s\n", r, clk->name); + if (!clkr->div) { + /* This indicates a data error */ + WARN(1, "clock: Could not find fieldval %d for clock %s parent " + "%s\n", field_val, clk->name, clk->parent->name); + return 0; + } - return; + return clkr->div; } -/* - * Used for clocks that are part of CLKSEL_xyz governed clocks. - * REVISIT: Maybe change to use clk->enable() functions like on omap1? +/** + * _divisor_to_clksel() - turn clksel integer divisor into a field value + * @clk: OMAP struct clk to use + * @div: integer divisor to search for + * + * Given a struct clk of a rate-selectable clksel clock, and a clock + * divisor, find the corresponding register field value. Returns the + * register field value _before_ left-shifting (i.e., LSB is at bit + * 0); or returns 0xFFFFFFFF (~0) upon error. */ -unsigned long omap2_clksel_recalc(struct clk *clk) +static u32 _divisor_to_clksel(struct clk *clk, u32 div) { - unsigned long rate; - u32 div = 0; + const struct clksel *clks; + const struct clksel_rate *clkr; - pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); + /* should never happen */ + WARN_ON(div == 0); - div = omap2_clksel_get_divisor(clk); - if (div == 0) - return clk->rate; + clks = _get_clksel_by_parent(clk, clk->parent); + if (!clks) + return ~0; - rate = clk->parent->rate / div; + for (clkr = clks->rates; clkr->div; clkr++) { + if (!(clkr->flags & cpu_mask)) + continue; - pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); + if (clkr->div == div) + break; + } - return rate; + if (!clkr->div) { + pr_err("clock: Could not find divisor %d for clock %s parent " + "%s\n", div, clk->name, clk->parent->name); + return ~0; + } + + return clkr->val; +} + +/** + * _read_divisor() - get current divisor applied to parent clock (from hdwr) + * @clk: OMAP struct clk to use. + * + * Read the current divisor register value for @clk that is programmed + * into the hardware, convert it into the actual divisor value, and + * return it; or return 0 on error. + */ +static u32 _read_divisor(struct clk *clk) +{ + u32 v; + + if (!clk->clksel || !clk->clksel_mask) + return 0; + + v = __raw_readl(clk->clksel_reg); + v &= clk->clksel_mask; + v >>= __ffs(clk->clksel_mask); + + return _clksel_to_divisor(clk, v); } +/* Public functions */ + /** - * omap2_clksel_round_rate_div - find divisor for the given clock and rate + * omap2_clksel_round_rate_div() - find divisor for the given clock and rate * @clk: OMAP struct clk to use * @target_rate: desired clock rate * @new_div: ptr to where we should store the divisor * * Finds 'best' divider value in an array based on the source and target * rates. The divider array must be sorted with smallest divider first. - * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, - * they are only settable as part of virtual_prcm set. + * This function is also used by the DPLL3 M2 divider code. * * Returns the rounded clock rate or returns 0xffffffff on error. */ @@ -190,12 +281,15 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, const struct clksel_rate *clkr; u32 last_div = 0; + if (!clk->clksel || !clk->clksel_mask) + return ~0; + pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", clk->name, target_rate); *new_div = 1; - clks = _omap2_get_clksel_by_parent(clk, clk->parent); + clks = _get_clksel_by_parent(clk, clk->parent); if (!clks) return ~0; @@ -231,168 +325,174 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, return clk->parent->rate / clkr->div; } -/** - * omap2_clksel_round_rate - find rounded rate for the given clock and rate - * @clk: OMAP struct clk to use - * @target_rate: desired clock rate - * - * Compatibility wrapper for OMAP clock framework - * Finds best target rate based on the source clock and possible dividers. - * rates. The divider array must be sorted with smallest divider first. - * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, - * they are only settable as part of virtual_prcm set. - * - * Returns the rounded clock rate or returns 0xffffffff on error. +/* + * Clocktype interface functions to the OMAP clock code + * (i.e., those used in struct clk field function pointers, etc.) */ -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) -{ - u32 new_div; - - return omap2_clksel_round_rate_div(clk, target_rate, &new_div); -} - - -/* Given a clock and a rate apply a clock specific rounding function */ -long omap2_clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (clk->round_rate) - return clk->round_rate(clk, rate); - - return clk->rate; -} /** - * omap2_clksel_to_divisor() - turn clksel field value into integer divider - * @clk: OMAP struct clk to use - * @field_val: register field value to find + * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr + * @clk: OMAP clock struct ptr to use * - * Given a struct clk of a rate-selectable clksel clock, and a register field - * value to search for, find the corresponding clock divisor. The register - * field value should be pre-masked and shifted down so the LSB is at bit 0 - * before calling. Returns 0 on error + * Given a pointer @clk to a source-selectable struct clk, read the + * hardware register and determine what its parent is currently set + * to. Update @clk's .parent field with the appropriate clk ptr. No + * return value. */ -u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) +void omap2_init_clksel_parent(struct clk *clk) { const struct clksel *clks; const struct clksel_rate *clkr; + u32 r, found = 0; - clks = _omap2_get_clksel_by_parent(clk, clk->parent); - if (!clks) - return 0; + if (!clk->clksel || !clk->clksel_mask) + return; - for (clkr = clks->rates; clkr->div; clkr++) { - if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) - break; - } + r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; + r >>= __ffs(clk->clksel_mask); - if (!clkr->div) { - printk(KERN_ERR "clock: Could not find fieldval %d for " - "clock %s parent %s\n", field_val, clk->name, - clk->parent->name); - return 0; + for (clks = clk->clksel; clks->parent && !found; clks++) { + for (clkr = clks->rates; clkr->div && !found; clkr++) { + if (!(clkr->flags & cpu_mask)) + continue; + + if (clkr->val == r) { + if (clk->parent != clks->parent) { + pr_debug("clock: inited %s parent " + "to %s (was %s)\n", + clk->name, clks->parent->name, + ((clk->parent) ? + clk->parent->name : "NULL")); + clk_reparent(clk, clks->parent); + }; + found = 1; + } + } } - return clkr->div; + /* This indicates a data error */ + WARN(!found, "clock: %s: init parent: could not find regval %0x\n", + clk->name, r); + + return; } /** - * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value - * @clk: OMAP struct clk to use - * @div: integer divisor to search for + * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field + * @clk: struct clk * * - * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, - * find the corresponding register field value. The return register value is - * the value before left-shifting. Returns ~0 on error + * This function is intended to be called only by the clock framework. + * Each clksel clock should have its struct clk .recalc field set to this + * function. Returns the clock's current rate, based on its parent's rate + * and its current divisor setting in the hardware. */ -u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) +unsigned long omap2_clksel_recalc(struct clk *clk) { - const struct clksel *clks; - const struct clksel_rate *clkr; - - /* should never happen */ - WARN_ON(div == 0); + unsigned long rate; + u32 div = 0; - clks = _omap2_get_clksel_by_parent(clk, clk->parent); - if (!clks) - return ~0; + div = _read_divisor(clk); + if (div == 0) + return clk->rate; - for (clkr = clks->rates; clkr->div; clkr++) { - if ((clkr->flags & cpu_mask) && (clkr->div == div)) - break; - } + rate = clk->parent->rate / div; - if (!clkr->div) { - printk(KERN_ERR "clock: Could not find divisor %d for " - "clock %s parent %s\n", div, clk->name, - clk->parent->name); - return ~0; - } + pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name, + rate, div); - return clkr->val; + return rate; } /** - * omap2_clksel_get_divisor - get current divider applied to parent clock. - * @clk: OMAP struct clk to use. + * omap2_clksel_round_rate() - find rounded rate for the given clock and rate + * @clk: OMAP struct clk to use + * @target_rate: desired clock rate + * + * This function is intended to be called only by the clock framework. + * Finds best target rate based on the source clock and possible dividers. + * rates. The divider array must be sorted with smallest divider first. * - * Returns the integer divisor upon success or 0 on error. + * Returns the rounded clock rate or returns 0xffffffff on error. */ -u32 omap2_clksel_get_divisor(struct clk *clk) +long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) { - u32 v; - - if (!clk->clksel_mask) - return 0; - - v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; - v >>= __ffs(clk->clksel_mask); + u32 new_div; - return omap2_clksel_to_divisor(clk, v); + return omap2_clksel_round_rate_div(clk, target_rate, &new_div); } +/** + * omap2_clksel_set_rate() - program clock rate in hardware + * @clk: struct clk * to program rate + * @rate: target rate to program + * + * This function is intended to be called only by the clock framework. + * Program @clk's rate to @rate in the hardware. The clock can be + * either enabled or disabled when this happens, although if the clock + * is enabled, some downstream devices may glitch or behave + * unpredictably when the clock rate is changed - this depends on the + * hardware. This function does not currently check the usecount of + * the clock, so if multiple drivers are using the clock, and the rate + * is changed, they will all be affected without any notification. + * Returns -EINVAL upon error, or 0 upon success. + */ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) { - u32 v, field_val, validrate, new_div = 0; + u32 field_val, validrate, new_div = 0; - if (!clk->clksel_mask) + if (!clk->clksel || !clk->clksel_mask) return -EINVAL; validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); if (validrate != rate) return -EINVAL; - field_val = omap2_divisor_to_clksel(clk, new_div); + field_val = _divisor_to_clksel(clk, new_div); if (field_val == ~0) return -EINVAL; - v = __raw_readl(clk->clksel_reg); - v &= ~clk->clksel_mask; - v |= field_val << __ffs(clk->clksel_mask); - __raw_writel(v, clk->clksel_reg); - v = __raw_readl(clk->clksel_reg); /* OCP barrier */ + _write_clksel_reg(clk, field_val); clk->rate = clk->parent->rate / new_div; + pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate); + return 0; } +/* + * Clksel parent setting function - not passed in struct clk function + * pointer - instead, the OMAP clock code currently assumes that any + * parent-setting clock is a clksel clock, and calls + * omap2_clksel_set_parent() by default + */ + +/** + * omap2_clksel_set_parent() - change a clock's parent clock + * @clk: struct clk * of the child clock + * @new_parent: struct clk * of the new parent clock + * + * This function is intended to be called only by the clock framework. + * Change the parent clock of clock @clk to @new_parent. This is + * intended to be used while @clk is disabled. This function does not + * currently check the usecount of the clock, so if multiple drivers + * are using the clock, and the parent is changed, they will all be + * affected without any notification. Returns -EINVAL upon error, or + * 0 upon success. + */ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) { - u32 field_val, v, parent_div; + u32 field_val = 0; + u32 parent_div; - if (!clk->clksel) + if (!clk->clksel || !clk->clksel_mask) return -EINVAL; - parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); + parent_div = _get_div_and_fieldval(new_parent, clk, &field_val); if (!parent_div) return -EINVAL; - /* Set new source value (previous dividers if any in effect) */ - v = __raw_readl(clk->clksel_reg); - v &= ~clk->clksel_mask; - v |= field_val << __ffs(clk->clksel_mask); - __raw_writel(v, clk->clksel_reg); - v = __raw_readl(clk->clksel_reg); /* OCP barrier */ + _write_clksel_reg(clk, field_val); clk_reparent(clk, new_parent); @@ -402,7 +502,7 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) if (parent_div > 0) clk->rate /= parent_div; - pr_debug("clock: set parent of %s to %s (new rate %ld)\n", + pr_debug("clock: %s: set parent to %s (new rate %ld)\n", clk->name, clk->parent->name, clk->rate); return 0; diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index a6d0b34b799..605f531783a 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -334,6 +334,15 @@ oce_err1: return ret; } +/* Given a clock and a rate apply a clock specific rounding function */ +long omap2_clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk->round_rate) + return clk->round_rate(clk, rate); + + return clk->rate; +} + /* Set the clock rate for a clock source */ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) { diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index ad8a1f7c1af..a535c7a2a62 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -73,19 +73,20 @@ void omap2_clk_disable_unused(struct clk *clk); #define omap2_clk_disable_unused NULL #endif -unsigned long omap2_clksel_recalc(struct clk *clk); void omap2_init_clk_clkdm(struct clk *clk); -void omap2_init_clksel_parent(struct clk *clk); -u32 omap2_clksel_get_divisor(struct clk *clk); + +/* clkt_clksel.c public functions */ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, u32 *new_div); -u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); -u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); +void omap2_init_clksel_parent(struct clk *clk); +unsigned long omap2_clksel_recalc(struct clk *clk); long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); + u32 omap2_get_dpll_rate(struct clk *clk); void omap2_init_dpll_parent(struct clk *clk); + int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index d932b142d0b..37d65d62ed8 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -155,12 +155,12 @@ static struct clk apll54_ck = { /* func_54m_ck */ static const struct clksel_rate func_54m_apll54_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, { .div = 0 }, }; static const struct clksel_rate func_54m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 0 }, }; @@ -177,7 +177,7 @@ static struct clk func_54m_ck = { .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_54M_SOURCE, + .clksel_mask = OMAP24XX_54M_SOURCE_MASK, .clksel = func_54m_clksel, .recalc = &omap2_clksel_recalc, }; @@ -201,12 +201,12 @@ static struct clk func_96m_ck = { /* func_48m_ck */ static const struct clksel_rate func_48m_apll96_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 2, .val = 0, .flags = RATE_IN_24XX }, { .div = 0 }, }; static const struct clksel_rate func_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 0 }, }; @@ -223,7 +223,7 @@ static struct clk func_48m_ck = { .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_48M_SOURCE, + .clksel_mask = OMAP24XX_48M_SOURCE_MASK, .clksel = func_48m_clksel, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, @@ -256,22 +256,22 @@ static struct clk wdt1_osc_ck = { * flags fields, which mark them as 2420-only. */ static const struct clksel_rate common_clkout_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, { .div = 0 } }; static const struct clksel_rate common_clkout_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 0 } }; static const struct clksel_rate common_clkout_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, { .div = 0 } }; static const struct clksel_rate common_clkout_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 3, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -300,7 +300,7 @@ static struct clk sys_clkout_src = { }; static const struct clksel_rate common_clkout_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, { .div = 2, .val = 1, .flags = RATE_IN_24XX }, { .div = 4, .val = 2, .flags = RATE_IN_24XX }, { .div = 8, .val = 3, .flags = RATE_IN_24XX }, @@ -384,7 +384,7 @@ static struct clk emul_ck = { * */ static const struct clksel_rate mpu_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 4, .val = 4, .flags = RATE_IN_242X }, { .div = 6, .val = 6, .flags = RATE_IN_242X }, @@ -420,7 +420,7 @@ static struct clk mpu_ck = { /* Control cpu */ * routed into a synchronizer and out of clocks abc. */ static const struct clksel_rate dsp_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 3, .val = 3, .flags = RATE_IN_24XX }, { .div = 4, .val = 4, .flags = RATE_IN_24XX }, @@ -450,7 +450,7 @@ static struct clk dsp_fck = { /* DSP interface clock */ static const struct clksel_rate dsp_irate_ick_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 0 }, }; @@ -532,7 +532,7 @@ static struct clk iva1_mpu_int_ifck = { static const struct clksel_rate core_l3_core_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 2, .val = 2, .flags = RATE_IN_242X }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, { .div = 6, .val = 6, .flags = RATE_IN_24XX }, { .div = 8, .val = 8, .flags = RATE_IN_242X }, { .div = 12, .val = 12, .flags = RATE_IN_242X }, @@ -559,7 +559,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ /* usb_l4_ick */ static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 4, .val = 4, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -591,7 +591,7 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */ * this domain. */ static const struct clksel_rate l4_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -622,7 +622,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */ */ static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 3, .val = 3, .flags = RATE_IN_24XX }, { .div = 4, .val = 4, .flags = RATE_IN_24XX }, { .div = 6, .val = 6, .flags = RATE_IN_242X }, @@ -730,7 +730,7 @@ static struct clk gfx_ick = { /* XXX Add RATE_NOT_VALIDATED */ static const struct clksel_rate dss1_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -744,7 +744,7 @@ static const struct clksel_rate dss1_fck_core_rates[] = { { .div = 8, .val = 8, .flags = RATE_IN_24XX }, { .div = 9, .val = 9, .flags = RATE_IN_24XX }, { .div = 12, .val = 12, .flags = RATE_IN_24XX }, - { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 16, .val = 16, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -779,12 +779,12 @@ static struct clk dss1_fck = { }; static const struct clksel_rate dss2_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, { .div = 0 } }; static const struct clksel_rate dss2_fck_48m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -825,7 +825,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */ * functional clock parents. */ static const struct clksel_rate gpt_alt_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -1588,7 +1588,7 @@ static struct clk vlynq_ick = { }; static const struct clksel_rate vlynq_fck_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_242X }, { .div = 0 } }; @@ -1601,7 +1601,7 @@ static const struct clksel_rate vlynq_fck_core_rates[] = { { .div = 8, .val = 8, .flags = RATE_IN_242X }, { .div = 9, .val = 9, .flags = RATE_IN_242X }, { .div = 12, .val = 12, .flags = RATE_IN_242X }, - { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, + { .div = 16, .val = 16, .flags = RATE_IN_242X }, { .div = 18, .val = 18, .flags = RATE_IN_242X }, { .div = 0 } }; @@ -1836,7 +1836,7 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), CLK(NULL, "des_ick", &des_ick, CK_242X), - CLK(NULL, "sha_ick", &sha_ick, CK_242X), + CLK("omap-sham", "ick", &sha_ick, CK_242X), CLK("omap_rng", "ick", &rng_ick, CK_242X), CLK(NULL, "aes_ick", &aes_ick, CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 0438b6e4f51..b33118fb6a8 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -155,12 +155,12 @@ static struct clk apll54_ck = { /* func_54m_ck */ static const struct clksel_rate func_54m_apll54_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, { .div = 0 }, }; static const struct clksel_rate func_54m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 0 }, }; @@ -177,7 +177,7 @@ static struct clk func_54m_ck = { .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_54M_SOURCE, + .clksel_mask = OMAP24XX_54M_SOURCE_MASK, .clksel = func_54m_clksel, .recalc = &omap2_clksel_recalc, }; @@ -192,12 +192,12 @@ static struct clk core_ck = { /* func_96m_ck */ static const struct clksel_rate func_96m_apll96_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, { .div = 0 }, }; static const struct clksel_rate func_96m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_243X }, { .div = 0 }, }; @@ -214,7 +214,7 @@ static struct clk func_96m_ck = { .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP2430_96M_SOURCE, + .clksel_mask = OMAP2430_96M_SOURCE_MASK, .clksel = func_96m_clksel, .recalc = &omap2_clksel_recalc, }; @@ -222,12 +222,12 @@ static struct clk func_96m_ck = { /* func_48m_ck */ static const struct clksel_rate func_48m_apll96_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 2, .val = 0, .flags = RATE_IN_24XX }, { .div = 0 }, }; static const struct clksel_rate func_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 0 }, }; @@ -244,7 +244,7 @@ static struct clk func_48m_ck = { .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_48M_SOURCE, + .clksel_mask = OMAP24XX_48M_SOURCE_MASK, .clksel = func_48m_clksel, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, @@ -277,22 +277,22 @@ static struct clk wdt1_osc_ck = { * flags fields, which mark them as 2420-only. */ static const struct clksel_rate common_clkout_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, { .div = 0 } }; static const struct clksel_rate common_clkout_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 0 } }; static const struct clksel_rate common_clkout_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, { .div = 0 } }; static const struct clksel_rate common_clkout_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 3, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -321,7 +321,7 @@ static struct clk sys_clkout_src = { }; static const struct clksel_rate common_clkout_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, { .div = 2, .val = 1, .flags = RATE_IN_24XX }, { .div = 4, .val = 2, .flags = RATE_IN_24XX }, { .div = 8, .val = 3, .flags = RATE_IN_24XX }, @@ -369,7 +369,7 @@ static struct clk emul_ck = { * */ static const struct clksel_rate mpu_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 0 }, }; @@ -402,7 +402,7 @@ static struct clk mpu_ck = { /* Control cpu */ * routed into a synchronizer and out of clocks abc. */ static const struct clksel_rate dsp_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 3, .val = 3, .flags = RATE_IN_24XX }, { .div = 4, .val = 4, .flags = RATE_IN_24XX }, @@ -429,7 +429,7 @@ static struct clk dsp_fck = { /* DSP interface clock */ static const struct clksel_rate dsp_irate_ick_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 3, .val = 3, .flags = RATE_IN_243X }, { .div = 0 }, @@ -481,7 +481,7 @@ static struct clk iva2_1_ick = { */ static const struct clksel_rate core_l3_core_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, { .div = 6, .val = 6, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -505,7 +505,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ /* usb_l4_ick */ static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 4, .val = 4, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -537,7 +537,7 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */ * this domain. */ static const struct clksel_rate l4_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -568,7 +568,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */ */ static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, { .div = 3, .val = 3, .flags = RATE_IN_24XX }, { .div = 4, .val = 4, .flags = RATE_IN_24XX }, { .div = 5, .val = 5, .flags = RATE_IN_243X }, @@ -673,7 +673,7 @@ static struct clk gfx_ick = { */ static const struct clksel_rate mdm_ick_core_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_243X }, - { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE }, + { .div = 4, .val = 4, .flags = RATE_IN_243X }, { .div = 6, .val = 6, .flags = RATE_IN_243X }, { .div = 9, .val = 9, .flags = RATE_IN_243X }, { .div = 0 } @@ -718,7 +718,7 @@ static struct clk mdm_osc_ck = { /* XXX Add RATE_NOT_VALIDATED */ static const struct clksel_rate dss1_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -732,7 +732,7 @@ static const struct clksel_rate dss1_fck_core_rates[] = { { .div = 8, .val = 8, .flags = RATE_IN_24XX }, { .div = 9, .val = 9, .flags = RATE_IN_24XX }, { .div = 12, .val = 12, .flags = RATE_IN_24XX }, - { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 16, .val = 16, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -767,12 +767,12 @@ static struct clk dss1_fck = { }; static const struct clksel_rate dss2_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, { .div = 0 } }; static const struct clksel_rate dss2_fck_48m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -813,7 +813,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */ * functional clock parents. */ static const struct clksel_rate gpt_alt_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, { .div = 0 } }; @@ -1924,7 +1924,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), CLK(NULL, "des_ick", &des_ick, CK_243X), - CLK(NULL, "sha_ick", &sha_ick, CK_243X), + CLK("omap-sham", "ick", &sha_ick, CK_243X), CLK("omap_rng", "ick", &rng_ick, CK_243X), CLK(NULL, "aes_ick", &aes_ick, CK_243X), CLK(NULL, "pka_ick", &pka_ick, CK_243X), diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 9cba5560519..41b155acfca 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -110,32 +110,32 @@ static struct clk virt_38_4m_ck = { }; static const struct clksel_rate osc_sys_12m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, { .div = 0 } }; static const struct clksel_rate osc_sys_13m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 0 } }; static const struct clksel_rate osc_sys_16_8m_rates[] = { - { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, + { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS }, { .div = 0 } }; static const struct clksel_rate osc_sys_19_2m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, { .div = 0 } }; static const struct clksel_rate osc_sys_26m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, { .div = 0 } }; static const struct clksel_rate osc_sys_38_4m_rates[] = { - { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 4, .flags = RATE_IN_3XXX }, { .div = 0 } }; @@ -163,8 +163,8 @@ static struct clk osc_sys_ck = { }; static const struct clksel_rate div2_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, { .div = 0 } }; @@ -213,42 +213,42 @@ static struct clk sys_clkout1 = { /* CM CLOCKS */ static const struct clksel_rate div16_dpll_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 3, .val = 3, .flags = RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, - { .div = 5, .val = 5, .flags = RATE_IN_343X }, - { .div = 6, .val = 6, .flags = RATE_IN_343X }, - { .div = 7, .val = 7, .flags = RATE_IN_343X }, - { .div = 8, .val = 8, .flags = RATE_IN_343X }, - { .div = 9, .val = 9, .flags = RATE_IN_343X }, - { .div = 10, .val = 10, .flags = RATE_IN_343X }, - { .div = 11, .val = 11, .flags = RATE_IN_343X }, - { .div = 12, .val = 12, .flags = RATE_IN_343X }, - { .div = 13, .val = 13, .flags = RATE_IN_343X }, - { .div = 14, .val = 14, .flags = RATE_IN_343X }, - { .div = 15, .val = 15, .flags = RATE_IN_343X }, - { .div = 16, .val = 16, .flags = RATE_IN_343X }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, + { .div = 5, .val = 5, .flags = RATE_IN_3XXX }, + { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, + { .div = 7, .val = 7, .flags = RATE_IN_3XXX }, + { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, + { .div = 9, .val = 9, .flags = RATE_IN_3XXX }, + { .div = 10, .val = 10, .flags = RATE_IN_3XXX }, + { .div = 11, .val = 11, .flags = RATE_IN_3XXX }, + { .div = 12, .val = 12, .flags = RATE_IN_3XXX }, + { .div = 13, .val = 13, .flags = RATE_IN_3XXX }, + { .div = 14, .val = 14, .flags = RATE_IN_3XXX }, + { .div = 15, .val = 15, .flags = RATE_IN_3XXX }, + { .div = 16, .val = 16, .flags = RATE_IN_3XXX }, { .div = 0 } }; -static const struct clksel_rate div32_dpll4_rates_3630[] = { - { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_36XX }, - { .div = 3, .val = 3, .flags = RATE_IN_36XX }, - { .div = 4, .val = 4, .flags = RATE_IN_36XX }, - { .div = 5, .val = 5, .flags = RATE_IN_36XX }, - { .div = 6, .val = 6, .flags = RATE_IN_36XX }, - { .div = 7, .val = 7, .flags = RATE_IN_36XX }, - { .div = 8, .val = 8, .flags = RATE_IN_36XX }, - { .div = 9, .val = 9, .flags = RATE_IN_36XX }, - { .div = 10, .val = 10, .flags = RATE_IN_36XX }, - { .div = 11, .val = 11, .flags = RATE_IN_36XX }, - { .div = 12, .val = 12, .flags = RATE_IN_36XX }, - { .div = 13, .val = 13, .flags = RATE_IN_36XX }, - { .div = 14, .val = 14, .flags = RATE_IN_36XX }, - { .div = 15, .val = 15, .flags = RATE_IN_36XX }, - { .div = 16, .val = 16, .flags = RATE_IN_36XX }, +static const struct clksel_rate dpll4_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, + { .div = 5, .val = 5, .flags = RATE_IN_3XXX }, + { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, + { .div = 7, .val = 7, .flags = RATE_IN_3XXX }, + { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, + { .div = 9, .val = 9, .flags = RATE_IN_3XXX }, + { .div = 10, .val = 10, .flags = RATE_IN_3XXX }, + { .div = 11, .val = 11, .flags = RATE_IN_3XXX }, + { .div = 12, .val = 12, .flags = RATE_IN_3XXX }, + { .div = 13, .val = 13, .flags = RATE_IN_3XXX }, + { .div = 14, .val = 14, .flags = RATE_IN_3XXX }, + { .div = 15, .val = 15, .flags = RATE_IN_3XXX }, + { .div = 16, .val = 16, .flags = RATE_IN_3XXX }, { .div = 17, .val = 17, .flags = RATE_IN_36XX }, { .div = 18, .val = 18, .flags = RATE_IN_36XX }, { .div = 19, .val = 19, .flags = RATE_IN_36XX }, @@ -450,37 +450,37 @@ static struct clk dpll3_x2_ck = { }; static const struct clksel_rate div31_dpll3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, - { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, - { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, - { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, - { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, - { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, - { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, - { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, - { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, - { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, - { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, - { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, - { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, - { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, - { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, - { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, - { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, - { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, - { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, - { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, - { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, - { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, - { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, - { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, - { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, - { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, - { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, - { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, - { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS }, + { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS }, + { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS }, + { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS }, + { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS }, + { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS }, + { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS }, + { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS }, + { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS }, + { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS }, + { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS }, + { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS }, + { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS }, + { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS }, + { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS }, + { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS }, + { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS }, + { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS }, + { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS }, + { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS }, + { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS }, + { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS }, + { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS }, + { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS }, + { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS }, + { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS }, + { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS }, + { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS }, + { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS }, { .div = 0 }, }; @@ -562,6 +562,7 @@ static struct clk emu_core_alwon_ck = { /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ /* Type: DPLL */ static struct dpll_data dpll4_dd; + static struct dpll_data dpll4_dd_34xx __initdata = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, @@ -632,39 +633,20 @@ static struct clk dpll4_x2_ck = { .recalc = &omap3_clkoutx2_recalc, }; -static const struct clksel div16_dpll4_clksel[] = { - { .parent = &dpll4_ck, .rates = div16_dpll_rates }, - { .parent = NULL } -}; - -static const struct clksel div32_dpll4_clksel[] = { - { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 }, +static const struct clksel dpll4_clksel[] = { + { .parent = &dpll4_ck, .rates = dpll4_rates }, { .parent = NULL } }; /* This virtual clock is the source for dpll4_m2x2_ck */ -static struct clk dpll4_m2_ck; - -static struct clk dpll4_m2_ck_34xx __initdata = { - .name = "dpll4_m2_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), - .clksel_mask = OMAP3430_DIV_96M_MASK, - .clksel = div16_dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk dpll4_m2_ck_3630 __initdata = { +static struct clk dpll4_m2_ck = { .name = "dpll4_m2_ck", .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), .clksel_mask = OMAP3630_DIV_96M_MASK, - .clksel = div32_dpll4_clksel, + .clksel = dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -698,7 +680,7 @@ static struct clk omap_192m_alwon_fck = { static const struct clksel_rate omap_96m_alwon_fck_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_36XX }, - { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_36XX }, { .div = 0 } }; @@ -708,12 +690,12 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = { }; static const struct clksel_rate omap_96m_dpll_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, { .div = 0 } }; static const struct clksel_rate omap_96m_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 0 } }; @@ -760,28 +742,14 @@ static struct clk omap_96m_fck = { }; /* This virtual clock is the source for dpll4_m3x2_ck */ -static struct clk dpll4_m3_ck; - -static struct clk dpll4_m3_ck_34xx __initdata = { +static struct clk dpll4_m3_ck = { .name = "dpll4_m3_ck", .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_TV_MASK, - .clksel = div16_dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk dpll4_m3_ck_3630 __initdata = { - .name = "dpll4_m3_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), - .clksel_mask = OMAP3630_CLKSEL_TV_MASK, - .clksel = div32_dpll4_clksel, + .clksel = dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -799,12 +767,12 @@ static struct clk dpll4_m3x2_ck = { }; static const struct clksel_rate omap_54m_d4m3x2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, { .div = 0 } }; static const struct clksel_rate omap_54m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 0 } }; @@ -825,12 +793,12 @@ static struct clk omap_54m_fck = { }; static const struct clksel_rate omap_48m_cm96m_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 0, .flags = RATE_IN_3XXX }, { .div = 0 } }; static const struct clksel_rate omap_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 0 } }; @@ -858,31 +826,15 @@ static struct clk omap_12m_fck = { .recalc = &omap_fixed_divisor_recalc, }; -/* This virstual clock is the source for dpll4_m4x2_ck */ -static struct clk dpll4_m4_ck; - -static struct clk dpll4_m4_ck_34xx __initdata = { +/* This virtual clock is the source for dpll4_m4x2_ck */ +static struct clk dpll4_m4_ck = { .name = "dpll4_m4_ck", .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, - .clksel = div16_dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, -}; - -static struct clk dpll4_m4_ck_3630 __initdata = { - .name = "dpll4_m4_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), - .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK, - .clksel = div32_dpll4_clksel, + .clksel = dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, .set_rate = &omap2_clksel_set_rate, @@ -902,30 +854,14 @@ static struct clk dpll4_m4x2_ck = { }; /* This virtual clock is the source for dpll4_m5x2_ck */ -static struct clk dpll4_m5_ck; - -static struct clk dpll4_m5_ck_34xx __initdata = { +static struct clk dpll4_m5_ck = { .name = "dpll4_m5_ck", .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, - .clksel = div16_dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk dpll4_m5_ck_3630 __initdata = { - .name = "dpll4_m5_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), - .clksel_mask = OMAP3630_CLKSEL_CAM_MASK, - .clksel = div32_dpll4_clksel, + .clksel = dpll4_clksel, .clkdm_name = "dpll4_clkdm", .set_rate = &omap2_clksel_set_rate, .round_rate = &omap2_clksel_round_rate, @@ -945,28 +881,14 @@ static struct clk dpll4_m5x2_ck = { }; /* This virtual clock is the source for dpll4_m6x2_ck */ -static struct clk dpll4_m6_ck; - -static struct clk dpll4_m6_ck_34xx __initdata = { +static struct clk dpll4_m6_ck = { .name = "dpll4_m6_ck", .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL4_MASK, - .clksel = div16_dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk dpll4_m6_ck_3630 __initdata = { - .name = "dpll4_m6_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3630_DIV_DPLL4_MASK, - .clksel = div32_dpll4_clksel, + .clksel = dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1049,22 +971,22 @@ static struct clk dpll5_m2_ck = { /* CM EXTERNAL CLOCK OUTPUTS */ static const struct clksel_rate clkout2_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, { .div = 0 } }; static const struct clksel_rate clkout2_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 0 } }; static const struct clksel_rate clkout2_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, { .div = 0 } }; static const struct clksel_rate clkout2_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, { .div = 0 } }; @@ -1090,11 +1012,11 @@ static struct clk clkout2_src_ck = { }; static const struct clksel_rate sys_clkout2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 1, .flags = RATE_IN_343X }, - { .div = 4, .val = 2, .flags = RATE_IN_343X }, - { .div = 8, .val = 3, .flags = RATE_IN_343X }, - { .div = 16, .val = 4, .flags = RATE_IN_343X }, + { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 8, .val = 3, .flags = RATE_IN_3XXX }, + { .div = 16, .val = 4, .flags = RATE_IN_3XXX }, { .div = 0 }, }; @@ -1111,6 +1033,8 @@ static struct clk sys_clkout2 = { .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, .clksel = sys_clkout2_clksel, .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate }; /* CM OUTPUT CLOCKS */ @@ -1125,9 +1049,9 @@ static struct clk corex2_fck = { /* DPLL power domain clock controls */ static const struct clksel_rate div4_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, { .div = 0 } }; @@ -1161,8 +1085,8 @@ static struct clk mpu_ck = { /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ static const struct clksel_rate arm_fck_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 1, .flags = RATE_IN_343X }, + { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 1, .flags = RATE_IN_3XXX }, { .div = 0 }, }; @@ -1333,25 +1257,25 @@ static struct clk gfx_cg2_ck = { static const struct clksel_rate sgx_core_rates[] = { { .div = 2, .val = 5, .flags = RATE_IN_36XX }, - { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 4, .val = 1, .flags = RATE_IN_343X }, - { .div = 6, .val = 2, .flags = RATE_IN_343X }, + { .div = 3, .val = 0, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 6, .val = 2, .flags = RATE_IN_3XXX }, { .div = 0 }, }; static const struct clksel_rate sgx_192m_rates[] = { - { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE }, + { .div = 1, .val = 4, .flags = RATE_IN_36XX }, { .div = 0 }, }; static const struct clksel_rate sgx_corex2_rates[] = { - { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE }, + { .div = 3, .val = 6, .flags = RATE_IN_36XX }, { .div = 5, .val = 7, .flags = RATE_IN_36XX }, { .div = 0 }, }; static const struct clksel_rate sgx_96m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, { .div = 0 }, }; @@ -1576,12 +1500,12 @@ static struct clk i2c1_fck = { * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. */ static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, { .div = 0 } }; static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 0 } }; @@ -1714,12 +1638,12 @@ static struct clk hdq_fck = { /* DPLL3-derived clock */ static const struct clksel_rate ssi_ssr_corex2_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 3, .val = 3, .flags = RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, - { .div = 6, .val = 6, .flags = RATE_IN_343X }, - { .div = 8, .val = 8, .flags = RATE_IN_343X }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, + { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, + { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, { .div = 0 } }; @@ -2353,18 +2277,18 @@ static struct clk usbhost_ick = { /* WKUP */ static const struct clksel_rate usim_96m_rates[] = { - { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, - { .div = 8, .val = 5, .flags = RATE_IN_343X }, - { .div = 10, .val = 6, .flags = RATE_IN_343X }, + { .div = 2, .val = 3, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, + { .div = 8, .val = 5, .flags = RATE_IN_3XXX }, + { .div = 10, .val = 6, .flags = RATE_IN_3XXX }, { .div = 0 }, }; static const struct clksel_rate usim_120m_rates[] = { - { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 8, .val = 8, .flags = RATE_IN_343X }, - { .div = 16, .val = 9, .flags = RATE_IN_343X }, - { .div = 20, .val = 10, .flags = RATE_IN_343X }, + { .div = 4, .val = 7, .flags = RATE_IN_3XXX }, + { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, + { .div = 16, .val = 9, .flags = RATE_IN_3XXX }, + { .div = 20, .val = 10, .flags = RATE_IN_3XXX }, { .div = 0 }, }; @@ -2951,22 +2875,22 @@ static struct clk mcbsp4_fck = { /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ static const struct clksel_rate emu_src_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, { .div = 0 }, }; static const struct clksel_rate emu_src_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 0 }, }; static const struct clksel_rate emu_src_per_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, { .div = 0 }, }; static const struct clksel_rate emu_src_mpu_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, { .div = 0 }, }; @@ -2995,10 +2919,10 @@ static struct clk emu_src_ck = { }; static const struct clksel_rate pclk_emu_rates[] = { - { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 3, .val = 3, .flags = RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, - { .div = 6, .val = 6, .flags = RATE_IN_343X }, + { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, + { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, { .div = 0 }, }; @@ -3019,9 +2943,9 @@ static struct clk pclk_fck = { }; static const struct clksel_rate pclkx2_emu_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 3, .val = 3, .flags = RATE_IN_343X }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, { .div = 0 }, }; @@ -3069,9 +2993,9 @@ static struct clk traceclk_src_fck = { }; static const struct clksel_rate traceclk_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, { .div = 0 }, }; @@ -3360,7 +3284,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), CLK(NULL, "icr_ick", &icr_ick, CK_343X), CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), - CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), + CLK("omap-sham", "ick", &sha12_ick, CK_343X), CLK(NULL, "des2_ick", &des2_ick, CK_343X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), @@ -3472,8 +3396,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), - CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX), - CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX), + CLK("davinci_emac", "emac_clk", &emac_ick, CK_AM35XX), + CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX), CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), @@ -3488,14 +3412,8 @@ int __init omap3xxx_clk_init(void) struct omap_clk *c; u32 cpu_clkflg = CK_3XXX; - if (cpu_is_omap3517()) { - cpu_mask = RATE_IN_343X | RATE_IN_3430ES2; - cpu_clkflg |= CK_3517; - } else if (cpu_is_omap3505()) { - cpu_mask = RATE_IN_343X | RATE_IN_3430ES2; - cpu_clkflg |= CK_3505; - } else if (cpu_is_omap34xx()) { - cpu_mask = RATE_IN_343X; + if (cpu_is_omap34xx()) { + cpu_mask = RATE_IN_3XXX; cpu_clkflg |= CK_343X; /* @@ -3506,10 +3424,17 @@ int __init omap3xxx_clk_init(void) /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ cpu_clkflg |= CK_3430ES1; } else { - cpu_mask |= RATE_IN_3430ES2; + cpu_mask |= RATE_IN_3430ES2PLUS; cpu_clkflg |= CK_3430ES2; } + } else if (cpu_is_omap3517()) { + cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; + cpu_clkflg |= CK_3517; + } else if (cpu_is_omap3505()) { + cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; + cpu_clkflg |= CK_3505; } + if (omap3_has_192mhz_clk()) omap_96m_alwon_fck = omap_96m_alwon_fck_3630; @@ -3520,14 +3445,7 @@ int __init omap3xxx_clk_init(void) /* * XXX This type of dynamic rewriting of the clock tree is * deprecated and should be revised soon. - */ - dpll4_m2_ck = dpll4_m2_ck_3630; - dpll4_m3_ck = dpll4_m3_ck_3630; - dpll4_m4_ck = dpll4_m4_ck_3630; - dpll4_m5_ck = dpll4_m5_ck_3630; - dpll4_m6_ck = dpll4_m6_ck_3630; - - /* + * * For 3630: override clkops_omap2_dflt_wait for the * clocks affected from PWRDN reset Limitation */ @@ -3543,18 +3461,12 @@ int __init omap3xxx_clk_init(void) &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; dpll4_m6x2_ck.ops = &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; - } else { - /* - * XXX This type of dynamic rewriting of the clock tree is - * deprecated and should be revised soon. - */ - dpll4_m2_ck = dpll4_m2_ck_34xx; - dpll4_m3_ck = dpll4_m3_ck_34xx; - dpll4_m4_ck = dpll4_m4_ck_34xx; - dpll4_m5_ck = dpll4_m5_ck_34xx; - dpll4_m6_ck = dpll4_m6_ck_34xx; } + /* + * XXX This type of dynamic rewriting of the clock tree is + * deprecated and should be revised soon. + */ if (cpu_is_omap3630()) dpll4_dd = dpll4_dd_3630; else diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index a5c0c9c8e49..02804224517 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -2675,6 +2675,11 @@ static struct omap_clk omap44xx_clks[] = { CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index f69096b88cd..1cf8131205f 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -20,20 +20,20 @@ /* clksel_rate data common to 24xx/343x */ const struct clksel_rate gpt_32k_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX }, { .div = 0 } }; const struct clksel_rate gpt_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX }, { .div = 0 } }; const struct clksel_rate gfx_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, - { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, + { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX }, + { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX }, + { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX }, { .div = 0 } }; diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 6e568ec995e..5d80cb89748 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -809,7 +809,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { - cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, + cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { @@ -853,7 +853,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { - cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, + cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx.h index 438aaee2e39..7e5ba0f6792 100644 --- a/arch/arm/mach-omap2/clockdomains44xx.h +++ b/arch/arm/mach-omap2/clockdomains44xx.h @@ -131,7 +131,7 @@ static struct clockdomain mpuss_44xx_clkdm = { static struct clockdomain mpu0_44xx_clkdm = { .name = "mpu0_clkdm", .pwrdm = { .name = "cpu0_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_PDA_CPU0_CLKSTCTRL, + .clkstctrl_reg = OMAP4430_CM_CPU0_CLKSTCTRL, .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), @@ -140,7 +140,7 @@ static struct clockdomain mpu0_44xx_clkdm = { static struct clockdomain mpu1_44xx_clkdm = { .name = "mpu1_clkdm", .pwrdm = { .name = "cpu1_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_PDA_CPU1_CLKSTCTRL, + .clkstctrl_reg = OMAP4430_CM_CPU1_CLKSTCTRL, .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 297a2fe634e..da51cc3ed7e 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -20,43 +20,43 @@ /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ #define OMAP24XX_EN_CAM_SHIFT 31 -#define OMAP24XX_EN_CAM (1 << 31) +#define OMAP24XX_EN_CAM_MASK (1 << 31) #define OMAP24XX_EN_WDT4_SHIFT 29 -#define OMAP24XX_EN_WDT4 (1 << 29) +#define OMAP24XX_EN_WDT4_MASK (1 << 29) #define OMAP2420_EN_WDT3_SHIFT 28 -#define OMAP2420_EN_WDT3 (1 << 28) +#define OMAP2420_EN_WDT3_MASK (1 << 28) #define OMAP24XX_EN_MSPRO_SHIFT 27 -#define OMAP24XX_EN_MSPRO (1 << 27) +#define OMAP24XX_EN_MSPRO_MASK (1 << 27) #define OMAP24XX_EN_FAC_SHIFT 25 -#define OMAP24XX_EN_FAC (1 << 25) +#define OMAP24XX_EN_FAC_MASK (1 << 25) #define OMAP2420_EN_EAC_SHIFT 24 -#define OMAP2420_EN_EAC (1 << 24) +#define OMAP2420_EN_EAC_MASK (1 << 24) #define OMAP24XX_EN_HDQ_SHIFT 23 -#define OMAP24XX_EN_HDQ (1 << 23) +#define OMAP24XX_EN_HDQ_MASK (1 << 23) #define OMAP2420_EN_I2C2_SHIFT 20 -#define OMAP2420_EN_I2C2 (1 << 20) +#define OMAP2420_EN_I2C2_MASK (1 << 20) #define OMAP2420_EN_I2C1_SHIFT 19 -#define OMAP2420_EN_I2C1 (1 << 19) +#define OMAP2420_EN_I2C1_MASK (1 << 19) /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ #define OMAP2430_EN_MCBSP5_SHIFT 5 -#define OMAP2430_EN_MCBSP5 (1 << 5) +#define OMAP2430_EN_MCBSP5_MASK (1 << 5) #define OMAP2430_EN_MCBSP4_SHIFT 4 -#define OMAP2430_EN_MCBSP4 (1 << 4) +#define OMAP2430_EN_MCBSP4_MASK (1 << 4) #define OMAP2430_EN_MCBSP3_SHIFT 3 -#define OMAP2430_EN_MCBSP3 (1 << 3) +#define OMAP2430_EN_MCBSP3_MASK (1 << 3) #define OMAP24XX_EN_SSI_SHIFT 1 -#define OMAP24XX_EN_SSI (1 << 1) +#define OMAP24XX_EN_SSI_MASK (1 << 1) /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ #define OMAP24XX_EN_MPU_WDT_SHIFT 3 -#define OMAP24XX_EN_MPU_WDT (1 << 3) +#define OMAP24XX_EN_MPU_WDT_MASK (1 << 3) /* Bits specific to each register */ /* CM_IDLEST_MPU */ /* 2430 only */ -#define OMAP2430_ST_MPU (1 << 0) +#define OMAP2430_ST_MPU_MASK (1 << 0) /* CM_CLKSEL_MPU */ #define OMAP24XX_CLKSEL_MPU_SHIFT 0 @@ -68,46 +68,46 @@ /* CM_FCLKEN1_CORE specific bits*/ #define OMAP24XX_EN_TV_SHIFT 2 -#define OMAP24XX_EN_TV (1 << 2) +#define OMAP24XX_EN_TV_MASK (1 << 2) #define OMAP24XX_EN_DSS2_SHIFT 1 -#define OMAP24XX_EN_DSS2 (1 << 1) +#define OMAP24XX_EN_DSS2_MASK (1 << 1) #define OMAP24XX_EN_DSS1_SHIFT 0 -#define OMAP24XX_EN_DSS1 (1 << 0) +#define OMAP24XX_EN_DSS1_MASK (1 << 0) /* CM_FCLKEN2_CORE specific bits */ #define OMAP2430_EN_I2CHS2_SHIFT 20 -#define OMAP2430_EN_I2CHS2 (1 << 20) +#define OMAP2430_EN_I2CHS2_MASK (1 << 20) #define OMAP2430_EN_I2CHS1_SHIFT 19 -#define OMAP2430_EN_I2CHS1 (1 << 19) +#define OMAP2430_EN_I2CHS1_MASK (1 << 19) #define OMAP2430_EN_MMCHSDB2_SHIFT 17 -#define OMAP2430_EN_MMCHSDB2 (1 << 17) +#define OMAP2430_EN_MMCHSDB2_MASK (1 << 17) #define OMAP2430_EN_MMCHSDB1_SHIFT 16 -#define OMAP2430_EN_MMCHSDB1 (1 << 16) +#define OMAP2430_EN_MMCHSDB1_MASK (1 << 16) /* CM_ICLKEN1_CORE specific bits */ #define OMAP24XX_EN_MAILBOXES_SHIFT 30 -#define OMAP24XX_EN_MAILBOXES (1 << 30) +#define OMAP24XX_EN_MAILBOXES_MASK (1 << 30) #define OMAP24XX_EN_DSS_SHIFT 0 -#define OMAP24XX_EN_DSS (1 << 0) +#define OMAP24XX_EN_DSS_MASK (1 << 0) /* CM_ICLKEN2_CORE specific bits */ /* CM_ICLKEN3_CORE */ /* 2430 only */ #define OMAP2430_EN_SDRC_SHIFT 2 -#define OMAP2430_EN_SDRC (1 << 2) +#define OMAP2430_EN_SDRC_MASK (1 << 2) /* CM_ICLKEN4_CORE */ #define OMAP24XX_EN_PKA_SHIFT 4 -#define OMAP24XX_EN_PKA (1 << 4) +#define OMAP24XX_EN_PKA_MASK (1 << 4) #define OMAP24XX_EN_AES_SHIFT 3 -#define OMAP24XX_EN_AES (1 << 3) +#define OMAP24XX_EN_AES_MASK (1 << 3) #define OMAP24XX_EN_RNG_SHIFT 2 -#define OMAP24XX_EN_RNG (1 << 2) +#define OMAP24XX_EN_RNG_MASK (1 << 2) #define OMAP24XX_EN_SHA_SHIFT 1 -#define OMAP24XX_EN_SHA (1 << 1) +#define OMAP24XX_EN_SHA_MASK (1 << 1) #define OMAP24XX_EN_DES_SHIFT 0 -#define OMAP24XX_EN_DES (1 << 0) +#define OMAP24XX_EN_DES_MASK (1 << 0) /* CM_IDLEST1_CORE specific bits */ #define OMAP24XX_ST_MAILBOXES_SHIFT 30 @@ -138,9 +138,9 @@ /* CM_IDLEST2_CORE */ #define OMAP2430_ST_MCBSP5_SHIFT 5 #define OMAP2430_ST_MCBSP5_MASK (1 << 5) -#define OMAP2430_ST_MCBSP4_SHIFT 4 +#define OMAP2430_ST_MCBSP4_SHIFT 4 #define OMAP2430_ST_MCBSP4_MASK (1 << 4) -#define OMAP2430_ST_MCBSP3_SHIFT 3 +#define OMAP2430_ST_MCBSP3_SHIFT 3 #define OMAP2430_ST_MCBSP3_MASK (1 << 3) #define OMAP24XX_ST_SSI_SHIFT 1 #define OMAP24XX_ST_SSI_MASK (1 << 1) @@ -162,62 +162,62 @@ #define OMAP24XX_ST_DES_MASK (1 << 0) /* CM_AUTOIDLE1_CORE */ -#define OMAP24XX_AUTO_CAM (1 << 31) -#define OMAP24XX_AUTO_MAILBOXES (1 << 30) -#define OMAP24XX_AUTO_WDT4 (1 << 29) -#define OMAP2420_AUTO_WDT3 (1 << 28) -#define OMAP24XX_AUTO_MSPRO (1 << 27) -#define OMAP2420_AUTO_MMC (1 << 26) -#define OMAP24XX_AUTO_FAC (1 << 25) -#define OMAP2420_AUTO_EAC (1 << 24) -#define OMAP24XX_AUTO_HDQ (1 << 23) -#define OMAP24XX_AUTO_UART2 (1 << 22) -#define OMAP24XX_AUTO_UART1 (1 << 21) -#define OMAP24XX_AUTO_I2C2 (1 << 20) -#define OMAP24XX_AUTO_I2C1 (1 << 19) -#define OMAP24XX_AUTO_MCSPI2 (1 << 18) -#define OMAP24XX_AUTO_MCSPI1 (1 << 17) -#define OMAP24XX_AUTO_MCBSP2 (1 << 16) -#define OMAP24XX_AUTO_MCBSP1 (1 << 15) -#define OMAP24XX_AUTO_GPT12 (1 << 14) -#define OMAP24XX_AUTO_GPT11 (1 << 13) -#define OMAP24XX_AUTO_GPT10 (1 << 12) -#define OMAP24XX_AUTO_GPT9 (1 << 11) -#define OMAP24XX_AUTO_GPT8 (1 << 10) -#define OMAP24XX_AUTO_GPT7 (1 << 9) -#define OMAP24XX_AUTO_GPT6 (1 << 8) -#define OMAP24XX_AUTO_GPT5 (1 << 7) -#define OMAP24XX_AUTO_GPT4 (1 << 6) -#define OMAP24XX_AUTO_GPT3 (1 << 5) -#define OMAP24XX_AUTO_GPT2 (1 << 4) -#define OMAP2420_AUTO_VLYNQ (1 << 3) -#define OMAP24XX_AUTO_DSS (1 << 0) +#define OMAP24XX_AUTO_CAM_MASK (1 << 31) +#define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30) +#define OMAP24XX_AUTO_WDT4_MASK (1 << 29) +#define OMAP2420_AUTO_WDT3_MASK (1 << 28) +#define OMAP24XX_AUTO_MSPRO_MASK (1 << 27) +#define OMAP2420_AUTO_MMC_MASK (1 << 26) +#define OMAP24XX_AUTO_FAC_MASK (1 << 25) +#define OMAP2420_AUTO_EAC_MASK (1 << 24) +#define OMAP24XX_AUTO_HDQ_MASK (1 << 23) +#define OMAP24XX_AUTO_UART2_MASK (1 << 22) +#define OMAP24XX_AUTO_UART1_MASK (1 << 21) +#define OMAP24XX_AUTO_I2C2_MASK (1 << 20) +#define OMAP24XX_AUTO_I2C1_MASK (1 << 19) +#define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18) +#define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17) +#define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16) +#define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15) +#define OMAP24XX_AUTO_GPT12_MASK (1 << 14) +#define OMAP24XX_AUTO_GPT11_MASK (1 << 13) +#define OMAP24XX_AUTO_GPT10_MASK (1 << 12) +#define OMAP24XX_AUTO_GPT9_MASK (1 << 11) +#define OMAP24XX_AUTO_GPT8_MASK (1 << 10) +#define OMAP24XX_AUTO_GPT7_MASK (1 << 9) +#define OMAP24XX_AUTO_GPT6_MASK (1 << 8) +#define OMAP24XX_AUTO_GPT5_MASK (1 << 7) +#define OMAP24XX_AUTO_GPT4_MASK (1 << 6) +#define OMAP24XX_AUTO_GPT3_MASK (1 << 5) +#define OMAP24XX_AUTO_GPT2_MASK (1 << 4) +#define OMAP2420_AUTO_VLYNQ_MASK (1 << 3) +#define OMAP24XX_AUTO_DSS_MASK (1 << 0) /* CM_AUTOIDLE2_CORE */ -#define OMAP2430_AUTO_MDM_INTC (1 << 11) -#define OMAP2430_AUTO_GPIO5 (1 << 10) -#define OMAP2430_AUTO_MCSPI3 (1 << 9) -#define OMAP2430_AUTO_MMCHS2 (1 << 8) -#define OMAP2430_AUTO_MMCHS1 (1 << 7) -#define OMAP2430_AUTO_USBHS (1 << 6) -#define OMAP2430_AUTO_MCBSP5 (1 << 5) -#define OMAP2430_AUTO_MCBSP4 (1 << 4) -#define OMAP2430_AUTO_MCBSP3 (1 << 3) -#define OMAP24XX_AUTO_UART3 (1 << 2) -#define OMAP24XX_AUTO_SSI (1 << 1) -#define OMAP24XX_AUTO_USB (1 << 0) +#define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11) +#define OMAP2430_AUTO_GPIO5_MASK (1 << 10) +#define OMAP2430_AUTO_MCSPI3_MASK (1 << 9) +#define OMAP2430_AUTO_MMCHS2_MASK (1 << 8) +#define OMAP2430_AUTO_MMCHS1_MASK (1 << 7) +#define OMAP2430_AUTO_USBHS_MASK (1 << 6) +#define OMAP2430_AUTO_MCBSP5_MASK (1 << 5) +#define OMAP2430_AUTO_MCBSP4_MASK (1 << 4) +#define OMAP2430_AUTO_MCBSP3_MASK (1 << 3) +#define OMAP24XX_AUTO_UART3_MASK (1 << 2) +#define OMAP24XX_AUTO_SSI_MASK (1 << 1) +#define OMAP24XX_AUTO_USB_MASK (1 << 0) /* CM_AUTOIDLE3_CORE */ -#define OMAP24XX_AUTO_SDRC (1 << 2) -#define OMAP24XX_AUTO_GPMC (1 << 1) -#define OMAP24XX_AUTO_SDMA (1 << 0) +#define OMAP24XX_AUTO_SDRC_MASK (1 << 2) +#define OMAP24XX_AUTO_GPMC_MASK (1 << 1) +#define OMAP24XX_AUTO_SDMA_MASK (1 << 0) /* CM_AUTOIDLE4_CORE */ -#define OMAP24XX_AUTO_PKA (1 << 4) -#define OMAP24XX_AUTO_AES (1 << 3) -#define OMAP24XX_AUTO_RNG (1 << 2) -#define OMAP24XX_AUTO_SHA (1 << 1) -#define OMAP24XX_AUTO_DES (1 << 0) +#define OMAP24XX_AUTO_PKA_MASK (1 << 4) +#define OMAP24XX_AUTO_AES_MASK (1 << 3) +#define OMAP24XX_AUTO_RNG_MASK (1 << 2) +#define OMAP24XX_AUTO_SHA_MASK (1 << 1) +#define OMAP24XX_AUTO_DES_MASK (1 << 0) /* CM_CLKSEL1_CORE */ #define OMAP24XX_CLKSEL_USB_SHIFT 25 @@ -269,9 +269,9 @@ /* CM_FCLKEN_GFX */ #define OMAP24XX_EN_3D_SHIFT 2 -#define OMAP24XX_EN_3D (1 << 2) +#define OMAP24XX_EN_3D_MASK (1 << 2) #define OMAP24XX_EN_2D_SHIFT 1 -#define OMAP24XX_EN_2D (1 << 1) +#define OMAP24XX_EN_2D_MASK (1 << 1) /* CM_ICLKEN_GFX specific bits */ @@ -287,13 +287,13 @@ /* CM_ICLKEN_WKUP specific bits */ #define OMAP2430_EN_ICR_SHIFT 6 -#define OMAP2430_EN_ICR (1 << 6) +#define OMAP2430_EN_ICR_MASK (1 << 6) #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 -#define OMAP24XX_EN_OMAPCTRL (1 << 5) +#define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5) #define OMAP24XX_EN_WDT1_SHIFT 4 -#define OMAP24XX_EN_WDT1 (1 << 4) +#define OMAP24XX_EN_WDT1_MASK (1 << 4) #define OMAP24XX_EN_32KSYNC_SHIFT 1 -#define OMAP24XX_EN_32KSYNC (1 << 1) +#define OMAP24XX_EN_32KSYNC_MASK (1 << 1) /* CM_IDLEST_WKUP specific bits */ #define OMAP2430_ST_ICR_SHIFT 6 @@ -308,12 +308,12 @@ #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) /* CM_AUTOIDLE_WKUP */ -#define OMAP24XX_AUTO_OMAPCTRL (1 << 5) -#define OMAP24XX_AUTO_WDT1 (1 << 4) -#define OMAP24XX_AUTO_MPU_WDT (1 << 3) -#define OMAP24XX_AUTO_GPIOS (1 << 2) -#define OMAP24XX_AUTO_32KSYNC (1 << 1) -#define OMAP24XX_AUTO_GPT1 (1 << 0) +#define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5) +#define OMAP24XX_AUTO_WDT1_MASK (1 << 4) +#define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3) +#define OMAP24XX_AUTO_GPIOS_MASK (1 << 2) +#define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1) +#define OMAP24XX_AUTO_GPT1_MASK (1 << 0) /* CM_CLKSEL_WKUP */ #define OMAP24XX_CLKSEL_GPT1_SHIFT 0 @@ -328,12 +328,12 @@ #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) /* CM_IDLEST_CKGEN */ -#define OMAP24XX_ST_54M_APLL (1 << 9) -#define OMAP24XX_ST_96M_APLL (1 << 8) -#define OMAP24XX_ST_54M_CLK (1 << 6) -#define OMAP24XX_ST_12M_CLK (1 << 5) -#define OMAP24XX_ST_48M_CLK (1 << 4) -#define OMAP24XX_ST_96M_CLK (1 << 2) +#define OMAP24XX_ST_54M_APLL_MASK (1 << 9) +#define OMAP24XX_ST_96M_APLL_MASK (1 << 8) +#define OMAP24XX_ST_54M_CLK_MASK (1 << 6) +#define OMAP24XX_ST_12M_CLK_MASK (1 << 5) +#define OMAP24XX_ST_48M_CLK_MASK (1 << 4) +#define OMAP24XX_ST_96M_CLK_MASK (1 << 2) #define OMAP24XX_ST_CORE_CLK_SHIFT 0 #define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) @@ -355,11 +355,11 @@ #define OMAP24XX_DPLL_DIV_SHIFT 8 #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) #define OMAP24XX_54M_SOURCE_SHIFT 5 -#define OMAP24XX_54M_SOURCE (1 << 5) +#define OMAP24XX_54M_SOURCE_MASK (1 << 5) #define OMAP2430_96M_SOURCE_SHIFT 4 -#define OMAP2430_96M_SOURCE (1 << 4) +#define OMAP2430_96M_SOURCE_MASK (1 << 4) #define OMAP24XX_48M_SOURCE_SHIFT 3 -#define OMAP24XX_48M_SOURCE (1 << 3) +#define OMAP24XX_48M_SOURCE_MASK (1 << 3) #define OMAP2430_ALTCLK_SOURCE_SHIFT 0 #define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) @@ -369,29 +369,29 @@ /* CM_FCLKEN_DSP */ #define OMAP2420_EN_IVA_COP_SHIFT 10 -#define OMAP2420_EN_IVA_COP (1 << 10) +#define OMAP2420_EN_IVA_COP_MASK (1 << 10) #define OMAP2420_EN_IVA_MPU_SHIFT 8 -#define OMAP2420_EN_IVA_MPU (1 << 8) +#define OMAP2420_EN_IVA_MPU_MASK (1 << 8) #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 -#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0) +#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0) /* CM_ICLKEN_DSP */ #define OMAP2420_EN_DSP_IPI_SHIFT 1 -#define OMAP2420_EN_DSP_IPI (1 << 1) +#define OMAP2420_EN_DSP_IPI_MASK (1 << 1) /* CM_IDLEST_DSP */ -#define OMAP2420_ST_IVA (1 << 8) -#define OMAP2420_ST_IPI (1 << 1) -#define OMAP24XX_ST_DSP (1 << 0) +#define OMAP2420_ST_IVA_MASK (1 << 8) +#define OMAP2420_ST_IPI_MASK (1 << 1) +#define OMAP24XX_ST_DSP_MASK (1 << 0) /* CM_AUTOIDLE_DSP */ -#define OMAP2420_AUTO_DSP_IPI (1 << 1) +#define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1) /* CM_CLKSEL_DSP */ -#define OMAP2420_SYNC_IVA (1 << 13) +#define OMAP2420_SYNC_IVA_MASK (1 << 13) #define OMAP2420_CLKSEL_IVA_SHIFT 8 #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) -#define OMAP24XX_SYNC_DSP (1 << 7) +#define OMAP24XX_SYNC_DSP_MASK (1 << 7) #define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) #define OMAP24XX_CLKSEL_DSP_SHIFT 0 @@ -406,24 +406,24 @@ /* CM_FCLKEN_MDM */ /* 2430 only */ #define OMAP2430_EN_OSC_SHIFT 1 -#define OMAP2430_EN_OSC (1 << 1) +#define OMAP2430_EN_OSC_MASK (1 << 1) /* CM_ICLKEN_MDM */ /* 2430 only */ #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 -#define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0) +#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0) /* CM_IDLEST_MDM specific bits */ /* 2430 only */ /* CM_AUTOIDLE_MDM */ /* 2430 only */ -#define OMAP2430_AUTO_OSC (1 << 1) -#define OMAP2430_AUTO_MDM (1 << 0) +#define OMAP2430_AUTO_OSC_MASK (1 << 1) +#define OMAP2430_AUTO_MDM_MASK (1 << 0) /* CM_CLKSEL_MDM */ /* 2430 only */ -#define OMAP2430_SYNC_MDM (1 << 4) +#define OMAP2430_SYNC_MDM_MASK (1 << 4) #define OMAP2430_CLKSEL_MDM_SHIFT 0 #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index a3a3ca07e38..fe82b79d5f3 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -21,15 +21,15 @@ /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) #define OMAP3430ES2_EN_MMC3_SHIFT 30 -#define OMAP3430_EN_MSPRO (1 << 23) +#define OMAP3430_EN_MSPRO_MASK (1 << 23) #define OMAP3430_EN_MSPRO_SHIFT 23 -#define OMAP3430_EN_HDQ (1 << 22) +#define OMAP3430_EN_HDQ_MASK (1 << 22) #define OMAP3430_EN_HDQ_SHIFT 22 -#define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) +#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 -#define OMAP3430ES1_EN_D2D (1 << 3) +#define OMAP3430ES1_EN_D2D_MASK (1 << 3) #define OMAP3430ES1_EN_D2D_SHIFT 3 -#define OMAP3430_EN_SSI (1 << 0) +#define OMAP3430_EN_SSI_MASK (1 << 0) #define OMAP3430_EN_SSI_SHIFT 0 /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ @@ -37,19 +37,19 @@ #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ -#define OMAP3430_EN_WDT2 (1 << 5) +#define OMAP3430_EN_WDT2_MASK (1 << 5) #define OMAP3430_EN_WDT2_SHIFT 5 /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ -#define OMAP3430_EN_CAM (1 << 0) +#define OMAP3430_EN_CAM_MASK (1 << 0) #define OMAP3430_EN_CAM_SHIFT 0 /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ -#define OMAP3430_EN_WDT3 (1 << 12) +#define OMAP3430_EN_WDT3_MASK (1 << 12) #define OMAP3430_EN_WDT3_SHIFT 12 /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ -#define OMAP3430_OVERRIDE_ENABLE (1 << 19) +#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) /* Bits specific to each register */ @@ -69,7 +69,7 @@ #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) /* CM_IDLEST_IVA2 */ -#define OMAP3430_ST_IVA2 (1 << 0) +#define OMAP3430_ST_IVA2_MASK (1 << 0) /* CM_IDLEST_PLL_IVA2 */ #define OMAP3430_ST_IVA2_CLK_SHIFT 0 @@ -114,7 +114,7 @@ #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) /* CM_IDLEST_MPU */ -#define OMAP3430_ST_MPU (1 << 0) +#define OMAP3430_ST_MPU_MASK (1 << 0) /* CM_IDLEST_PLL_MPU */ #define OMAP3430_ST_MPU_CLK_SHIFT 0 @@ -145,50 +145,50 @@ #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) /* CM_FCLKEN1_CORE specific bits */ -#define OMAP3430_EN_MODEM (1 << 31) +#define OMAP3430_EN_MODEM_MASK (1 << 31) #define OMAP3430_EN_MODEM_SHIFT 31 /* CM_ICLKEN1_CORE specific bits */ -#define OMAP3430_EN_ICR (1 << 29) +#define OMAP3430_EN_ICR_MASK (1 << 29) #define OMAP3430_EN_ICR_SHIFT 29 -#define OMAP3430_EN_AES2 (1 << 28) +#define OMAP3430_EN_AES2_MASK (1 << 28) #define OMAP3430_EN_AES2_SHIFT 28 -#define OMAP3430_EN_SHA12 (1 << 27) +#define OMAP3430_EN_SHA12_MASK (1 << 27) #define OMAP3430_EN_SHA12_SHIFT 27 -#define OMAP3430_EN_DES2 (1 << 26) +#define OMAP3430_EN_DES2_MASK (1 << 26) #define OMAP3430_EN_DES2_SHIFT 26 -#define OMAP3430ES1_EN_FAC (1 << 8) +#define OMAP3430ES1_EN_FAC_MASK (1 << 8) #define OMAP3430ES1_EN_FAC_SHIFT 8 -#define OMAP3430_EN_MAILBOXES (1 << 7) +#define OMAP3430_EN_MAILBOXES_MASK (1 << 7) #define OMAP3430_EN_MAILBOXES_SHIFT 7 -#define OMAP3430_EN_OMAPCTRL (1 << 6) +#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) #define OMAP3430_EN_OMAPCTRL_SHIFT 6 -#define OMAP3430_EN_SAD2D (1 << 3) +#define OMAP3430_EN_SAD2D_MASK (1 << 3) #define OMAP3430_EN_SAD2D_SHIFT 3 -#define OMAP3430_EN_SDRC (1 << 1) +#define OMAP3430_EN_SDRC_MASK (1 << 1) #define OMAP3430_EN_SDRC_SHIFT 1 /* AM35XX specific CM_ICLKEN1_CORE bits */ #define AM35XX_EN_IPSS_MASK (1 << 4) #define AM35XX_EN_IPSS_SHIFT 4 -#define AM35XX_EN_UART4_MASK (1 << 23) +#define AM35XX_EN_UART4_MASK (1 << 23) #define AM35XX_EN_UART4_SHIFT 23 /* CM_ICLKEN2_CORE */ -#define OMAP3430_EN_PKA (1 << 4) +#define OMAP3430_EN_PKA_MASK (1 << 4) #define OMAP3430_EN_PKA_SHIFT 4 -#define OMAP3430_EN_AES1 (1 << 3) +#define OMAP3430_EN_AES1_MASK (1 << 3) #define OMAP3430_EN_AES1_SHIFT 3 -#define OMAP3430_EN_RNG (1 << 2) +#define OMAP3430_EN_RNG_MASK (1 << 2) #define OMAP3430_EN_RNG_SHIFT 2 -#define OMAP3430_EN_SHA11 (1 << 1) +#define OMAP3430_EN_SHA11_MASK (1 << 1) #define OMAP3430_EN_SHA11_SHIFT 1 -#define OMAP3430_EN_DES1 (1 << 0) +#define OMAP3430_EN_DES1_MASK (1 << 0) #define OMAP3430_EN_DES1_SHIFT 0 /* CM_ICLKEN3_CORE */ #define OMAP3430_EN_MAD2D_SHIFT 3 -#define OMAP3430_EN_MAD2D (1 << 3) +#define OMAP3430_EN_MAD2D_MASK (1 << 3) /* CM_FCLKEN3_CORE specific bits */ #define OMAP3430ES2_EN_TS_SHIFT 1 @@ -249,79 +249,79 @@ #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) /* CM_AUTOIDLE1_CORE */ -#define OMAP3430_AUTO_MODEM (1 << 31) +#define OMAP3430_AUTO_MODEM_MASK (1 << 31) #define OMAP3430_AUTO_MODEM_SHIFT 31 -#define OMAP3430ES2_AUTO_MMC3 (1 << 30) +#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 -#define OMAP3430ES2_AUTO_ICR (1 << 29) +#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) #define OMAP3430ES2_AUTO_ICR_SHIFT 29 -#define OMAP3430_AUTO_AES2 (1 << 28) +#define OMAP3430_AUTO_AES2_MASK (1 << 28) #define OMAP3430_AUTO_AES2_SHIFT 28 -#define OMAP3430_AUTO_SHA12 (1 << 27) +#define OMAP3430_AUTO_SHA12_MASK (1 << 27) #define OMAP3430_AUTO_SHA12_SHIFT 27 -#define OMAP3430_AUTO_DES2 (1 << 26) +#define OMAP3430_AUTO_DES2_MASK (1 << 26) #define OMAP3430_AUTO_DES2_SHIFT 26 -#define OMAP3430_AUTO_MMC2 (1 << 25) +#define OMAP3430_AUTO_MMC2_MASK (1 << 25) #define OMAP3430_AUTO_MMC2_SHIFT 25 -#define OMAP3430_AUTO_MMC1 (1 << 24) +#define OMAP3430_AUTO_MMC1_MASK (1 << 24) #define OMAP3430_AUTO_MMC1_SHIFT 24 -#define OMAP3430_AUTO_MSPRO (1 << 23) +#define OMAP3430_AUTO_MSPRO_MASK (1 << 23) #define OMAP3430_AUTO_MSPRO_SHIFT 23 -#define OMAP3430_AUTO_HDQ (1 << 22) +#define OMAP3430_AUTO_HDQ_MASK (1 << 22) #define OMAP3430_AUTO_HDQ_SHIFT 22 -#define OMAP3430_AUTO_MCSPI4 (1 << 21) +#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) #define OMAP3430_AUTO_MCSPI4_SHIFT 21 -#define OMAP3430_AUTO_MCSPI3 (1 << 20) +#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) #define OMAP3430_AUTO_MCSPI3_SHIFT 20 -#define OMAP3430_AUTO_MCSPI2 (1 << 19) +#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) #define OMAP3430_AUTO_MCSPI2_SHIFT 19 -#define OMAP3430_AUTO_MCSPI1 (1 << 18) +#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) #define OMAP3430_AUTO_MCSPI1_SHIFT 18 -#define OMAP3430_AUTO_I2C3 (1 << 17) +#define OMAP3430_AUTO_I2C3_MASK (1 << 17) #define OMAP3430_AUTO_I2C3_SHIFT 17 -#define OMAP3430_AUTO_I2C2 (1 << 16) +#define OMAP3430_AUTO_I2C2_MASK (1 << 16) #define OMAP3430_AUTO_I2C2_SHIFT 16 -#define OMAP3430_AUTO_I2C1 (1 << 15) +#define OMAP3430_AUTO_I2C1_MASK (1 << 15) #define OMAP3430_AUTO_I2C1_SHIFT 15 -#define OMAP3430_AUTO_UART2 (1 << 14) +#define OMAP3430_AUTO_UART2_MASK (1 << 14) #define OMAP3430_AUTO_UART2_SHIFT 14 -#define OMAP3430_AUTO_UART1 (1 << 13) +#define OMAP3430_AUTO_UART1_MASK (1 << 13) #define OMAP3430_AUTO_UART1_SHIFT 13 -#define OMAP3430_AUTO_GPT11 (1 << 12) +#define OMAP3430_AUTO_GPT11_MASK (1 << 12) #define OMAP3430_AUTO_GPT11_SHIFT 12 -#define OMAP3430_AUTO_GPT10 (1 << 11) +#define OMAP3430_AUTO_GPT10_MASK (1 << 11) #define OMAP3430_AUTO_GPT10_SHIFT 11 -#define OMAP3430_AUTO_MCBSP5 (1 << 10) +#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) #define OMAP3430_AUTO_MCBSP5_SHIFT 10 -#define OMAP3430_AUTO_MCBSP1 (1 << 9) +#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) #define OMAP3430_AUTO_MCBSP1_SHIFT 9 -#define OMAP3430ES1_AUTO_FAC (1 << 8) +#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) #define OMAP3430ES1_AUTO_FAC_SHIFT 8 -#define OMAP3430_AUTO_MAILBOXES (1 << 7) +#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 -#define OMAP3430_AUTO_OMAPCTRL (1 << 6) +#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 -#define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) +#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 -#define OMAP3430_AUTO_HSOTGUSB (1 << 4) +#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 -#define OMAP3430ES1_AUTO_D2D (1 << 3) +#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) #define OMAP3430ES1_AUTO_D2D_SHIFT 3 -#define OMAP3430_AUTO_SAD2D (1 << 3) +#define OMAP3430_AUTO_SAD2D_MASK (1 << 3) #define OMAP3430_AUTO_SAD2D_SHIFT 3 -#define OMAP3430_AUTO_SSI (1 << 0) +#define OMAP3430_AUTO_SSI_MASK (1 << 0) #define OMAP3430_AUTO_SSI_SHIFT 0 /* CM_AUTOIDLE2_CORE */ -#define OMAP3430_AUTO_PKA (1 << 4) +#define OMAP3430_AUTO_PKA_MASK (1 << 4) #define OMAP3430_AUTO_PKA_SHIFT 4 -#define OMAP3430_AUTO_AES1 (1 << 3) +#define OMAP3430_AUTO_AES1_MASK (1 << 3) #define OMAP3430_AUTO_AES1_SHIFT 3 -#define OMAP3430_AUTO_RNG (1 << 2) +#define OMAP3430_AUTO_RNG_MASK (1 << 2) #define OMAP3430_AUTO_RNG_SHIFT 2 -#define OMAP3430_AUTO_SHA11 (1 << 1) +#define OMAP3430_AUTO_SHA11_MASK (1 << 1) #define OMAP3430_AUTO_SHA11_SHIFT 1 -#define OMAP3430_AUTO_DES1 (1 << 0) +#define OMAP3430_AUTO_DES1_MASK (1 << 0) #define OMAP3430_AUTO_DES1_SHIFT 0 /* CM_AUTOIDLE3_CORE */ @@ -331,7 +331,7 @@ #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) #define OMAP3430_AUTO_MAD2D_SHIFT 3 -#define OMAP3430_AUTO_MAD2D (1 << 3) +#define OMAP3430_AUTO_MAD2D_MASK (1 << 3) /* CM_CLKSEL_CORE */ #define OMAP3430_CLKSEL_SSI_SHIFT 8 @@ -366,9 +366,9 @@ #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) /* CM_FCLKEN_GFX */ -#define OMAP3430ES1_EN_3D (1 << 2) +#define OMAP3430ES1_EN_3D_MASK (1 << 2) #define OMAP3430ES1_EN_3D_SHIFT 2 -#define OMAP3430ES1_EN_2D (1 << 1) +#define OMAP3430ES1_EN_2D_MASK (1 << 1) #define OMAP3430ES1_EN_2D_SHIFT 1 /* CM_ICLKEN_GFX specific bits */ @@ -416,9 +416,9 @@ #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) /* CM_ICLKEN_WKUP specific bits */ -#define OMAP3430_EN_WDT1 (1 << 4) +#define OMAP3430_EN_WDT1_MASK (1 << 4) #define OMAP3430_EN_WDT1_SHIFT 4 -#define OMAP3430_EN_32KSYNC (1 << 2) +#define OMAP3430_EN_32KSYNC_MASK (1 << 2) #define OMAP3430_EN_32KSYNC_SHIFT 2 /* CM_IDLEST_WKUP specific bits */ @@ -432,19 +432,19 @@ #define OMAP3430_ST_32KSYNC_MASK (1 << 2) /* CM_AUTOIDLE_WKUP */ -#define OMAP3430ES2_AUTO_USIMOCP (1 << 9) +#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 -#define OMAP3430_AUTO_WDT2 (1 << 5) +#define OMAP3430_AUTO_WDT2_MASK (1 << 5) #define OMAP3430_AUTO_WDT2_SHIFT 5 -#define OMAP3430_AUTO_WDT1 (1 << 4) +#define OMAP3430_AUTO_WDT1_MASK (1 << 4) #define OMAP3430_AUTO_WDT1_SHIFT 4 -#define OMAP3430_AUTO_GPIO1 (1 << 3) +#define OMAP3430_AUTO_GPIO1_MASK (1 << 3) #define OMAP3430_AUTO_GPIO1_SHIFT 3 -#define OMAP3430_AUTO_32KSYNC (1 << 2) +#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) #define OMAP3430_AUTO_32KSYNC_SHIFT 2 -#define OMAP3430_AUTO_GPT12 (1 << 1) +#define OMAP3430_AUTO_GPT12_MASK (1 << 1) #define OMAP3430_AUTO_GPT12_SHIFT 1 -#define OMAP3430_AUTO_GPT1 (1 << 0) +#define OMAP3430_AUTO_GPT1_MASK (1 << 0) #define OMAP3430_AUTO_GPT1_SHIFT 0 /* CM_CLKSEL_WKUP */ @@ -479,7 +479,7 @@ #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) /* CM_CLKEN2_PLL */ -#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 +#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) @@ -488,10 +488,10 @@ #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) /* CM_IDLEST_CKGEN */ -#define OMAP3430_ST_54M_CLK (1 << 5) -#define OMAP3430_ST_12M_CLK (1 << 4) -#define OMAP3430_ST_48M_CLK (1 << 3) -#define OMAP3430_ST_96M_CLK (1 << 2) +#define OMAP3430_ST_54M_CLK_MASK (1 << 5) +#define OMAP3430_ST_12M_CLK_MASK (1 << 4) +#define OMAP3430_ST_48M_CLK_MASK (1 << 3) +#define OMAP3430_ST_96M_CLK_MASK (1 << 2) #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) #define OMAP3430_ST_CORE_CLK_SHIFT 0 @@ -558,22 +558,22 @@ /* CM_CLKOUT_CTRL */ #define OMAP3430_CLKOUT2_EN_SHIFT 7 -#define OMAP3430_CLKOUT2_EN (1 << 7) +#define OMAP3430_CLKOUT2_EN_MASK (1 << 7) #define OMAP3430_CLKOUT2_DIV_SHIFT 3 #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) /* CM_FCLKEN_DSS */ -#define OMAP3430_EN_TV (1 << 2) +#define OMAP3430_EN_TV_MASK (1 << 2) #define OMAP3430_EN_TV_SHIFT 2 -#define OMAP3430_EN_DSS2 (1 << 1) +#define OMAP3430_EN_DSS2_MASK (1 << 1) #define OMAP3430_EN_DSS2_SHIFT 1 -#define OMAP3430_EN_DSS1 (1 << 0) +#define OMAP3430_EN_DSS1_MASK (1 << 0) #define OMAP3430_EN_DSS1_SHIFT 0 /* CM_ICLKEN_DSS */ -#define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) +#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 /* CM_IDLEST_DSS */ @@ -585,7 +585,7 @@ #define OMAP3430ES1_ST_DSS_MASK (1 << 0) /* CM_AUTOIDLE_DSS */ -#define OMAP3430_AUTO_DSS (1 << 0) +#define OMAP3430_AUTO_DSS_MASK (1 << 0) #define OMAP3430_AUTO_DSS_SHIFT 0 /* CM_CLKSEL_DSS */ @@ -607,16 +607,16 @@ #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) /* CM_FCLKEN_CAM specific bits */ -#define OMAP3430_EN_CSI2 (1 << 1) +#define OMAP3430_EN_CSI2_MASK (1 << 1) #define OMAP3430_EN_CSI2_SHIFT 1 /* CM_ICLKEN_CAM specific bits */ /* CM_IDLEST_CAM */ -#define OMAP3430_ST_CAM (1 << 0) +#define OMAP3430_ST_CAM_MASK (1 << 0) /* CM_AUTOIDLE_CAM */ -#define OMAP3430_AUTO_CAM (1 << 0) +#define OMAP3430_AUTO_CAM_MASK (1 << 0) #define OMAP3430_AUTO_CAM_SHIFT 0 /* CM_CLKSEL_CAM */ @@ -649,41 +649,41 @@ #define OMAP3430_ST_MCBSP2_MASK (1 << 0) /* CM_AUTOIDLE_PER */ -#define OMAP3430_AUTO_GPIO6 (1 << 17) +#define OMAP3430_AUTO_GPIO6_MASK (1 << 17) #define OMAP3430_AUTO_GPIO6_SHIFT 17 -#define OMAP3430_AUTO_GPIO5 (1 << 16) +#define OMAP3430_AUTO_GPIO5_MASK (1 << 16) #define OMAP3430_AUTO_GPIO5_SHIFT 16 -#define OMAP3430_AUTO_GPIO4 (1 << 15) +#define OMAP3430_AUTO_GPIO4_MASK (1 << 15) #define OMAP3430_AUTO_GPIO4_SHIFT 15 -#define OMAP3430_AUTO_GPIO3 (1 << 14) +#define OMAP3430_AUTO_GPIO3_MASK (1 << 14) #define OMAP3430_AUTO_GPIO3_SHIFT 14 -#define OMAP3430_AUTO_GPIO2 (1 << 13) +#define OMAP3430_AUTO_GPIO2_MASK (1 << 13) #define OMAP3430_AUTO_GPIO2_SHIFT 13 -#define OMAP3430_AUTO_WDT3 (1 << 12) +#define OMAP3430_AUTO_WDT3_MASK (1 << 12) #define OMAP3430_AUTO_WDT3_SHIFT 12 -#define OMAP3430_AUTO_UART3 (1 << 11) +#define OMAP3430_AUTO_UART3_MASK (1 << 11) #define OMAP3430_AUTO_UART3_SHIFT 11 -#define OMAP3430_AUTO_GPT9 (1 << 10) +#define OMAP3430_AUTO_GPT9_MASK (1 << 10) #define OMAP3430_AUTO_GPT9_SHIFT 10 -#define OMAP3430_AUTO_GPT8 (1 << 9) +#define OMAP3430_AUTO_GPT8_MASK (1 << 9) #define OMAP3430_AUTO_GPT8_SHIFT 9 -#define OMAP3430_AUTO_GPT7 (1 << 8) +#define OMAP3430_AUTO_GPT7_MASK (1 << 8) #define OMAP3430_AUTO_GPT7_SHIFT 8 -#define OMAP3430_AUTO_GPT6 (1 << 7) +#define OMAP3430_AUTO_GPT6_MASK (1 << 7) #define OMAP3430_AUTO_GPT6_SHIFT 7 -#define OMAP3430_AUTO_GPT5 (1 << 6) +#define OMAP3430_AUTO_GPT5_MASK (1 << 6) #define OMAP3430_AUTO_GPT5_SHIFT 6 -#define OMAP3430_AUTO_GPT4 (1 << 5) +#define OMAP3430_AUTO_GPT4_MASK (1 << 5) #define OMAP3430_AUTO_GPT4_SHIFT 5 -#define OMAP3430_AUTO_GPT3 (1 << 4) +#define OMAP3430_AUTO_GPT3_MASK (1 << 4) #define OMAP3430_AUTO_GPT3_SHIFT 4 -#define OMAP3430_AUTO_GPT2 (1 << 3) +#define OMAP3430_AUTO_GPT2_MASK (1 << 3) #define OMAP3430_AUTO_GPT2_SHIFT 3 -#define OMAP3430_AUTO_MCBSP4 (1 << 2) +#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) #define OMAP3430_AUTO_MCBSP4_SHIFT 2 -#define OMAP3430_AUTO_MCBSP3 (1 << 1) +#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) #define OMAP3430_AUTO_MCBSP3_SHIFT 1 -#define OMAP3430_AUTO_MCBSP2 (1 << 0) +#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) #define OMAP3430_AUTO_MCBSP2_SHIFT 0 /* CM_CLKSEL_PER */ @@ -705,7 +705,7 @@ #define OMAP3430_CLKSEL_GPT2_SHIFT 0 /* CM_SLEEPDEP_PER specific bits */ -#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) +#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) /* CM_CLKSTCTRL_PER */ #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 @@ -755,10 +755,10 @@ #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) /* CM_POLCTRL */ -#define OMAP3430_CLKOUT2_POL (1 << 0) +#define OMAP3430_CLKOUT2_POL_MASK (1 << 0) /* CM_IDLEST_NEON */ -#define OMAP3430_ST_NEON (1 << 0) +#define OMAP3430_ST_NEON_MASK (1 << 0) /* CM_CLKSTCTRL_NEON */ #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c index 58e4a1c557d..2d83565d2be 100644 --- a/arch/arm/mach-omap2/cm.c +++ b/arch/arm/mach-omap2/cm.c @@ -27,9 +27,6 @@ #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" -/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */ -#define MAX_MODULE_READY_TIME 20000 - static const u8 cm_idlest_offs[] = { CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 }; diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 94728b1ee3c..a02ca30423d 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -112,7 +112,7 @@ extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift); -extern int omap4_cm_wait_module_ready(u32 prcm_mod, u8 prcm_dev_offs); +extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) { @@ -134,13 +134,23 @@ static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) /* CM_ICLKEN_GFX */ #define OMAP_EN_GFX_SHIFT 0 -#define OMAP_EN_GFX (1 << 0) +#define OMAP_EN_GFX_MASK (1 << 0) /* CM_IDLEST_GFX */ -#define OMAP_ST_GFX (1 << 0) +#define OMAP_ST_GFX_MASK (1 << 0) + /* CM_IDLEST indicator */ #define OMAP24XX_CM_IDLEST_VAL 0 #define OMAP34XX_CM_IDLEST_VAL 1 +/* + * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the + * PRCM to request that a module exit the inactive state in the case of + * OMAP2 & 3. + * In the case of OMAP4 this is the max duration in microseconds for the + * module to reach the functionnal state from an inactive state. + */ +#define MAX_MODULE_READY_TIME 2000 + #endif diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h index c575b9b0c04..336d94889e5 100644 --- a/arch/arm/mach-omap2/cm44xx.h +++ b/arch/arm/mach-omap2/cm44xx.h @@ -1,8 +1,8 @@ /* * OMAP44xx CM1 & CM2 instance offset macros * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) @@ -25,334 +25,557 @@ /* CM1 */ - /* CM1.OCP_SOCKET_CM1 register offsets */ +#define OMAP4_REVISION_CM1_OFFSET 0x0000 #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000) +#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040) /* CM1.CKGEN_CM1 register offsets */ +#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000) +#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008) +#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010) +#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020) +#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024) +#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028) +#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c) +#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030) +#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034) +#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038) +#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c) +#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040) +#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048) +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c) +#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050) +#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060) +#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064) +#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068) +#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c) +#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088) +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c) +#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c) +#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0) +#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4) +#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8) +#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac) +#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8) +#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8) +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc) +#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc) +#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0) +#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4) +#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8) +#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec) +#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0) +#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108) +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c) +#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120) +#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124) +#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128) +#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c) +#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130) +#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138) +#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c) +#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148) +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c) +#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160) +#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164) +#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170) +#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180) /* CM1.MPU_CM1 register offsets */ +#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000) +#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004) +#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008) +#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020) /* CM1.TESLA_CM1 register offsets */ +#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000) +#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004) +#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008) +#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020) /* CM1.ABE_CM1 register offsets */ +#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000) +#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020) +#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028) +#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030) +#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038) +#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040) +#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048) +#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050) +#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058) +#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060) +#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068) +#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070) +#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078) +#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080) +#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) -/* CM1.RESTORE_CM1 register offsets */ -#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000) -#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004) -#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008) -#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c) -#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010) -#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014) -#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018) -#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c) -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020) -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024) -#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028) -#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c) -#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030) -#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034) - /* CM2 */ - /* CM2.OCP_SOCKET_CM2 register offsets */ +#define OMAP4_REVISION_CM2_OFFSET 0x0000 #define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000) +#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 #define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040) /* CM2.CKGEN_CM2 register offsets */ +#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000) +#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 #define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004) +#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 #define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008) +#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 #define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010) +#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 #define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014) +#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 #define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018) +#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c #define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c) +#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 #define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024) +#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 #define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028) +#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c) +#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 #define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030) +#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 #define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038) +#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 #define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040) +#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 #define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044) +#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 #define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048) +#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c #define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c) +#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 #define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050) +#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 #define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054) +#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 #define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058) +#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c #define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c) +#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 #define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060) +#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) +#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070 #define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070) +#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) +#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 #define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084) +#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 #define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088) +#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c #define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c) +#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8) +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac) +#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4) +#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0) +#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 #define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4) +#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8) +#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc) +#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8) +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec) /* CM2.ALWAYS_ON_CM2 register offsets */ +#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000) +#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020) +#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028) +#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) +#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) /* CM2.CORE_CM2 register offsets */ +#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000) +#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 #define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008) +#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020) +#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 #define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100) +#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 #define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108) +#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 #define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120) +#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 #define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128) +#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130) +#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 #define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200) +#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 #define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204) +#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 #define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208) +#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220) +#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 #define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300) +#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 #define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304) +#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 #define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308) +#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 #define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320) +#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 #define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400) +#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 #define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420) +#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428) +#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430) +#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438) +#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 #define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440) +#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450) +#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458) +#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460) +#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 #define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500) +#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 #define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504) +#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508) +#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520) +#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528 #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528) +#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530) +#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 #define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600) +#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 #define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608) +#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620) +#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628) +#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630) +#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638) +#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 #define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700) +#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720) +#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728) +#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740) /* CM2.IVAHD_CM2 register offsets */ +#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000) +#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 #define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004) +#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 #define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008) +#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020) +#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 #define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028) /* CM2.CAM_CM2 register offsets */ +#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000) +#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 #define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004) +#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 #define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008) +#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020) +#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 #define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028) /* CM2.DSS_CM2 register offsets */ +#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000) +#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 #define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004) +#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 #define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008) +#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020) +#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 #define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028) /* CM2.GFX_CM2 register offsets */ +#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000) +#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 #define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004) +#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 #define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008) +#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020) /* CM2.L3INIT_CM2 register offsets */ +#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000) +#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 #define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004) +#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 #define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008) +#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028) +#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030) +#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 #define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038) +#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040) +#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058) +#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060) +#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068) +#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 #define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078) +#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080) +#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 #define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088) +#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090) +#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098) +#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8) +#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0) +#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8) +#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0) +#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0) /* CM2.L4PER_CM2 register offsets */ +#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000) +#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 #define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008) +#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020) +#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028) +#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030) +#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038) +#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040) +#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048) +#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050) +#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 #define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058) +#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060) +#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068) +#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070) +#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078) +#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080) +#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088) +#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 #define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090) +#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 #define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098) +#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 #define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0) +#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 #define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8) +#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 #define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0) +#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 #define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8) +#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 #define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0) +#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0) +#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8) +#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0) +#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 #define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8) +#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0) +#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8) +#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100) +#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108) +#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120) +#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128) +#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130) +#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138) +#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 #define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140) +#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 #define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148) +#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 #define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150) +#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 #define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158) +#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160) +#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 #define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168) +#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 #define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180) +#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 #define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184) +#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 #define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188) +#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 #define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0) +#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 #define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8) +#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0) +#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8) +#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 #define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0) +#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8) +#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8) /* CM2.CEFUSE_CM2 register offsets */ +#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) +#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) - -/* CM2.RESTORE_CM2 register offsets */ -#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000) -#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004) -#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008) -#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c) -#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010) -#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014) -#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018) -#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c) -#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020) -#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024) -#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028) -#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c) -#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030) -#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034) -#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038) -#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c) -#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040) #endif diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c index 4af76bb1003..b101091e95d 100644 --- a/arch/arm/mach-omap2/cm4xxx.c +++ b/arch/arm/mach-omap2/cm4xxx.c @@ -21,35 +21,41 @@ #include <asm/atomic.h> -#include "cm.h" - -/* XXX move this to cm.h */ -/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */ -#define MAX_MODULE_READY_TIME 20000 +#include <plat/common.h> -/* - * OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK: isolates the IDLEST field in the - * CM_CLKCTRL register. - */ -#define OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK (0x2 << 16) - -/* - * OMAP4 prcm_mod u32 fields contain packed data: the CM ID in bit 16 and - * the PRCM module offset address (from the CM module base) in bits 15-0. - */ -#define OMAP4_PRCM_MOD_CM_ID_SHIFT 16 -#define OMAP4_PRCM_MOD_OFFS_MASK 0xffff +#include "cm.h" +#include "cm-regbits-44xx.h" /** - * omap4_cm_wait_idlest_ready - wait for a module to leave idle or standby - * @prcm_mod: PRCM module offset (XXX example) - * @prcm_dev_offs: PRCM device offset (e.g. MCASP XXX example) + * omap4_cm_wait_module_ready - wait for a module to be in 'func' state + * @clkctrl_reg: CLKCTRL module address + * + * Wait for the module IDLEST to be functional. If the idle state is in any + * the non functional state (trans, idle or disabled), module and thus the + * sysconfig cannot be accessed and will probably lead to an "imprecise + * external abort" + * + * Module idle state: + * 0x0 func: Module is fully functional, including OCP + * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep + * abortion + * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if + * using separate functional clock + * 0x3 disabled: Module is disabled and cannot be accessed * - * XXX document + * TODO: Need to handle module accessible in idle state */ -int omap4_cm_wait_idlest_ready(u32 prcm_mod, u8 prcm_dev_offs) +int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) { - /* FIXME: Add clock manager related code */ - return 0; + int i = 0; + + if (!clkctrl_reg) + return 0; + + omap_test_timeout(((__raw_readl(clkctrl_reg) & + OMAP4430_IDLEST_MASK) == 0), + MAX_MODULE_READY_TIME, i); + + return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; } diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 43f8a33655d..a8d20eef230 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -194,11 +194,12 @@ void omap3_clear_scratchpad_contents(void) u32 offset = 0; v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & - OMAP3430_GLOBAL_COLD_RST) { + OMAP3430_GLOBAL_COLD_RST_MASK) { for ( ; offset <= max_offset; offset += 0x4) __raw_writel(0x0, (v_addr + offset)); - prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD, - OMAP3_PRM_RSTST_OFFSET); + prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, + OMAP3430_GR_MOD, + OMAP3_PRM_RSTST_OFFSET); } } diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 2271b9bd1f5..03e6c9ed82a 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -17,8 +17,10 @@ #include <linux/clk.h> #include <mach/hardware.h> +#include <mach/irqs.h> #include <asm/mach-types.h> #include <asm/mach/map.h> +#include <asm/pmu.h> #include <plat/control.h> #include <plat/tc.h> @@ -26,6 +28,7 @@ #include <plat/mux.h> #include <mach/gpio.h> #include <plat/mmc.h> +#include <plat/dma.h> #include "mux.h" @@ -453,8 +456,41 @@ static void omap_init_mcspi(void) static inline void omap_init_mcspi(void) {} #endif -#ifdef CONFIG_OMAP_SHA1_MD5 -static struct resource sha1_md5_resources[] = { +static struct resource omap2_pmu_resource = { + .start = 3, + .end = 3, + .flags = IORESOURCE_IRQ, +}; + +static struct resource omap3_pmu_resource = { + .start = INT_34XX_BENCH_MPU_EMUL, + .end = INT_34XX_BENCH_MPU_EMUL, + .flags = IORESOURCE_IRQ, +}; + +static struct platform_device omap_pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = 1, +}; + +static void omap_init_pmu(void) +{ + if (cpu_is_omap24xx()) + omap_pmu_device.resource = &omap2_pmu_resource; + else if (cpu_is_omap34xx()) + omap_pmu_device.resource = &omap3_pmu_resource; + else + return; + + platform_device_register(&omap_pmu_device); +} + + +#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) + +#ifdef CONFIG_ARCH_OMAP2 +static struct resource omap2_sham_resources[] = { { .start = OMAP24XX_SEC_SHA1MD5_BASE, .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, @@ -465,20 +501,55 @@ static struct resource sha1_md5_resources[] = { .flags = IORESOURCE_IRQ, } }; +static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); +#else +#define omap2_sham_resources NULL +#define omap2_sham_resources_sz 0 +#endif -static struct platform_device sha1_md5_device = { - .name = "OMAP SHA1/MD5", +#ifdef CONFIG_ARCH_OMAP3 +static struct resource omap3_sham_resources[] = { + { + .start = OMAP34XX_SEC_SHA1MD5_BASE, + .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_34XX_SHA1MD52_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = OMAP34XX_DMA_SHA1MD5_RX, + .flags = IORESOURCE_DMA, + } +}; +static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); +#else +#define omap3_sham_resources NULL +#define omap3_sham_resources_sz 0 +#endif + +static struct platform_device sham_device = { + .name = "omap-sham", .id = -1, - .num_resources = ARRAY_SIZE(sha1_md5_resources), - .resource = sha1_md5_resources, }; -static void omap_init_sha1_md5(void) +static void omap_init_sham(void) { - platform_device_register(&sha1_md5_device); + if (cpu_is_omap24xx()) { + sham_device.resource = omap2_sham_resources; + sham_device.num_resources = omap2_sham_resources_sz; + } else if (cpu_is_omap34xx()) { + sham_device.resource = omap3_sham_resources; + sham_device.num_resources = omap3_sham_resources_sz; + } else { + pr_err("%s: platform not supported\n", __func__); + return; + } + platform_device_register(&sham_device); } #else -static inline void omap_init_sha1_md5(void) { } +static inline void omap_init_sham(void) { } #endif /*-------------------------------------------------------------------------*/ @@ -591,6 +662,15 @@ static inline void omap_hsmmc_reset(void) {} static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, int controller_nr) { + if ((mmc_controller->slots[0].switch_pin > 0) && \ + (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) + omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, + OMAP_PIN_INPUT_PULLUP); + if ((mmc_controller->slots[0].gpio_wp > 0) && \ + (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) + omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, + OMAP_PIN_INPUT_PULLUP); + if (cpu_is_omap2420() && controller_nr == 0) { omap_cfg_reg(H18_24XX_MMC_CMD); omap_cfg_reg(H15_24XX_MMC_CLKI); @@ -786,6 +866,33 @@ static inline void omap_hdq_init(void) static inline void omap_hdq_init(void) {} #endif +/*---------------------------------------------------------------------------*/ + +#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \ + defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) +#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) +static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = { +}; +#else +static struct resource omap_vout_resource[2] = { +}; +#endif + +static struct platform_device omap_vout_device = { + .name = "omap_vout", + .num_resources = ARRAY_SIZE(omap_vout_resource), + .resource = &omap_vout_resource[0], + .id = -1, +}; +static void omap_init_vout(void) +{ + if (platform_device_register(&omap_vout_device) < 0) + printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); +} +#else +static inline void omap_init_vout(void) {} +#endif + /*-------------------------------------------------------------------------*/ static int __init omap2_init_devices(void) @@ -797,9 +904,11 @@ static int __init omap2_init_devices(void) omap_init_camera(); omap_init_mbox(); omap_init_mcspi(); + omap_init_pmu(); omap_hdq_init(); omap_init_sti(); - omap_init_sha1_md5(); + omap_init_sham(); + omap_init_vout(); return 0; } diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 9ad229594b4..1ef54b03610 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -24,6 +24,7 @@ static u16 control_pbias_offset; static u16 control_devconf1_offset; +static u16 control_mmc1; #define HSMMC_NAME_LEN 9 @@ -42,7 +43,7 @@ static int hsmmc_get_context_loss(struct device *dev) #define hsmmc_get_context_loss NULL #endif -static void hsmmc1_before_set_reg(struct device *dev, int slot, +static void omap_hsmmc1_before_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg, prog_io; @@ -95,7 +96,7 @@ static void hsmmc1_before_set_reg(struct device *dev, int slot, } } -static void hsmmc1_after_set_reg(struct device *dev, int slot, +static void omap_hsmmc1_after_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg; @@ -119,6 +120,60 @@ static void hsmmc1_after_set_reg(struct device *dev, int slot, } } +static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, + int power_on, int vdd) +{ + u32 reg; + + /* + * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the + * card with Vcc regulator (from twl4030 or whatever). OMAP has both + * 1.8V and 3.0V modes, controlled by the PBIAS register. + * + * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which + * is most naturally TWL VSIM; those pins also use PBIAS. + * + * FIXME handle VMMC1A as needed ... + */ + reg = omap_ctrl_readl(control_pbias_offset); + reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | + OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); +} + +static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, + int power_on, int vdd) +{ + u32 reg; + + if (power_on) { + reg = omap_ctrl_readl(control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ; + if ((1 << vdd) <= MMC_VDD_165_195) + reg &= ~OMAP4_MMC1_PBIASLITE_VMODE; + else + reg |= OMAP4_MMC1_PBIASLITE_VMODE; + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | + OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); + /* 4 microsec delay for comparator to generate an error*/ + udelay(4); + reg = omap_ctrl_readl(control_pbias_offset); + if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) { + pr_err("Pbias Voltage is not same as LDO\n"); + /* Caution : On VMODE_ERROR Power Down MMC IO */ + reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); + } + } else { + reg = omap_ctrl_readl(control_pbias_offset); + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | + OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ | + OMAP4_USBC1_ICUSB_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); + } +} + static void hsmmc23_before_set_reg(struct device *dev, int slot, int power_on, int vdd) { @@ -139,6 +194,12 @@ static void hsmmc23_before_set_reg(struct device *dev, int slot, } } +static int nop_mmc_set_power(struct device *dev, int slot, int power_on, + int vdd) +{ + return 0; +} + static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) @@ -146,13 +207,28 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) struct omap2_hsmmc_info *c; int nr_hsmmc = ARRAY_SIZE(hsmmc_data); int i; + u32 reg; - if (cpu_is_omap2430()) { - control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; - control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; + if (!cpu_is_omap44xx()) { + if (cpu_is_omap2430()) { + control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; + control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; + } else { + control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; + control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; + } } else { - control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; - control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; + control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE; + control_mmc1 = OMAP44XX_CONTROL_MMC1; + reg = omap_ctrl_readl(control_mmc1); + reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 | + OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1); + reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 | + OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3); + reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL | + OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL | + OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL); + omap_ctrl_writel(reg, control_mmc1); } for (c = controllers; c->mmc; c++) { @@ -216,11 +292,27 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) */ mmc->slots[0].ocr_mask = c->ocr_mask; + if (cpu_is_omap3517() || cpu_is_omap3505()) + mmc->slots[0].set_power = nop_mmc_set_power; + else + mmc->slots[0].features |= HSMMC_HAS_PBIAS; + switch (c->mmc) { case 1: - /* on-chip level shifting via PBIAS0/PBIAS1 */ - mmc->slots[0].before_set_reg = hsmmc1_before_set_reg; - mmc->slots[0].after_set_reg = hsmmc1_after_set_reg; + if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { + /* on-chip level shifting via PBIAS0/PBIAS1 */ + if (cpu_is_omap44xx()) { + mmc->slots[0].before_set_reg = + omap4_hsmmc1_before_set_reg; + mmc->slots[0].after_set_reg = + omap4_hsmmc1_after_set_reg; + } else { + mmc->slots[0].before_set_reg = + omap_hsmmc1_before_set_reg; + mmc->slots[0].after_set_reg = + omap_hsmmc1_after_set_reg; + } + } /* Omap3630 HSMMC1 supports only 4-bit */ if (cpu_is_omap3630() && c->wires > 4) { @@ -235,9 +327,11 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) c->wires = 4; /* FALLTHROUGH */ case 3: - /* off-chip level shifting, or none */ - mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; - mmc->slots[0].after_set_reg = NULL; + if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { + /* off-chip level shifting, or none */ + mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; + mmc->slots[0].after_set_reg = NULL; + } break; default: pr_err("MMC%d configuration not supported!\n", c->mmc); diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h index a705f946fc4..f1e13d1ca5e 100644 --- a/arch/arm/mach-omap2/include/mach/am35xx.h +++ b/arch/arm/mach-omap2/include/mach/am35xx.h @@ -23,4 +23,22 @@ #define AM35XX_IPSS_HECC_BASE 0x5C050000 #define AM35XX_IPSS_VPFE_BASE 0x5C060000 -#endif /* __ASM_ARCH_AM35XX_H */ + +/* HECC module specifc offset definitions */ +#define AM35XX_HECC_SCC_HECC_OFFSET (0x0) +#define AM35XX_HECC_SCC_RAM_OFFSET (0x3000) +#define AM35XX_HECC_RAM_OFFSET (0x3000) +#define AM35XX_HECC_MBOX_OFFSET (0x2000) +#define AM35XX_HECC_INT_LINE (0x0) +#define AM35XX_HECC_VERSION (0x1) + +#define AM35XX_EMAC_CNTRL_OFFSET (0x10000) +#define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0) +#define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000) +#define AM35XX_EMAC_MDIO_OFFSET (0x30000) +#define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000) +#define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \ + AM3517_EMAC_CNTRL_RAM_OFFSET) +#define AM35XX_EMAC_HW_RAM_ADDR (0x01E20000) + +#endif /* __ASM_ARCH_AM35XX_H */ diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index 4a63a2ea484..35b24409a0c 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -13,6 +13,8 @@ #include <linux/serial_reg.h> +#include <asm/memory.h> + #include <plat/serial.h> #define UART_OFFSET(addr) ((addr) & 0x00ffffff) @@ -40,13 +42,12 @@ omap_uart_lsr: .word 0 cmp \rx, #0 @ is port configured? bne 99f @ already configured - /* Check UART1 scratchpad register for uart to use */ + /* Check the debug UART configuration set in uncompress.h */ mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - moveq \rx, #0x48000000 @ physical base address - movne \rx, #0xfa000000 @ virtual base - orr \rx, \rx, #0x0006a000 @ uart1 on omap2/3/4 - ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)] @ scratchpad + ldreq \rx, =OMAP_UART_INFO + ldrne \rx, =__phys_to_virt(OMAP_UART_INFO) + ldr \rx, [\rx, #0] /* Select the UART to use based on the UART1 scratchpad value */ cmp \rx, #0 @ no port configured? @@ -87,10 +88,10 @@ omap_uart_lsr: .word 0 b 98f 44: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE) b 98f -95: mov \rx, #ZOOM_UART_BASE +95: ldr \rx, =ZOOM_UART_BASE ldr \tmp, =omap_uart_phys str \rx, [\tmp, #0] - mov \rx, #ZOOM_UART_VIRT + ldr \rx, =ZOOM_UART_VIRT ldr \tmp, =omap_uart_virt str \rx, [\tmp, #0] mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT) diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h new file mode 100644 index 00000000000..423af3a6dd3 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/omap4-common.h @@ -0,0 +1,26 @@ +/* + * omap4-common.h: OMAP4 specific common header file + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Author: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP_ARCH_OMAP4_COMMON_H +#define OMAP_ARCH_OMAP4_COMMON_H + +#ifdef CONFIG_CACHE_L2X0 +extern void __iomem *l2cache_base; +#endif + +extern void __iomem *gic_cpu_base_addr; +extern void __iomem *gic_dist_base_addr; + +extern void __init gic_init_irq(void); +extern void omap_smc1(u32 fn, u32 arg); + +#endif diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 87f676acf61..3cfb425ea67 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -166,6 +166,15 @@ static struct map_desc omap34xx_io_desc[] __initdata = { .length = L4_EMU_34XX_SIZE, .type = MT_DEVICE }, +#if defined(CONFIG_DEBUG_LL) && \ + (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) + { + .virtual = ZOOM_UART_VIRT, + .pfn = __phys_to_pfn(ZOOM_UART_BASE), + .length = SZ_1M, + .type = MT_DEVICE + }, +#endif }; #endif #ifdef CONFIG_ARCH_OMAP4 diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index 4f63dc6859a..e82da680d90 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -147,6 +147,7 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) printk("\n"); iommu_write_reg(obj, stat, MMU_IRQSTATUS); + omap2_iommu_disable(obj); return stat; } @@ -184,7 +185,7 @@ static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e) if (!cr) return ERR_PTR(-ENOMEM); - cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz; + cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; cr->ram = e->pa | e->endian | e->elsz | e->mixed; return cr; @@ -212,7 +213,8 @@ static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf) char *p = buf; /* FIXME: Need more detail analysis of cam/ram */ - p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram); + p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram, + (cr->cam & MMU_CAM_P) ? 1 : 0); return p - buf; } diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 2f3cad6f940..c29337074ad 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -187,32 +187,28 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .phys_base = OMAP44XX_MCBSP1_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, - .rx_irq = INT_24XX_MCBSP1_IRQ_RX, - .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + .tx_irq = OMAP44XX_IRQ_MCBSP1, .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP2_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, - .rx_irq = INT_24XX_MCBSP2_IRQ_RX, - .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + .tx_irq = OMAP44XX_IRQ_MCBSP2, .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP3_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, - .rx_irq = INT_24XX_MCBSP3_IRQ_RX, - .tx_irq = INT_24XX_MCBSP3_IRQ_TX, + .tx_irq = OMAP44XX_IRQ_MCBSP3, .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP4_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, - .rx_irq = INT_24XX_MCBSP4_IRQ_RX, - .tx_irq = INT_24XX_MCBSP4_IRQ_TX, + .tx_irq = OMAP44XX_IRQ_MCBSP4, .ops = &omap2_mcbsp_ops, }, }; diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index 07aa7b3c95f..2ff4dce95ee 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -1901,26 +1901,15 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = { _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"), _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"), _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"), - _OMAP3_BALLENTRY(GPMC_D0, "k1", "m2"), - _OMAP3_BALLENTRY(GPMC_D1, "l1", "m1"), _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"), _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"), _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"), _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"), _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"), _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"), - _OMAP3_BALLENTRY(GPMC_D2, "l2", "n2"), - _OMAP3_BALLENTRY(GPMC_D3, "p2", "n1"), - _OMAP3_BALLENTRY(GPMC_D4, "t1", "r2"), - _OMAP3_BALLENTRY(GPMC_D5, "v1", "r1"), - _OMAP3_BALLENTRY(GPMC_D6, "v2", "t2"), - _OMAP3_BALLENTRY(GPMC_D7, "w2", "t1"), - _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"), _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"), - _OMAP3_BALLENTRY(GPMC_NADV_ALE, "f3", "w1"), _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"), _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL), - _OMAP3_BALLENTRY(GPMC_NCS0, "g4", "y2"), _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"), _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL), _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL), @@ -1928,10 +1917,7 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = { _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL), _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL), _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL), - _OMAP3_BALLENTRY(GPMC_NOE, "g2", "v2"), - _OMAP3_BALLENTRY(GPMC_NWE, "f4", "v1"), _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"), - _OMAP3_BALLENTRY(GPMC_WAIT0, "m8", "ab12"), _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"), _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL), _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL), @@ -1948,8 +1934,6 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = { _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL), _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL), _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL), - _OMAP3_BALLENTRY(I2C1_SCL, "k21", NULL), - _OMAP3_BALLENTRY(I2C1_SDA, "j21", NULL), _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL), _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL), _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL), @@ -1958,11 +1942,6 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = { _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL), _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL), _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL), - _OMAP3_BALLENTRY(JTAG_RTCK, "aa12", NULL), - _OMAP3_BALLENTRY(JTAG_TCK, "aa13", NULL), - _OMAP3_BALLENTRY(JTAG_TDI, "aa20", NULL), - _OMAP3_BALLENTRY(JTAG_TDO, "aa19", NULL), - _OMAP3_BALLENTRY(JTAG_TMS_TMSC, "aa18", NULL), _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL), _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL), _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL), @@ -2010,77 +1989,12 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = { _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL), _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL), _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL), - _OMAP3_BALLENTRY(SDRC_A0, NULL, "n22"), - _OMAP3_BALLENTRY(SDRC_A1, NULL, "n23"), - _OMAP3_BALLENTRY(SDRC_A10, NULL, "v22"), - _OMAP3_BALLENTRY(SDRC_A11, NULL, "v23"), - _OMAP3_BALLENTRY(SDRC_A12, NULL, "w22"), - _OMAP3_BALLENTRY(SDRC_A13, NULL, "w23"), - _OMAP3_BALLENTRY(SDRC_A14, NULL, "y22"), - _OMAP3_BALLENTRY(SDRC_A2, NULL, "p22"), - _OMAP3_BALLENTRY(SDRC_A3, NULL, "p23"), - _OMAP3_BALLENTRY(SDRC_A4, NULL, "r22"), - _OMAP3_BALLENTRY(SDRC_A5, NULL, "r23"), - _OMAP3_BALLENTRY(SDRC_A6, NULL, "t22"), - _OMAP3_BALLENTRY(SDRC_A7, NULL, "t23"), - _OMAP3_BALLENTRY(SDRC_A8, NULL, "u22"), - _OMAP3_BALLENTRY(SDRC_A9, NULL, "u23"), - _OMAP3_BALLENTRY(SDRC_BA0, "h9", "ab21"), - _OMAP3_BALLENTRY(SDRC_BA1, "h10", "ac21"), _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"), _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"), - _OMAP3_BALLENTRY(SDRC_CLK, "a13", "a11"), - _OMAP3_BALLENTRY(SDRC_D0, NULL, "j2"), - _OMAP3_BALLENTRY(SDRC_D1, NULL, "j1"), - _OMAP3_BALLENTRY(SDRC_D10, "c15", "b14"), - _OMAP3_BALLENTRY(SDRC_D11, "b16", "a14"), - _OMAP3_BALLENTRY(SDRC_D12, "d17", "b16"), - _OMAP3_BALLENTRY(SDRC_D13, "c17", "a16"), - _OMAP3_BALLENTRY(SDRC_D14, "b17", "b19"), - _OMAP3_BALLENTRY(SDRC_D15, "d18", "a19"), - _OMAP3_BALLENTRY(SDRC_D16, NULL, "b3"), - _OMAP3_BALLENTRY(SDRC_D17, NULL, "a3"), - _OMAP3_BALLENTRY(SDRC_D18, NULL, "b5"), - _OMAP3_BALLENTRY(SDRC_D19, NULL, "a5"), - _OMAP3_BALLENTRY(SDRC_D2, NULL, "g2"), - _OMAP3_BALLENTRY(SDRC_D20, NULL, "b8"), - _OMAP3_BALLENTRY(SDRC_D21, NULL, "a8"), - _OMAP3_BALLENTRY(SDRC_D22, NULL, "b9"), - _OMAP3_BALLENTRY(SDRC_D23, NULL, "a9"), - _OMAP3_BALLENTRY(SDRC_D24, NULL, "b21"), - _OMAP3_BALLENTRY(SDRC_D25, NULL, "a21"), - _OMAP3_BALLENTRY(SDRC_D26, NULL, "d22"), - _OMAP3_BALLENTRY(SDRC_D27, NULL, "d23"), - _OMAP3_BALLENTRY(SDRC_D28, NULL, "e22"), - _OMAP3_BALLENTRY(SDRC_D29, NULL, "e23"), - _OMAP3_BALLENTRY(SDRC_D3, NULL, "g1"), - _OMAP3_BALLENTRY(SDRC_D30, NULL, "g22"), - _OMAP3_BALLENTRY(SDRC_D31, NULL, "g23"), - _OMAP3_BALLENTRY(SDRC_D4, NULL, "f2"), - _OMAP3_BALLENTRY(SDRC_D5, NULL, "f1"), - _OMAP3_BALLENTRY(SDRC_D6, NULL, "d2"), - _OMAP3_BALLENTRY(SDRC_D7, NULL, "d1"), - _OMAP3_BALLENTRY(SDRC_D8, "c14", "b13"), - _OMAP3_BALLENTRY(SDRC_D9, "b14", "a13"), - _OMAP3_BALLENTRY(SDRC_DM0, NULL, "c1"), - _OMAP3_BALLENTRY(SDRC_DM1, "a16", "a17"), - _OMAP3_BALLENTRY(SDRC_DM2, NULL, "a6"), - _OMAP3_BALLENTRY(SDRC_DM3, NULL, "a20"), - _OMAP3_BALLENTRY(SDRC_DQS0, NULL, "c2"), - _OMAP3_BALLENTRY(SDRC_DQS1, "a17", "b17"), - _OMAP3_BALLENTRY(SDRC_DQS2, NULL, "b6"), - _OMAP3_BALLENTRY(SDRC_DQS3, NULL, "b20"), - _OMAP3_BALLENTRY(SDRC_NCAS, "h13", "l22"), - _OMAP3_BALLENTRY(SDRC_NCLK, "a14", "b11"), - _OMAP3_BALLENTRY(SDRC_NCS0, "h11", "m22"), - _OMAP3_BALLENTRY(SDRC_NCS1, "h12", "m23"), - _OMAP3_BALLENTRY(SDRC_NRAS, "h14", "l23"), - _OMAP3_BALLENTRY(SDRC_NWE, "h15", "k23"), _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL), _OMAP3_BALLENTRY(SIM_IO, "p27", NULL), _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL), _OMAP3_BALLENTRY(SIM_RST, "r25", NULL), - _OMAP3_BALLENTRY(SYS_32K, "ae25", NULL), _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL), _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL), _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL), diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c new file mode 100644 index 00000000000..eb9bee73e0c --- /dev/null +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -0,0 +1,157 @@ +/* + * omap iommu: omap device registration + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> + +#include <plat/iommu.h> +#include <plat/irqs.h> + +struct iommu_device { + resource_size_t base; + int irq; + struct iommu_platform_data pdata; + struct resource res[2]; +}; +static struct iommu_device *devices; +static int num_iommu_devices; + +#ifdef CONFIG_ARCH_OMAP3 +static struct iommu_device omap3_devices[] = { + { + .base = 0x480bd400, + .irq = 24, + .pdata = { + .name = "isp", + .nr_tlb_entries = 8, + .clk_name = "cam_ick", + }, + }, +#if defined(CONFIG_MPU_BRIDGE_IOMMU) + { + .base = 0x5d000000, + .irq = 28, + .pdata = { + .name = "iva2", + .nr_tlb_entries = 32, + .clk_name = "iva2_ck", + }, + }, +#endif +}; +#define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices) +static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES]; +#else +#define omap3_devices NULL +#define NR_OMAP3_IOMMU_DEVICES 0 +#define omap3_iommu_pdev NULL +#endif + +#ifdef CONFIG_ARCH_OMAP4 +static struct iommu_device omap4_devices[] = { + { + .base = OMAP4_MMU1_BASE, + .irq = INT_44XX_DUCATI_MMU_IRQ, + .pdata = { + .name = "ducati", + .nr_tlb_entries = 32, + .clk_name = "ducati_ick", + }, + }, +#if defined(CONFIG_MPU_TESLA_IOMMU) + { + .base = OMAP4_MMU2_BASE, + .irq = INT_44XX_DSP_MMU, + .pdata = { + .name = "tesla", + .nr_tlb_entries = 32, + .clk_name = "tesla_ick", + }, + }, +#endif +}; +#define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices) +static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES]; +#else +#define omap4_devices NULL +#define NR_OMAP4_IOMMU_DEVICES 0 +#define omap4_iommu_pdev NULL +#endif + +static struct platform_device **omap_iommu_pdev; + +static int __init omap_iommu_init(void) +{ + int i, err; + struct resource res[] = { + { .flags = IORESOURCE_MEM }, + { .flags = IORESOURCE_IRQ }, + }; + + if (cpu_is_omap34xx()) { + devices = omap3_devices; + omap_iommu_pdev = omap3_iommu_pdev; + num_iommu_devices = NR_OMAP3_IOMMU_DEVICES; + } else if (cpu_is_omap44xx()) { + devices = omap4_devices; + omap_iommu_pdev = omap4_iommu_pdev; + num_iommu_devices = NR_OMAP4_IOMMU_DEVICES; + } else + return -ENODEV; + + for (i = 0; i < num_iommu_devices; i++) { + struct platform_device *pdev; + const struct iommu_device *d = &devices[i]; + + pdev = platform_device_alloc("omap-iommu", i); + if (!pdev) { + err = -ENOMEM; + goto err_out; + } + + res[0].start = d->base; + res[0].end = d->base + MMU_REG_SIZE - 1; + res[1].start = res[1].end = d->irq; + + err = platform_device_add_resources(pdev, res, + ARRAY_SIZE(res)); + if (err) + goto err_out; + err = platform_device_add_data(pdev, &d->pdata, + sizeof(d->pdata)); + if (err) + goto err_out; + err = platform_device_add(pdev); + if (err) + goto err_out; + omap_iommu_pdev[i] = pdev; + } + return 0; + +err_out: + while (i--) + platform_device_put(omap_iommu_pdev[i]); + return err; +} +module_init(omap_iommu_init); + +static void __exit omap_iommu_exit(void) +{ + int i; + + for (i = 0; i < num_iommu_devices; i++) + platform_device_unregister(omap_iommu_pdev[i]); +} +module_exit(omap_iommu_exit); + +MODULE_AUTHOR("Hiroshi DOYU"); +MODULE_DESCRIPTION("omap iommu: omap device registration"); +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 38153e5fbca..1cf52313759 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -24,7 +24,7 @@ #include <asm/localtimer.h> #include <asm/smp_scu.h> #include <mach/hardware.h> -#include <plat/common.h> +#include <mach/omap4-common.h> /* SCU base address */ static void __iomem *scu_base; diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c deleted file mode 100644 index fbbcb5c8336..00000000000 --- a/arch/arm/mach-omap2/omap3-iommu.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * omap iommu: omap3 device registration - * - * Copyright (C) 2008-2009 Nokia Corporation - * - * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> - -#include <plat/iommu.h> - -struct iommu_device { - resource_size_t base; - int irq; - struct iommu_platform_data pdata; - struct resource res[2]; -}; - -static struct iommu_device devices[] = { - { - .base = 0x480bd400, - .irq = 24, - .pdata = { - .name = "isp", - .nr_tlb_entries = 8, - .clk_name = "cam_ick", - }, - }, -#if defined(CONFIG_MPU_BRIDGE_IOMMU) - { - .base = 0x5d000000, - .irq = 28, - .pdata = { - .name = "iva2", - .nr_tlb_entries = 32, - .clk_name = "iva2_ck", - }, - }, -#endif -}; -#define NR_IOMMU_DEVICES ARRAY_SIZE(devices) - -static struct platform_device *omap3_iommu_pdev[NR_IOMMU_DEVICES]; - -static int __init omap3_iommu_init(void) -{ - int i, err; - struct resource res[] = { - { .flags = IORESOURCE_MEM }, - { .flags = IORESOURCE_IRQ }, - }; - - for (i = 0; i < NR_IOMMU_DEVICES; i++) { - struct platform_device *pdev; - const struct iommu_device *d = &devices[i]; - - pdev = platform_device_alloc("omap-iommu", i); - if (!pdev) { - err = -ENOMEM; - goto err_out; - } - - res[0].start = d->base; - res[0].end = d->base + MMU_REG_SIZE - 1; - res[1].start = res[1].end = d->irq; - - err = platform_device_add_resources(pdev, res, - ARRAY_SIZE(res)); - if (err) - goto err_out; - err = platform_device_add_data(pdev, &d->pdata, - sizeof(d->pdata)); - if (err) - goto err_out; - err = platform_device_add(pdev); - if (err) - goto err_out; - omap3_iommu_pdev[i] = pdev; - } - return 0; - -err_out: - while (i--) - platform_device_put(omap3_iommu_pdev[i]); - return err; -} -module_init(omap3_iommu_init); - -static void __exit omap3_iommu_exit(void) -{ - int i; - - for (i = 0; i < NR_IOMMU_DEVICES; i++) - platform_device_unregister(omap3_iommu_pdev[i]); -} -module_exit(omap3_iommu_exit); - -MODULE_AUTHOR("Hiroshi DOYU"); -MODULE_DESCRIPTION("omap iommu: omap3 device registration"); -MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c new file mode 100644 index 00000000000..13dc9794dcc --- /dev/null +++ b/arch/arm/mach-omap2/omap4-common.c @@ -0,0 +1,72 @@ +/* + * OMAP4 specific common source file. + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Author: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * + * This program is free software,you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> + +#include <asm/hardware/gic.h> +#include <asm/hardware/cache-l2x0.h> + +#include <mach/hardware.h> +#include <mach/omap4-common.h> + +#ifdef CONFIG_CACHE_L2X0 +void __iomem *l2cache_base; +#endif + +void __iomem *gic_cpu_base_addr; +void __iomem *gic_dist_base_addr; + + +void __init gic_init_irq(void) +{ + /* Static mapping, never released */ + gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); + BUG_ON(!gic_dist_base_addr); + gic_dist_init(0, gic_dist_base_addr, 29); + + /* Static mapping, never released */ + gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); + BUG_ON(!gic_cpu_base_addr); + gic_cpu_init(0, gic_cpu_base_addr); +} + +#ifdef CONFIG_CACHE_L2X0 +static int __init omap_l2_cache_init(void) +{ + /* + * To avoid code running on other OMAPs in + * multi-omap builds + */ + if (!cpu_is_omap44xx()) + return -ENODEV; + + /* Static mapping, never released */ + l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); + BUG_ON(!l2cache_base); + + /* Enable PL310 L2 Cache controller */ + omap_smc1(0x102, 0x1); + + /* + * 32KB way size, 16-way associativity, + * parity disabled + */ + l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); + + return 0; +} +early_initcall(omap_l2_cache_init); +#endif diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index e436dcb1979..95c9a5f774e 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2,12 +2,12 @@ * omap_hwmod implementation for OMAP2/3/4 * * Copyright (C) 2009 Nokia Corporation - * Paul Walmsley - * With fixes and testing from Kevin Hilman * - * Created in collaboration with (alphabetical order): Benoit Cousson, - * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari - * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff + * Paul Walmsley, Benoît Cousson, Kevin Hilman + * + * Created in collaboration with (alphabetical order): Thara Gopinath, + * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand + * Sawant, Santosh Shilimkar, Richard Woodruff * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -43,7 +43,6 @@ #include <linux/err.h> #include <linux/list.h> #include <linux/mutex.h> -#include <linux/bootmem.h> #include <plat/common.h> #include <plat/cpu.h> @@ -58,7 +57,7 @@ #define MAX_MODULE_RESET_WAIT 10000 /* Name of the OMAP hwmod for the MPU */ -#define MPU_INITIATOR_NAME "mpu_hwmod" +#define MPU_INITIATOR_NAME "mpu" /* omap_hwmod_list contains all registered struct omap_hwmods */ static LIST_HEAD(omap_hwmod_list); @@ -404,21 +403,20 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) */ static int _init_main_clk(struct omap_hwmod *oh) { - struct clk *c; int ret = 0; if (!oh->main_clk) return 0; - c = omap_clk_get_by_name(oh->main_clk); - WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get main_clk %s\n", - oh->name, oh->main_clk); - if (IS_ERR(c)) - ret = -EINVAL; - oh->_clk = c; + oh->_clk = omap_clk_get_by_name(oh->main_clk); + if (!oh->_clk) + pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", + oh->name, oh->main_clk); + return -EINVAL; - WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n", - oh->main_clk, c->name); + if (!oh->_clk->clkdm) + pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", + oh->main_clk, oh->_clk->name); return ret; } @@ -432,7 +430,6 @@ static int _init_main_clk(struct omap_hwmod *oh) */ static int _init_interface_clks(struct omap_hwmod *oh) { - struct omap_hwmod_ocp_if *os; struct clk *c; int i; int ret = 0; @@ -440,14 +437,16 @@ static int _init_interface_clks(struct omap_hwmod *oh) if (oh->slaves_cnt == 0) return 0; - for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os = oh->slaves[i]; + if (!os->clk) continue; c = omap_clk_get_by_name(os->clk); - WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get " - "interface_clk %s\n", oh->name, os->clk); - if (IS_ERR(c)) + if (!c) + pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", + oh->name, os->clk); ret = -EINVAL; os->_clk = c; } @@ -471,9 +470,9 @@ static int _init_opt_clks(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { c = omap_clk_get_by_name(oc->clk); - WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get opt_clk " - "%s\n", oh->name, oc->clk); - if (IS_ERR(c)) + if (!c) + pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", + oh->name, oc->clk); ret = -EINVAL; oc->_clk = c; } @@ -490,19 +489,19 @@ static int _init_opt_clks(struct omap_hwmod *oh) */ static int _enable_clocks(struct omap_hwmod *oh) { - struct omap_hwmod_ocp_if *os; int i; pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); - if (oh->_clk && !IS_ERR(oh->_clk)) + if (oh->_clk) clk_enable(oh->_clk); if (oh->slaves_cnt > 0) { - for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os = oh->slaves[i]; struct clk *c = os->_clk; - if (c && !IS_ERR(c) && (os->flags & OCPIF_SWSUP_IDLE)) + if (c && (os->flags & OCPIF_SWSUP_IDLE)) clk_enable(c); } } @@ -520,19 +519,19 @@ static int _enable_clocks(struct omap_hwmod *oh) */ static int _disable_clocks(struct omap_hwmod *oh) { - struct omap_hwmod_ocp_if *os; int i; pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); - if (oh->_clk && !IS_ERR(oh->_clk)) + if (oh->_clk) clk_disable(oh->_clk); if (oh->slaves_cnt > 0) { - for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os = oh->slaves[i]; struct clk *c = os->_clk; - if (c && !IS_ERR(c) && (os->flags & OCPIF_SWSUP_IDLE)) + if (c && (os->flags & OCPIF_SWSUP_IDLE)) clk_disable(c); } } @@ -551,14 +550,15 @@ static int _disable_clocks(struct omap_hwmod *oh) */ static int _find_mpu_port_index(struct omap_hwmod *oh) { - struct omap_hwmod_ocp_if *os; int i; int found = 0; if (!oh || oh->slaves_cnt == 0) return -EINVAL; - for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os = oh->slaves[i]; + if (os->user & OCP_USER_MPU) { found = 1; break; @@ -593,7 +593,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) if (!oh || oh->slaves_cnt == 0) return NULL; - os = *oh->slaves + index; + os = oh->slaves[index]; for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) { if (mem->flags & ADDR_TYPE_RT) { @@ -781,9 +781,10 @@ static int _init_clocks(struct omap_hwmod *oh) ret |= _init_interface_clks(oh); ret |= _init_opt_clks(oh); - oh->_state = _HWMOD_STATE_CLKS_INITED; + if (!ret) + oh->_state = _HWMOD_STATE_CLKS_INITED; - return ret; + return 0; } /** @@ -806,9 +807,9 @@ static int _wait_target_ready(struct omap_hwmod *oh) if (oh->_int_flags & _HWMOD_NO_MPU_PORT) return 0; - os = *oh->slaves + oh->_mpu_port_index; + os = oh->slaves[oh->_mpu_port_index]; - if (!(os->flags & OCPIF_HAS_IDLEST)) + if (oh->flags & HWMOD_NO_IDLEST) return 0; /* XXX check module SIDLEMODE */ @@ -819,11 +820,8 @@ static int _wait_target_ready(struct omap_hwmod *oh) ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, oh->prcm.omap2.idlest_reg_id, oh->prcm.omap2.idlest_idle_bit); -#if 0 } else if (cpu_is_omap44xx()) { - ret = omap4_cm_wait_module_ready(oh->prcm.omap4.module_offs, - oh->prcm.omap4.device_offs); -#endif + ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg); } else { BUG(); }; @@ -912,16 +910,21 @@ static int _enable(struct omap_hwmod *oh) _add_initiator_dep(oh, mpu_oh); _enable_clocks(oh); - if (oh->class->sysc) { - if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) - _update_sysc_cache(oh); - _sysc_enable(oh); - } - r = _wait_target_ready(oh); - if (!r) + if (!r) { oh->_state = _HWMOD_STATE_ENABLED; + /* Access the sysconfig only if the target is ready */ + if (oh->class->sysc) { + if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) + _update_sysc_cache(oh); + _sysc_enable(oh); + } + } else { + pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", + oh->name, r); + } + return r; } @@ -998,18 +1001,18 @@ static int _shutdown(struct omap_hwmod *oh) */ static int _setup(struct omap_hwmod *oh) { - struct omap_hwmod_ocp_if *os; - int i; + int i, r; if (!oh) return -EINVAL; /* Set iclk autoidle mode */ if (oh->slaves_cnt > 0) { - for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os = oh->slaves[i]; struct clk *c = os->_clk; - if (!c || IS_ERR(c)) + if (!c) continue; if (os->flags & OCPIF_SWSUP_IDLE) { @@ -1023,7 +1026,12 @@ static int _setup(struct omap_hwmod *oh) oh->_state = _HWMOD_STATE_INITIALIZED; - _enable(oh); + r = _enable(oh); + if (r) { + pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", + oh->name, oh->_state); + return 0; + } if (!(oh->flags & HWMOD_INIT_NO_RESET)) { /* @@ -1431,7 +1439,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh) ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt; for (i = 0; i < oh->slaves_cnt; i++) - ret += (*oh->slaves + i)->addr_cnt; + ret += oh->slaves[i]->addr_cnt; return ret; } @@ -1472,7 +1480,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) for (i = 0; i < oh->slaves_cnt; i++) { struct omap_hwmod_ocp_if *os; - os = *oh->slaves + i; + os = oh->slaves[i]; for (j = 0; j < os->addr_cnt; j++) { (res + r)->start = (os->addr + j)->pa_start; diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index eb7ee2453b2..e5530c51f77 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -125,7 +125,7 @@ static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { /* MPU */ static struct omap_hwmod omap2420_mpu_hwmod = { - .name = "mpu_hwmod", + .name = "mpu", .class = &mpu_hwmod_class, .main_clk = "mpu_ck", .masters = omap2420_mpu_masters, diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 241bd823072..0852d954da4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -127,7 +127,7 @@ static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { /* MPU */ static struct omap_hwmod omap2430_mpu_hwmod = { - .name = "mpu_hwmod", + .name = "mpu", .class = &mpu_hwmod_class, .main_clk = "mpu_ck", .masters = omap2430_mpu_masters, diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index ed608400426..39b0c0eaa37 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -156,7 +156,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { /* MPU */ static struct omap_hwmod omap3xxx_mpu_hwmod = { - .name = "mpu_hwmod", + .name = "mpu", .class = &mpu_hwmod_class, .main_clk = "arm_fck", .masters = omap3xxx_mpu_masters, diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 6cac9817c24..723b44e252f 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -548,6 +548,9 @@ static int option_set(void *data, u64 val) { u32 *option = data; + if (option == &wakeup_timer_milliseconds && val >= 1000) + return -EINVAL; + *option = val; if (option == &enable_off_mode) diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index bd6466a2b03..3de6ece23fc 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -43,6 +43,7 @@ extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); extern u32 wakeup_timer_seconds; +extern u32 wakeup_timer_milliseconds; extern struct omap_dm_timer *gptimer_wakeup; #ifdef CONFIG_PM_DEBUG diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 374299ea7ad..e321281ab6e 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -70,8 +70,8 @@ static int omap2_fclks_active(void) f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); /* Ignore UART clocks. These are handled by UART core (serial.c) */ - f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2); - f2 &= ~OMAP24XX_EN_UART3; + f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); + f2 &= ~OMAP24XX_EN_UART3_MASK; if (f1 | f2) return 1; @@ -107,7 +107,7 @@ static void omap2_enter_full_retention(void) l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); - omap2_gpio_prepare_for_retention(); + omap2_gpio_prepare_for_idle(PWRDM_POWER_RET); if (omap2_pm_debug) { omap2_pm_dump(0, 0, 0); @@ -141,7 +141,7 @@ no_sleep: tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; omap2_pm_dump(0, 1, tmp); } - omap2_gpio_resume_after_retention(); + omap2_gpio_resume_after_idle(); clk_enable(osc_ck); @@ -170,7 +170,7 @@ static int omap2_i2c_active(void) u32 l; l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1); + return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK); } static int sti_console_enabled; @@ -181,13 +181,13 @@ static int omap2_allow_mpu_retention(void) /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 | - OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 | - OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1)) + if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | + OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | + OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) return 0; /* Check for UART3. */ l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); - if (l & OMAP24XX_EN_UART3) + if (l & OMAP24XX_EN_UART3_MASK) return 0; if (sti_console_enabled) return 0; @@ -215,12 +215,12 @@ static void omap2_enter_mpu_retention(void) /* Try to enter MPU retention */ prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | - OMAP_LOGICRETSTATE, + OMAP_LOGICRETSTATE_MASK, MPU_MOD, OMAP2_PM_PWSTCTRL); } else { /* Block MPU retention */ - prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, + prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, OMAP2_PM_PWSTCTRL); only_idle = 1; } @@ -288,7 +288,8 @@ static int omap2_pm_suspend(void) u32 wken_wkup, mir1; wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); - prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN); + wken_wkup &= ~OMAP24XX_EN_GPT1_MASK; + prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); /* Mask GPT1 */ mir1 = omap_readl(0x480fe0a4); @@ -351,7 +352,7 @@ static void __init prcm_setup_regs(void) struct powerdomain *pwrdm; /* Enable autoidle */ - prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD, + prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, OMAP2_PRCM_SYSCONFIG_OFFSET); /* @@ -390,53 +391,54 @@ static void __init prcm_setup_regs(void) clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); /* Enable clock autoidle for all domains */ - cm_write_mod_reg(OMAP24XX_AUTO_CAM | - OMAP24XX_AUTO_MAILBOXES | - OMAP24XX_AUTO_WDT4 | - OMAP2420_AUTO_WDT3 | - OMAP24XX_AUTO_MSPRO | - OMAP2420_AUTO_MMC | - OMAP24XX_AUTO_FAC | - OMAP2420_AUTO_EAC | - OMAP24XX_AUTO_HDQ | - OMAP24XX_AUTO_UART2 | - OMAP24XX_AUTO_UART1 | - OMAP24XX_AUTO_I2C2 | - OMAP24XX_AUTO_I2C1 | - OMAP24XX_AUTO_MCSPI2 | - OMAP24XX_AUTO_MCSPI1 | - OMAP24XX_AUTO_MCBSP2 | - OMAP24XX_AUTO_MCBSP1 | - OMAP24XX_AUTO_GPT12 | - OMAP24XX_AUTO_GPT11 | - OMAP24XX_AUTO_GPT10 | - OMAP24XX_AUTO_GPT9 | - OMAP24XX_AUTO_GPT8 | - OMAP24XX_AUTO_GPT7 | - OMAP24XX_AUTO_GPT6 | - OMAP24XX_AUTO_GPT5 | - OMAP24XX_AUTO_GPT4 | - OMAP24XX_AUTO_GPT3 | - OMAP24XX_AUTO_GPT2 | - OMAP2420_AUTO_VLYNQ | - OMAP24XX_AUTO_DSS, + cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | + OMAP24XX_AUTO_MAILBOXES_MASK | + OMAP24XX_AUTO_WDT4_MASK | + OMAP2420_AUTO_WDT3_MASK | + OMAP24XX_AUTO_MSPRO_MASK | + OMAP2420_AUTO_MMC_MASK | + OMAP24XX_AUTO_FAC_MASK | + OMAP2420_AUTO_EAC_MASK | + OMAP24XX_AUTO_HDQ_MASK | + OMAP24XX_AUTO_UART2_MASK | + OMAP24XX_AUTO_UART1_MASK | + OMAP24XX_AUTO_I2C2_MASK | + OMAP24XX_AUTO_I2C1_MASK | + OMAP24XX_AUTO_MCSPI2_MASK | + OMAP24XX_AUTO_MCSPI1_MASK | + OMAP24XX_AUTO_MCBSP2_MASK | + OMAP24XX_AUTO_MCBSP1_MASK | + OMAP24XX_AUTO_GPT12_MASK | + OMAP24XX_AUTO_GPT11_MASK | + OMAP24XX_AUTO_GPT10_MASK | + OMAP24XX_AUTO_GPT9_MASK | + OMAP24XX_AUTO_GPT8_MASK | + OMAP24XX_AUTO_GPT7_MASK | + OMAP24XX_AUTO_GPT6_MASK | + OMAP24XX_AUTO_GPT5_MASK | + OMAP24XX_AUTO_GPT4_MASK | + OMAP24XX_AUTO_GPT3_MASK | + OMAP24XX_AUTO_GPT2_MASK | + OMAP2420_AUTO_VLYNQ_MASK | + OMAP24XX_AUTO_DSS_MASK, CORE_MOD, CM_AUTOIDLE1); - cm_write_mod_reg(OMAP24XX_AUTO_UART3 | - OMAP24XX_AUTO_SSI | - OMAP24XX_AUTO_USB, + cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | + OMAP24XX_AUTO_SSI_MASK | + OMAP24XX_AUTO_USB_MASK, CORE_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(OMAP24XX_AUTO_SDRC | - OMAP24XX_AUTO_GPMC | - OMAP24XX_AUTO_SDMA, + cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | + OMAP24XX_AUTO_GPMC_MASK | + OMAP24XX_AUTO_SDMA_MASK, CORE_MOD, CM_AUTOIDLE3); - cm_write_mod_reg(OMAP24XX_AUTO_PKA | - OMAP24XX_AUTO_AES | - OMAP24XX_AUTO_RNG | - OMAP24XX_AUTO_SHA | - OMAP24XX_AUTO_DES, + cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | + OMAP24XX_AUTO_AES_MASK | + OMAP24XX_AUTO_RNG_MASK | + OMAP24XX_AUTO_SHA_MASK | + OMAP24XX_AUTO_DES_MASK, CORE_MOD, OMAP24XX_CM_AUTOIDLE4); - cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE); + cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, + CM_AUTOIDLE); /* Put DPLL and both APLLs into autoidle mode */ cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | @@ -444,12 +446,12 @@ static void __init prcm_setup_regs(void) (0x03 << OMAP24XX_AUTO_54M_SHIFT), PLL_MOD, CM_AUTOIDLE); - cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL | - OMAP24XX_AUTO_WDT1 | - OMAP24XX_AUTO_MPU_WDT | - OMAP24XX_AUTO_GPIOS | - OMAP24XX_AUTO_32KSYNC | - OMAP24XX_AUTO_GPT1, + cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | + OMAP24XX_AUTO_WDT1_MASK | + OMAP24XX_AUTO_MPU_WDT_MASK | + OMAP24XX_AUTO_GPIOS_MASK | + OMAP24XX_AUTO_32KSYNC_MASK | + OMAP24XX_AUTO_GPT1_MASK, WKUP_MOD, CM_AUTOIDLE); /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk @@ -460,15 +462,15 @@ static void __init prcm_setup_regs(void) /* Configure automatic voltage transition */ prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTSETUP_OFFSET); - prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT | + prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | - OMAP24XX_MEMRETCTRL | + OMAP24XX_MEMRETCTRL_MASK | (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); /* Enable wake-up events */ - prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1, + prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, WKUP_MOD, PM_WKEN); } diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index ea0000bc535..2e967716cc3 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -58,6 +58,7 @@ u32 enable_off_mode; u32 sleep_while_idle; u32 wakeup_timer_seconds; +u32 wakeup_timer_milliseconds; struct power_state { struct powerdomain *pwrdm; @@ -93,19 +94,20 @@ static void omap3_enable_io_chain(void) int timeout = 0; if (omap_rev() >= OMAP3430_REV_ES3_1) { - prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); + prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, + PM_WKEN); /* Do a readback to assure write has been done */ prm_read_mod_reg(WKUP_MOD, PM_WKEN); while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) & - OMAP3430_ST_IO_CHAIN)) { + OMAP3430_ST_IO_CHAIN_MASK)) { timeout++; if (timeout > 1000) { printk(KERN_ERR "Wake up daisy chain " "activation failed.\n"); return; } - prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, + prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD, PM_WKST); } } @@ -114,7 +116,8 @@ static void omap3_enable_io_chain(void) static void omap3_disable_io_chain(void) { if (omap_rev() >= OMAP3430_REV_ES3_1) - prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); + prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, + PM_WKEN); } static void omap3_core_save_context(void) @@ -267,14 +270,18 @@ static int _prcm_int_handle_wakeup(void) */ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) { - u32 irqstatus_mpu; + u32 irqenable_mpu, irqstatus_mpu; int c = 0; - do { - irqstatus_mpu = prm_read_mod_reg(OCP_MOD, - OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + irqenable_mpu = prm_read_mod_reg(OCP_MOD, + OMAP3_PRM_IRQENABLE_MPU_OFFSET); + irqstatus_mpu = prm_read_mod_reg(OCP_MOD, + OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + irqstatus_mpu &= irqenable_mpu; - if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { + do { + if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | + OMAP3430_IO_ST_MASK)) { c = _prcm_int_handle_wakeup(); /* @@ -292,7 +299,11 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) prm_write_mod_reg(irqstatus_mpu, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); + irqstatus_mpu = prm_read_mod_reg(OCP_MOD, + OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + irqstatus_mpu &= irqenable_mpu; + + } while (irqstatus_mpu); return IRQ_HANDLED; } @@ -371,12 +382,19 @@ void omap_sram_idle(void) if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); - /* PER */ + /* Enable IO-PAD and IO-CHAIN wakeups */ per_next_state = pwrdm_read_next_pwrst(per_pwrdm); core_next_state = pwrdm_read_next_pwrst(core_pwrdm); + if (per_next_state < PWRDM_POWER_ON || + core_next_state < PWRDM_POWER_ON) { + prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); + omap3_enable_io_chain(); + } + + /* PER */ if (per_next_state < PWRDM_POWER_ON) { omap_uart_prepare_idle(2); - omap2_gpio_prepare_for_retention(); + omap2_gpio_prepare_for_idle(per_next_state); if (per_next_state == PWRDM_POWER_OFF) { if (core_next_state == PWRDM_POWER_ON) { per_next_state = PWRDM_POWER_RET; @@ -398,10 +416,8 @@ void omap_sram_idle(void) omap3_core_save_context(); omap3_prcm_save_context(); } - /* Enable IO-PAD and IO-CHAIN wakeups */ - prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); - omap3_enable_io_chain(); } + omap3_intc_prepare_idle(); /* @@ -445,7 +461,7 @@ void omap_sram_idle(void) omap_uart_resume_idle(0); omap_uart_resume_idle(1); if (core_next_state == PWRDM_POWER_OFF) - prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF, + prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET); } @@ -454,9 +470,9 @@ void omap_sram_idle(void) /* PER */ if (per_next_state < PWRDM_POWER_ON) { per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); + omap2_gpio_resume_after_idle(); if (per_prev_state == PWRDM_POWER_OFF) omap3_per_restore_context(); - omap2_gpio_resume_after_retention(); omap_uart_resume_idle(2); if (per_state_modified) pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); @@ -464,7 +480,7 @@ void omap_sram_idle(void) /* Disable IO-PAD and IO-CHAIN wakeup */ if (core_next_state < PWRDM_POWER_ON) { - prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); + prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_disable_io_chain(); } @@ -548,20 +564,21 @@ out: #ifdef CONFIG_SUSPEND static suspend_state_t suspend_state; -static void omap2_pm_wakeup_on_timer(u32 seconds) +static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds) { u32 tick_rate, cycles; - if (!seconds) + if (!seconds && !milliseconds) return; tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); - cycles = tick_rate * seconds; + cycles = tick_rate * seconds + tick_rate * milliseconds / 1000; omap_dm_timer_stop(gptimer_wakeup); omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); - pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n", - seconds, cycles, tick_rate); + pr_info("PM: Resume timer in %u.%03u secs" + " (%d ticks at %d ticks/sec.)\n", + seconds, milliseconds, cycles, tick_rate); } static int omap3_pm_prepare(void) @@ -575,8 +592,9 @@ static int omap3_pm_suspend(void) struct power_state *pwrst; int state, ret = 0; - if (wakeup_timer_seconds) - omap2_pm_wakeup_on_timer(wakeup_timer_seconds); + if (wakeup_timer_seconds || wakeup_timer_milliseconds) + omap2_pm_wakeup_on_timer(wakeup_timer_seconds, + wakeup_timer_milliseconds); /* Read current next_pwrsts */ list_for_each_entry(pwrst, &pwrst_list, node) @@ -683,9 +701,9 @@ static void __init omap3_iva_idle(void) return; /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2 | - OMAP3430_RST2_IVA2 | - OMAP3430_RST3_IVA2, + prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | + OMAP3430_RST2_IVA2_MASK | + OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Enable IVA2 clock */ @@ -703,9 +721,9 @@ static void __init omap3_iva_idle(void) cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2 | - OMAP3430_RST2_IVA2 | - OMAP3430_RST3_IVA2, + prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | + OMAP3430_RST2_IVA2_MASK | + OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); } @@ -727,8 +745,8 @@ static void __init omap3_d2d_idle(void) omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); /* reset modem */ - prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | - OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, + prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | + OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, CORE_MOD, OMAP2_RM_RSTCTRL); prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); } @@ -754,102 +772,102 @@ static void __init prcm_setup_regs(void) * Note that in the long run this should be done by clockfw */ cm_write_mod_reg( - OMAP3430_AUTO_MODEM | - OMAP3430ES2_AUTO_MMC3 | - OMAP3430ES2_AUTO_ICR | - OMAP3430_AUTO_AES2 | - OMAP3430_AUTO_SHA12 | - OMAP3430_AUTO_DES2 | - OMAP3430_AUTO_MMC2 | - OMAP3430_AUTO_MMC1 | - OMAP3430_AUTO_MSPRO | - OMAP3430_AUTO_HDQ | - OMAP3430_AUTO_MCSPI4 | - OMAP3430_AUTO_MCSPI3 | - OMAP3430_AUTO_MCSPI2 | - OMAP3430_AUTO_MCSPI1 | - OMAP3430_AUTO_I2C3 | - OMAP3430_AUTO_I2C2 | - OMAP3430_AUTO_I2C1 | - OMAP3430_AUTO_UART2 | - OMAP3430_AUTO_UART1 | - OMAP3430_AUTO_GPT11 | - OMAP3430_AUTO_GPT10 | - OMAP3430_AUTO_MCBSP5 | - OMAP3430_AUTO_MCBSP1 | - OMAP3430ES1_AUTO_FAC | /* This is es1 only */ - OMAP3430_AUTO_MAILBOXES | - OMAP3430_AUTO_OMAPCTRL | - OMAP3430ES1_AUTO_FSHOSTUSB | - OMAP3430_AUTO_HSOTGUSB | - OMAP3430_AUTO_SAD2D | - OMAP3430_AUTO_SSI, + OMAP3430_AUTO_MODEM_MASK | + OMAP3430ES2_AUTO_MMC3_MASK | + OMAP3430ES2_AUTO_ICR_MASK | + OMAP3430_AUTO_AES2_MASK | + OMAP3430_AUTO_SHA12_MASK | + OMAP3430_AUTO_DES2_MASK | + OMAP3430_AUTO_MMC2_MASK | + OMAP3430_AUTO_MMC1_MASK | + OMAP3430_AUTO_MSPRO_MASK | + OMAP3430_AUTO_HDQ_MASK | + OMAP3430_AUTO_MCSPI4_MASK | + OMAP3430_AUTO_MCSPI3_MASK | + OMAP3430_AUTO_MCSPI2_MASK | + OMAP3430_AUTO_MCSPI1_MASK | + OMAP3430_AUTO_I2C3_MASK | + OMAP3430_AUTO_I2C2_MASK | + OMAP3430_AUTO_I2C1_MASK | + OMAP3430_AUTO_UART2_MASK | + OMAP3430_AUTO_UART1_MASK | + OMAP3430_AUTO_GPT11_MASK | + OMAP3430_AUTO_GPT10_MASK | + OMAP3430_AUTO_MCBSP5_MASK | + OMAP3430_AUTO_MCBSP1_MASK | + OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */ + OMAP3430_AUTO_MAILBOXES_MASK | + OMAP3430_AUTO_OMAPCTRL_MASK | + OMAP3430ES1_AUTO_FSHOSTUSB_MASK | + OMAP3430_AUTO_HSOTGUSB_MASK | + OMAP3430_AUTO_SAD2D_MASK | + OMAP3430_AUTO_SSI_MASK, CORE_MOD, CM_AUTOIDLE1); cm_write_mod_reg( - OMAP3430_AUTO_PKA | - OMAP3430_AUTO_AES1 | - OMAP3430_AUTO_RNG | - OMAP3430_AUTO_SHA11 | - OMAP3430_AUTO_DES1, + OMAP3430_AUTO_PKA_MASK | + OMAP3430_AUTO_AES1_MASK | + OMAP3430_AUTO_RNG_MASK | + OMAP3430_AUTO_SHA11_MASK | + OMAP3430_AUTO_DES1_MASK, CORE_MOD, CM_AUTOIDLE2); if (omap_rev() > OMAP3430_REV_ES1_0) { cm_write_mod_reg( - OMAP3430_AUTO_MAD2D | - OMAP3430ES2_AUTO_USBTLL, + OMAP3430_AUTO_MAD2D_MASK | + OMAP3430ES2_AUTO_USBTLL_MASK, CORE_MOD, CM_AUTOIDLE3); } cm_write_mod_reg( - OMAP3430_AUTO_WDT2 | - OMAP3430_AUTO_WDT1 | - OMAP3430_AUTO_GPIO1 | - OMAP3430_AUTO_32KSYNC | - OMAP3430_AUTO_GPT12 | - OMAP3430_AUTO_GPT1 , + OMAP3430_AUTO_WDT2_MASK | + OMAP3430_AUTO_WDT1_MASK | + OMAP3430_AUTO_GPIO1_MASK | + OMAP3430_AUTO_32KSYNC_MASK | + OMAP3430_AUTO_GPT12_MASK | + OMAP3430_AUTO_GPT1_MASK, WKUP_MOD, CM_AUTOIDLE); cm_write_mod_reg( - OMAP3430_AUTO_DSS, + OMAP3430_AUTO_DSS_MASK, OMAP3430_DSS_MOD, CM_AUTOIDLE); cm_write_mod_reg( - OMAP3430_AUTO_CAM, + OMAP3430_AUTO_CAM_MASK, OMAP3430_CAM_MOD, CM_AUTOIDLE); cm_write_mod_reg( - OMAP3430_AUTO_GPIO6 | - OMAP3430_AUTO_GPIO5 | - OMAP3430_AUTO_GPIO4 | - OMAP3430_AUTO_GPIO3 | - OMAP3430_AUTO_GPIO2 | - OMAP3430_AUTO_WDT3 | - OMAP3430_AUTO_UART3 | - OMAP3430_AUTO_GPT9 | - OMAP3430_AUTO_GPT8 | - OMAP3430_AUTO_GPT7 | - OMAP3430_AUTO_GPT6 | - OMAP3430_AUTO_GPT5 | - OMAP3430_AUTO_GPT4 | - OMAP3430_AUTO_GPT3 | - OMAP3430_AUTO_GPT2 | - OMAP3430_AUTO_MCBSP4 | - OMAP3430_AUTO_MCBSP3 | - OMAP3430_AUTO_MCBSP2, + OMAP3430_AUTO_GPIO6_MASK | + OMAP3430_AUTO_GPIO5_MASK | + OMAP3430_AUTO_GPIO4_MASK | + OMAP3430_AUTO_GPIO3_MASK | + OMAP3430_AUTO_GPIO2_MASK | + OMAP3430_AUTO_WDT3_MASK | + OMAP3430_AUTO_UART3_MASK | + OMAP3430_AUTO_GPT9_MASK | + OMAP3430_AUTO_GPT8_MASK | + OMAP3430_AUTO_GPT7_MASK | + OMAP3430_AUTO_GPT6_MASK | + OMAP3430_AUTO_GPT5_MASK | + OMAP3430_AUTO_GPT4_MASK | + OMAP3430_AUTO_GPT3_MASK | + OMAP3430_AUTO_GPT2_MASK | + OMAP3430_AUTO_MCBSP4_MASK | + OMAP3430_AUTO_MCBSP3_MASK | + OMAP3430_AUTO_MCBSP2_MASK, OMAP3430_PER_MOD, CM_AUTOIDLE); if (omap_rev() > OMAP3430_REV_ES1_0) { cm_write_mod_reg( - OMAP3430ES2_AUTO_USBHOST, + OMAP3430ES2_AUTO_USBHOST_MASK, OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); } - omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG); + omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); /* * Set all plls to autoidle. This is needed until autoidle is @@ -879,35 +897,40 @@ static void __init prcm_setup_regs(void) OMAP3_PRM_CLKSRC_CTRL_OFFSET); /* setup wakup source */ - prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | - OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, + prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | + OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, WKUP_MOD, PM_WKEN); /* No need to write EN_IO, that is always enabled */ - prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | - OMAP3430_EN_GPT12, + prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | + OMAP3430_GRPSEL_GPT1_MASK | + OMAP3430_GRPSEL_GPT12_MASK, WKUP_MOD, OMAP3430_PM_MPUGRPSEL); /* For some reason IO doesn't generate wakeup event even if * it is selected to mpu wakeup goup */ - prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, + prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); /* Enable PM_WKEN to support DSS LPR */ - prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS, + prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, OMAP3430_DSS_MOD, PM_WKEN); /* Enable wakeups in PER */ - prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | - OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | - OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 | - OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | - OMAP3430_EN_MCBSP4, + prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | + OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | + OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | + OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | + OMAP3430_EN_MCBSP4_MASK, OMAP3430_PER_MOD, PM_WKEN); /* and allow them to wake up MPU */ - prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | - OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | - OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 | - OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | - OMAP3430_EN_MCBSP4, + prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK | + OMAP3430_GRPSEL_GPIO3_MASK | + OMAP3430_GRPSEL_GPIO4_MASK | + OMAP3430_GRPSEL_GPIO5_MASK | + OMAP3430_GRPSEL_GPIO6_MASK | + OMAP3430_GRPSEL_UART3_MASK | + OMAP3430_GRPSEL_MCBSP2_MASK | + OMAP3430_GRPSEL_MCBSP3_MASK | + OMAP3430_GRPSEL_MCBSP4_MASK, OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); /* Don't attach IVA interrupts */ @@ -1080,14 +1103,6 @@ static int __init omap3_pm_init(void) omap3_idle_init(); clkdm_add_wkdep(neon_clkdm, mpu_clkdm); - /* - * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for - * IO-pad wakeup. Otherwise it will unnecessarily waste power - * waking up PER with every CORE wakeup - see - * http://marc.info/?l=linux-omap&m=121852150710062&w=2 - */ - clkdm_add_wkdep(per_clkdm, core_clkdm); - if (omap_type() != OMAP2_DEVICE_TYPE_GP) { omap3_secure_ram_storage = kmalloc(0x803F, GFP_KERNEL); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index ebfce7d1a5d..a2904aa7065 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -5,8 +5,8 @@ * Copyright (C) 2007-2009 Nokia Corporation * * Written by Paul Walmsley - * * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> + * State counting code by Tero Kristo <tero.kristo@nokia.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -64,10 +64,10 @@ static u16 pwrstst_reg_offs; #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ -#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE -#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE -#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE -#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE +#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK +#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK +#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK +#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK /* OMAP3 and OMAP4 Memory Status bits */ @@ -511,6 +511,8 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) */ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) { + u32 v; + if (!pwrdm) return -EINVAL; @@ -526,9 +528,9 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) * but the type of value returned is the same for each * powerdomain. */ - prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE, - (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)), - pwrdm->prcm_offs, pwrstctrl_reg_offs); + v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); + prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, + pwrdm->prcm_offs, pwrstctrl_reg_offs); return 0; } @@ -676,8 +678,8 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, - pwrstst_reg_offs, OMAP3430_LOGICSTATEST); + return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstst_reg_offs, + OMAP3430_LOGICSTATEST_MASK); } /** @@ -700,7 +702,7 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) * powerdomain. */ return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, - OMAP3430_LASTLOGICSTATEENTERED); + OMAP3430_LASTLOGICSTATEENTERED_MASK); } /** @@ -723,7 +725,7 @@ int pwrdm_read_logic_retst(struct powerdomain *pwrdm) * powerdomain. */ return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs, - OMAP3430_LOGICSTATEST); + OMAP3430_LOGICSTATEST_MASK); } /** @@ -978,6 +980,34 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) } /** + * pwrdm_set_lowpwrstchange - Request a low power state change + * @pwrdm: struct powerdomain * + * + * Allows a powerdomain to transtion to a lower power sleep state + * from an existing sleep state without waking up the powerdomain. + * Returns -EINVAL if the powerdomain pointer is null or if the + * powerdomain does not support LOWPOWERSTATECHANGE, or returns 0 + * upon success. + */ +int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) +{ + if (!pwrdm) + return -EINVAL; + + if (!(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) + return -EINVAL; + + pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n", + pwrdm->name); + + prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, + (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), + pwrdm->prcm_offs, pwrstctrl_reg_offs); + + return 0; +} + +/** * pwrdm_wait_transition - wait for powerdomain power transition to finish * @pwrdm: struct powerdomain * to wait for * @@ -1002,7 +1032,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) /* XXX Is this udelay() value meaningful? */ while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) & - OMAP_INTRANSITION) && + OMAP_INTRANSITION_MASK) && (c++ < PWRDM_TRANSITION_BAILOUT)) udelay(1); diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h index c1015147d57..c7219513472 100644 --- a/arch/arm/mach-omap2/powerdomains44xx.h +++ b/arch/arm/mach-omap2/powerdomains44xx.h @@ -1,12 +1,12 @@ /* * OMAP4 Power domains framework * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation * * Abhijit Pagare (abhijitpagare@ti.com) * Benoit Cousson (b-cousson@ti.com) - * Paul Walmsley + * Paul Walmsley (paul@pwsan.com) * * This file is automatically generated from the OMAP hardware databases. * We respectfully ask that any modifications to this file be coordinated @@ -54,6 +54,7 @@ static struct powerdomain core_44xx_pwrdm = { [3] = PWRDM_POWER_ON, /* ducati_l2ram */ [4] = PWRDM_POWER_ON, /* ducati_unicache */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* gfx_44xx_pwrdm: 3D accelerator power domain */ @@ -69,6 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = { .pwrsts_mem_on = { [0] = PWRDM_POWER_ON, /* gfx_mem */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* abe_44xx_pwrdm: Audio back end power domain */ @@ -87,6 +89,7 @@ static struct powerdomain abe_44xx_pwrdm = { [0] = PWRDM_POWER_ON, /* aessmem */ [1] = PWRDM_POWER_ON, /* periphmem */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* dss_44xx_pwrdm: Display subsystem power domain */ @@ -103,6 +106,7 @@ static struct powerdomain dss_44xx_pwrdm = { .pwrsts_mem_on = { [0] = PWRDM_POWER_ON, /* dss_mem */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* tesla_44xx_pwrdm: Tesla processor power domain */ @@ -123,6 +127,7 @@ static struct powerdomain tesla_44xx_pwrdm = { [1] = PWRDM_POWER_ON, /* tesla_l1 */ [2] = PWRDM_POWER_ON, /* tesla_l2 */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* wkup_44xx_pwrdm: Wake-up power domain */ @@ -130,7 +135,7 @@ static struct powerdomain wkup_44xx_pwrdm = { .name = "wkup_pwrdm", .prcm_offs = OMAP4430_PRM_WKUP_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRDM_POWER_ON, + .pwrsts = PWRSTS_ON, .banks = 1, .pwrsts_mem_ret = { [0] = PWRDM_POWER_OFF, /* wkup_bank */ @@ -143,7 +148,7 @@ static struct powerdomain wkup_44xx_pwrdm = { /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ static struct powerdomain cpu0_44xx_pwrdm = { .name = "cpu0_pwrdm", - .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, + .prcm_offs = OMAP4430_PRCM_MPU_CPU0_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, @@ -159,7 +164,7 @@ static struct powerdomain cpu0_44xx_pwrdm = { /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ static struct powerdomain cpu1_44xx_pwrdm = { .name = "cpu1_pwrdm", - .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, + .prcm_offs = OMAP4430_PRCM_MPU_CPU1_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, @@ -227,6 +232,7 @@ static struct powerdomain ivahd_44xx_pwrdm = { [2] = PWRDM_POWER_ON, /* tcm1_mem */ [3] = PWRDM_POWER_ON, /* tcm2_mem */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* cam_44xx_pwrdm: Camera subsystem power domain */ @@ -242,6 +248,7 @@ static struct powerdomain cam_44xx_pwrdm = { .pwrsts_mem_on = { [0] = PWRDM_POWER_ON, /* cam_mem */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ @@ -258,6 +265,7 @@ static struct powerdomain l3init_44xx_pwrdm = { .pwrsts_mem_on = { [0] = PWRDM_POWER_ON, /* l3init_bank1 */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* l4per_44xx_pwrdm: Target peripherals power domain */ @@ -276,6 +284,7 @@ static struct powerdomain l4per_44xx_pwrdm = { [0] = PWRDM_POWER_ON, /* nonretained_bank */ [1] = PWRDM_POWER_ON, /* retained_bank */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* @@ -286,7 +295,7 @@ static struct powerdomain always_on_core_44xx_pwrdm = { .name = "always_on_core_pwrdm", .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRDM_POWER_ON, + .pwrsts = PWRSTS_ON, }; /* cefuse_44xx_pwrdm: Customer efuse controller power domain */ diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 90f603d434c..995b7edbf18 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -112,83 +112,75 @@ #define OMAP4430_SCRM_SCRM_MOD 0x0000 -/* CHIRONSS instances */ +/* PRCM_MPU instances */ -#define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD 0x0000 -#define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD 0x0200 -#define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400 -#define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800 - -/* Base Addresses for the OMAP4 */ - -#define OMAP4430_CM1_BASE 0x4a004000 -#define OMAP4430_CM2_BASE 0x4a008000 -#define OMAP4430_PRM_BASE 0x4a306000 -#define OMAP4430_SCRM_BASE 0x4a30a000 -#define OMAP4430_CHIRONSS_BASE 0x48243000 +#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD 0x0000 +#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200 +#define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400 +#define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800 /* 24XX register bits shared between CM & PRM registers */ /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ #define OMAP2420_EN_MMC_SHIFT 26 -#define OMAP2420_EN_MMC (1 << 26) +#define OMAP2420_EN_MMC_MASK (1 << 26) #define OMAP24XX_EN_UART2_SHIFT 22 -#define OMAP24XX_EN_UART2 (1 << 22) +#define OMAP24XX_EN_UART2_MASK (1 << 22) #define OMAP24XX_EN_UART1_SHIFT 21 -#define OMAP24XX_EN_UART1 (1 << 21) +#define OMAP24XX_EN_UART1_MASK (1 << 21) #define OMAP24XX_EN_MCSPI2_SHIFT 18 -#define OMAP24XX_EN_MCSPI2 (1 << 18) +#define OMAP24XX_EN_MCSPI2_MASK (1 << 18) #define OMAP24XX_EN_MCSPI1_SHIFT 17 -#define OMAP24XX_EN_MCSPI1 (1 << 17) +#define OMAP24XX_EN_MCSPI1_MASK (1 << 17) #define OMAP24XX_EN_MCBSP2_SHIFT 16 -#define OMAP24XX_EN_MCBSP2 (1 << 16) +#define OMAP24XX_EN_MCBSP2_MASK (1 << 16) #define OMAP24XX_EN_MCBSP1_SHIFT 15 -#define OMAP24XX_EN_MCBSP1 (1 << 15) +#define OMAP24XX_EN_MCBSP1_MASK (1 << 15) #define OMAP24XX_EN_GPT12_SHIFT 14 -#define OMAP24XX_EN_GPT12 (1 << 14) +#define OMAP24XX_EN_GPT12_MASK (1 << 14) #define OMAP24XX_EN_GPT11_SHIFT 13 -#define OMAP24XX_EN_GPT11 (1 << 13) +#define OMAP24XX_EN_GPT11_MASK (1 << 13) #define OMAP24XX_EN_GPT10_SHIFT 12 -#define OMAP24XX_EN_GPT10 (1 << 12) +#define OMAP24XX_EN_GPT10_MASK (1 << 12) #define OMAP24XX_EN_GPT9_SHIFT 11 -#define OMAP24XX_EN_GPT9 (1 << 11) +#define OMAP24XX_EN_GPT9_MASK (1 << 11) #define OMAP24XX_EN_GPT8_SHIFT 10 -#define OMAP24XX_EN_GPT8 (1 << 10) +#define OMAP24XX_EN_GPT8_MASK (1 << 10) #define OMAP24XX_EN_GPT7_SHIFT 9 -#define OMAP24XX_EN_GPT7 (1 << 9) +#define OMAP24XX_EN_GPT7_MASK (1 << 9) #define OMAP24XX_EN_GPT6_SHIFT 8 -#define OMAP24XX_EN_GPT6 (1 << 8) +#define OMAP24XX_EN_GPT6_MASK (1 << 8) #define OMAP24XX_EN_GPT5_SHIFT 7 -#define OMAP24XX_EN_GPT5 (1 << 7) +#define OMAP24XX_EN_GPT5_MASK (1 << 7) #define OMAP24XX_EN_GPT4_SHIFT 6 -#define OMAP24XX_EN_GPT4 (1 << 6) +#define OMAP24XX_EN_GPT4_MASK (1 << 6) #define OMAP24XX_EN_GPT3_SHIFT 5 -#define OMAP24XX_EN_GPT3 (1 << 5) +#define OMAP24XX_EN_GPT3_MASK (1 << 5) #define OMAP24XX_EN_GPT2_SHIFT 4 -#define OMAP24XX_EN_GPT2 (1 << 4) +#define OMAP24XX_EN_GPT2_MASK (1 << 4) #define OMAP2420_EN_VLYNQ_SHIFT 3 -#define OMAP2420_EN_VLYNQ (1 << 3) +#define OMAP2420_EN_VLYNQ_MASK (1 << 3) /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ #define OMAP2430_EN_GPIO5_SHIFT 10 -#define OMAP2430_EN_GPIO5 (1 << 10) +#define OMAP2430_EN_GPIO5_MASK (1 << 10) #define OMAP2430_EN_MCSPI3_SHIFT 9 -#define OMAP2430_EN_MCSPI3 (1 << 9) +#define OMAP2430_EN_MCSPI3_MASK (1 << 9) #define OMAP2430_EN_MMCHS2_SHIFT 8 -#define OMAP2430_EN_MMCHS2 (1 << 8) +#define OMAP2430_EN_MMCHS2_MASK (1 << 8) #define OMAP2430_EN_MMCHS1_SHIFT 7 -#define OMAP2430_EN_MMCHS1 (1 << 7) +#define OMAP2430_EN_MMCHS1_MASK (1 << 7) #define OMAP24XX_EN_UART3_SHIFT 2 -#define OMAP24XX_EN_UART3 (1 << 2) +#define OMAP24XX_EN_UART3_MASK (1 << 2) #define OMAP24XX_EN_USB_SHIFT 0 -#define OMAP24XX_EN_USB (1 << 0) +#define OMAP24XX_EN_USB_MASK (1 << 0) /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ #define OMAP2430_EN_MDM_INTC_SHIFT 11 -#define OMAP2430_EN_MDM_INTC (1 << 11) +#define OMAP2430_EN_MDM_INTC_MASK (1 << 11) #define OMAP2430_EN_USBHS_SHIFT 6 -#define OMAP2430_EN_USBHS (1 << 6) +#define OMAP2430_EN_USBHS_MASK (1 << 6) /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ #define OMAP2420_ST_MMC_SHIFT 26 @@ -246,9 +238,9 @@ /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ #define OMAP24XX_EN_GPIOS_SHIFT 2 -#define OMAP24XX_EN_GPIOS (1 << 2) +#define OMAP24XX_EN_GPIOS_MASK (1 << 2) #define OMAP24XX_EN_GPT1_SHIFT 0 -#define OMAP24XX_EN_GPT1 (1 << 0) +#define OMAP24XX_EN_GPT1_MASK (1 << 0) /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ #define OMAP24XX_ST_GPIOS_SHIFT (1 << 2) @@ -267,47 +259,47 @@ #define OMAP3430_REV_MASK (0xff << 0) /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ -#define OMAP3430_AUTOIDLE (1 << 0) +#define OMAP3430_AUTOIDLE_MASK (1 << 0) /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ -#define OMAP3430_EN_MMC2 (1 << 25) +#define OMAP3430_EN_MMC2_MASK (1 << 25) #define OMAP3430_EN_MMC2_SHIFT 25 -#define OMAP3430_EN_MMC1 (1 << 24) +#define OMAP3430_EN_MMC1_MASK (1 << 24) #define OMAP3430_EN_MMC1_SHIFT 24 -#define OMAP3430_EN_MCSPI4 (1 << 21) +#define OMAP3430_EN_MCSPI4_MASK (1 << 21) #define OMAP3430_EN_MCSPI4_SHIFT 21 -#define OMAP3430_EN_MCSPI3 (1 << 20) +#define OMAP3430_EN_MCSPI3_MASK (1 << 20) #define OMAP3430_EN_MCSPI3_SHIFT 20 -#define OMAP3430_EN_MCSPI2 (1 << 19) +#define OMAP3430_EN_MCSPI2_MASK (1 << 19) #define OMAP3430_EN_MCSPI2_SHIFT 19 -#define OMAP3430_EN_MCSPI1 (1 << 18) +#define OMAP3430_EN_MCSPI1_MASK (1 << 18) #define OMAP3430_EN_MCSPI1_SHIFT 18 -#define OMAP3430_EN_I2C3 (1 << 17) +#define OMAP3430_EN_I2C3_MASK (1 << 17) #define OMAP3430_EN_I2C3_SHIFT 17 -#define OMAP3430_EN_I2C2 (1 << 16) +#define OMAP3430_EN_I2C2_MASK (1 << 16) #define OMAP3430_EN_I2C2_SHIFT 16 -#define OMAP3430_EN_I2C1 (1 << 15) +#define OMAP3430_EN_I2C1_MASK (1 << 15) #define OMAP3430_EN_I2C1_SHIFT 15 -#define OMAP3430_EN_UART2 (1 << 14) +#define OMAP3430_EN_UART2_MASK (1 << 14) #define OMAP3430_EN_UART2_SHIFT 14 -#define OMAP3430_EN_UART1 (1 << 13) +#define OMAP3430_EN_UART1_MASK (1 << 13) #define OMAP3430_EN_UART1_SHIFT 13 -#define OMAP3430_EN_GPT11 (1 << 12) +#define OMAP3430_EN_GPT11_MASK (1 << 12) #define OMAP3430_EN_GPT11_SHIFT 12 -#define OMAP3430_EN_GPT10 (1 << 11) +#define OMAP3430_EN_GPT10_MASK (1 << 11) #define OMAP3430_EN_GPT10_SHIFT 11 -#define OMAP3430_EN_MCBSP5 (1 << 10) +#define OMAP3430_EN_MCBSP5_MASK (1 << 10) #define OMAP3430_EN_MCBSP5_SHIFT 10 -#define OMAP3430_EN_MCBSP1 (1 << 9) +#define OMAP3430_EN_MCBSP1_MASK (1 << 9) #define OMAP3430_EN_MCBSP1_SHIFT 9 -#define OMAP3430_EN_FSHOSTUSB (1 << 5) +#define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5) #define OMAP3430_EN_FSHOSTUSB_SHIFT 5 -#define OMAP3430_EN_D2D (1 << 3) +#define OMAP3430_EN_D2D_MASK (1 << 3) #define OMAP3430_EN_D2D_SHIFT 3 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ -#define OMAP3430_EN_HSOTGUSB (1 << 4) -#define OMAP3430_EN_HSOTGUSB_SHIFT 4 +#define OMAP3430_EN_HSOTGUSB_MASK (1 << 4) +#define OMAP3430_EN_HSOTGUSB_SHIFT 4 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ #define OMAP3430_ST_MMC2_SHIFT 25 @@ -352,21 +344,21 @@ #define OMAP3430_ST_D2D_MASK (1 << 3) /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ -#define OMAP3430_EN_GPIO1 (1 << 3) +#define OMAP3430_EN_GPIO1_MASK (1 << 3) #define OMAP3430_EN_GPIO1_SHIFT 3 -#define OMAP3430_EN_GPT12 (1 << 1) +#define OMAP3430_EN_GPT12_MASK (1 << 1) #define OMAP3430_EN_GPT12_SHIFT 1 -#define OMAP3430_EN_GPT1 (1 << 0) +#define OMAP3430_EN_GPT1_MASK (1 << 0) #define OMAP3430_EN_GPT1_SHIFT 0 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ -#define OMAP3430_EN_SR2 (1 << 7) +#define OMAP3430_EN_SR2_MASK (1 << 7) #define OMAP3430_EN_SR2_SHIFT 7 -#define OMAP3430_EN_SR1 (1 << 6) +#define OMAP3430_EN_SR1_MASK (1 << 6) #define OMAP3430_EN_SR1_SHIFT 6 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ -#define OMAP3430_EN_GPT12 (1 << 1) +#define OMAP3430_EN_GPT12_MASK (1 << 1) #define OMAP3430_EN_GPT12_SHIFT 1 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ @@ -386,47 +378,47 @@ * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits */ -#define OMAP3430_EN_MPU (1 << 1) +#define OMAP3430_EN_MPU_MASK (1 << 1) #define OMAP3430_EN_MPU_SHIFT 1 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ -#define OMAP3430_EN_GPIO6 (1 << 17) +#define OMAP3430_EN_GPIO6_MASK (1 << 17) #define OMAP3430_EN_GPIO6_SHIFT 17 -#define OMAP3430_EN_GPIO5 (1 << 16) +#define OMAP3430_EN_GPIO5_MASK (1 << 16) #define OMAP3430_EN_GPIO5_SHIFT 16 -#define OMAP3430_EN_GPIO4 (1 << 15) +#define OMAP3430_EN_GPIO4_MASK (1 << 15) #define OMAP3430_EN_GPIO4_SHIFT 15 -#define OMAP3430_EN_GPIO3 (1 << 14) +#define OMAP3430_EN_GPIO3_MASK (1 << 14) #define OMAP3430_EN_GPIO3_SHIFT 14 -#define OMAP3430_EN_GPIO2 (1 << 13) +#define OMAP3430_EN_GPIO2_MASK (1 << 13) #define OMAP3430_EN_GPIO2_SHIFT 13 -#define OMAP3430_EN_UART3 (1 << 11) +#define OMAP3430_EN_UART3_MASK (1 << 11) #define OMAP3430_EN_UART3_SHIFT 11 -#define OMAP3430_EN_GPT9 (1 << 10) +#define OMAP3430_EN_GPT9_MASK (1 << 10) #define OMAP3430_EN_GPT9_SHIFT 10 -#define OMAP3430_EN_GPT8 (1 << 9) +#define OMAP3430_EN_GPT8_MASK (1 << 9) #define OMAP3430_EN_GPT8_SHIFT 9 -#define OMAP3430_EN_GPT7 (1 << 8) +#define OMAP3430_EN_GPT7_MASK (1 << 8) #define OMAP3430_EN_GPT7_SHIFT 8 -#define OMAP3430_EN_GPT6 (1 << 7) +#define OMAP3430_EN_GPT6_MASK (1 << 7) #define OMAP3430_EN_GPT6_SHIFT 7 -#define OMAP3430_EN_GPT5 (1 << 6) +#define OMAP3430_EN_GPT5_MASK (1 << 6) #define OMAP3430_EN_GPT5_SHIFT 6 -#define OMAP3430_EN_GPT4 (1 << 5) +#define OMAP3430_EN_GPT4_MASK (1 << 5) #define OMAP3430_EN_GPT4_SHIFT 5 -#define OMAP3430_EN_GPT3 (1 << 4) +#define OMAP3430_EN_GPT3_MASK (1 << 4) #define OMAP3430_EN_GPT3_SHIFT 4 -#define OMAP3430_EN_GPT2 (1 << 3) +#define OMAP3430_EN_GPT2_MASK (1 << 3) #define OMAP3430_EN_GPT2_SHIFT 3 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits * be ST_* bits instead? */ -#define OMAP3430_EN_MCBSP4 (1 << 2) +#define OMAP3430_EN_MCBSP4_MASK (1 << 2) #define OMAP3430_EN_MCBSP4_SHIFT 2 -#define OMAP3430_EN_MCBSP3 (1 << 1) +#define OMAP3430_EN_MCBSP3_MASK (1 << 1) #define OMAP3430_EN_MCBSP3_SHIFT 1 -#define OMAP3430_EN_MCBSP2 (1 << 0) +#define OMAP3430_EN_MCBSP2_MASK (1 << 0) #define OMAP3430_EN_MCBSP2_SHIFT 0 /* CM_IDLEST_PER, PM_WKST_PER shared bits */ diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 07a60f1204c..c20137497c9 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -158,10 +158,10 @@ void omap_prcm_arch_reset(char mode, const char *cmd) WARN_ON(1); if (cpu_is_omap24xx() || cpu_is_omap34xx()) - prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, + prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, OMAP2_RM_RSTCTRL); if (cpu_is_omap44xx()) - prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, + prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, OMAP4_RM_RSTCTRL); } diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 4002051c20b..0b188ffa710 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h @@ -19,14 +19,14 @@ /* Bits shared between registers */ /* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */ -#define OMAP24XX_VOLTTRANS_ST (1 << 2) -#define OMAP24XX_WKUP2_ST (1 << 1) -#define OMAP24XX_WKUP1_ST (1 << 0) +#define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2) +#define OMAP24XX_WKUP2_ST_MASK (1 << 1) +#define OMAP24XX_WKUP1_ST_MASK (1 << 0) /* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */ -#define OMAP24XX_VOLTTRANS_EN (1 << 2) -#define OMAP24XX_WKUP2_EN (1 << 1) -#define OMAP24XX_WKUP1_EN (1 << 0) +#define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2) +#define OMAP24XX_WKUP2_EN_MASK (1 << 1) +#define OMAP24XX_WKUP1_EN_MASK (1 << 0) /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ #define OMAP24XX_EN_MPU_SHIFT 1 @@ -40,16 +40,16 @@ */ #define OMAP24XX_MEMONSTATE_SHIFT 10 #define OMAP24XX_MEMONSTATE_MASK (0x3 << 10) -#define OMAP24XX_MEMRETSTATE (1 << 3) +#define OMAP24XX_MEMRETSTATE_MASK (1 << 3) /* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */ -#define OMAP24XX_FORCESTATE (1 << 18) +#define OMAP24XX_FORCESTATE_MASK (1 << 18) /* * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP, * PM_PWSTST_MDM shared bits */ -#define OMAP24XX_CLKACTIVITY (1 << 19) +#define OMAP24XX_CLKACTIVITY_MASK (1 << 19) /* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */ #define OMAP24XX_LASTSTATEENTERED_SHIFT 4 @@ -71,26 +71,26 @@ #define OMAP24XX_REV_MASK (0xff << 0) /* PRCM_SYSCONFIG */ -#define OMAP24XX_AUTOIDLE (1 << 0) +#define OMAP24XX_AUTOIDLE_MASK (1 << 0) /* PRCM_IRQSTATUS_MPU specific bits */ -#define OMAP2430_DPLL_RECAL_ST (1 << 6) -#define OMAP24XX_TRANSITION_ST (1 << 5) -#define OMAP24XX_EVGENOFF_ST (1 << 4) -#define OMAP24XX_EVGENON_ST (1 << 3) +#define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6) +#define OMAP24XX_TRANSITION_ST_MASK (1 << 5) +#define OMAP24XX_EVGENOFF_ST_MASK (1 << 4) +#define OMAP24XX_EVGENON_ST_MASK (1 << 3) /* PRCM_IRQENABLE_MPU specific bits */ -#define OMAP2430_DPLL_RECAL_EN (1 << 6) -#define OMAP24XX_TRANSITION_EN (1 << 5) -#define OMAP24XX_EVGENOFF_EN (1 << 4) -#define OMAP24XX_EVGENON_EN (1 << 3) +#define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6) +#define OMAP24XX_TRANSITION_EN_MASK (1 << 5) +#define OMAP24XX_EVGENOFF_EN_MASK (1 << 4) +#define OMAP24XX_EVGENON_EN_MASK (1 << 3) /* PRCM_VOLTCTRL */ -#define OMAP24XX_AUTO_EXTVOLT (1 << 15) -#define OMAP24XX_FORCE_EXTVOLT (1 << 14) +#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15) +#define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14) #define OMAP24XX_SETOFF_LEVEL_SHIFT 12 #define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12) -#define OMAP24XX_MEMRETCTRL (1 << 8) +#define OMAP24XX_MEMRETCTRL_MASK (1 << 8) #define OMAP24XX_SETRET_LEVEL_SHIFT 6 #define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6) #define OMAP24XX_VOLT_LEVEL_SHIFT 0 @@ -104,13 +104,13 @@ /* PRCM_CLKOUT_CTRL */ #define OMAP2420_CLKOUT2_EN_SHIFT 15 -#define OMAP2420_CLKOUT2_EN (1 << 15) +#define OMAP2420_CLKOUT2_EN_MASK (1 << 15) #define OMAP2420_CLKOUT2_DIV_SHIFT 11 #define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) #define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) #define OMAP24XX_CLKOUT_EN_SHIFT 7 -#define OMAP24XX_CLKOUT_EN (1 << 7) +#define OMAP24XX_CLKOUT_EN_MASK (1 << 7) #define OMAP24XX_CLKOUT_DIV_SHIFT 3 #define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) #define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 @@ -118,25 +118,25 @@ /* PRCM_CLKEMUL_CTRL */ #define OMAP24XX_EMULATION_EN_SHIFT 0 -#define OMAP24XX_EMULATION_EN (1 << 0) +#define OMAP24XX_EMULATION_EN_MASK (1 << 0) /* PRCM_CLKCFG_CTRL */ -#define OMAP24XX_VALID_CONFIG (1 << 0) +#define OMAP24XX_VALID_CONFIG_MASK (1 << 0) /* PRCM_CLKCFG_STATUS */ -#define OMAP24XX_CONFIG_STATUS (1 << 0) +#define OMAP24XX_CONFIG_STATUS_MASK (1 << 0) /* PRCM_VOLTSETUP specific bits */ /* PRCM_CLKSSETUP specific bits */ /* PRCM_POLCTRL */ -#define OMAP2420_CLKOUT2_POL (1 << 10) -#define OMAP24XX_CLKOUT_POL (1 << 9) -#define OMAP24XX_CLKREQ_POL (1 << 8) -#define OMAP2430_USE_POWEROK (1 << 2) -#define OMAP2430_POWEROK_POL (1 << 1) -#define OMAP24XX_EXTVOL_POL (1 << 0) +#define OMAP2420_CLKOUT2_POL_MASK (1 << 10) +#define OMAP24XX_CLKOUT_POL_MASK (1 << 9) +#define OMAP24XX_CLKREQ_POL_MASK (1 << 8) +#define OMAP2430_USE_POWEROK_MASK (1 << 2) +#define OMAP2430_POWEROK_POL_MASK (1 << 1) +#define OMAP24XX_EXTVOL_POL_MASK (1 << 0) /* RM_RSTST_MPU specific bits */ /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ @@ -154,7 +154,7 @@ /* PM_EVEGENOFFTIM_MPU specific bits */ /* PM_PWSTCTRL_MPU specific bits */ -#define OMAP2430_FORCESTATE (1 << 18) +#define OMAP2430_FORCESTATE_MASK (1 << 18) /* PM_PWSTST_MPU specific bits */ /* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */ @@ -168,21 +168,21 @@ /* PM_WKST2_CORE specific bits */ /* PM_WKDEP_CORE specific bits*/ -#define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5) -#define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3) -#define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2) +#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5) +#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3) +#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2) /* PM_PWSTCTRL_CORE specific bits */ -#define OMAP24XX_MEMORYCHANGE (1 << 20) +#define OMAP24XX_MEMORYCHANGE_MASK (1 << 20) #define OMAP24XX_MEM3ONSTATE_SHIFT 14 #define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14) #define OMAP24XX_MEM2ONSTATE_SHIFT 12 #define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12) #define OMAP24XX_MEM1ONSTATE_SHIFT 10 #define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10) -#define OMAP24XX_MEM3RETSTATE (1 << 5) -#define OMAP24XX_MEM2RETSTATE (1 << 4) -#define OMAP24XX_MEM1RETSTATE (1 << 3) +#define OMAP24XX_MEM3RETSTATE_MASK (1 << 5) +#define OMAP24XX_MEM2RETSTATE_MASK (1 << 4) +#define OMAP24XX_MEM1RETSTATE_MASK (1 << 3) /* PM_PWSTST_CORE specific bits */ #define OMAP24XX_MEM3STATEST_SHIFT 14 @@ -193,10 +193,10 @@ #define OMAP24XX_MEM1STATEST_MASK (0x3 << 10) /* RM_RSTCTRL_GFX */ -#define OMAP24XX_GFX_RST (1 << 0) +#define OMAP24XX_GFX_RST_MASK (1 << 0) /* RM_RSTST_GFX specific bits */ -#define OMAP24XX_GFX_SW_RST (1 << 4) +#define OMAP24XX_GFX_SW_RST_MASK (1 << 4) /* PM_PWSTCTRL_GFX specific bits */ @@ -209,25 +209,25 @@ /* RM_RSTST_WKUP specific bits */ /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ -#define OMAP24XX_EXTWMPU_RST (1 << 6) -#define OMAP24XX_SECU_WD_RST (1 << 5) -#define OMAP24XX_MPU_WD_RST (1 << 4) -#define OMAP24XX_SECU_VIOL_RST (1 << 3) +#define OMAP24XX_EXTWMPU_RST_MASK (1 << 6) +#define OMAP24XX_SECU_WD_RST_MASK (1 << 5) +#define OMAP24XX_MPU_WD_RST_MASK (1 << 4) +#define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3) /* PM_WKEN_WKUP specific bits */ /* PM_WKST_WKUP specific bits */ /* RM_RSTCTRL_DSP */ -#define OMAP2420_RST_IVA (1 << 8) -#define OMAP24XX_RST2_DSP (1 << 1) -#define OMAP24XX_RST1_DSP (1 << 0) +#define OMAP2420_RST_IVA_MASK (1 << 8) +#define OMAP24XX_RST2_DSP_MASK (1 << 1) +#define OMAP24XX_RST1_DSP_MASK (1 << 0) /* RM_RSTST_DSP specific bits */ /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */ -#define OMAP2420_IVA_SW_RST (1 << 8) -#define OMAP24XX_DSP_SW_RST2 (1 << 5) -#define OMAP24XX_DSP_SW_RST1 (1 << 4) +#define OMAP2420_IVA_SW_RST_MASK (1 << 8) +#define OMAP24XX_DSP_SW_RST2_MASK (1 << 5) +#define OMAP24XX_DSP_SW_RST1_MASK (1 << 4) /* PM_WKDEP_DSP specific bits */ @@ -235,7 +235,7 @@ /* 2430 only: MEMONSTATE, MEMRETSTATE */ #define OMAP2420_MEMIONSTATE_SHIFT 12 #define OMAP2420_MEMIONSTATE_MASK (0x3 << 12) -#define OMAP2420_MEMIRETSTATE (1 << 4) +#define OMAP2420_MEMIRETSTATE_MASK (1 << 4) /* PM_PWSTST_DSP specific bits */ /* MEMSTATEST is 2430 only */ @@ -248,18 +248,18 @@ /* RM_RSTCTRL_MDM */ /* 2430 only */ -#define OMAP2430_PWRON1_MDM (1 << 1) -#define OMAP2430_RST1_MDM (1 << 0) +#define OMAP2430_PWRON1_MDM_MASK (1 << 1) +#define OMAP2430_RST1_MDM_MASK (1 << 0) /* RM_RSTST_MDM specific bits */ /* 2430 only */ -#define OMAP2430_MDM_SECU_VIOL (1 << 6) -#define OMAP2430_MDM_SW_PWRON1 (1 << 5) -#define OMAP2430_MDM_SW_RST1 (1 << 4) +#define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6) +#define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5) +#define OMAP2430_MDM_SW_RST1_MASK (1 << 4) /* PM_WKEN_MDM */ /* 2430 only */ -#define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0) +#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0) /* PM_WKST_MDM specific bits */ /* 2430 only */ @@ -269,7 +269,7 @@ /* PM_PWSTCTRL_MDM specific bits */ /* 2430 only */ -#define OMAP2430_KILLDOMAINWKUP (1 << 19) +#define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19) /* PM_PWSTST_MDM specific bits */ /* 2430 only */ diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 8f21bae6dc1..7fd6023edf9 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -35,10 +35,10 @@ #define OMAP3430_ERRORGAIN_MASK (0xff << 16) #define OMAP3430_INITVOLTAGE_SHIFT 8 #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) -#define OMAP3430_TIMEOUTEN (1 << 3) -#define OMAP3430_INITVDD (1 << 2) -#define OMAP3430_FORCEUPDATE (1 << 1) -#define OMAP3430_VPENABLE (1 << 0) +#define OMAP3430_TIMEOUTEN_MASK (1 << 3) +#define OMAP3430_INITVDD_MASK (1 << 2) +#define OMAP3430_FORCEUPDATE_MASK (1 << 1) +#define OMAP3430_VPENABLE_MASK (1 << 0) /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 @@ -65,53 +65,53 @@ #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ -#define OMAP3430_VPINIDLE (1 << 0) +#define OMAP3430_VPINIDLE_MASK (1 << 0) /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ #define OMAP3430_EN_PER_SHIFT 7 #define OMAP3430_EN_PER_MASK (1 << 7) /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ -#define OMAP3430_MEMORYCHANGE (1 << 3) +#define OMAP3430_MEMORYCHANGE_MASK (1 << 3) /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ -#define OMAP3430_LOGICSTATEST (1 << 2) +#define OMAP3430_LOGICSTATEST_MASK (1 << 2) /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ -#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2) +#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) /* * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits */ -#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 -#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) +#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 +#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ -#define OMAP3430_WKUP_ST (1 << 0) +#define OMAP3430_WKUP_ST_MASK (1 << 0) /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ -#define OMAP3430_WKUP_EN (1 << 0) +#define OMAP3430_WKUP_EN_MASK (1 << 0) /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ -#define OMAP3430_GRPSEL_MMC2 (1 << 25) -#define OMAP3430_GRPSEL_MMC1 (1 << 24) -#define OMAP3430_GRPSEL_MCSPI4 (1 << 21) -#define OMAP3430_GRPSEL_MCSPI3 (1 << 20) -#define OMAP3430_GRPSEL_MCSPI2 (1 << 19) -#define OMAP3430_GRPSEL_MCSPI1 (1 << 18) -#define OMAP3430_GRPSEL_I2C3 (1 << 17) -#define OMAP3430_GRPSEL_I2C2 (1 << 16) -#define OMAP3430_GRPSEL_I2C1 (1 << 15) -#define OMAP3430_GRPSEL_UART2 (1 << 14) -#define OMAP3430_GRPSEL_UART1 (1 << 13) -#define OMAP3430_GRPSEL_GPT11 (1 << 12) -#define OMAP3430_GRPSEL_GPT10 (1 << 11) -#define OMAP3430_GRPSEL_MCBSP5 (1 << 10) -#define OMAP3430_GRPSEL_MCBSP1 (1 << 9) -#define OMAP3430_GRPSEL_HSOTGUSB (1 << 4) -#define OMAP3430_GRPSEL_D2D (1 << 3) +#define OMAP3430_GRPSEL_MMC2_MASK (1 << 25) +#define OMAP3430_GRPSEL_MMC1_MASK (1 << 24) +#define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21) +#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) +#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) +#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) +#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) +#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) +#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) +#define OMAP3430_GRPSEL_UART2_MASK (1 << 14) +#define OMAP3430_GRPSEL_UART1_MASK (1 << 13) +#define OMAP3430_GRPSEL_GPT11_MASK (1 << 12) +#define OMAP3430_GRPSEL_GPT10_MASK (1 << 11) +#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10) +#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9) +#define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4) +#define OMAP3430_GRPSEL_D2D_MASK (1 << 3) /* * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, @@ -119,49 +119,49 @@ */ #define OMAP3430_MEMONSTATE_SHIFT 16 #define OMAP3430_MEMONSTATE_MASK (0x3 << 16) -#define OMAP3430_MEMRETSTATE (1 << 8) +#define OMAP3430_MEMRETSTATE_MASK (1 << 8) /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ -#define OMAP3430_GRPSEL_GPIO6 (1 << 17) -#define OMAP3430_GRPSEL_GPIO5 (1 << 16) -#define OMAP3430_GRPSEL_GPIO4 (1 << 15) -#define OMAP3430_GRPSEL_GPIO3 (1 << 14) -#define OMAP3430_GRPSEL_GPIO2 (1 << 13) -#define OMAP3430_GRPSEL_UART3 (1 << 11) -#define OMAP3430_GRPSEL_GPT9 (1 << 10) -#define OMAP3430_GRPSEL_GPT8 (1 << 9) -#define OMAP3430_GRPSEL_GPT7 (1 << 8) -#define OMAP3430_GRPSEL_GPT6 (1 << 7) -#define OMAP3430_GRPSEL_GPT5 (1 << 6) -#define OMAP3430_GRPSEL_GPT4 (1 << 5) -#define OMAP3430_GRPSEL_GPT3 (1 << 4) -#define OMAP3430_GRPSEL_GPT2 (1 << 3) -#define OMAP3430_GRPSEL_MCBSP4 (1 << 2) -#define OMAP3430_GRPSEL_MCBSP3 (1 << 1) -#define OMAP3430_GRPSEL_MCBSP2 (1 << 0) +#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) +#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) +#define OMAP3430_GRPSEL_GPIO4_MASK (1 << 15) +#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) +#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) +#define OMAP3430_GRPSEL_UART3_MASK (1 << 11) +#define OMAP3430_GRPSEL_GPT9_MASK (1 << 10) +#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9) +#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8) +#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7) +#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6) +#define OMAP3430_GRPSEL_GPT4_MASK (1 << 5) +#define OMAP3430_GRPSEL_GPT3_MASK (1 << 4) +#define OMAP3430_GRPSEL_GPT2_MASK (1 << 3) +#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) +#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) +#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ -#define OMAP3430_GRPSEL_IO (1 << 8) -#define OMAP3430_GRPSEL_SR2 (1 << 7) -#define OMAP3430_GRPSEL_SR1 (1 << 6) -#define OMAP3430_GRPSEL_GPIO1 (1 << 3) -#define OMAP3430_GRPSEL_GPT12 (1 << 1) -#define OMAP3430_GRPSEL_GPT1 (1 << 0) +#define OMAP3430_GRPSEL_IO_MASK (1 << 8) +#define OMAP3430_GRPSEL_SR2_MASK (1 << 7) +#define OMAP3430_GRPSEL_SR1_MASK (1 << 6) +#define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) +#define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) +#define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) /* Bits specific to each register */ /* RM_RSTCTRL_IVA2 */ -#define OMAP3430_RST3_IVA2 (1 << 2) -#define OMAP3430_RST2_IVA2 (1 << 1) -#define OMAP3430_RST1_IVA2 (1 << 0) +#define OMAP3430_RST3_IVA2_MASK (1 << 2) +#define OMAP3430_RST2_IVA2_MASK (1 << 1) +#define OMAP3430_RST1_IVA2_MASK (1 << 0) /* RM_RSTST_IVA2 specific bits */ -#define OMAP3430_EMULATION_VSEQ_RST (1 << 13) -#define OMAP3430_EMULATION_VHWA_RST (1 << 12) -#define OMAP3430_EMULATION_IVA2_RST (1 << 11) -#define OMAP3430_IVA2_SW_RST3 (1 << 10) -#define OMAP3430_IVA2_SW_RST2 (1 << 9) -#define OMAP3430_IVA2_SW_RST1 (1 << 8) +#define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13) +#define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12) +#define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11) +#define OMAP3430_IVA2_SW_RST3_MASK (1 << 10) +#define OMAP3430_IVA2_SW_RST2_MASK (1 << 9) +#define OMAP3430_IVA2_SW_RST1_MASK (1 << 8) /* PM_WKDEP_IVA2 specific bits */ @@ -174,10 +174,10 @@ #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) -#define OMAP3430_L2FLATMEMRETSTATE (1 << 11) -#define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10) -#define OMAP3430_L1FLATMEMRETSTATE (1 << 9) -#define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8) +#define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11) +#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10) +#define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9) +#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8) /* PM_PWSTST_IVA2 specific bits */ #define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 @@ -200,12 +200,12 @@ #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) /* PRM_IRQSTATUS_IVA2 specific bits */ -#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2) -#define OMAP3430_FORCEWKUP_ST (1 << 1) +#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2) +#define OMAP3430_FORCEWKUP_ST_MASK (1 << 1) /* PRM_IRQENABLE_IVA2 specific bits */ -#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2) -#define OMAP3430_FORCEWKUP_EN (1 << 1) +#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2) +#define OMAP3430_FORCEWKUP_EN_MASK (1 << 1) /* PRM_REVISION specific bits */ @@ -213,70 +213,70 @@ /* PRM_IRQSTATUS_MPU specific bits */ #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 -#define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25) -#define OMAP3430_VC_TIMEOUTERR_ST (1 << 24) -#define OMAP3430_VC_RAERR_ST (1 << 23) -#define OMAP3430_VC_SAERR_ST (1 << 22) -#define OMAP3430_VP2_TRANXDONE_ST (1 << 21) -#define OMAP3430_VP2_EQVALUE_ST (1 << 20) -#define OMAP3430_VP2_NOSMPSACK_ST (1 << 19) -#define OMAP3430_VP2_MAXVDD_ST (1 << 18) -#define OMAP3430_VP2_MINVDD_ST (1 << 17) -#define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16) -#define OMAP3430_VP1_TRANXDONE_ST (1 << 15) -#define OMAP3430_VP1_EQVALUE_ST (1 << 14) -#define OMAP3430_VP1_NOSMPSACK_ST (1 << 13) -#define OMAP3430_VP1_MAXVDD_ST (1 << 12) -#define OMAP3430_VP1_MINVDD_ST (1 << 11) -#define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10) -#define OMAP3430_IO_ST (1 << 9) -#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8) +#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25) +#define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24) +#define OMAP3430_VC_RAERR_ST_MASK (1 << 23) +#define OMAP3430_VC_SAERR_ST_MASK (1 << 22) +#define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) +#define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20) +#define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19) +#define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18) +#define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17) +#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16) +#define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) +#define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14) +#define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13) +#define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12) +#define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11) +#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10) +#define OMAP3430_IO_ST_MASK (1 << 9) +#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8) #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 -#define OMAP3430_MPU_DPLL_ST (1 << 7) +#define OMAP3430_MPU_DPLL_ST_MASK (1 << 7) #define OMAP3430_MPU_DPLL_ST_SHIFT 7 -#define OMAP3430_PERIPH_DPLL_ST (1 << 6) +#define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6) #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 -#define OMAP3430_CORE_DPLL_ST (1 << 5) +#define OMAP3430_CORE_DPLL_ST_MASK (1 << 5) #define OMAP3430_CORE_DPLL_ST_SHIFT 5 -#define OMAP3430_TRANSITION_ST (1 << 4) -#define OMAP3430_EVGENOFF_ST (1 << 3) -#define OMAP3430_EVGENON_ST (1 << 2) -#define OMAP3430_FS_USB_WKUP_ST (1 << 1) +#define OMAP3430_TRANSITION_ST_MASK (1 << 4) +#define OMAP3430_EVGENOFF_ST_MASK (1 << 3) +#define OMAP3430_EVGENON_ST_MASK (1 << 2) +#define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1) /* PRM_IRQENABLE_MPU specific bits */ #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 -#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25) -#define OMAP3430_VC_TIMEOUTERR_EN (1 << 24) -#define OMAP3430_VC_RAERR_EN (1 << 23) -#define OMAP3430_VC_SAERR_EN (1 << 22) -#define OMAP3430_VP2_TRANXDONE_EN (1 << 21) -#define OMAP3430_VP2_EQVALUE_EN (1 << 20) -#define OMAP3430_VP2_NOSMPSACK_EN (1 << 19) -#define OMAP3430_VP2_MAXVDD_EN (1 << 18) -#define OMAP3430_VP2_MINVDD_EN (1 << 17) -#define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16) -#define OMAP3430_VP1_TRANXDONE_EN (1 << 15) -#define OMAP3430_VP1_EQVALUE_EN (1 << 14) -#define OMAP3430_VP1_NOSMPSACK_EN (1 << 13) -#define OMAP3430_VP1_MAXVDD_EN (1 << 12) -#define OMAP3430_VP1_MINVDD_EN (1 << 11) -#define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10) -#define OMAP3430_IO_EN (1 << 9) -#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8) +#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25) +#define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24) +#define OMAP3430_VC_RAERR_EN_MASK (1 << 23) +#define OMAP3430_VC_SAERR_EN_MASK (1 << 22) +#define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21) +#define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20) +#define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19) +#define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18) +#define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17) +#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16) +#define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15) +#define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14) +#define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13) +#define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12) +#define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11) +#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10) +#define OMAP3430_IO_EN_MASK (1 << 9) +#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8) #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 -#define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7) +#define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7) #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 -#define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6) +#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6) #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 -#define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5) +#define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5) #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 -#define OMAP3430_TRANSITION_EN (1 << 4) -#define OMAP3430_EVGENOFF_EN (1 << 3) -#define OMAP3430_EVGENON_EN (1 << 2) -#define OMAP3430_FS_USB_WKUP_EN (1 << 1) +#define OMAP3430_TRANSITION_EN_MASK (1 << 4) +#define OMAP3430_EVGENOFF_EN_MASK (1 << 3) +#define OMAP3430_EVGENON_EN_MASK (1 << 2) +#define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1) /* RM_RSTST_MPU specific bits */ -#define OMAP3430_EMULATION_MPU_RST (1 << 11) +#define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11) /* PM_WKDEP_MPU specific bits */ #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 @@ -289,7 +289,7 @@ #define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) #define OMAP3430_ONLOADMODE_SHIFT 1 #define OMAP3430_ONLOADMODE_MASK (0x3 << 1) -#define OMAP3430_ENABLE (1 << 0) +#define OMAP3430_ENABLE_MASK (1 << 0) /* PM_EVGENONTIM_MPU */ #define OMAP3430_ONTIMEVAL_SHIFT 0 @@ -302,32 +302,32 @@ /* PM_PWSTCTRL_MPU specific bits */ #define OMAP3430_L2CACHEONSTATE_SHIFT 16 #define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) -#define OMAP3430_L2CACHERETSTATE (1 << 8) -#define OMAP3430_LOGICL1CACHERETSTATE (1 << 2) +#define OMAP3430_L2CACHERETSTATE_MASK (1 << 8) +#define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2) /* PM_PWSTST_MPU specific bits */ #define OMAP3430_L2CACHESTATEST_SHIFT 6 #define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) -#define OMAP3430_LOGICL1CACHESTATEST (1 << 2) +#define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2) /* PM_PREPWSTST_MPU specific bits */ #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 #define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) -#define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2) +#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2) /* RM_RSTCTRL_CORE */ -#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1) -#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0) +#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) +#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) /* RM_RSTST_CORE specific bits */ -#define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10) -#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9) -#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8) +#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10) +#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9) +#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8) /* PM_WKEN1_CORE specific bits */ /* PM_MPUGRPSEL1_CORE specific bits */ -#define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5) +#define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5) /* PM_IVA2GRPSEL1_CORE specific bits */ @@ -338,8 +338,8 @@ #define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) #define OMAP3430_MEM1ONSTATE_SHIFT 16 #define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) -#define OMAP3430_MEM2RETSTATE (1 << 9) -#define OMAP3430_MEM1RETSTATE (1 << 8) +#define OMAP3430_MEM2RETSTATE_MASK (1 << 9) +#define OMAP3430_MEM1RETSTATE_MASK (1 << 8) /* PM_PWSTST_CORE specific bits */ #define OMAP3430_MEM2STATEST_SHIFT 6 @@ -356,7 +356,7 @@ /* RM_RSTST_GFX specific bits */ /* PM_WKDEP_GFX specific bits */ -#define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2) +#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2) /* PM_PWSTCTRL_GFX specific bits */ @@ -365,33 +365,33 @@ /* PM_PREPWSTST_GFX specific bits */ /* PM_WKEN_WKUP specific bits */ -#define OMAP3430_EN_IO_CHAIN (1 << 16) -#define OMAP3430_EN_IO (1 << 8) -#define OMAP3430_EN_GPIO1 (1 << 3) +#define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) +#define OMAP3430_EN_IO_MASK (1 << 8) +#define OMAP3430_EN_GPIO1_MASK (1 << 3) /* PM_MPUGRPSEL_WKUP specific bits */ /* PM_IVA2GRPSEL_WKUP specific bits */ /* PM_WKST_WKUP specific bits */ -#define OMAP3430_ST_IO_CHAIN (1 << 16) -#define OMAP3430_ST_IO (1 << 8) +#define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) +#define OMAP3430_ST_IO_MASK (1 << 8) /* PRM_CLKSEL */ #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) /* PRM_CLKOUT_CTRL */ -#define OMAP3430_CLKOUT_EN (1 << 7) +#define OMAP3430_CLKOUT_EN_MASK (1 << 7) #define OMAP3430_CLKOUT_EN_SHIFT 7 /* RM_RSTST_DSS specific bits */ /* PM_WKEN_DSS */ -#define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0) +#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) /* PM_WKDEP_DSS specific bits */ -#define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2) +#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2) /* PM_PWSTCTRL_DSS specific bits */ @@ -402,7 +402,7 @@ /* RM_RSTST_CAM specific bits */ /* PM_WKDEP_CAM specific bits */ -#define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2) +#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2) /* PM_PWSTCTRL_CAM specific bits */ @@ -424,7 +424,7 @@ /* PM_WKST_PER specific bits */ /* PM_WKDEP_PER specific bits */ -#define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2) +#define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2) /* PM_PWSTCTRL_PER specific bits */ @@ -467,26 +467,26 @@ /* PRM_VC_CMD_VAL_1 specific bits */ /* PRM_VC_CH_CONF */ -#define OMAP3430_CMD1 (1 << 20) -#define OMAP3430_RACEN1 (1 << 19) -#define OMAP3430_RAC1 (1 << 18) -#define OMAP3430_RAV1 (1 << 17) -#define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16) -#define OMAP3430_CMD0 (1 << 4) -#define OMAP3430_RACEN0 (1 << 3) -#define OMAP3430_RAC0 (1 << 2) -#define OMAP3430_RAV0 (1 << 1) -#define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0) +#define OMAP3430_CMD1_MASK (1 << 20) +#define OMAP3430_RACEN1_MASK (1 << 19) +#define OMAP3430_RAC1_MASK (1 << 18) +#define OMAP3430_RAV1_MASK (1 << 17) +#define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16) +#define OMAP3430_CMD0_MASK (1 << 4) +#define OMAP3430_RACEN0_MASK (1 << 3) +#define OMAP3430_RAC0_MASK (1 << 2) +#define OMAP3430_RAV0_MASK (1 << 1) +#define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0) /* PRM_VC_I2C_CFG */ -#define OMAP3430_HSMASTER (1 << 5) -#define OMAP3430_SREN (1 << 4) -#define OMAP3430_HSEN (1 << 3) +#define OMAP3430_HSMASTER_MASK (1 << 5) +#define OMAP3430_SREN_MASK (1 << 4) +#define OMAP3430_HSEN_MASK (1 << 3) #define OMAP3430_MCODE_SHIFT 0 #define OMAP3430_MCODE_MASK (0x7 << 0) /* PRM_VC_BYPASS_VAL */ -#define OMAP3430_VALID (1 << 24) +#define OMAP3430_VALID_MASK (1 << 24) #define OMAP3430_DATA_SHIFT 16 #define OMAP3430_DATA_MASK (0xff << 16) #define OMAP3430_REGADDR_SHIFT 8 @@ -495,8 +495,8 @@ #define OMAP3430_SLAVEADDR_MASK (0x7f << 0) /* PRM_RSTCTRL */ -#define OMAP3430_RST_DPLL3 (1 << 2) -#define OMAP3430_RST_GS (1 << 1) +#define OMAP3430_RST_DPLL3_MASK (1 << 2) +#define OMAP3430_RST_GS_MASK (1 << 1) /* PRM_RSTTIME */ #define OMAP3430_RSTTIME2_SHIFT 8 @@ -505,23 +505,23 @@ #define OMAP3430_RSTTIME1_MASK (0xff << 0) /* PRM_RSTST */ -#define OMAP3430_ICECRUSHER_RST (1 << 10) -#define OMAP3430_ICEPICK_RST (1 << 9) -#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8) -#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7) -#define OMAP3430_EXTERNAL_WARM_RST (1 << 6) -#define OMAP3430_SECURE_WD_RST (1 << 5) -#define OMAP3430_MPU_WD_RST (1 << 4) -#define OMAP3430_SECURITY_VIOL_RST (1 << 3) -#define OMAP3430_GLOBAL_SW_RST (1 << 1) -#define OMAP3430_GLOBAL_COLD_RST (1 << 0) +#define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) +#define OMAP3430_ICEPICK_RST_MASK (1 << 9) +#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) +#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) +#define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) +#define OMAP3430_SECURE_WD_RST_MASK (1 << 5) +#define OMAP3430_MPU_WD_RST_MASK (1 << 4) +#define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) +#define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) +#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) /* PRM_VOLTCTRL */ -#define OMAP3430_SEL_VMODE (1 << 4) -#define OMAP3430_SEL_OFF (1 << 3) -#define OMAP3430_AUTO_OFF (1 << 2) -#define OMAP3430_AUTO_RET (1 << 1) -#define OMAP3430_AUTO_SLEEP (1 << 0) +#define OMAP3430_SEL_VMODE_MASK (1 << 4) +#define OMAP3430_SEL_OFF_MASK (1 << 3) +#define OMAP3430_AUTO_OFF_MASK (1 << 2) +#define OMAP3430_AUTO_RET_MASK (1 << 1) +#define OMAP3430_AUTO_SLEEP_MASK (1 << 0) /* PRM_SRAM_PCHARGE */ #define OMAP3430_PCHARGE_TIME_SHIFT 0 @@ -550,10 +550,10 @@ #define OMAP3430_SETUP_TIME_MASK (0xffff << 0) /* PRM_POLCTRL */ -#define OMAP3430_OFFMODE_POL (1 << 3) -#define OMAP3430_CLKOUT_POL (1 << 2) -#define OMAP3430_CLKREQ_POL (1 << 1) -#define OMAP3430_EXTVOL_POL (1 << 0) +#define OMAP3430_OFFMODE_POL_MASK (1 << 3) +#define OMAP3430_CLKOUT_POL_MASK (1 << 2) +#define OMAP3430_CLKREQ_POL_MASK (1 << 1) +#define OMAP3430_EXTVOL_POL_MASK (1 << 0) /* PRM_VOLTSETUP2 */ #define OMAP3430_OFFMODESETUPTIME_SHIFT 0 diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 5fba2aa8932..588873b9303 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -24,8 +24,8 @@ OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) #define OMAP44XX_PRM_REGADDR(module, reg) \ OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) -#define OMAP44XX_CHIRONSS_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg)) +#define OMAP44XX_PRCM_MPU_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg)) #include "prm44xx.h" @@ -284,7 +284,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) #define OMAP_OFFLOADMODE_MASK (0x3 << 3) #define OMAP_ONLOADMODE_SHIFT 1 #define OMAP_ONLOADMODE_MASK (0x3 << 1) -#define OMAP_ENABLE (1 << 0) +#define OMAP_ENABLE_MASK (1 << 0) /* PRM_RSTTIME */ /* Named RM_RSTTIME_WKUP on the 24xx */ @@ -296,8 +296,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) /* PRM_RSTCTRL */ /* Named RM_RSTCTRL_WKUP on the 24xx */ /* 2420 calls RST_DPLL3 'RST_DPLL' */ -#define OMAP_RST_DPLL3 (1 << 2) -#define OMAP_RST_GS (1 << 1) +#define OMAP_RST_DPLL3_MASK (1 << 2) +#define OMAP_RST_GS_MASK (1 << 1) /* @@ -316,7 +316,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, * PM_PWSTST_NEON */ -#define OMAP_INTRANSITION (1 << 20) +#define OMAP_INTRANSITION_MASK (1 << 20) /* @@ -338,7 +338,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON */ -#define OMAP_COREDOMAINWKUP_RST (1 << 3) +#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3) /* * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP @@ -347,7 +347,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) * * 3430: RM_RSTST_CORE, RM_RSTST_EMU */ -#define OMAP_DOMAINWKUP_RST (1 << 2) +#define OMAP_DOMAINWKUP_RST_MASK (1 << 2) /* * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP @@ -357,8 +357,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) * * 3430: RM_RSTST_CORE, RM_RSTST_EMU */ -#define OMAP_GLOBALWARM_RST (1 << 1) -#define OMAP_GLOBALCOLD_RST (1 << 0) +#define OMAP_GLOBALWARM_RST_MASK (1 << 1) +#define OMAP_GLOBALCOLD_RST_MASK (1 << 0) /* * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP @@ -382,7 +382,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, * PM_PWSTCTRL_NEON */ -#define OMAP_LOGICRETSTATE (1 << 2) +#define OMAP_LOGICRETSTATE_MASK (1 << 2) /* * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index adb2558bb12..fe8ef26431e 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -1,8 +1,8 @@ /* * OMAP44xx PRM instance offset macros * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) @@ -25,387 +25,726 @@ /* PRM */ - /* PRM.OCP_SOCKET_PRM register offsets */ +#define OMAP4_REVISION_PRM_OFFSET 0x0000 #define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000) +#define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010 #define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010) +#define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 #define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014) +#define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018 #define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018) +#define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c #define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c) +#define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020 #define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020) +#define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028 #define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028) +#define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030 #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) +#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) +#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 #define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) /* PRM.CKGEN_PRM register offsets */ +#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) +#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET 0x0004 #define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004) +#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) +#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c #define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c) +#define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010 #define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010) /* PRM.MPU_PRM register offsets */ +#define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000) +#define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004) +#define OMAP4_RM_MPU_RSTST_OFFSET 0x0014 #define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014) +#define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024) /* PRM.TESLA_PRM register offsets */ +#define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000) +#define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004) +#define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010 #define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010) +#define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014 #define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014) +#define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024) /* PRM.ABE_PRM register offsets */ +#define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000) +#define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004) +#define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c #define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c) +#define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030 #define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030) +#define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034 #define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034) +#define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 #define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038) +#define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c #define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c) +#define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 #define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040) +#define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 #define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044) +#define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 #define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048) +#define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c #define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c) +#define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 #define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050) +#define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 #define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054) +#define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 #define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058) +#define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c #define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c) +#define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060 #define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060) +#define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064 #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064) +#define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 #define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068) +#define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c #define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c) +#define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 #define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070) +#define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 #define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074) +#define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 #define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078) +#define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c #define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c) +#define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 #define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080) +#define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 #define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084) +#define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088 #define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088) +#define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c #define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c) /* PRM.ALWAYS_ON_PRM register offsets */ +#define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024) +#define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028 #define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028) +#define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c) +#define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030 #define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030) +#define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034 #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034) +#define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038 #define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038) +#define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c) /* PRM.CORE_PRM register offsets */ +#define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000) +#define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004) +#define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024) +#define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124 #define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124) +#define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c #define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c) +#define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134 #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134) +#define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210 #define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210) +#define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214 #define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214) +#define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224 #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224) +#define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324 #define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324) +#define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424 #define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424) +#define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c) +#define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434 #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434) +#define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c) +#define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444 #define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444) +#define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454 #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454) +#define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c) +#define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464 #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464) +#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524) +#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c) +#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534) +#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624) +#define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c) +#define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634) +#define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c) +#define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724 #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724) +#define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c) +#define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744 #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744) /* PRM.IVAHD_PRM register offsets */ +#define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000) +#define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004) +#define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010 #define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010) +#define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014 #define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014) +#define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024) +#define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c #define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c) /* PRM.CAM_PRM register offsets */ +#define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000) +#define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004) +#define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024) +#define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c #define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c) /* PRM.DSS_PRM register offsets */ +#define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000) +#define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004) +#define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020 #define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020) +#define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024) +#define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c #define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c) /* PRM.GFX_PRM register offsets */ +#define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000) +#define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004) +#define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024) /* PRM.L3INIT_PRM register offsets */ +#define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000) +#define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004) +#define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 #define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028) +#define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c #define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c) +#define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 #define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030) +#define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 #define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034) +#define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 #define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038) +#define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c #define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c) +#define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040 #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040) +#define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044 #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044) +#define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058 #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058) +#define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c) +#define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060 #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060) +#define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064 #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064) +#define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068 #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068) +#define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c) +#define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c #define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c) +#define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084 #define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084) +#define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 #define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088) +#define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c #define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c) +#define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094 #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094) +#define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098 #define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098) +#define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c) +#define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac) +#define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0 #define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0) +#define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4 #define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4) +#define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8 #define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8) +#define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc #define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc) +#define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0 #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0) +#define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4 #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4) +#define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4 #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4) /* PRM.L4PER_PRM register offsets */ +#define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000) +#define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004) +#define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024) +#define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028 #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028) +#define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c) +#define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030 #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030) +#define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034 #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034) +#define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038 #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038) +#define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c) +#define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040 #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040) +#define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044 #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044) +#define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048 #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048) +#define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c) +#define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050 #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050) +#define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054 #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054) +#define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c #define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c) +#define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 #define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060) +#define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 #define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064) +#define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 #define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068) +#define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c #define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c) +#define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 #define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070) +#define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 #define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074) +#define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 #define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078) +#define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c #define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c) +#define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 #define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080) +#define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 #define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084) +#define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c) +#define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090 #define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090) +#define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094 #define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094) +#define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098 #define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098) +#define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c #define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c) +#define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 #define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0) +#define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 #define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4) +#define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 #define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8) +#define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac #define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac) +#define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 #define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0) +#define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 #define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4) +#define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 #define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8) +#define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc #define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc) +#define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0 #define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0) +#define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0 #define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0) +#define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4 #define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4) +#define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8 #define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8) +#define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc #define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc) +#define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0 #define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0) +#define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4 #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4) +#define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec #define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec) +#define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 #define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0) +#define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4) +#define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 #define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8) +#define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc) +#define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 #define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100) +#define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104) +#define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 #define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108) +#define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c) +#define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120 #define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120) +#define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124 #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124) +#define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128 #define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128) +#define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c) +#define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134 #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134) +#define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138 #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138) +#define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c) +#define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 #define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140) +#define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 #define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144) +#define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 #define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148) +#define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c #define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c) +#define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 #define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150) +#define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 #define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154) +#define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 #define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158) +#define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c #define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c) +#define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160 #define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160) +#define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164 #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164) +#define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168 #define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168) +#define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c #define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c) +#define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 #define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4) +#define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac #define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac) +#define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4) +#define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc) +#define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 #define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4) +#define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc) +#define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc) /* PRM.CEFUSE_PRM register offsets */ +#define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000) +#define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004) +#define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024) /* PRM.WKUP_PRM register offsets */ +#define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024) +#define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c #define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c) +#define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030 #define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030) +#define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034 #define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034) +#define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038 #define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038) +#define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c #define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c) +#define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040 #define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040) +#define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044 #define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044) +#define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048 #define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048) +#define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c #define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c) +#define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054 #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054) +#define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058 #define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058) +#define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c #define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c) +#define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064 #define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064) +#define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078 #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078) +#define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c) +#define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080 #define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080) +#define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084 #define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084) /* PRM.WKUP_CM register offsets */ +#define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000) +#define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020) +#define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028 #define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028) +#define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030 #define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030) +#define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038 #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038) +#define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040 #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040) +#define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048 #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048) +#define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050 #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050) +#define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058 #define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058) +#define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060 #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060) +#define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078 #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078) +#define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080 #define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080) +#define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088 #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088) /* PRM.EMU_PRM register offsets */ +#define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000 #define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000) +#define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004 #define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004) +#define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024) /* PRM.EMU_CM register offsets */ +#define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000 #define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000) +#define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008 #define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008) +#define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020) /* PRM.DEVICE_PRM register offsets */ +#define OMAP4_PRM_RSTCTRL_OFFSET 0x0000 #define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000) +#define OMAP4_PRM_RSTST_OFFSET 0x0004 #define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004) +#define OMAP4_PRM_RSTTIME_OFFSET 0x0008 #define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008) +#define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c #define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c) +#define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010 #define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010) +#define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014 #define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014) +#define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018 #define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018) +#define OMAP4_PRM_IO_COUNT_OFFSET 0x001c #define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c) +#define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020 #define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020) +#define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 #define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024) +#define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 #define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028) +#define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c #define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c) +#define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030 #define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030) +#define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034) +#define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038) +#define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c) +#define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040 #define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040) +#define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044 #define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044) +#define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 #define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048) +#define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c #define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c) +#define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 #define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050) +#define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 #define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054) +#define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058 #define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058) +#define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c #define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c) +#define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 #define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060) +#define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 #define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064) +#define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 #define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068) +#define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c #define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c) +#define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070 #define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070) +#define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074 #define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074) +#define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078 #define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078) +#define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c #define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c) +#define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080 #define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080) +#define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084 #define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084) +#define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088 #define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088) +#define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c) +#define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090 #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090) +#define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094) +#define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098 #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098) +#define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c) +#define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0) +#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4) +#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8 #define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8) +#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac) +#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 #define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0) +#define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4 #define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4) +#define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8 #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8) +#define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc) +#define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0 #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0) +#define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4 #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4) +#define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8 #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8) +#define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc) +#define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0 #define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0) +#define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4 #define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4) +#define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8 #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) +#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) +#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET 0x00e0 #define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) +#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) +#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 #define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8) +#define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec) +#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) +#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) -/* CHIRON_PRCM */ - +/* + * PRCM_MPU + * + * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) + * point of view the PRCM_MPU is a single entity. It shares the same + * programming model as the global PRCM and thus can be assimilate as two new + * MOD inside the PRCM + */ -/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */ -#define OMAP4430_REVISION_PRCM OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000) +/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ +#define OMAP4_REVISION_PRCM_OFFSET 0x0000 +#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000) -/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */ -#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000) +/* PRCM_MPU.DEVICE_PRM register offsets */ +#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 +#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000) -/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */ -#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000) -#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004) -#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008) -#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c) -#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010) -#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014) -#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018) +/* PRCM_MPU.CPU0 register offsets */ +#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 +#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000) +#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 +#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004) +#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 +#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008) +#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c +#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c) +#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 +#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010) +#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 +#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014) +#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 +#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018) -/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */ -#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000) -#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004) -#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008) -#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c) -#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010) -#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014) -#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018) +/* PRCM_MPU.CPU1 register offsets */ +#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 +#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000) +#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 +#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004) +#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 +#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008) +#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c +#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c) +#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 +#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010) +#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 +#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014) +#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 +#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018) #endif diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c index ee9f548d5d8..c68f799e83c 100644 --- a/arch/arm/mach-omap2/usb-ehci.c +++ b/arch/arm/mach-omap2/usb-ehci.c @@ -236,3 +236,158 @@ void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata) #endif /* CONFIG_USB_EHCI_HCD */ +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) + +static struct resource ohci_resources[] = { + { + .start = OMAP34XX_OHCI_BASE, + .end = OMAP34XX_OHCI_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP34XX_UHH_CONFIG_BASE, + .end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP34XX_USBTLL_BASE, + .end = OMAP34XX_USBTLL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { /* general IRQ */ + .start = INT_34XX_OHCI_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 ohci_dmamask = DMA_BIT_MASK(32); + +static struct platform_device ohci_device = { + .name = "ohci-omap3", + .id = 0, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(ohci_resources), + .resource = ohci_resources, +}; + +static void setup_ohci_io_mux(const enum ohci_omap3_port_mode *port_mode) +{ + switch (port_mode[0]) { + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: + omap_mux_init_signal("mm1_rxdp", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("mm1_rxdm", + OMAP_PIN_INPUT_PULLDOWN); + /* FALLTHROUGH */ + case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: + omap_mux_init_signal("mm1_rxrcv", + OMAP_PIN_INPUT_PULLDOWN); + /* FALLTHROUGH */ + case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: + omap_mux_init_signal("mm1_txen_n", OMAP_PIN_OUTPUT); + /* FALLTHROUGH */ + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: + omap_mux_init_signal("mm1_txse0", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("mm1_txdat", + OMAP_PIN_INPUT_PULLDOWN); + break; + case OMAP_OHCI_PORT_MODE_UNUSED: + /* FALLTHROUGH */ + default: + break; + } + switch (port_mode[1]) { + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: + omap_mux_init_signal("mm2_rxdp", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("mm2_rxdm", + OMAP_PIN_INPUT_PULLDOWN); + /* FALLTHROUGH */ + case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: + omap_mux_init_signal("mm2_rxrcv", + OMAP_PIN_INPUT_PULLDOWN); + /* FALLTHROUGH */ + case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: + omap_mux_init_signal("mm2_txen_n", OMAP_PIN_OUTPUT); + /* FALLTHROUGH */ + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: + omap_mux_init_signal("mm2_txse0", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("mm2_txdat", + OMAP_PIN_INPUT_PULLDOWN); + break; + case OMAP_OHCI_PORT_MODE_UNUSED: + /* FALLTHROUGH */ + default: + break; + } + switch (port_mode[2]) { + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: + omap_mux_init_signal("mm3_rxdp", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("mm3_rxdm", + OMAP_PIN_INPUT_PULLDOWN); + /* FALLTHROUGH */ + case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: + omap_mux_init_signal("mm3_rxrcv", + OMAP_PIN_INPUT_PULLDOWN); + /* FALLTHROUGH */ + case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: + omap_mux_init_signal("mm3_txen_n", OMAP_PIN_OUTPUT); + /* FALLTHROUGH */ + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: + omap_mux_init_signal("mm3_txse0", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("mm3_txdat", + OMAP_PIN_INPUT_PULLDOWN); + break; + case OMAP_OHCI_PORT_MODE_UNUSED: + /* FALLTHROUGH */ + default: + break; + } +} + +void __init usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata) +{ + platform_device_add_data(&ohci_device, pdata, sizeof(*pdata)); + + /* Setup Pin IO MUX for OHCI */ + if (cpu_is_omap34xx()) + setup_ohci_io_mux(pdata->port_mode); + + if (platform_device_register(&ohci_device) < 0) { + pr_err("Unable to register FS-USB (OHCI) device\n"); + return; + } +} + +#else + +void __init usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata) +{ +} + +#endif /* CONFIG_USB_OHCI_HCD */ diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 6d41fa7b2ce..96f6787e00b 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -107,6 +107,7 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) musb_plat.board_data = board_data; musb_plat.power = board_data->power >> 1; musb_plat.mode = board_data->mode; + musb_plat.extvbus = board_data->extvbus; if (platform_device_register(&musb_device) < 0) printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 421b82f7c63..685f34a9634 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -439,6 +439,7 @@ static void __init dns323_init(void) */ if (dns323_dev_id() == MV88F5181_DEV_ID) { dns323_leds[0].active_low = 1; + gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable"); gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); } diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 5b6ee46fa7f..3b51741a481 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -19,7 +19,6 @@ config MACH_MAINSTONE config MACH_ZYLONITE bool select PXA3xx - select PXA_SSP select HAVE_PWM select PXA_HAVE_BOARD_IRQS @@ -39,7 +38,6 @@ config MACH_LITTLETON select PXA3xx select CPU_PXA300 select CPU_PXA310 - select PXA_SSP config MACH_TAVOREVB bool "PXA930 Evaluation Board (aka TavorEVB)" @@ -98,7 +96,6 @@ config MACH_ARMCORE select PXA27x select IWMMXT select PXA25x - select PXA_SSP config MACH_EM_X270 bool "CompuLab EM-x270 platform" @@ -161,7 +158,6 @@ config MACH_XCEP select MTD_CFI select MTD_CHAR select SMC91X - select PXA_SSP help PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash. Tuned for usage in Libera instruments for particle accelerators. @@ -180,7 +176,6 @@ config MACH_TRIZEPS4WL depends on TRIZEPS_PXA select TRIZEPS_PCMCIA select PXA27x - select PXA_SSP choice prompt "Select base board for Trizeps module" @@ -217,7 +212,6 @@ config MACH_PCM027 bool "Phytec phyCORE-PXA270 CPU module (PCM-027)" select PXA27x select IWMMXT - select PXA_SSP select PXA_HAVE_BOARD_IRQS config MACH_PCM990_BASEBOARD @@ -255,13 +249,19 @@ config MACH_COLIBRI320 select PXA3xx select CPU_PXA320 +config MACH_VPAC270 + bool "Voipac PXA270" + select PXA27x + select HAVE_PATA_PLATFORM + help + PXA270 based Single Board Computer. + comment "End-user Products (sorted by vendor name)" config MACH_H4700 bool "HP iPAQ hx4700" select PXA27x select IWMMXT - select PXA_SSP select HAVE_PWM select PXA_HAVE_BOARD_IRQS @@ -277,7 +277,6 @@ config MACH_MAGICIAN bool "Enable HTC Magician Support" select PXA27x select IWMMXT - select PXA_SSP select HAVE_PWM select PXA_HAVE_BOARD_IRQS @@ -431,13 +430,11 @@ config MACH_RAUMFELD_CONNECTOR bool "Raumfeld Connector" select PXA3xx select CPU_PXA300 - select PXA_SSP config MACH_RAUMFELD_SPEAKER bool "Raumfeld Speaker" select PXA3xx select CPU_PXA300 - select PXA_SSP config PXA_SHARPSL bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" @@ -461,21 +458,11 @@ config SHARPSL_PM_MAX1111 select HWMON select SENSORS_MAX1111 -config CORGI_SSP_DEPRECATED - bool - select PXA_SSP - select PXA_SSP_LEGACY - help - This option will include corgi_ssp.c and corgi_lcd.c - that corgi_ts.c and other legacy drivers (corgi_bl.c - and sharpsl_pm.c) may depend on. - config MACH_POODLE bool "Enable Sharp SL-5600 (Poodle) Support" depends on PXA_SHARPSL select PXA25x select SHARP_LOCOMO - select PXA_SSP select PXA_HAVE_BOARD_IRQS config MACH_CORGI @@ -581,6 +568,12 @@ config MACH_E800 Say Y here if you intend to run this kernel on a Toshiba e800 family PDA. +config MACH_ZIPIT2 + bool "Zipit Z2 Handheld" + select PXA27x + select HAVE_PWM + select PXA_HAVE_BOARD_IRQS + endmenu config PXA25x @@ -645,28 +638,16 @@ config CPU_PXA950 config PXA_SHARP_C7xx bool - select PXA_SSP select SHARPSL_PM help Enable support for all Sharp C7xx models config PXA_SHARP_Cxx00 bool - select PXA_SSP select SHARPSL_PM help Enable common support for Sharp Cxx00 models -config PXA_SSP - tristate - help - Enable support for PXA2xx SSP ports - -config PXA_SSP_LEGACY - bool - help - Support of legacy SSP API - config TOSA_BT tristate "Control the state of built-in bluetooth chip on Sharp SL-6000" depends on MACH_TOSA @@ -675,6 +656,18 @@ config TOSA_BT This is a simple driver that is able to control the state of built in bluetooth chip on tosa. +config TOSA_USE_EXT_KEYCODES + bool "Tosa keyboard: use extended keycodes" + depends on MACH_TOSA + default n + help + Say Y here to enable the tosa keyboard driver to generate extended + (>= 127) keycodes. Be aware, that they can't be correctly interpreted + by either console keyboard driver or by Kdrive keybd driver. + + Say Y only if you know, what you are doing! + + config PXA_HAVE_BOARD_IRQS bool diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 86bc87b7f2d..b8f1f4bc7ca 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_PXA3xx) += cpufreq-pxa3xx.o endif # Generic drivers that other drivers may depend upon -obj-$(CONFIG_PXA_SSP) += ssp.o # SoC-specific code obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o @@ -62,6 +61,7 @@ obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o +obj-$(CONFIG_MACH_VPAC270) += vpac270.o # End-user Products obj-$(CONFIG_MACH_H4700) += hx4700.o @@ -80,7 +80,6 @@ obj-$(CONFIG_MACH_PALMLD) += palmld.o obj-$(CONFIG_PALM_TREO) += palmtreo.o obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o -obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o obj-$(CONFIG_MACH_POODLE) += poodle.o obj-$(CONFIG_MACH_TOSA) += tosa.o obj-$(CONFIG_MACH_ICONTROL) += icontrol.o mxm8x10.o @@ -94,6 +93,7 @@ obj-$(CONFIG_MACH_E800) += e800.o obj-$(CONFIG_MACH_RAUMFELD_RC) += raumfeld.o obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR) += raumfeld.o obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o +obj-$(CONFIG_MACH_ZIPIT2) += z2.o # Support for blinky lights led-y := leds.o diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index d37cfa132a6..fdda6be6c39 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -30,6 +30,9 @@ #include <linux/i2c/pca953x.h> #include <linux/mfd/da903x.h> +#include <linux/regulator/machine.h> +#include <linux/power_supply.h> +#include <linux/apm-emulation.h> #include <linux/spi/spi.h> #include <linux/spi/spi_gpio.h> @@ -430,7 +433,7 @@ static inline void cm_x300_init_nand(void) {} #if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE) static struct pxamci_platform_data cm_x300_mci_platform_data = { - .detect_delay = 20, + .detect_delay_ms = 200, .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .gpio_card_detect = GPIO82_MMC_IRQ, .gpio_card_ro = GPIO85_MMC_WP, @@ -451,7 +454,7 @@ static void cm_x300_mci2_exit(struct device *dev, void *data) } static struct pxamci_platform_data cm_x300_mci2_platform_data = { - .detect_delay = 20, + .detect_delay_ms = 200, .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .init = cm_x300_mci2_init, .exit = cm_x300_mci2_exit, @@ -584,12 +587,87 @@ static void __init cm_x300_init_rtc(void) static inline void cm_x300_init_rtc(void) {} #endif +/* Battery */ +struct power_supply_info cm_x300_psy_info = { + .name = "battery", + .technology = POWER_SUPPLY_TECHNOLOGY_LIPO, + .voltage_max_design = 4200000, + .voltage_min_design = 3000000, + .use_for_apm = 1, +}; + +static void cm_x300_battery_low(void) +{ +#if defined(CONFIG_APM_EMULATION) + apm_queue_event(APM_LOW_BATTERY); +#endif +} + +static void cm_x300_battery_critical(void) +{ +#if defined(CONFIG_APM_EMULATION) + apm_queue_event(APM_CRITICAL_SUSPEND); +#endif +} + +struct da9030_battery_info cm_x300_battery_info = { + .battery_info = &cm_x300_psy_info, + + .charge_milliamp = 1000, + .charge_millivolt = 4200, + + .vbat_low = 3600, + .vbat_crit = 3400, + .vbat_charge_start = 4100, + .vbat_charge_stop = 4200, + .vbat_charge_restart = 4000, + + .vcharge_min = 3200, + .vcharge_max = 5500, + + .tbat_low = 197, + .tbat_high = 78, + .tbat_restart = 100, + + .batmon_interval = 0, + + .battery_low = cm_x300_battery_low, + .battery_critical = cm_x300_battery_critical, +}; + +static struct regulator_consumer_supply buck2_consumers[] = { + { + .dev = NULL, + .supply = "vcc_core", + }, +}; + +static struct regulator_init_data buck2_data = { + .constraints = { + .min_uV = 1375000, + .max_uV = 1375000, + .state_mem = { + .enabled = 0, + }, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .apply_uV = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(buck2_consumers), + .consumer_supplies = buck2_consumers, +}; + /* DA9030 */ struct da903x_subdev_info cm_x300_da9030_subdevs[] = { { - .name = "da903x-backlight", - .id = DA9030_ID_WLED, - } + .name = "da903x-battery", + .id = DA9030_ID_BAT, + .platform_data = &cm_x300_battery_info, + }, + { + .name = "da903x-regulator", + .id = DA9030_ID_BUCK2, + .platform_data = &buck2_data, + }, }; static struct da903x_platform_data cm_x300_da9030_info = { @@ -599,7 +677,7 @@ static struct da903x_platform_data cm_x300_da9030_info = { static struct i2c_board_info cm_x300_pmic_info = { I2C_BOARD_INFO("da9030", 0x49), - .irq = IRQ_GPIO(0), + .irq = IRQ_WAKEUP0, .platform_data = &cm_x300_da9030_info, }; @@ -689,13 +767,13 @@ static void __init cm_x300_init(void) static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags, char **cmdline, struct meminfo *mi) { - mi->nr_banks = 2; - mi->bank[0].start = 0xa0000000; - mi->bank[0].node = 0; - mi->bank[0].size = (64*1024*1024); - mi->bank[1].start = 0xc0000000; - mi->bank[1].node = 0; - mi->bank[1].size = (64*1024*1024); + /* Make sure that mi->bank[0].start = PHYS_ADDR */ + for (; tags->hdr.size; tags = tag_next(tags)) + if (tags->hdr.tag == ATAG_MEM && + tags->u.mem.start == 0x80000000) { + tags->u.mem.start = 0xa0000000; + break; + } } MACHINE_START(CM_X300, "CM-X300 module") diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index e6c0a2287eb..199afa2ae30 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c @@ -96,7 +96,7 @@ static void colibri_pxa3xx_mci_exit(struct device *dev, void *data) } static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = { - .detect_delay = 20, + .detect_delay_ms = 200, .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .init = colibri_pxa3xx_mci_init, .exit = colibri_pxa3xx_mci_exit, diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index da3156d8690..3d1dcb9ac08 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -106,18 +106,18 @@ static unsigned long corgi_pin_config[] __initdata = { GPIO8_MMC_CS0, /* GPIO Matrix Keypad */ - GPIO66_GPIO, /* column 0 */ - GPIO67_GPIO, /* column 1 */ - GPIO68_GPIO, /* column 2 */ - GPIO69_GPIO, /* column 3 */ - GPIO70_GPIO, /* column 4 */ - GPIO71_GPIO, /* column 5 */ - GPIO72_GPIO, /* column 6 */ - GPIO73_GPIO, /* column 7 */ - GPIO74_GPIO, /* column 8 */ - GPIO75_GPIO, /* column 9 */ - GPIO76_GPIO, /* column 10 */ - GPIO77_GPIO, /* column 11 */ + GPIO66_GPIO | MFP_LPM_DRIVE_HIGH, /* column 0 */ + GPIO67_GPIO | MFP_LPM_DRIVE_HIGH, /* column 1 */ + GPIO68_GPIO | MFP_LPM_DRIVE_HIGH, /* column 2 */ + GPIO69_GPIO | MFP_LPM_DRIVE_HIGH, /* column 3 */ + GPIO70_GPIO | MFP_LPM_DRIVE_HIGH, /* column 4 */ + GPIO71_GPIO | MFP_LPM_DRIVE_HIGH, /* column 5 */ + GPIO72_GPIO | MFP_LPM_DRIVE_HIGH, /* column 6 */ + GPIO73_GPIO | MFP_LPM_DRIVE_HIGH, /* column 7 */ + GPIO74_GPIO | MFP_LPM_DRIVE_HIGH, /* column 8 */ + GPIO75_GPIO | MFP_LPM_DRIVE_HIGH, /* column 9 */ + GPIO76_GPIO | MFP_LPM_DRIVE_HIGH, /* column 10 */ + GPIO77_GPIO | MFP_LPM_DRIVE_HIGH, /* column 11 */ GPIO58_GPIO, /* row 0 */ GPIO59_GPIO, /* row 1 */ GPIO60_GPIO, /* row 2 */ @@ -128,13 +128,20 @@ static unsigned long corgi_pin_config[] __initdata = { GPIO65_GPIO, /* row 7 */ /* GPIO */ - GPIO9_GPIO, /* CORGI_GPIO_nSD_DETECT */ - GPIO7_GPIO, /* CORGI_GPIO_nSD_WP */ - GPIO33_GPIO, /* CORGI_GPIO_SD_PWR */ - GPIO22_GPIO, /* CORGI_GPIO_IR_ON */ - GPIO44_GPIO, /* CORGI_GPIO_HSYNC */ - - GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, + GPIO9_GPIO, /* CORGI_GPIO_nSD_DETECT */ + GPIO7_GPIO, /* CORGI_GPIO_nSD_WP */ + GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* CORGI_GPIO_MAIN_BAT_{LOW,COVER} */ + GPIO13_GPIO | MFP_LPM_KEEP_OUTPUT, /* CORGI_GPIO_LED_ORANGE */ + GPIO21_GPIO, /* CORGI_GPIO_ADC_TEMP */ + GPIO22_GPIO, /* CORGI_GPIO_IR_ON */ + GPIO33_GPIO, /* CORGI_GPIO_SD_PWR */ + GPIO38_GPIO | MFP_LPM_KEEP_OUTPUT, /* CORGI_GPIO_CHRG_ON */ + GPIO43_GPIO | MFP_LPM_KEEP_OUTPUT, /* CORGI_GPIO_CHRG_UKN */ + GPIO44_GPIO, /* CORGI_GPIO_HSYNC */ + + GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* CORGI_GPIO_KEY_INT */ + GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, /* CORGI_GPIO_AC_IN */ + GPIO3_GPIO | WAKEUP_ON_EDGE_BOTH, /* CORGI_GPIO_WAKEUP */ }; /* @@ -437,6 +444,7 @@ static struct platform_device corgiled_device = { * to give the card a chance to fully insert/eject. */ static struct pxamci_platform_data corgi_mci_platform_data = { + .detect_delay_ms = 250, .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .gpio_card_detect = -1, .gpio_card_ro = CORGI_GPIO_nSD_WP, @@ -672,6 +680,15 @@ static void __init corgi_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(corgi_pin_config)); + /* allow wakeup from various GPIOs */ + gpio_set_wake(CORGI_GPIO_KEY_INT, 1); + gpio_set_wake(CORGI_GPIO_WAKEUP, 1); + gpio_set_wake(CORGI_GPIO_AC_IN, 1); + gpio_set_wake(CORGI_GPIO_CHRG_FULL, 1); + + if (!machine_is_corgi()) + gpio_set_wake(CORGI_GPIO_MAIN_BAT_LOW, 1); + pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); @@ -679,7 +696,6 @@ static void __init corgi_init(void) corgi_init_spi(); pxa_set_udc_info(&udc_info); - corgi_mci_platform_data.detect_delay = msecs_to_jiffies(250); pxa_set_mci_info(&corgi_mci_platform_data); pxa_set_ficp_info(&corgi_ficp_platform_data); pxa_set_i2c_info(NULL); diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c deleted file mode 100644 index d9b96319d49..00000000000 --- a/arch/arm/mach-pxa/corgi_lcd.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * linux/arch/arm/mach-pxa/corgi_lcd.c - * - * Corgi/Spitz LCD Specific Code - * - * Copyright (C) 2005 Richard Purdie - * - * Connectivity: - * Corgi - LCD to ATI Imageon w100 (Wallaby) - * Spitz - LCD to PXA Framebuffer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/delay.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/module.h> -#include <linux/string.h> -#include <mach/corgi.h> -#include <mach/hardware.h> -#include <mach/sharpsl.h> -#include <mach/spitz.h> -#include <asm/hardware/scoop.h> -#include <asm/mach/sharpsl_param.h> -#include "generic.h" - -/* Register Addresses */ -#define RESCTL_ADRS 0x00 -#define PHACTRL_ADRS 0x01 -#define DUTYCTRL_ADRS 0x02 -#define POWERREG0_ADRS 0x03 -#define POWERREG1_ADRS 0x04 -#define GPOR3_ADRS 0x05 -#define PICTRL_ADRS 0x06 -#define POLCTRL_ADRS 0x07 - -/* Register Bit Definitions */ -#define RESCTL_QVGA 0x01 -#define RESCTL_VGA 0x00 - -#define POWER1_VW_ON 0x01 /* VW Supply FET ON */ -#define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */ -#define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */ - -#define POWER1_VW_OFF 0x00 /* VW Supply FET OFF */ -#define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */ -#define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */ - -#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */ -#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */ -#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */ -#define POWER0_COM_ON 0x08 /* COM Power Supply ON */ -#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */ - -#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */ -#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */ -#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */ - -#define PICTRL_INIT_STATE 0x01 -#define PICTRL_INIOFF 0x02 -#define PICTRL_POWER_DOWN 0x04 -#define PICTRL_COM_SIGNAL_OFF 0x08 -#define PICTRL_DAC_SIGNAL_OFF 0x10 - -#define POLCTRL_SYNC_POL_FALL 0x01 -#define POLCTRL_EN_POL_FALL 0x02 -#define POLCTRL_DATA_POL_FALL 0x04 -#define POLCTRL_SYNC_ACT_H 0x08 -#define POLCTRL_EN_ACT_L 0x10 - -#define POLCTRL_SYNC_POL_RISE 0x00 -#define POLCTRL_EN_POL_RISE 0x00 -#define POLCTRL_DATA_POL_RISE 0x00 -#define POLCTRL_SYNC_ACT_L 0x00 -#define POLCTRL_EN_ACT_H 0x00 - -#define PHACTRL_PHASE_MANUAL 0x01 -#define DEFAULT_PHAD_QVGA (9) -#define DEFAULT_COMADJ (125) - -/* - * This is only a psuedo I2C interface. We can't use the standard kernel - * routines as the interface is write only. We just assume the data is acked... - */ -static void lcdtg_ssp_i2c_send(u8 data) -{ - corgi_ssp_lcdtg_send(POWERREG0_ADRS, data); - udelay(10); -} - -static void lcdtg_i2c_send_bit(u8 data) -{ - lcdtg_ssp_i2c_send(data); - lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK); - lcdtg_ssp_i2c_send(data); -} - -static void lcdtg_i2c_send_start(u8 base) -{ - lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT); - lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK); - lcdtg_ssp_i2c_send(base); -} - -static void lcdtg_i2c_send_stop(u8 base) -{ - lcdtg_ssp_i2c_send(base); - lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK); - lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT); -} - -static void lcdtg_i2c_send_byte(u8 base, u8 data) -{ - int i; - for (i = 0; i < 8; i++) { - if (data & 0x80) - lcdtg_i2c_send_bit(base | POWER0_COM_DOUT); - else - lcdtg_i2c_send_bit(base); - data <<= 1; - } -} - -static void lcdtg_i2c_wait_ack(u8 base) -{ - lcdtg_i2c_send_bit(base); -} - -static void lcdtg_set_common_voltage(u8 base_data, u8 data) -{ - /* Set Common Voltage to M62332FP via I2C */ - lcdtg_i2c_send_start(base_data); - lcdtg_i2c_send_byte(base_data, 0x9c); - lcdtg_i2c_wait_ack(base_data); - lcdtg_i2c_send_byte(base_data, 0x00); - lcdtg_i2c_wait_ack(base_data); - lcdtg_i2c_send_byte(base_data, data); - lcdtg_i2c_wait_ack(base_data); - lcdtg_i2c_send_stop(base_data); -} - -/* Set Phase Adjust */ -static void lcdtg_set_phadadj(int mode) -{ - int adj; - switch(mode) { - case 480: - case 640: - /* Setting for VGA */ - adj = sharpsl_param.phadadj; - if (adj < 0) { - adj = PHACTRL_PHASE_MANUAL; - } else { - adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL; - } - break; - case 240: - case 320: - default: - /* Setting for QVGA */ - adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL; - break; - } - - corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj); -} - -static int lcd_inited; - -void corgi_lcdtg_hw_init(int mode) -{ - if (!lcd_inited) { - int comadj; - - /* Initialize Internal Logic & Port */ - corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE - | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF); - - corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF - | POWER0_COM_OFF | POWER0_VCC5_OFF); - - corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF); - - /* VDD(+8V), SVSS(-4V) ON */ - corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON); - mdelay(3); - - /* DAC ON */ - corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON - | POWER0_COM_OFF | POWER0_VCC5_OFF); - - /* INIB = H, INI = L */ - /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */ - corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF); - - /* Set Common Voltage */ - comadj = sharpsl_param.comadj; - if (comadj < 0) - comadj = DEFAULT_COMADJ; - lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj); - - /* VCC5 ON, DAC ON */ - corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON | - POWER0_COM_OFF | POWER0_VCC5_ON); - - /* GVSS(-8V) ON, VDD ON */ - corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON); - mdelay(2); - - /* COM SIGNAL ON (PICTL[3] = L) */ - corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE); - - /* COM ON, DAC ON, VCC5_ON */ - corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON - | POWER0_COM_ON | POWER0_VCC5_ON); - - /* VW ON, GVSS ON, VDD ON */ - corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON); - - /* Signals output enable */ - corgi_ssp_lcdtg_send(PICTRL_ADRS, 0); - - /* Set Phase Adjust */ - lcdtg_set_phadadj(mode); - - /* Initialize for Input Signals from ATI */ - corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE - | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H); - udelay(1000); - - lcd_inited=1; - } else { - lcdtg_set_phadadj(mode); - } - - switch(mode) { - case 480: - case 640: - /* Set Lcd Resolution (VGA) */ - corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA); - break; - case 240: - case 320: - default: - /* Set Lcd Resolution (QVGA) */ - corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA); - break; - } -} - -void corgi_lcdtg_suspend(void) -{ - /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */ - mdelay(34); - - /* (1)VW OFF */ - corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON); - - /* (2)COM OFF */ - corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF); - corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON); - - /* (3)Set Common Voltage Bias 0V */ - lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0); - - /* (4)GVSS OFF */ - corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON); - - /* (5)VCC5 OFF */ - corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF); - - /* (6)Set PDWN, INIOFF, DACOFF */ - corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF | - PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF); - - /* (7)DAC OFF */ - corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF); - - /* (8)VDD OFF */ - corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF); - - lcd_inited = 0; -} - diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index d4a0733e905..3f1dc74ac04 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c @@ -14,6 +14,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/delay.h> +#include <linux/gpio.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/apm-emulation.h> @@ -25,7 +26,8 @@ #include <mach/sharpsl.h> #include <mach/corgi.h> #include <mach/pxa2xx-regs.h> -#include <mach/pxa2xx-gpio.h> + +#include "generic.h" #include "sharpsl.h" #define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */ @@ -35,87 +37,46 @@ #define SHARPSL_FATAL_ACIN_VOLT 182 /* 3.45V */ #define SHARPSL_FATAL_NOACIN_VOLT 170 /* 3.40V */ +static struct gpio charger_gpios[] = { + { CORGI_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" }, + { CORGI_GPIO_CHRG_ON, GPIOF_OUT_INIT_LOW, "Charger On" }, + { CORGI_GPIO_CHRG_UKN, GPIOF_OUT_INIT_LOW, "Charger Unknown" }, + { CORGI_GPIO_KEY_INT, GPIOF_IN, "Key Interrupt" }, +}; + static void corgi_charger_init(void) { - pxa_gpio_mode(CORGI_GPIO_ADC_TEMP_ON | GPIO_OUT); - pxa_gpio_mode(CORGI_GPIO_CHRG_ON | GPIO_OUT); - pxa_gpio_mode(CORGI_GPIO_CHRG_UKN | GPIO_OUT); - pxa_gpio_mode(CORGI_GPIO_KEY_INT | GPIO_IN); + gpio_request_array(ARRAY_AND_SIZE(charger_gpios)); } static void corgi_measure_temp(int on) { - if (on) - GPSR(CORGI_GPIO_ADC_TEMP_ON) = GPIO_bit(CORGI_GPIO_ADC_TEMP_ON); - else - GPCR(CORGI_GPIO_ADC_TEMP_ON) = GPIO_bit(CORGI_GPIO_ADC_TEMP_ON); + gpio_set_value(CORGI_GPIO_ADC_TEMP_ON, on); } static void corgi_charge(int on) { if (on) { if (machine_is_corgi() && (sharpsl_pm.flags & SHARPSL_SUSPENDED)) { - GPCR(CORGI_GPIO_CHRG_ON) = GPIO_bit(CORGI_GPIO_CHRG_ON); - GPSR(CORGI_GPIO_CHRG_UKN) = GPIO_bit(CORGI_GPIO_CHRG_UKN); + gpio_set_value(CORGI_GPIO_CHRG_ON, 0); + gpio_set_value(CORGI_GPIO_CHRG_UKN, 1); } else { - GPSR(CORGI_GPIO_CHRG_ON) = GPIO_bit(CORGI_GPIO_CHRG_ON); - GPCR(CORGI_GPIO_CHRG_UKN) = GPIO_bit(CORGI_GPIO_CHRG_UKN); + gpio_set_value(CORGI_GPIO_CHRG_ON, 1); + gpio_set_value(CORGI_GPIO_CHRG_UKN, 0); } } else { - GPCR(CORGI_GPIO_CHRG_ON) = GPIO_bit(CORGI_GPIO_CHRG_ON); - GPCR(CORGI_GPIO_CHRG_UKN) = GPIO_bit(CORGI_GPIO_CHRG_UKN); + gpio_set_value(CORGI_GPIO_CHRG_ON, 0); + gpio_set_value(CORGI_GPIO_CHRG_UKN, 0); } } static void corgi_discharge(int on) { - if (on) - GPSR(CORGI_GPIO_DISCHARGE_ON) = GPIO_bit(CORGI_GPIO_DISCHARGE_ON); - else - GPCR(CORGI_GPIO_DISCHARGE_ON) = GPIO_bit(CORGI_GPIO_DISCHARGE_ON); + gpio_set_value(CORGI_GPIO_DISCHARGE_ON, on); } static void corgi_presuspend(void) { - int i; - unsigned long wakeup_mask; - - /* charging , so CHARGE_ON bit is HIGH during OFF. */ - if (READ_GPIO_BIT(CORGI_GPIO_CHRG_ON)) - PGSR1 |= GPIO_bit(CORGI_GPIO_CHRG_ON); - else - PGSR1 &= ~GPIO_bit(CORGI_GPIO_CHRG_ON); - - if (READ_GPIO_BIT(CORGI_GPIO_LED_ORANGE)) - PGSR0 |= GPIO_bit(CORGI_GPIO_LED_ORANGE); - else - PGSR0 &= ~GPIO_bit(CORGI_GPIO_LED_ORANGE); - - if (READ_GPIO_BIT(CORGI_GPIO_CHRG_UKN)) - PGSR1 |= GPIO_bit(CORGI_GPIO_CHRG_UKN); - else - PGSR1 &= ~GPIO_bit(CORGI_GPIO_CHRG_UKN); - - /* Resume on keyboard power key */ - PGSR2 = (PGSR2 & ~CORGI_GPIO_ALL_STROBE_BIT) | CORGI_GPIO_STROBE_BIT(0); - - wakeup_mask = GPIO_bit(CORGI_GPIO_KEY_INT) | GPIO_bit(CORGI_GPIO_WAKEUP) | GPIO_bit(CORGI_GPIO_AC_IN) | GPIO_bit(CORGI_GPIO_CHRG_FULL); - - if (!machine_is_corgi()) - wakeup_mask |= GPIO_bit(CORGI_GPIO_MAIN_BAT_LOW); - - PWER = wakeup_mask | PWER_RTC; - PRER = wakeup_mask; - PFER = wakeup_mask; - - for (i = 0; i <=15; i++) { - if (PRER & PFER & GPIO_bit(i)) { - if (GPLR0 & GPIO_bit(i) ) - PRER &= ~GPIO_bit(i); - else - PFER &= ~GPIO_bit(i); - } - } } static void corgi_postsuspend(void) diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c deleted file mode 100644 index 9347254f8bc..00000000000 --- a/arch/arm/mach-pxa/corgi_ssp.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * SSP control code for Sharp Corgi devices - * - * Copyright (c) 2004-2005 Richard Purdie - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/module.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#include <mach/ssp.h> -#include <mach/pxa2xx-gpio.h> -#include <mach/regs-ssp.h> -#include "sharpsl.h" - -static DEFINE_SPINLOCK(corgi_ssp_lock); -static struct ssp_dev corgi_ssp_dev; -static struct ssp_state corgi_ssp_state; -static struct corgissp_machinfo *ssp_machinfo; - -/* - * There are three devices connected to the SSP interface: - * 1. A touchscreen controller (TI ADS7846 compatible) - * 2. An LCD controller (with some Backlight functionality) - * 3. A battery monitoring IC (Maxim MAX1111) - * - * Each device uses a different speed/mode of communication. - * - * The touchscreen is very sensitive and the most frequently used - * so the port is left configured for this. - * - * Devices are selected using Chip Selects on GPIOs. - */ - -/* - * ADS7846 Routines - */ -unsigned long corgi_ssp_ads7846_putget(ulong data) -{ - unsigned long flag; - u32 ret = 0; - - spin_lock_irqsave(&corgi_ssp_lock, flag); - if (ssp_machinfo->cs_ads7846 >= 0) - GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); - - ssp_write_word(&corgi_ssp_dev,data); - ssp_read_word(&corgi_ssp_dev, &ret); - - if (ssp_machinfo->cs_ads7846 >= 0) - GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); - spin_unlock_irqrestore(&corgi_ssp_lock, flag); - - return ret; -} - -/* - * NOTE: These functions should always be called in interrupt context - * and use the _lock and _unlock functions. They are very time sensitive. - */ -void corgi_ssp_ads7846_lock(void) -{ - spin_lock(&corgi_ssp_lock); - if (ssp_machinfo->cs_ads7846 >= 0) - GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); -} - -void corgi_ssp_ads7846_unlock(void) -{ - if (ssp_machinfo->cs_ads7846 >= 0) - GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); - spin_unlock(&corgi_ssp_lock); -} - -void corgi_ssp_ads7846_put(ulong data) -{ - ssp_write_word(&corgi_ssp_dev,data); -} - -unsigned long corgi_ssp_ads7846_get(void) -{ - u32 ret = 0; - ssp_read_word(&corgi_ssp_dev, &ret); - return ret; -} - -EXPORT_SYMBOL(corgi_ssp_ads7846_putget); -EXPORT_SYMBOL(corgi_ssp_ads7846_lock); -EXPORT_SYMBOL(corgi_ssp_ads7846_unlock); -EXPORT_SYMBOL(corgi_ssp_ads7846_put); -EXPORT_SYMBOL(corgi_ssp_ads7846_get); - - -/* - * LCD/Backlight Routines - */ -unsigned long corgi_ssp_dac_put(ulong data) -{ - unsigned long flag, sscr1 = SSCR1_SPH; - u32 tmp; - - spin_lock_irqsave(&corgi_ssp_lock, flag); - - if (machine_is_spitz() || machine_is_akita() || machine_is_borzoi()) - sscr1 = 0; - - ssp_disable(&corgi_ssp_dev); - ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), sscr1, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_lcdcon)); - ssp_enable(&corgi_ssp_dev); - - if (ssp_machinfo->cs_lcdcon >= 0) - GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); - ssp_write_word(&corgi_ssp_dev,data); - /* Read null data back from device to prevent SSP overflow */ - ssp_read_word(&corgi_ssp_dev, &tmp); - if (ssp_machinfo->cs_lcdcon >= 0) - GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); - - ssp_disable(&corgi_ssp_dev); - ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846)); - ssp_enable(&corgi_ssp_dev); - - spin_unlock_irqrestore(&corgi_ssp_lock, flag); - - return 0; -} - -void corgi_ssp_lcdtg_send(u8 adrs, u8 data) -{ - corgi_ssp_dac_put(((adrs & 0x07) << 5) | (data & 0x1f)); -} - -void corgi_ssp_blduty_set(int duty) -{ - corgi_ssp_lcdtg_send(0x02,duty); -} - -EXPORT_SYMBOL(corgi_ssp_lcdtg_send); -EXPORT_SYMBOL(corgi_ssp_blduty_set); - -/* - * Max1111 Routines - */ -int corgi_ssp_max1111_get(ulong data) -{ - unsigned long flag; - long voltage = 0, voltage1 = 0, voltage2 = 0; - - spin_lock_irqsave(&corgi_ssp_lock, flag); - if (ssp_machinfo->cs_max1111 >= 0) - GPCR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111); - ssp_disable(&corgi_ssp_dev); - ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_max1111)); - ssp_enable(&corgi_ssp_dev); - - udelay(1); - - /* TB1/RB1 */ - ssp_write_word(&corgi_ssp_dev,data); - ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); /* null read */ - - /* TB12/RB2 */ - ssp_write_word(&corgi_ssp_dev,0); - ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); - - /* TB13/RB3*/ - ssp_write_word(&corgi_ssp_dev,0); - ssp_read_word(&corgi_ssp_dev, (u32*)&voltage2); - - ssp_disable(&corgi_ssp_dev); - ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846)); - ssp_enable(&corgi_ssp_dev); - if (ssp_machinfo->cs_max1111 >= 0) - GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111); - spin_unlock_irqrestore(&corgi_ssp_lock, flag); - - if (voltage1 & 0xc0 || voltage2 & 0x3f) - voltage = -1; - else - voltage = ((voltage1 << 2) & 0xfc) | ((voltage2 >> 6) & 0x03); - - return voltage; -} - -EXPORT_SYMBOL(corgi_ssp_max1111_get); - -/* - * Support Routines - */ - -void __init corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo) -{ - ssp_machinfo = machinfo; -} - -static int __devinit corgi_ssp_probe(struct platform_device *dev) -{ - int ret; - - /* Chip Select - Disable All */ - if (ssp_machinfo->cs_lcdcon >= 0) - pxa_gpio_mode(ssp_machinfo->cs_lcdcon | GPIO_OUT | GPIO_DFLT_HIGH); - if (ssp_machinfo->cs_max1111 >= 0) - pxa_gpio_mode(ssp_machinfo->cs_max1111 | GPIO_OUT | GPIO_DFLT_HIGH); - if (ssp_machinfo->cs_ads7846 >= 0) - pxa_gpio_mode(ssp_machinfo->cs_ads7846 | GPIO_OUT | GPIO_DFLT_HIGH); - - ret = ssp_init(&corgi_ssp_dev, ssp_machinfo->port, 0); - - if (ret) - printk(KERN_ERR "Unable to register SSP handler!\n"); - else { - ssp_disable(&corgi_ssp_dev); - ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846)); - ssp_enable(&corgi_ssp_dev); - } - - return ret; -} - -static int corgi_ssp_remove(struct platform_device *dev) -{ - ssp_exit(&corgi_ssp_dev); - return 0; -} - -static int corgi_ssp_suspend(struct platform_device *dev, pm_message_t state) -{ - ssp_flush(&corgi_ssp_dev); - ssp_save_state(&corgi_ssp_dev,&corgi_ssp_state); - - return 0; -} - -static int corgi_ssp_resume(struct platform_device *dev) -{ - if (ssp_machinfo->cs_lcdcon >= 0) - GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); /* High - Disable LCD Control/Timing Gen */ - if (ssp_machinfo->cs_max1111 >= 0) - GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111); /* High - Disable MAX1111*/ - if (ssp_machinfo->cs_ads7846 >= 0) - GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); /* High - Disable ADS7846*/ - ssp_restore_state(&corgi_ssp_dev,&corgi_ssp_state); - ssp_enable(&corgi_ssp_dev); - - return 0; -} - -static struct platform_driver corgissp_driver = { - .probe = corgi_ssp_probe, - .remove = corgi_ssp_remove, - .suspend = corgi_ssp_suspend, - .resume = corgi_ssp_resume, - .driver = { - .name = "corgi-ssp", - }, -}; - -int __init corgi_ssp_init(void) -{ - return platform_driver_register(&corgissp_driver); -} - -arch_initcall(corgi_ssp_init); diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index 88575b87bd3..91fd4fea6a5 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c @@ -125,18 +125,9 @@ static unsigned long csb726_pin_config[] = { GPIO118_I2C_SDA, }; -static struct pxamci_platform_data csb726_mci_data; - -static int csb726_mci_init(struct device *dev, - irq_handler_t detect, void *data) -{ - csb726_mci_data.detect_delay = msecs_to_jiffies(500); - return 0; -} - static struct pxamci_platform_data csb726_mci = { + .detect_delay_ms = 500, .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .init = csb726_mci_init, /* FIXME setpower */ .gpio_card_detect = CSB726_GPIO_MMC_DETECT, .gpio_card_ro = CSB726_GPIO_MMC_RO, diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index aab04f33e49..0517c17978f 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -626,6 +626,7 @@ static int em_x270_mci_get_ro(struct device *dev) } static struct pxamci_platform_data em_x270_mci_platform_data = { + .detect_delay_ms = 250, .ocr_mask = MMC_VDD_20_21|MMC_VDD_21_22|MMC_VDD_22_23| MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27| MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| @@ -643,7 +644,6 @@ static void __init em_x270_init_mmc(void) if (machine_is_em_x270()) em_x270_mci_platform_data.get_ro = em_x270_mci_get_ro; - em_x270_mci_platform_data.detect_delay = msecs_to_jiffies(250); pxa_set_mci_info(&em_x270_mci_platform_data); } #else diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 3126a35aa00..baabb3ce088 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -28,7 +28,6 @@ #include <mach/reset.h> #include <mach/gpio.h> -#include <mach/pxa2xx-gpio.h> #include "generic.h" @@ -128,33 +127,3 @@ void __init pxa_map_io(void) iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); get_clk_frequency_khz(1); } - -/* - * Configure pins for GPIO or other functions - */ -int pxa_gpio_mode(int gpio_mode) -{ - unsigned long flags; - int gpio = gpio_mode & GPIO_MD_MASK_NR; - int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; - int gafr; - - if (gpio > pxa_last_gpio) - return -EINVAL; - - local_irq_save(flags); - if (gpio_mode & GPIO_DFLT_LOW) - GPCR(gpio) = GPIO_bit(gpio); - else if (gpio_mode & GPIO_DFLT_HIGH) - GPSR(gpio) = GPIO_bit(gpio); - if (gpio_mode & GPIO_MD_MASK_DIR) - GPDR(gpio) |= GPIO_bit(gpio); - else - GPDR(gpio) &= ~GPIO_bit(gpio); - gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); - GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); - local_irq_restore(flags); - - return 0; -} -EXPORT_SYMBOL(pxa_gpio_mode); diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c index 771137fc1a8..5ccb0ceff6c 100644 --- a/arch/arm/mach-pxa/icontrol.c +++ b/arch/arm/mach-pxa/icontrol.c @@ -73,7 +73,6 @@ static struct pxa2xx_spi_chip mcp251x_chip_info4 = { static struct mcp251x_platform_data mcp251x_info = { .oscillator_frequency = 16E6, - .model = CAN_MCP251X_MCP2515, .board_specific_setup = NULL, .power_enable = NULL, .transceiver_enable = NULL @@ -81,7 +80,7 @@ static struct mcp251x_platform_data mcp251x_info = { static struct spi_board_info mcp251x_board_info[] = { { - .modalias = "mcp251x", + .modalias = "mcp2515", .max_speed_hz = 6500000, .bus_num = 3, .chip_select = 0, @@ -90,7 +89,7 @@ static struct spi_board_info mcp251x_board_info[] = { .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ1) }, { - .modalias = "mcp251x", + .modalias = "mcp2515", .max_speed_hz = 6500000, .bus_num = 3, .chip_select = 1, @@ -99,7 +98,7 @@ static struct spi_board_info mcp251x_board_info[] = { .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ2) }, { - .modalias = "mcp251x", + .modalias = "mcp2515", .max_speed_hz = 6500000, .bus_num = 4, .chip_select = 0, @@ -108,7 +107,7 @@ static struct spi_board_info mcp251x_board_info[] = { .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ3) }, { - .modalias = "mcp251x", + .modalias = "mcp2515", .max_speed_hz = 6500000, .bus_num = 4, .chip_select = 1, diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h index 7239281788d..585970ef08c 100644 --- a/arch/arm/mach-pxa/include/mach/corgi.h +++ b/arch/arm/mach-pxa/include/mach/corgi.h @@ -113,7 +113,6 @@ * Shared data structures */ extern struct platform_device corgiscoop_device; -extern struct platform_device corgissp_device; #endif /* __ASM_ARCH_CORGI_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h index 658b28ed129..c54cef25895 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h @@ -25,6 +25,8 @@ #define MFP_DIR(x) (((x) >> 23) & 0x1) #define MFP_LPM_CAN_WAKEUP (0x1 << 24) +#define MFP_LPM_KEEP_OUTPUT (0x1 << 25) + #define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) #define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL) #define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH) diff --git a/arch/arm/mach-pxa/include/mach/mmc.h b/arch/arm/mach-pxa/include/mach/mmc.h index 02a69dc2ee6..9eb515bb799 100644 --- a/arch/arm/mach-pxa/include/mach/mmc.h +++ b/arch/arm/mach-pxa/include/mach/mmc.h @@ -9,7 +9,7 @@ struct mmc_host; struct pxamci_platform_data { unsigned int ocr_mask; /* available voltages */ - unsigned long detect_delay; /* delay in jiffies before detecting cards after interrupt */ + unsigned long detect_delay_ms; /* delay in millisecond before detecting cards after interrupt */ int (*init)(struct device *, irq_handler_t , void *); int (*get_ro)(struct device *); void (*setpower)(struct device *, unsigned int); diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h deleted file mode 100644 index 1209c44aa6f..00000000000 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h +++ /dev/null @@ -1,375 +0,0 @@ -#ifndef __ASM_ARCH_PXA2XX_GPIO_H -#define __ASM_ARCH_PXA2XX_GPIO_H - -#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h - -#include <mach/gpio.h> - -/* GPIO alternate function assignments */ - -#define GPIO1_RST 1 /* reset */ -#define GPIO6_MMCCLK 6 /* MMC Clock */ -#define GPIO7_48MHz 7 /* 48 MHz clock output */ -#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ -#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ -#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ -#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ -#define GPIO12_32KHz 12 /* 32 kHz out */ -#define GPIO12_CIF_DD_7 12 /* Camera data pin 7 */ -#define GPIO13_MBGNT 13 /* memory controller grant */ -#define GPIO14_MBREQ 14 /* alternate bus master request */ -#define GPIO15_nCS_1 15 /* chip select 1 */ -#define GPIO16_PWM0 16 /* PWM0 output */ -#define GPIO17_PWM1 17 /* PWM1 output */ -#define GPIO17_CIF_DD_6 17 /* Camera data pin 6 */ -#define GPIO18_RDY 18 /* Ext. Bus Ready */ -#define GPIO19_DREQ1 19 /* External DMA Request */ -#define GPIO20_DREQ0 20 /* External DMA Request */ -#define GPIO23_SCLK 23 /* SSP clock */ -#define GPIO23_CIF_MCLK 23 /* Camera Master Clock */ -#define GPIO24_SFRM 24 /* SSP Frame */ -#define GPIO24_CIF_FV 24 /* Camera frame start signal */ -#define GPIO25_STXD 25 /* SSP transmit */ -#define GPIO25_CIF_LV 25 /* Camera line start signal */ -#define GPIO26_SRXD 26 /* SSP receive */ -#define GPIO26_CIF_PCLK 26 /* Camera Pixel Clock */ -#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ -#define GPIO27_CIF_DD_0 27 /* Camera data pin 0 */ -#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ -#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ -#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ -#define GPIO31_SYNC 31 /* AC97/I2S sync */ -#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ -#define GPIO32_SYSCLK 32 /* I2S System Clock */ -#define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */ -#define GPIO33_nCS_5 33 /* chip select 5 */ -#define GPIO34_FFRXD 34 /* FFUART receive */ -#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ -#define GPIO35_FFCTS 35 /* FFUART Clear to send */ -#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ -#define GPIO37_FFDSR 37 /* FFUART data set ready */ -#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ -#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ -#define GPIO39_FFTXD 39 /* FFUART transmit data */ -#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ -#define GPIO41_FFRTS 41 /* FFUART request to send */ -#define GPIO42_BTRXD 42 /* BTUART receive data */ -#define GPIO42_HWRXD 42 /* HWUART receive data */ -#define GPIO42_CIF_MCLK 42 /* Camera Master Clock */ -#define GPIO43_BTTXD 43 /* BTUART transmit data */ -#define GPIO43_HWTXD 43 /* HWUART transmit data */ -#define GPIO43_CIF_FV 43 /* Camera frame start signal */ -#define GPIO44_BTCTS 44 /* BTUART clear to send */ -#define GPIO44_HWCTS 44 /* HWUART clear to send */ -#define GPIO44_CIF_LV 44 /* Camera line start signal */ -#define GPIO45_BTRTS 45 /* BTUART request to send */ -#define GPIO45_HWRTS 45 /* HWUART request to send */ -#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ -#define GPIO45_CIF_PCLK 45 /* Camera Pixel Clock */ -#define GPIO46_ICPRXD 46 /* ICP receive data */ -#define GPIO46_STRXD 46 /* STD_UART receive data */ -#define GPIO47_ICPTXD 47 /* ICP transmit data */ -#define GPIO47_STTXD 47 /* STD_UART transmit data */ -#define GPIO47_CIF_DD_0 47 /* Camera data pin 0 */ -#define GPIO48_nPOE 48 /* Output Enable for Card Space */ -#define GPIO48_CIF_DD_5 48 /* Camera data pin 5 */ -#define GPIO49_nPWE 49 /* Write Enable for Card Space */ -#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ -#define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */ -#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ -#define GPIO51_CIF_DD_2 51 /* Camera data pin 2 */ -#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ -#define GPIO52_CIF_DD_4 52 /* Camera data pin 4 */ -#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ -#define GPIO53_MMCCLK 53 /* MMC Clock */ -#define GPIO53_CIF_MCLK 53 /* Camera Master Clock */ -#define GPIO54_MMCCLK 54 /* MMC Clock */ -#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ -#define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */ -#define GPIO54_CIF_PCLK 54 /* Camera Pixel Clock */ -#define GPIO55_nPREG 55 /* Card Address bit 26 */ -#define GPIO55_CIF_DD_1 55 /* Camera data pin 1 */ -#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ -#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ -#define GPIO58_LDD_0 58 /* LCD data pin 0 */ -#define GPIO59_LDD_1 59 /* LCD data pin 1 */ -#define GPIO60_LDD_2 60 /* LCD data pin 2 */ -#define GPIO61_LDD_3 61 /* LCD data pin 3 */ -#define GPIO62_LDD_4 62 /* LCD data pin 4 */ -#define GPIO63_LDD_5 63 /* LCD data pin 5 */ -#define GPIO64_LDD_6 64 /* LCD data pin 6 */ -#define GPIO65_LDD_7 65 /* LCD data pin 7 */ -#define GPIO66_LDD_8 66 /* LCD data pin 8 */ -#define GPIO66_MBREQ 66 /* alternate bus master req */ -#define GPIO67_LDD_9 67 /* LCD data pin 9 */ -#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ -#define GPIO68_LDD_10 68 /* LCD data pin 10 */ -#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ -#define GPIO69_LDD_11 69 /* LCD data pin 11 */ -#define GPIO69_MMCCLK 69 /* MMC_CLK */ -#define GPIO70_LDD_12 70 /* LCD data pin 12 */ -#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ -#define GPIO71_LDD_13 71 /* LCD data pin 13 */ -#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ -#define GPIO72_LDD_14 72 /* LCD data pin 14 */ -#define GPIO72_32kHz 72 /* 32 kHz clock */ -#define GPIO73_LDD_15 73 /* LCD data pin 15 */ -#define GPIO73_MBGNT 73 /* Memory controller grant */ -#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ -#define GPIO75_LCD_LCLK 75 /* LCD line clock */ -#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ -#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ -#define GPIO78_nCS_2 78 /* chip select 2 */ -#define GPIO79_nCS_3 79 /* chip select 3 */ -#define GPIO80_nCS_4 80 /* chip select 4 */ -#define GPIO81_NSCLK 81 /* NSSP clock */ -#define GPIO81_CIF_DD_0 81 /* Camera data pin 0 */ -#define GPIO82_NSFRM 82 /* NSSP Frame */ -#define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */ -#define GPIO83_NSTXD 83 /* NSSP transmit */ -#define GPIO83_CIF_DD_4 83 /* Camera data pin 4 */ -#define GPIO84_NSRXD 84 /* NSSP receive */ -#define GPIO84_CIF_FV 84 /* Camera frame start signal */ -#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ -#define GPIO85_CIF_LV 85 /* Camera line start signal */ -#define GPIO90_CIF_DD_4 90 /* Camera data pin 4 */ -#define GPIO91_CIF_DD_5 91 /* Camera data pin 5 */ -#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ -#define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */ -#define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */ -#define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */ -#define GPIO96_FFRXD 96 /* FFUART recieve */ -#define GPIO98_FFRTS 98 /* FFUART request to send */ -#define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */ -#define GPIO99_FFTXD 99 /* FFUART transmit data */ -#define GPIO100_FFCTS 100 /* FFUART Clear to send */ -#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ -#define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */ -#define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */ -#define GPIO105_CIF_DD_1 105 /* Camera data pin 1 */ -#define GPIO106_CIF_DD_9 106 /* Camera data pin 9 */ -#define GPIO107_CIF_DD_8 107 /* Camera data pin 8 */ -#define GPIO108_CIF_DD_7 108 /* Camera data pin 7 */ -#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ -#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ -#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ -#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */ -#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */ -#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */ -#define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */ -#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */ -#define GPIO114_CIF_DD_1 114 /* Camera data pin 1 */ -#define GPIO115_CIF_DD_3 115 /* Camera data pin 3 */ -#define GPIO116_CIF_DD_2 116 /* Camera data pin 2 */ - -/* GPIO alternate function mode & direction */ - -#define GPIO_IN 0x000 -#define GPIO_OUT 0x080 -#define GPIO_ALT_FN_1_IN 0x100 -#define GPIO_ALT_FN_1_OUT 0x180 -#define GPIO_ALT_FN_2_IN 0x200 -#define GPIO_ALT_FN_2_OUT 0x280 -#define GPIO_ALT_FN_3_IN 0x300 -#define GPIO_ALT_FN_3_OUT 0x380 -#define GPIO_MD_MASK_NR 0x07f -#define GPIO_MD_MASK_DIR 0x080 -#define GPIO_MD_MASK_FN 0x300 -#define GPIO_DFLT_LOW 0x400 -#define GPIO_DFLT_HIGH 0x800 - -#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) -#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) -#define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT) -#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) -#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) -#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) -#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) -#define GPIO12_CIF_DD_7_MD (12 | GPIO_ALT_FN_2_IN) -#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) -#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) -#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) -#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) -#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) -#define GPIO17_CIF_DD_6_MD (17 | GPIO_ALT_FN_2_IN) -#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) -#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) -#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) -#define GPIO23_CIF_MCLK_MD (23 | GPIO_ALT_FN_1_OUT) -#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT) -#define GPIO24_CIF_FV_MD (24 | GPIO_ALT_FN_1_OUT) -#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) -#define GPIO25_CIF_LV_MD (25 | GPIO_ALT_FN_1_OUT) -#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) -#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) -#define GPIO26_CIF_PCLK_MD (26 | GPIO_ALT_FN_2_IN) -#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) -#define GPIO27_CIF_DD_0_MD (27 | GPIO_ALT_FN_3_IN) -#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN) -#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT) -#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) -#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) -#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) -#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) -#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) -#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) -#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) -#define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT) -#define GPIO32_MMCCLK_MD (32 | GPIO_ALT_FN_2_OUT) -#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) -#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) -#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) -#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) -#define GPIO35_KP_MKOUT6_MD (35 | GPIO_ALT_FN_2_OUT) -#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) -#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) -#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) -#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) -#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) -#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) -#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) -#define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT) -#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) -#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) -#define GPIO42_CIF_MCLK_MD (42 | GPIO_ALT_FN_3_OUT) -#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) -#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) -#define GPIO43_CIF_FV_MD (43 | GPIO_ALT_FN_3_OUT) -#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) -#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) -#define GPIO44_CIF_LV_MD (44 | GPIO_ALT_FN_3_OUT) -#define GPIO45_CIF_PCLK_MD (45 | GPIO_ALT_FN_3_IN) -#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) -#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) -#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) -#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) -#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) -#define GPIO47_CIF_DD_0_MD (47 | GPIO_ALT_FN_1_IN) -#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) -#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) -#define GPIO48_CIF_DD_5_MD (48 | GPIO_ALT_FN_1_IN) -#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) -#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) -#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) -#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) -#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) -#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) -#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) -#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) -#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) -#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) -#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) -#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) -#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) -#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) -#define GPIO52_CIF_DD_4_MD (52 | GPIO_ALT_FN_1_IN) -#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) -#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) -#define GPIO53_CIF_MCLK_MD (53 | GPIO_ALT_FN_2_OUT) -#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) -#define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT) -#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) -#define GPIO54_CIF_PCLK_MD (54 | GPIO_ALT_FN_3_IN) -#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) -#define GPIO55_CIF_DD_1_MD (55 | GPIO_ALT_FN_1_IN) -#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) -#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) -#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) -#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) -#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) -#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) -#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) -#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) -#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) -#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) -#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) -#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) -#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) -#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) -#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) -#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) -#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) -#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) -#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) -#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) -#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) -#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) -#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) -#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) -#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) -#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) -#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) -#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) -#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) -#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) -#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) -#define GPIO78_nPCE_2_MD (78 | GPIO_ALT_FN_1_OUT) -#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) -#define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT) -#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) -#define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT) -#define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN) -#define GPIO81_CIF_DD_0_MD (81 | GPIO_ALT_FN_2_IN) -#define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT) -#define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN) -#define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN) -#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT) -#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN) -#define GPIO83_CIF_DD_4_MD (83 | GPIO_ALT_FN_3_IN) -#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) -#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) -#define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN) -#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) -#define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN) -#define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT) -#define GPIO88_USBH1_PWR_MD (88 | GPIO_ALT_FN_1_IN) -#define GPIO89_USBH1_PEN_MD (89 | GPIO_ALT_FN_2_OUT) -#define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN) -#define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN) -#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) -#define GPIO93_CIF_DD_6_MD (93 | GPIO_ALT_FN_2_IN) -#define GPIO94_CIF_DD_5_MD (94 | GPIO_ALT_FN_2_IN) -#define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN) -#define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN) -#define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN) -#define GPIO96_FFRXD_MD (96 | GPIO_ALT_FN_3_IN) -#define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN) -#define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN) -#define GPIO98_FFRTS_MD (98 | GPIO_ALT_FN_3_OUT) -#define GPIO99_FFTXD_MD (99 | GPIO_ALT_FN_3_OUT) -#define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN) -#define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN) -#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) -#define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN) -#define GPIO103_CIF_DD_3_MD (103 | GPIO_ALT_FN_1_IN) -#define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT) -#define GPIO104_CIF_DD_2_MD (104 | GPIO_ALT_FN_1_IN) -#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) -#define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT) -#define GPIO105_CIF_DD_1_MD (105 | GPIO_ALT_FN_1_IN) -#define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT) -#define GPIO106_CIF_DD_9_MD (106 | GPIO_ALT_FN_1_IN) -#define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT) -#define GPIO107_CIF_DD_8_MD (107 | GPIO_ALT_FN_1_IN) -#define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT) -#define GPIO108_CIF_DD_7_MD (108 | GPIO_ALT_FN_1_IN) -#define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT) -#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) -#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) -#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) -#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT) -#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT) -#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT) -#define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT) -#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT) -#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) -#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) - -/* - * Handy routine to set GPIO alternate functions - */ -extern int pxa_gpio_mode( int gpio_mode ); - -#endif /* __ASM_ARCH_PXA2XX_GPIO_H */ diff --git a/arch/arm/mach-pxa/include/mach/ssp.h b/arch/arm/mach-pxa/include/mach/ssp.h deleted file mode 100644 index be1be5b6db5..00000000000 --- a/arch/arm/mach-pxa/include/mach/ssp.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * ssp.h - * - * Copyright (C) 2003 Russell King, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This driver supports the following PXA CPU/SSP ports:- - * - * PXA250 SSP - * PXA255 SSP, NSSP - * PXA26x SSP, NSSP, ASSP - * PXA27x SSP1, SSP2, SSP3 - * PXA3xx SSP1, SSP2, SSP3, SSP4 - */ - -#ifndef __ASM_ARCH_SSP_H -#define __ASM_ARCH_SSP_H - -#include <linux/list.h> -#include <linux/io.h> - -enum pxa_ssp_type { - SSP_UNDEFINED = 0, - PXA25x_SSP, /* pxa 210, 250, 255, 26x */ - PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ - PXA27x_SSP, -}; - -struct ssp_device { - struct platform_device *pdev; - struct list_head node; - - struct clk *clk; - void __iomem *mmio_base; - unsigned long phys_base; - - const char *label; - int port_id; - int type; - int use_count; - int irq; - int drcmr_rx; - int drcmr_tx; -}; - -#ifdef CONFIG_PXA_SSP_LEGACY -/* - * SSP initialisation flags - */ -#define SSP_NO_IRQ 0x1 /* don't register an irq handler in SSP driver */ - -struct ssp_state { - u32 cr0; - u32 cr1; - u32 to; - u32 psp; -}; - -struct ssp_dev { - struct ssp_device *ssp; - u32 port; - u32 mode; - u32 flags; - u32 psp_flags; - u32 speed; - int irq; -}; - -int ssp_write_word(struct ssp_dev *dev, u32 data); -int ssp_read_word(struct ssp_dev *dev, u32 *data); -int ssp_flush(struct ssp_dev *dev); -void ssp_enable(struct ssp_dev *dev); -void ssp_disable(struct ssp_dev *dev); -void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp); -void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp); -int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags); -int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); -void ssp_exit(struct ssp_dev *dev); -#endif /* CONFIG_PXA_SSP_LEGACY */ - -/** - * ssp_write_reg - Write to a SSP register - * - * @dev: SSP device to access - * @reg: Register to write to - * @val: Value to be written. - */ -static inline void ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) -{ - __raw_writel(val, dev->mmio_base + reg); -} - -/** - * ssp_read_reg - Read from a SSP register - * - * @dev: SSP device to access - * @reg: Register to read from - */ -static inline u32 ssp_read_reg(struct ssp_device *dev, u32 reg) -{ - return __raw_readl(dev->mmio_base + reg); -} - -struct ssp_device *ssp_request(int port, const char *label); -void ssp_free(struct ssp_device *); -#endif /* __ASM_ARCH_SSP_H */ diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h index 4df2d38507d..1bbd1f2e4be 100644 --- a/arch/arm/mach-pxa/include/mach/tosa.h +++ b/arch/arm/mach-pxa/include/mach/tosa.h @@ -167,7 +167,7 @@ #define TOSA_KEY_SYNC KEY_102ND /* ??? */ -#ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES +#ifndef CONFIG_TOSA_USE_EXT_KEYCODES #define TOSA_KEY_RECORD KEY_YEN #define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA #define TOSA_KEY_CANCEL KEY_ESC diff --git a/arch/arm/mach-pxa/include/mach/vpac270.h b/arch/arm/mach-pxa/include/mach/vpac270.h new file mode 100644 index 00000000000..7bfa3dd0fd5 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/vpac270.h @@ -0,0 +1,42 @@ +/* + * GPIOs and interrupts for Voipac PXA270 + * + * Copyright (C) 2010 + * Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_VPAC270_H_ +#define _INCLUDE_VPAC270_H_ + +#define GPIO1_VPAC270_USER_BTN 1 + +#define GPIO15_VPAC270_LED_ORANGE 15 + +#define GPIO81_VPAC270_BKL_ON 81 +#define GPIO83_VPAC270_NL_ON 83 + +#define GPIO52_VPAC270_SD_READONLY 52 +#define GPIO53_VPAC270_SD_DETECT_N 53 + +#define GPIO84_VPAC270_PCMCIA_CD 84 +#define GPIO35_VPAC270_PCMCIA_RDY 35 +#define GPIO107_VPAC270_PCMCIA_PPEN 107 +#define GPIO11_VPAC270_PCMCIA_RESET 11 +#define GPIO17_VPAC270_CF_CD 17 +#define GPIO12_VPAC270_CF_RDY 12 +#define GPIO16_VPAC270_CF_RESET 16 + +#define GPIO41_VPAC270_UDC_DETECT 41 + +#define GPIO114_VPAC270_ETH_IRQ 114 + +#define GPIO36_VPAC270_IDE_IRQ 36 + +#define GPIO113_VPAC270_TS_IRQ 113 + +#endif diff --git a/arch/arm/mach-pxa/include/mach/z2.h b/arch/arm/mach-pxa/include/mach/z2.h new file mode 100644 index 00000000000..8835c16bc82 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/z2.h @@ -0,0 +1,41 @@ +/* + * arch/arm/mach-pxa/include/mach/z2.h + * + * Author: Ken McGuire + * Created: Feb 6, 2009 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef ASM_ARCH_ZIPIT2_H +#define ASM_ARCH_ZIPIT2_H + +/* LEDs */ +#define GPIO10_ZIPITZ2_LED_WIFI 10 +#define GPIO85_ZIPITZ2_LED_CHARGED 85 +#define GPIO83_ZIPITZ2_LED_CHARGING 83 + +/* SD/MMC */ +#define GPIO96_ZIPITZ2_SD_DETECT 96 + +/* GPIO Buttons */ +#define GPIO1_ZIPITZ2_POWER_BUTTON 1 +#define GPIO98_ZIPITZ2_LID_BUTTON 98 + +/* Libertas GSPI8686 WiFi */ +#define GPIO14_ZIPITZ2_WIFI_RESET 14 +#define GPIO15_ZIPITZ2_WIFI_POWER 15 +#define GPIO24_ZIPITZ2_WIFI_CS 24 +#define GPIO36_ZIPITZ2_WIFI_IRQ 36 + +/* LCD */ +#define GPIO19_ZIPITZ2_LCD_RESET 19 +#define GPIO88_ZIPITZ2_LCD_CS 88 + +/* MISC GPIOs */ +#define GPIO0_ZIPITZ2_AC_DETECT 0 +#define GPIO37_ZIPITZ2_HEADSET_DETECT 37 + +#endif diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index fa527b258d6..9b9046185b0 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -41,7 +41,6 @@ #include <mach/pxa300.h> #include <mach/pxafb.h> -#include <mach/ssp.h> #include <mach/mmc.h> #include <mach/pxa2xx_spi.h> #include <mach/pxa27x_keypad.h> @@ -272,7 +271,7 @@ static inline void littleton_init_keypad(void) {} #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) static struct pxamci_platform_data littleton_mci_platform_data = { - .detect_delay = 20, + .detect_delay_ms = 200, .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .gpio_card_detect = GPIO_MMC1_CARD_DETECT, .gpio_card_ro = -1, diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 63d65a2a038..330c3282856 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -478,7 +478,7 @@ static void lubbock_mci_exit(struct device *dev, void *data) static struct pxamci_platform_data lubbock_mci_platform_data = { .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .detect_delay = 1, + .detect_delay_ms = 10, .init = lubbock_mci_init, .get_ro = lubbock_mci_get_ro, .exit = lubbock_mci_exit, diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index cf6b720c055..1d1419b7345 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -81,6 +81,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) PGSR(bank) &= ~mask; is_out = 1; break; + case MFP_LPM_INPUT: case MFP_LPM_DEFAULT: break; default: @@ -178,8 +179,17 @@ int gpio_set_wake(unsigned int gpio, unsigned int on) if (!d->valid) return -EINVAL; - if (d->keypad_gpio) - return -EINVAL; + /* Allow keypad GPIOs to wakeup system when + * configured as generic GPIOs. + */ + if (d->keypad_gpio && (MFP_AF(d->config) == 0) && + (d->config & MFP_LPM_CAN_WAKEUP)) { + if (on) + PKWR |= d->mask; + else + PKWR &= ~d->mask; + return 0; + } mux_taken = (PWER & d->mux_mask) & (~d->mask); if (on && mux_taken) @@ -239,21 +249,25 @@ static int pxa27x_pkwr_gpio[] = { int keypad_set_wake(unsigned int on) { unsigned int i, gpio, mask = 0; - - if (!on) { - PKWR = 0; - return 0; - } + struct gpio_desc *d; for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) { gpio = pxa27x_pkwr_gpio[i]; + d = &gpio_desc[gpio]; - if (gpio_desc[gpio].config & MFP_LPM_CAN_WAKEUP) + /* skip if configured as generic GPIO */ + if (MFP_AF(d->config) == 0) + continue; + + if (d->config & MFP_LPM_CAN_WAKEUP) mask |= gpio_desc[gpio].mask; } - PKWR = mask; + if (on) + PKWR |= mask; + else + PKWR &= ~mask; return 0; } @@ -328,6 +342,17 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) { int i; + /* set corresponding PGSR bit of those marked MFP_LPM_KEEP_OUTPUT */ + for (i = 0; i < pxa_last_gpio; i++) { + if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) && + (GPDR(i) & GPIO_bit(i))) { + if (GPLR(i) & GPIO_bit(i)) + PGSR(i) |= GPIO_bit(i); + else + PGSR(i) &= ~GPIO_bit(i); + } + } + for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { saved_gafr[0][i] = GAFR_L(i); diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 7a50ed8fce9..d60db87dde0 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -426,6 +426,7 @@ struct gpio_vbus_mach_info gpio_vbus_data = { * to give the card a chance to fully insert/eject. */ static struct pxamci_platform_data mioa701_mci_info = { + .detect_delay_ms = 250, .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .gpio_card_detect = GPIO15_SDIO_INSERT, .gpio_card_ro = GPIO78_SDIO_RO, @@ -791,7 +792,6 @@ static void __init mioa701_machine_init(void) mio_gpio_request(ARRAY_AND_SIZE(global_gpios)); bootstrap_init(); set_pxa_fb_info(&mioa701_pxafb_info); - mioa701_mci_info.detect_delay = msecs_to_jiffies(250); pxa_set_mci_info(&mioa701_mci_info); pxa_set_keypad_info(&mioa701_keypad_info); wm97xx_bat_set_pdata(&mioa701_battery_data); diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c index 8c9c6f0d56b..462167ac05f 100644 --- a/arch/arm/mach-pxa/mxm8x10.c +++ b/arch/arm/mach-pxa/mxm8x10.c @@ -325,7 +325,7 @@ static mfp_cfg_t mfp_cfg[] __initdata = { #if defined(CONFIG_MMC) static struct pxamci_platform_data mxm_8x10_mci_platform_data = { .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .detect_delay = 1, + .detect_delay_ms = 10, .gpio_card_detect = MXM_8X10_SD_nCD, .gpio_card_ro = MXM_8X10_SD_WP, .gpio_power = -1 diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index f70c75b3876..1963819dba9 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -168,7 +168,7 @@ static struct pxamci_platform_data palmld_mci_platform_data = { .gpio_card_detect = GPIO_NR_PALMLD_SD_DETECT_N, .gpio_card_ro = GPIO_NR_PALMLD_SD_READONLY, .gpio_power = GPIO_NR_PALMLD_SD_POWER, - .detect_delay = 20, + .detect_delay_ms = 200, }; /****************************************************************************** diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index d902a813aae..5305a3993e6 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -110,7 +110,7 @@ static struct pxamci_platform_data palmt5_mci_platform_data = { .gpio_card_detect = GPIO_NR_PALMT5_SD_DETECT_N, .gpio_card_ro = GPIO_NR_PALMT5_SD_READONLY, .gpio_power = GPIO_NR_PALMT5_SD_POWER, - .detect_delay = 20, + .detect_delay_ms = 200, }; /****************************************************************************** diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index 717d7a63867..033b567e50b 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -121,7 +121,7 @@ static struct pxamci_platform_data palmtc_mci_platform_data = { .gpio_power = GPIO_NR_PALMTC_SD_POWER, .gpio_card_ro = GPIO_NR_PALMTC_SD_READONLY, .gpio_card_detect = GPIO_NR_PALMTC_SD_DETECT_N, - .detect_delay = 20, + .detect_delay_ms = 200, }; /****************************************************************************** diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index 007b58c11f8..ecc1a401598 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -170,7 +170,7 @@ static struct pxamci_platform_data palmtx_mci_platform_data = { .gpio_card_detect = GPIO_NR_PALMTX_SD_DETECT_N, .gpio_card_ro = GPIO_NR_PALMTX_SD_READONLY, .gpio_power = GPIO_NR_PALMTX_SD_POWER, - .detect_delay = 20, + .detect_delay_ms = 200, }; /****************************************************************************** diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 9d0ecea1760..f56ae100875 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -326,7 +326,7 @@ static void pcm990_mci_exit(struct device *dev, void *data) #define MSECS_PER_JIFFY (1000/HZ) static struct pxamci_platform_data pcm990_mci_platform_data = { - .detect_delay = 250 / MSECS_PER_JIFFY, + .detect_delay_ms = 250, .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .init = pcm990_mci_init, .setpower = pcm990_mci_setpower, diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index d58a52415d7..f4abdaafdac 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -40,13 +40,12 @@ #include <mach/pxa25x.h> #include <mach/mmc.h> #include <mach/udc.h> -#include <plat/i2c.h> #include <mach/irda.h> #include <mach/poodle.h> #include <mach/pxafb.h> #include <mach/sharpsl.h> -#include <mach/ssp.h> #include <mach/pxa2xx_spi.h> +#include <plat/i2c.h> #include <asm/hardware/scoop.h> #include <asm/hardware/locomo.h> @@ -277,6 +276,7 @@ static void poodle_mci_exit(struct device *dev, void *data) } static struct pxamci_platform_data poodle_mci_platform_data = { + .detect_delay_ms = 250, .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .init = poodle_mci_init, .setpower = poodle_mci_setpower, @@ -450,7 +450,6 @@ static void __init poodle_init(void) set_pxa_fb_parent(&poodle_locomo_device.dev); set_pxa_fb_info(&poodle_fb_info); pxa_set_udc_info(&udc_info); - poodle_mci_platform_data.detect_delay = msecs_to_jiffies(250); pxa_set_mci_info(&poodle_mci_platform_data); pxa_set_ficp_info(&poodle_ficp_platform_data); pxa_set_i2c_info(NULL); diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 4d7c03e7250..f544e58e153 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -29,7 +29,6 @@ #include <mach/ohci.h> #include <mach/pm.h> #include <mach/dma.h> -#include <mach/ssp.h> #include <mach/regs-intc.h> #include <plat/i2c.h> diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index d12667bd9eb..d4b61b3f08f 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -714,7 +714,7 @@ static void raumfeld_mci_exit(struct device *dev, void *data) static struct pxamci_platform_data raumfeld_mci_platform_data = { .init = raumfeld_mci_init, .exit = raumfeld_mci_exit, - .detect_delay = 20, + .detect_delay_ms = 200, .gpio_card_detect = -1, .gpio_card_ro = -1, .gpio_power = -1, diff --git a/arch/arm/mach-pxa/sharpsl.h b/arch/arm/mach-pxa/sharpsl.h index 1439785d397..0cc1203c5be 100644 --- a/arch/arm/mach-pxa/sharpsl.h +++ b/arch/arm/mach-pxa/sharpsl.h @@ -10,29 +10,6 @@ #include <mach/sharpsl_pm.h> /* - * SharpSL SSP Driver - */ -struct corgissp_machinfo { - int port; - int cs_lcdcon; - int cs_ads7846; - int cs_max1111; - int clk_lcdcon; - int clk_ads7846; - int clk_max1111; -}; - -void corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo); - - -/* - * SharpSL/Corgi LCD Driver - */ -void corgi_lcdtg_suspend(void); -void corgi_lcdtg_hw_init(int mode); - - -/* * SharpSL Battery/PM Driver */ #define READ_GPIO_BIT(x) (GPLR(x) & GPIO_bit(x)) diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 463d874bb86..cb4767251f3 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -28,7 +28,6 @@ #include <asm/mach-types.h> #include <mach/pm.h> #include <mach/pxa2xx-regs.h> -#include <mach/pxa2xx-gpio.h> #include <mach/regs-rtc.h> #include <mach/sharpsl.h> #include <mach/sharpsl_pm.h> diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 01bdd7500df..4d2413ed0ff 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -86,6 +86,7 @@ static unsigned long spitz_pin_config[] __initdata = { /* GPIOs */ GPIO9_GPIO, /* SPITZ_GPIO_nSD_DETECT */ + GPIO16_GPIO, /* SPITZ_GPIO_SYNC */ GPIO81_GPIO, /* SPITZ_GPIO_nSD_WP */ GPIO41_GPIO, /* SPITZ_GPIO_USB_CONNECT */ GPIO37_GPIO, /* SPITZ_GPIO_USB_HOST */ @@ -119,7 +120,8 @@ static unsigned long spitz_pin_config[] __initdata = { GPIO117_I2C_SCL, GPIO118_I2C_SDA, - GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, + GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, /* SPITZ_GPIO_KEY_INT */ + GPIO1_GPIO | WAKEUP_ON_EDGE_FALL, /* SPITZ_GPIO_RESET */ }; /* @@ -537,6 +539,7 @@ static void spitz_mci_setpower(struct device *dev, unsigned int vdd) } static struct pxamci_platform_data spitz_mci_platform_data = { + .detect_delay_ms = 250, .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .setpower = spitz_mci_setpower, .gpio_card_detect = SPITZ_GPIO_nSD_DETECT, @@ -757,7 +760,6 @@ static void __init common_init(void) spitz_init_spi(); platform_add_devices(devices, ARRAY_SIZE(devices)); - spitz_mci_platform_data.detect_delay = msecs_to_jiffies(250); pxa_set_mci_info(&spitz_mci_platform_data); pxa_set_ohci_info(&spitz_ohci_platform_data); pxa_set_ficp_info(&spitz_ficp_platform_data); diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index fc5a70c4035..4209ddf6da6 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -24,9 +24,10 @@ #include <mach/sharpsl.h> #include <mach/spitz.h> -#include <mach/pxa2xx-regs.h> -#include <mach/pxa2xx-gpio.h> +#include <mach/pxa27x.h> + #include "sharpsl.h" +#include "generic.h" #define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */ #define SHARPSL_CHARGE_ON_TEMP 0xe0 /* 2.9V */ @@ -37,10 +38,17 @@ static int spitz_last_ac_status; +static struct gpio spitz_charger_gpios[] = { + { SPITZ_GPIO_KEY_INT, GPIOF_IN, "Keyboard Interrupt" }, + { SPITZ_GPIO_SYNC, GPIOF_IN, "Sync" }, + { SPITZ_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" }, + { SPITZ_GPIO_JK_B, GPIOF_OUT_INIT_LOW, "JK B" }, + { SPITZ_GPIO_CHRG_ON, GPIOF_OUT_INIT_LOW, "Charger On" }, +}; + static void spitz_charger_init(void) { - pxa_gpio_mode(SPITZ_GPIO_KEY_INT | GPIO_IN); - pxa_gpio_mode(SPITZ_GPIO_SYNC | GPIO_IN); + gpio_request_array(ARRAY_AND_SIZE(spitz_charger_gpios)); } static void spitz_measure_temp(int on) @@ -76,6 +84,11 @@ static void spitz_discharge1(int on) gpio_set_value(SPITZ_GPIO_LED_GREEN, on); } +static unsigned long gpio18_config[] = { + GPIO18_RDY, + GPIO18_GPIO, +}; + static void spitz_presuspend(void) { spitz_last_ac_status = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN); @@ -97,7 +110,9 @@ static void spitz_presuspend(void) PGSR3 &= ~SPITZ_GPIO_G3_STROBE_BIT; PGSR2 |= GPIO_bit(SPITZ_GPIO_KEY_STROBE0); - pxa_gpio_mode(GPIO18_RDY|GPIO_OUT | GPIO_DFLT_HIGH); + pxa2xx_mfp_config(&gpio18_config[0], 1); + gpio_request_one(18, GPIOF_OUT_INIT_HIGH, "Unknown"); + gpio_free(18); PRER = GPIO_bit(SPITZ_GPIO_KEY_INT); PFER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET); @@ -114,8 +129,7 @@ static void spitz_presuspend(void) static void spitz_postsuspend(void) { - pxa_gpio_mode(GPIO18_RDY_MD); - pxa_gpio_mode(10 | GPIO_IN); + pxa2xx_mfp_config(&gpio18_config[1], 1); } static int spitz_should_wakeup(unsigned int resume_on_alarm) diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c deleted file mode 100644 index a81d6dbf662..00000000000 --- a/arch/arm/mach-pxa/ssp.c +++ /dev/null @@ -1,510 +0,0 @@ -/* - * linux/arch/arm/mach-pxa/ssp.c - * - * based on linux/arch/arm/mach-sa1100/ssp.c by Russell King - * - * Copyright (C) 2003 Russell King. - * Copyright (C) 2003 Wolfson Microelectronics PLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * PXA2xx SSP driver. This provides the generic core for simple - * IO-based SSP applications and allows easy port setup for DMA access. - * - * Author: Liam Girdwood <liam.girdwood@wolfsonmicro.com> - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/slab.h> -#include <linux/errno.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/init.h> -#include <linux/mutex.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <mach/hardware.h> -#include <mach/ssp.h> -#include <mach/regs-ssp.h> - -#ifdef CONFIG_PXA_SSP_LEGACY - -#define TIMEOUT 100000 - -static irqreturn_t ssp_interrupt(int irq, void *dev_id) -{ - struct ssp_dev *dev = dev_id; - struct ssp_device *ssp = dev->ssp; - unsigned int status; - - status = __raw_readl(ssp->mmio_base + SSSR); - __raw_writel(status, ssp->mmio_base + SSSR); - - if (status & SSSR_ROR) - printk(KERN_WARNING "SSP(%d): receiver overrun\n", dev->port); - - if (status & SSSR_TUR) - printk(KERN_WARNING "SSP(%d): transmitter underrun\n", dev->port); - - if (status & SSSR_BCE) - printk(KERN_WARNING "SSP(%d): bit count error\n", dev->port); - - return IRQ_HANDLED; -} - -/** - * ssp_write_word - write a word to the SSP port - * @data: 32-bit, MSB justified data to write. - * - * Wait for a free entry in the SSP transmit FIFO, and write a data - * word to the SSP port. - * - * The caller is expected to perform the necessary locking. - * - * Returns: - * %-ETIMEDOUT timeout occurred - * 0 success - */ -int ssp_write_word(struct ssp_dev *dev, u32 data) -{ - struct ssp_device *ssp = dev->ssp; - int timeout = TIMEOUT; - - while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_TNF)) { - if (!--timeout) - return -ETIMEDOUT; - cpu_relax(); - } - - __raw_writel(data, ssp->mmio_base + SSDR); - - return 0; -} - -/** - * ssp_read_word - read a word from the SSP port - * - * Wait for a data word in the SSP receive FIFO, and return the - * received data. Data is LSB justified. - * - * Note: Currently, if data is not expected to be received, this - * function will wait for ever. - * - * The caller is expected to perform the necessary locking. - * - * Returns: - * %-ETIMEDOUT timeout occurred - * 32-bit data success - */ -int ssp_read_word(struct ssp_dev *dev, u32 *data) -{ - struct ssp_device *ssp = dev->ssp; - int timeout = TIMEOUT; - - while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE)) { - if (!--timeout) - return -ETIMEDOUT; - cpu_relax(); - } - - *data = __raw_readl(ssp->mmio_base + SSDR); - return 0; -} - -/** - * ssp_flush - flush the transmit and receive FIFOs - * - * Wait for the SSP to idle, and ensure that the receive FIFO - * is empty. - * - * The caller is expected to perform the necessary locking. - */ -int ssp_flush(struct ssp_dev *dev) -{ - struct ssp_device *ssp = dev->ssp; - int timeout = TIMEOUT * 2; - - /* ensure TX FIFO is empty instead of not full */ - if (cpu_is_pxa3xx()) { - while (__raw_readl(ssp->mmio_base + SSSR) & 0xf00) { - if (!--timeout) - return -ETIMEDOUT; - cpu_relax(); - } - timeout = TIMEOUT * 2; - } - - do { - while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE) { - if (!--timeout) - return -ETIMEDOUT; - (void)__raw_readl(ssp->mmio_base + SSDR); - } - if (!--timeout) - return -ETIMEDOUT; - } while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_BSY); - - return 0; -} - -/** - * ssp_enable - enable the SSP port - * - * Turn on the SSP port. - */ -void ssp_enable(struct ssp_dev *dev) -{ - struct ssp_device *ssp = dev->ssp; - uint32_t sscr0; - - sscr0 = __raw_readl(ssp->mmio_base + SSCR0); - sscr0 |= SSCR0_SSE; - __raw_writel(sscr0, ssp->mmio_base + SSCR0); -} - -/** - * ssp_disable - shut down the SSP port - * - * Turn off the SSP port, optionally powering it down. - */ -void ssp_disable(struct ssp_dev *dev) -{ - struct ssp_device *ssp = dev->ssp; - uint32_t sscr0; - - sscr0 = __raw_readl(ssp->mmio_base + SSCR0); - sscr0 &= ~SSCR0_SSE; - __raw_writel(sscr0, ssp->mmio_base + SSCR0); -} - -/** - * ssp_save_state - save the SSP configuration - * @ssp: pointer to structure to save SSP configuration - * - * Save the configured SSP state for suspend. - */ -void ssp_save_state(struct ssp_dev *dev, struct ssp_state *state) -{ - struct ssp_device *ssp = dev->ssp; - - state->cr0 = __raw_readl(ssp->mmio_base + SSCR0); - state->cr1 = __raw_readl(ssp->mmio_base + SSCR1); - state->to = __raw_readl(ssp->mmio_base + SSTO); - state->psp = __raw_readl(ssp->mmio_base + SSPSP); - - ssp_disable(dev); -} - -/** - * ssp_restore_state - restore a previously saved SSP configuration - * @ssp: pointer to configuration saved by ssp_save_state - * - * Restore the SSP configuration saved previously by ssp_save_state. - */ -void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *state) -{ - struct ssp_device *ssp = dev->ssp; - uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE; - - __raw_writel(sssr, ssp->mmio_base + SSSR); - - __raw_writel(state->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0); - __raw_writel(state->cr1, ssp->mmio_base + SSCR1); - __raw_writel(state->to, ssp->mmio_base + SSTO); - __raw_writel(state->psp, ssp->mmio_base + SSPSP); - __raw_writel(state->cr0, ssp->mmio_base + SSCR0); -} - -/** - * ssp_config - configure SSP port settings - * @mode: port operating mode - * @flags: port config flags - * @psp_flags: port PSP config flags - * @speed: port speed - * - * Port MUST be disabled by ssp_disable before making any config changes. - */ -int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed) -{ - struct ssp_device *ssp = dev->ssp; - - dev->mode = mode; - dev->flags = flags; - dev->psp_flags = psp_flags; - dev->speed = speed; - - /* set up port type, speed, port settings */ - __raw_writel((dev->speed | dev->mode), ssp->mmio_base + SSCR0); - __raw_writel(dev->flags, ssp->mmio_base + SSCR1); - __raw_writel(dev->psp_flags, ssp->mmio_base + SSPSP); - - return 0; -} - -/** - * ssp_init - setup the SSP port - * - * initialise and claim resources for the SSP port. - * - * Returns: - * %-ENODEV if the SSP port is unavailable - * %-EBUSY if the resources are already in use - * %0 on success - */ -int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags) -{ - struct ssp_device *ssp; - int ret; - - ssp = ssp_request(port, "SSP"); - if (ssp == NULL) - return -ENODEV; - - dev->ssp = ssp; - dev->port = port; - - /* do we need to get irq */ - if (!(init_flags & SSP_NO_IRQ)) { - ret = request_irq(ssp->irq, ssp_interrupt, - 0, "SSP", dev); - if (ret) - goto out_region; - dev->irq = ssp->irq; - } else - dev->irq = NO_IRQ; - - /* turn on SSP port clock */ - clk_enable(ssp->clk); - return 0; - -out_region: - ssp_free(ssp); - return ret; -} - -/** - * ssp_exit - undo the effects of ssp_init - * - * release and free resources for the SSP port. - */ -void ssp_exit(struct ssp_dev *dev) -{ - struct ssp_device *ssp = dev->ssp; - - ssp_disable(dev); - if (dev->irq != NO_IRQ) - free_irq(dev->irq, dev); - clk_disable(ssp->clk); - ssp_free(ssp); -} -#endif /* CONFIG_PXA_SSP_LEGACY */ - -static DEFINE_MUTEX(ssp_lock); -static LIST_HEAD(ssp_list); - -struct ssp_device *ssp_request(int port, const char *label) -{ - struct ssp_device *ssp = NULL; - - mutex_lock(&ssp_lock); - - list_for_each_entry(ssp, &ssp_list, node) { - if (ssp->port_id == port && ssp->use_count == 0) { - ssp->use_count++; - ssp->label = label; - break; - } - } - - mutex_unlock(&ssp_lock); - - if (&ssp->node == &ssp_list) - return NULL; - - return ssp; -} -EXPORT_SYMBOL(ssp_request); - -void ssp_free(struct ssp_device *ssp) -{ - mutex_lock(&ssp_lock); - if (ssp->use_count) { - ssp->use_count--; - ssp->label = NULL; - } else - dev_err(&ssp->pdev->dev, "device already free\n"); - mutex_unlock(&ssp_lock); -} -EXPORT_SYMBOL(ssp_free); - -static int __devinit ssp_probe(struct platform_device *pdev) -{ - const struct platform_device_id *id = platform_get_device_id(pdev); - struct resource *res; - struct ssp_device *ssp; - int ret = 0; - - ssp = kzalloc(sizeof(struct ssp_device), GFP_KERNEL); - if (ssp == NULL) { - dev_err(&pdev->dev, "failed to allocate memory"); - return -ENOMEM; - } - ssp->pdev = pdev; - - ssp->clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(ssp->clk)) { - ret = PTR_ERR(ssp->clk); - goto err_free; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res == NULL) { - dev_err(&pdev->dev, "no memory resource defined\n"); - ret = -ENODEV; - goto err_free_clk; - } - - res = request_mem_region(res->start, res->end - res->start + 1, - pdev->name); - if (res == NULL) { - dev_err(&pdev->dev, "failed to request memory resource\n"); - ret = -EBUSY; - goto err_free_clk; - } - - ssp->phys_base = res->start; - - ssp->mmio_base = ioremap(res->start, res->end - res->start + 1); - if (ssp->mmio_base == NULL) { - dev_err(&pdev->dev, "failed to ioremap() registers\n"); - ret = -ENODEV; - goto err_free_mem; - } - - ssp->irq = platform_get_irq(pdev, 0); - if (ssp->irq < 0) { - dev_err(&pdev->dev, "no IRQ resource defined\n"); - ret = -ENODEV; - goto err_free_io; - } - - res = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (res == NULL) { - dev_err(&pdev->dev, "no SSP RX DRCMR defined\n"); - ret = -ENODEV; - goto err_free_io; - } - ssp->drcmr_rx = res->start; - - res = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (res == NULL) { - dev_err(&pdev->dev, "no SSP TX DRCMR defined\n"); - ret = -ENODEV; - goto err_free_io; - } - ssp->drcmr_tx = res->start; - - /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id - * starts from 0, do a translation here - */ - ssp->port_id = pdev->id + 1; - ssp->use_count = 0; - ssp->type = (int)id->driver_data; - - mutex_lock(&ssp_lock); - list_add(&ssp->node, &ssp_list); - mutex_unlock(&ssp_lock); - - platform_set_drvdata(pdev, ssp); - return 0; - -err_free_io: - iounmap(ssp->mmio_base); -err_free_mem: - release_mem_region(res->start, res->end - res->start + 1); -err_free_clk: - clk_put(ssp->clk); -err_free: - kfree(ssp); - return ret; -} - -static int __devexit ssp_remove(struct platform_device *pdev) -{ - struct resource *res; - struct ssp_device *ssp; - - ssp = platform_get_drvdata(pdev); - if (ssp == NULL) - return -ENODEV; - - iounmap(ssp->mmio_base); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - release_mem_region(res->start, res->end - res->start + 1); - - clk_put(ssp->clk); - - mutex_lock(&ssp_lock); - list_del(&ssp->node); - mutex_unlock(&ssp_lock); - - kfree(ssp); - return 0; -} - -static const struct platform_device_id ssp_id_table[] = { - { "pxa25x-ssp", PXA25x_SSP }, - { "pxa25x-nssp", PXA25x_NSSP }, - { "pxa27x-ssp", PXA27x_SSP }, - { }, -}; - -static struct platform_driver ssp_driver = { - .probe = ssp_probe, - .remove = __devexit_p(ssp_remove), - .driver = { - .owner = THIS_MODULE, - .name = "pxa2xx-ssp", - }, - .id_table = ssp_id_table, -}; - -static int __init pxa_ssp_init(void) -{ - return platform_driver_register(&ssp_driver); -} - -static void __exit pxa_ssp_exit(void) -{ - platform_driver_unregister(&ssp_driver); -} - -arch_initcall(pxa_ssp_init); -module_exit(pxa_ssp_exit); - -#ifdef CONFIG_PXA_SSP_LEGACY -EXPORT_SYMBOL(ssp_write_word); -EXPORT_SYMBOL(ssp_read_word); -EXPORT_SYMBOL(ssp_flush); -EXPORT_SYMBOL(ssp_enable); -EXPORT_SYMBOL(ssp_disable); -EXPORT_SYMBOL(ssp_save_state); -EXPORT_SYMBOL(ssp_restore_state); -EXPORT_SYMBOL(ssp_init); -EXPORT_SYMBOL(ssp_exit); -EXPORT_SYMBOL(ssp_config); -#endif - -MODULE_DESCRIPTION("PXA SSP driver"); -MODULE_AUTHOR("Liam Girdwood"); -MODULE_LICENSE("GPL"); - diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 2041eb1d90b..af40d2a12d3 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -464,8 +464,6 @@ static struct platform_device smc91x_device = { -static struct pxamci_platform_data stargate2_mci_platform_data; - /* * The card detect interrupt isn't debounced so we delay it by 250ms * to give the card a chance to fully insert / eject. @@ -489,8 +487,6 @@ static int stargate2_mci_init(struct device *dev, goto free_power_en; } gpio_direction_input(SG2_GPIO_nSD_DETECT); - /* Delay to allow for full insertion */ - stargate2_mci_platform_data.detect_delay = msecs_to_jiffies(250); err = request_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT), stargate2_detect_int, @@ -529,6 +525,7 @@ static void stargate2_mci_exit(struct device *dev, void *data) } static struct pxamci_platform_data stargate2_mci_platform_data = { + .detect_delay_ms = 250, .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .init = stargate2_mci_init, .setpower = stargate2_mci_setpower, diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index ad552791c4c..7512b822c6c 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -275,6 +275,7 @@ static void tosa_mci_exit(struct device *dev, void *data) } static struct pxamci_platform_data tosa_mci_platform_data = { + .detect_delay_ms = 250, .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .init = tosa_mci_init, .exit = tosa_mci_exit, @@ -926,7 +927,6 @@ static void __init tosa_init(void) dummy = gpiochip_reserve(TOSA_SCOOP_JC_GPIO_BASE, 12); dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16); - tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250); pxa_set_mci_info(&tosa_mci_platform_data); pxa_set_udc_info(&udc_info); pxa_set_ficp_info(&tosa_ficp_platform_data); diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 797f2544d0c..69689112eae 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -349,7 +349,7 @@ static void trizeps4_mci_exit(struct device *dev, void *data) static struct pxamci_platform_data trizeps4_mci_platform_data = { .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .detect_delay = 1, + .detect_delay_ms= 10, .init = trizeps4_mci_init, .exit = trizeps4_mci_exit, .get_ro = NULL, /* write-protection not supported */ diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c new file mode 100644 index 00000000000..9884fa978f1 --- /dev/null +++ b/arch/arm/mach-pxa/vpac270.c @@ -0,0 +1,615 @@ +/* + * Hardware definitions for Voipac PXA270 + * + * Copyright (C) 2010 + * Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/irq.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/gpio.h> +#include <linux/sysdev.h> +#include <linux/usb/gpio_vbus.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/onenand.h> +#include <linux/dm9000.h> +#include <linux/ucb1400.h> +#include <linux/ata_platform.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/pxa27x.h> +#include <mach/audio.h> +#include <mach/vpac270.h> +#include <mach/mmc.h> +#include <mach/pxafb.h> +#include <mach/ohci.h> +#include <mach/pxa27x-udc.h> +#include <mach/udc.h> + +#include <plat/i2c.h> + +#include "generic.h" +#include "devices.h" + +/****************************************************************************** + * Pin configuration + ******************************************************************************/ +static unsigned long vpac270_pin_config[] __initdata = { + /* MMC */ + GPIO32_MMC_CLK, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + GPIO112_MMC_CMD, + GPIO53_GPIO, /* SD detect */ + GPIO52_GPIO, /* SD r/o switch */ + + /* GPIO KEYS */ + GPIO1_GPIO, /* USER BTN */ + + /* LEDs */ + GPIO15_GPIO, /* orange led */ + + /* FFUART */ + GPIO34_FFUART_RXD, + GPIO39_FFUART_TXD, + GPIO27_FFUART_RTS, + GPIO100_FFUART_CTS, + GPIO33_FFUART_DSR, + GPIO40_FFUART_DTR, + GPIO10_FFUART_DCD, + GPIO38_FFUART_RI, + + /* LCD */ + GPIO58_LCD_LDD_0, + GPIO59_LCD_LDD_1, + GPIO60_LCD_LDD_2, + GPIO61_LCD_LDD_3, + GPIO62_LCD_LDD_4, + GPIO63_LCD_LDD_5, + GPIO64_LCD_LDD_6, + GPIO65_LCD_LDD_7, + GPIO66_LCD_LDD_8, + GPIO67_LCD_LDD_9, + GPIO68_LCD_LDD_10, + GPIO69_LCD_LDD_11, + GPIO70_LCD_LDD_12, + GPIO71_LCD_LDD_13, + GPIO72_LCD_LDD_14, + GPIO73_LCD_LDD_15, + GPIO86_LCD_LDD_16, + GPIO87_LCD_LDD_17, + GPIO74_LCD_FCLK, + GPIO75_LCD_LCLK, + GPIO76_LCD_PCLK, + GPIO77_LCD_BIAS, + + /* PCMCIA */ + GPIO48_nPOE, + GPIO49_nPWE, + GPIO50_nPIOR, + GPIO51_nPIOW, + GPIO85_nPCE_1, + GPIO54_nPCE_2, + GPIO55_nPREG, + GPIO57_nIOIS16, + GPIO56_nPWAIT, + GPIO104_PSKTSEL, + GPIO84_GPIO, /* PCMCIA CD */ + GPIO35_GPIO, /* PCMCIA RDY */ + GPIO107_GPIO, /* PCMCIA PPEN */ + GPIO11_GPIO, /* PCMCIA RESET */ + GPIO17_GPIO, /* CF CD */ + GPIO12_GPIO, /* CF RDY */ + GPIO16_GPIO, /* CF RESET */ + + /* UHC */ + GPIO88_USBH1_PWR, + GPIO89_USBH1_PEN, + GPIO119_USBH2_PWR, + GPIO120_USBH2_PEN, + + /* UDC */ + GPIO41_GPIO, + + /* Ethernet */ + GPIO114_GPIO, /* IRQ */ + + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + GPIO95_AC97_nRESET, + GPIO98_AC97_SYSCLK, + GPIO113_GPIO, /* TS IRQ */ + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + + /* IDE */ + GPIO36_GPIO, /* IDE IRQ */ + GPIO80_DREQ_1, +}; + +/****************************************************************************** + * NOR Flash + ******************************************************************************/ +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) +static struct mtd_partition vpac270_nor_partitions[] = { + { + .name = "Flash", + .offset = 0x00000000, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct physmap_flash_data vpac270_flash_data[] = { + { + .width = 2, /* bankwidth in bytes */ + .parts = vpac270_nor_partitions, + .nr_parts = ARRAY_SIZE(vpac270_nor_partitions) + } +}; + +static struct resource vpac270_flash_resource = { + .start = PXA_CS0_PHYS, + .end = PXA_CS0_PHYS + SZ_64M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device vpac270_flash = { + .name = "physmap-flash", + .id = 0, + .resource = &vpac270_flash_resource, + .num_resources = 1, + .dev = { + .platform_data = vpac270_flash_data, + }, +}; +static void __init vpac270_nor_init(void) +{ + platform_device_register(&vpac270_flash); +} +#else +static inline void vpac270_nor_init(void) {} +#endif + +/****************************************************************************** + * OneNAND Flash + ******************************************************************************/ +#if defined(CONFIG_MTD_ONENAND) || defined(CONFIG_MTD_ONENAND_MODULE) +static struct mtd_partition vpac270_onenand_partitions[] = { + { + .name = "Flash", + .offset = 0x00000000, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct onenand_platform_data vpac270_onenand_info = { + .parts = vpac270_onenand_partitions, + .nr_parts = ARRAY_SIZE(vpac270_onenand_partitions), +}; + +static struct resource vpac270_onenand_resources[] = { + [0] = { + .start = PXA_CS0_PHYS, + .end = PXA_CS0_PHYS + SZ_1M, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device vpac270_onenand = { + .name = "onenand-flash", + .id = -1, + .resource = vpac270_onenand_resources, + .num_resources = ARRAY_SIZE(vpac270_onenand_resources), + .dev = { + .platform_data = &vpac270_onenand_info, + }, +}; + +static void __init vpac270_onenand_init(void) +{ + platform_device_register(&vpac270_onenand); +} +#else +static void __init vpac270_onenand_init(void) {} +#endif + +/****************************************************************************** + * SD/MMC card controller + ******************************************************************************/ +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +static struct pxamci_platform_data vpac270_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = GPIO53_VPAC270_SD_DETECT_N, + .gpio_card_ro = GPIO52_VPAC270_SD_READONLY, + .detect_delay_ms = 200, +}; + +static void __init vpac270_mmc_init(void) +{ + pxa_set_mci_info(&vpac270_mci_platform_data); +} +#else +static inline void vpac270_mmc_init(void) {} +#endif + +/****************************************************************************** + * GPIO keys + ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button vpac270_pxa_buttons[] = { + {KEY_POWER, GPIO1_VPAC270_USER_BTN, 0, "USER BTN"}, +}; + +static struct gpio_keys_platform_data vpac270_pxa_keys_data = { + .buttons = vpac270_pxa_buttons, + .nbuttons = ARRAY_SIZE(vpac270_pxa_buttons), +}; + +static struct platform_device vpac270_pxa_keys = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &vpac270_pxa_keys_data, + }, +}; + +static void __init vpac270_keys_init(void) +{ + platform_device_register(&vpac270_pxa_keys); +} +#else +static inline void vpac270_keys_init(void) {} +#endif + +/****************************************************************************** + * LED + ******************************************************************************/ +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +struct gpio_led vpac270_gpio_leds[] = { +{ + .name = "vpac270:orange:user", + .default_trigger = "none", + .gpio = GPIO15_VPAC270_LED_ORANGE, + .active_low = 1, +} +}; + +static struct gpio_led_platform_data vpac270_gpio_led_info = { + .leds = vpac270_gpio_leds, + .num_leds = ARRAY_SIZE(vpac270_gpio_leds), +}; + +static struct platform_device vpac270_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &vpac270_gpio_led_info, + } +}; + +static void __init vpac270_leds_init(void) +{ + platform_device_register(&vpac270_leds); +} +#else +static inline void vpac270_leds_init(void) {} +#endif + +/****************************************************************************** + * USB Host + ******************************************************************************/ +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) +static int vpac270_ohci_init(struct device *dev) +{ + UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE; + return 0; +} + +static struct pxaohci_platform_data vpac270_ohci_info = { + .port_mode = PMM_PERPORT_MODE, + .flags = ENABLE_PORT1 | ENABLE_PORT2 | + POWER_CONTROL_LOW | POWER_SENSE_LOW, + .init = vpac270_ohci_init, +}; + +static void __init vpac270_uhc_init(void) +{ + pxa_set_ohci_info(&vpac270_ohci_info); +} +#else +static inline void vpac270_uhc_init(void) {} +#endif + +/****************************************************************************** + * USB Gadget + ******************************************************************************/ +#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE) +static struct gpio_vbus_mach_info vpac270_gpio_vbus_info = { + .gpio_vbus = GPIO41_VPAC270_UDC_DETECT, + .gpio_pullup = -1, +}; + +static struct platform_device vpac270_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &vpac270_gpio_vbus_info, + }, +}; + +static void vpac270_udc_command(int cmd) +{ + if (cmd == PXA2XX_UDC_CMD_CONNECT) + UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE; + else if (cmd == PXA2XX_UDC_CMD_DISCONNECT) + UP2OCR = UP2OCR_HXOE; +} + +static struct pxa2xx_udc_mach_info vpac270_udc_info __initdata = { + .udc_command = vpac270_udc_command, + .gpio_pullup = -1, +}; + +static void __init vpac270_udc_init(void) +{ + pxa_set_udc_info(&vpac270_udc_info); + platform_device_register(&vpac270_gpio_vbus); +} +#else +static inline void vpac270_udc_init(void) {} +#endif + +/****************************************************************************** + * Ethernet + ******************************************************************************/ +#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) +static struct resource vpac270_dm9000_resources[] = { + [0] = { + .start = PXA_CS2_PHYS + 0x300, + .end = PXA_CS2_PHYS + 0x303, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PXA_CS2_PHYS + 0x304, + .end = PXA_CS2_PHYS + 0x343, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ), + .end = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + }, +}; + +static struct dm9000_plat_data vpac270_dm9000_platdata = { + .flags = DM9000_PLATF_32BITONLY, +}; + +static struct platform_device vpac270_dm9000_device = { + .name = "dm9000", + .id = -1, + .num_resources = ARRAY_SIZE(vpac270_dm9000_resources), + .resource = vpac270_dm9000_resources, + .dev = { + .platform_data = &vpac270_dm9000_platdata, + } +}; + +static void __init vpac270_eth_init(void) +{ + platform_device_register(&vpac270_dm9000_device); +} +#else +static inline void vpac270_eth_init(void) {} +#endif + +/****************************************************************************** + * Audio and Touchscreen + ******************************************************************************/ +#if defined(CONFIG_TOUCHSCREEN_UCB1400) || \ + defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE) +static pxa2xx_audio_ops_t vpac270_ac97_pdata = { + .reset_gpio = 95, +}; + +static struct ucb1400_pdata vpac270_ucb1400_pdata = { + .irq = IRQ_GPIO(GPIO113_VPAC270_TS_IRQ), +}; + +static struct platform_device vpac270_ucb1400_device = { + .name = "ucb1400_core", + .id = -1, + .dev = { + .platform_data = &vpac270_ucb1400_pdata, + }, +}; + +static void __init vpac270_ts_init(void) +{ + pxa_set_ac97_info(&vpac270_ac97_pdata); + platform_device_register(&vpac270_ucb1400_device); +} +#else +static inline void vpac270_ts_init(void) {} +#endif + +/****************************************************************************** + * RTC + ******************************************************************************/ +#if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE) +static struct i2c_board_info __initdata vpac270_i2c_devs[] = { + { + I2C_BOARD_INFO("ds1339", 0x68), + }, +}; + +static void __init vpac270_rtc_init(void) +{ + pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(vpac270_i2c_devs)); +} +#else +static inline void vpac270_rtc_init(void) {} +#endif + +/****************************************************************************** + * Framebuffer + ******************************************************************************/ +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +static struct pxafb_mode_info vpac270_lcd_modes[] = { +{ + .pixclock = 57692, + .xres = 640, + .yres = 480, + .bpp = 32, + .depth = 18, + + .left_margin = 144, + .right_margin = 32, + .upper_margin = 13, + .lower_margin = 30, + + .hsync_len = 32, + .vsync_len = 2, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +}, +}; + +static struct pxafb_mach_info vpac270_lcd_screen = { + .modes = vpac270_lcd_modes, + .num_modes = ARRAY_SIZE(vpac270_lcd_modes), + .lcd_conn = LCD_COLOR_TFT_18BPP, +}; + +static void vpac270_lcd_power(int on, struct fb_var_screeninfo *info) +{ + gpio_set_value(GPIO81_VPAC270_BKL_ON, on); +} + +static void __init vpac270_lcd_init(void) +{ + int ret; + + ret = gpio_request(GPIO81_VPAC270_BKL_ON, "BKL-ON"); + if (ret) { + pr_err("Requesting BKL-ON GPIO failed!\n"); + goto err; + } + + ret = gpio_direction_output(GPIO81_VPAC270_BKL_ON, 1); + if (ret) { + pr_err("Setting BKL-ON GPIO direction failed!\n"); + goto err2; + } + + vpac270_lcd_screen.pxafb_lcd_power = vpac270_lcd_power; + set_pxa_fb_info(&vpac270_lcd_screen); + return; + +err2: + gpio_free(GPIO81_VPAC270_BKL_ON); +err: + return; +} +#else +static inline void vpac270_lcd_init(void) {} +#endif + +/****************************************************************************** + * PATA IDE + ******************************************************************************/ +#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) +static struct pata_platform_info vpac270_pata_pdata = { + .ioport_shift = 1, + .irq_flags = IRQF_TRIGGER_RISING, +}; + +static struct resource vpac270_ide_resources[] = { + [0] = { /* I/O Base address */ + .start = PXA_CS3_PHYS + 0x120, + .end = PXA_CS3_PHYS + 0x13f, + .flags = IORESOURCE_MEM + }, + [1] = { /* CTL Base address */ + .start = PXA_CS3_PHYS + 0x15c, + .end = PXA_CS3_PHYS + 0x15f, + .flags = IORESOURCE_MEM + }, + [2] = { /* IDE IRQ pin */ + .start = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), + .end = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device vpac270_ide_device = { + .name = "pata_platform", + .num_resources = ARRAY_SIZE(vpac270_ide_resources), + .resource = vpac270_ide_resources, + .dev = { + .platform_data = &vpac270_pata_pdata, + } +}; + +static void __init vpac270_ide_init(void) +{ + platform_device_register(&vpac270_ide_device); +} +#else +static inline void vpac270_ide_init(void) {} +#endif + +/****************************************************************************** + * Machine init + ******************************************************************************/ +static void __init vpac270_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(vpac270_pin_config)); + + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + + vpac270_lcd_init(); + vpac270_mmc_init(); + vpac270_nor_init(); + vpac270_onenand_init(); + vpac270_leds_init(); + vpac270_keys_init(); + vpac270_uhc_init(); + vpac270_udc_init(); + vpac270_eth_init(); + vpac270_ts_init(); + vpac270_rtc_init(); + vpac270_ide_init(); +} + +MACHINE_START(VPAC270, "Voipac PXA270") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa27x_init_irq, + .timer = &pxa_timer, + .init_machine = vpac270_init +MACHINE_END diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c new file mode 100644 index 00000000000..f5d1ae3db3a --- /dev/null +++ b/arch/arm/mach-pxa/z2.c @@ -0,0 +1,609 @@ +/* + * linux/arch/arm/mach-pxa/z2.c + * + * Support for the Zipit Z2 Handheld device. + * + * Author: Ken McGuire + * Created: Jan 25, 2009 + * Based on mainstone.c as modified for the Zipit Z2. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/pwm_backlight.h> +#include <linux/dma-mapping.h> +#include <linux/spi/spi.h> +#include <linux/spi/libertas_spi.h> +#include <linux/spi/lms283gf05.h> +#include <linux/power_supply.h> +#include <linux/mtd/physmap.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/delay.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/pxa27x.h> +#include <mach/mfp-pxa27x.h> +#include <mach/z2.h> +#include <mach/pxafb.h> +#include <mach/mmc.h> +#include <mach/pxa27x_keypad.h> +#include <mach/pxa2xx_spi.h> + +#include <plat/i2c.h> + +#include "generic.h" +#include "devices.h" + +/****************************************************************************** + * Pin configuration + ******************************************************************************/ +static unsigned long z2_pin_config[] = { + + /* LCD - 16bpp Active TFT */ + GPIO58_LCD_LDD_0, + GPIO59_LCD_LDD_1, + GPIO60_LCD_LDD_2, + GPIO61_LCD_LDD_3, + GPIO62_LCD_LDD_4, + GPIO63_LCD_LDD_5, + GPIO64_LCD_LDD_6, + GPIO65_LCD_LDD_7, + GPIO66_LCD_LDD_8, + GPIO67_LCD_LDD_9, + GPIO68_LCD_LDD_10, + GPIO69_LCD_LDD_11, + GPIO70_LCD_LDD_12, + GPIO71_LCD_LDD_13, + GPIO72_LCD_LDD_14, + GPIO73_LCD_LDD_15, + GPIO74_LCD_FCLK, + GPIO75_LCD_LCLK, + GPIO76_LCD_PCLK, + GPIO77_LCD_BIAS, + GPIO19_GPIO, /* LCD reset */ + GPIO88_GPIO, /* LCD chipselect */ + + /* PWM */ + GPIO115_PWM1_OUT, /* Keypad Backlight */ + GPIO11_PWM2_OUT, /* LCD Backlight */ + + /* MMC */ + GPIO32_MMC_CLK, + GPIO112_MMC_CMD, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + GPIO96_GPIO, /* SD detect */ + + /* STUART */ + GPIO46_STUART_RXD, + GPIO47_STUART_TXD, + + /* Keypad */ + GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, + GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, + GPIO34_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, + GPIO38_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, + GPIO16_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH, + GPIO17_KP_MKIN_6 | WAKEUP_ON_LEVEL_HIGH, + GPIO103_KP_MKOUT_0, + GPIO104_KP_MKOUT_1, + GPIO105_KP_MKOUT_2, + GPIO106_KP_MKOUT_3, + GPIO107_KP_MKOUT_4, + GPIO108_KP_MKOUT_5, + GPIO35_KP_MKOUT_6, + GPIO41_KP_MKOUT_7, + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + + /* SSP1 */ + GPIO23_SSP1_SCLK, /* SSP1_SCK */ + GPIO25_SSP1_TXD, /* SSP1_TXD */ + GPIO26_SSP1_RXD, /* SSP1_RXD */ + + /* SSP2 */ + GPIO22_SSP2_SCLK, /* SSP2_SCK */ + GPIO13_SSP2_TXD, /* SSP2_TXD */ + GPIO40_SSP2_RXD, /* SSP2_RXD */ + + /* LEDs */ + GPIO10_GPIO, /* WiFi LED */ + GPIO83_GPIO, /* Charging LED */ + GPIO85_GPIO, /* Charged LED */ + + /* I2S */ + GPIO28_I2S_BITCLK_OUT, + GPIO29_I2S_SDATA_IN, + GPIO30_I2S_SDATA_OUT, + GPIO31_I2S_SYNC, + GPIO113_I2S_SYSCLK, + + /* MISC */ + GPIO0_GPIO, /* AC power detect */ + GPIO1_GPIO, /* Power button */ + GPIO37_GPIO, /* Headphone detect */ + GPIO98_GPIO, /* Lid switch */ + GPIO14_GPIO, /* WiFi Reset */ + GPIO15_GPIO, /* WiFi Power */ + GPIO24_GPIO, /* WiFi CS */ + GPIO36_GPIO, /* WiFi IRQ */ + GPIO88_GPIO, /* LCD CS */ +}; + +/****************************************************************************** + * NOR Flash + ******************************************************************************/ +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) +static struct resource z2_flash_resource = { + .start = PXA_CS0_PHYS, + .end = PXA_CS0_PHYS + SZ_8M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct mtd_partition z2_flash_parts[] = { + { + .name = "U-Boot Bootloader", + .offset = 0x0, + .size = 0x20000, + }, + { + .name = "Linux Kernel", + .offset = 0x20000, + .size = 0x220000, + }, + { + .name = "Filesystem", + .offset = 0x240000, + .size = 0x5b0000, + }, + { + .name = "U-Boot Environment", + .offset = 0x7f0000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data z2_flash_data = { + .width = 2, + .parts = z2_flash_parts, + .nr_parts = ARRAY_SIZE(z2_flash_parts), +}; + +static struct platform_device z2_flash = { + .name = "physmap-flash", + .id = -1, + .resource = &z2_flash_resource, + .num_resources = 1, + .dev = { + .platform_data = &z2_flash_data, + }, +}; + +static void __init z2_nor_init(void) +{ + platform_device_register(&z2_flash); +} +#else +static inline void z2_nor_init(void) {} +#endif + +/****************************************************************************** + * Backlight + ******************************************************************************/ +#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) +static struct platform_pwm_backlight_data z2_backlight_data[] = { + [0] = { + /* Keypad Backlight */ + .pwm_id = 1, + .max_brightness = 1023, + .dft_brightness = 512, + .pwm_period_ns = 1260320, + }, + [1] = { + /* LCD Backlight */ + .pwm_id = 2, + .max_brightness = 1023, + .dft_brightness = 512, + .pwm_period_ns = 1260320, + }, +}; + +static struct platform_device z2_backlight_devices[2] = { + { + .name = "pwm-backlight", + .id = 0, + .dev = { + .platform_data = &z2_backlight_data[1], + }, + }, + { + .name = "pwm-backlight", + .id = 1, + .dev = { + .platform_data = &z2_backlight_data[0], + }, + }, +}; +static void __init z2_pwm_init(void) +{ + platform_device_register(&z2_backlight_devices[0]); + platform_device_register(&z2_backlight_devices[1]); +} +#else +static inline void z2_pwm_init(void) {} +#endif + +/****************************************************************************** + * Framebuffer + ******************************************************************************/ +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +static struct pxafb_mode_info z2_lcd_modes[] = { +{ + .pixclock = 192000, + .xres = 240, + .yres = 320, + .bpp = 16, + + .left_margin = 4, + .right_margin = 8, + .upper_margin = 4, + .lower_margin = 8, + + .hsync_len = 4, + .vsync_len = 4, +}, +}; + +static struct pxafb_mach_info z2_lcd_screen = { + .modes = z2_lcd_modes, + .num_modes = ARRAY_SIZE(z2_lcd_modes), + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_BIAS_ACTIVE_LOW | + LCD_ALTERNATE_MAPPING, +}; + +static void __init z2_lcd_init(void) +{ + set_pxa_fb_info(&z2_lcd_screen); +} +#else +static inline void z2_lcd_init(void) {} +#endif + +/****************************************************************************** + * SD/MMC card controller + ******************************************************************************/ +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +static struct pxamci_platform_data z2_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = GPIO96_ZIPITZ2_SD_DETECT, + .gpio_power = -1, + .gpio_card_ro = -1, + .detect_delay_ms = 200, +}; + +static void __init z2_mmc_init(void) +{ + pxa_set_mci_info(&z2_mci_platform_data); +} +#else +static inline void z2_mmc_init(void) {} +#endif + +/****************************************************************************** + * LEDs + ******************************************************************************/ +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +struct gpio_led z2_gpio_leds[] = { +{ + .name = "z2:green:wifi", + .default_trigger = "none", + .gpio = GPIO10_ZIPITZ2_LED_WIFI, + .active_low = 1, +}, { + .name = "z2:green:charged", + .default_trigger = "none", + .gpio = GPIO85_ZIPITZ2_LED_CHARGED, + .active_low = 1, +}, { + .name = "z2:amber:charging", + .default_trigger = "none", + .gpio = GPIO83_ZIPITZ2_LED_CHARGING, + .active_low = 1, +}, +}; + +static struct gpio_led_platform_data z2_gpio_led_info = { + .leds = z2_gpio_leds, + .num_leds = ARRAY_SIZE(z2_gpio_leds), +}; + +static struct platform_device z2_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &z2_gpio_led_info, + } +}; + +static void __init z2_leds_init(void) +{ + platform_device_register(&z2_leds); +} +#else +static inline void z2_leds_init(void) {} +#endif + +/****************************************************************************** + * GPIO keyboard + ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) +static unsigned int z2_matrix_keys[] = { + KEY(0, 0, KEY_OPTION), + KEY(1, 0, KEY_UP), + KEY(2, 0, KEY_DOWN), + KEY(3, 0, KEY_LEFT), + KEY(4, 0, KEY_RIGHT), + KEY(5, 0, KEY_END), + KEY(6, 0, KEY_KPPLUS), + + KEY(0, 1, KEY_HOME), + KEY(1, 1, KEY_Q), + KEY(2, 1, KEY_I), + KEY(3, 1, KEY_G), + KEY(4, 1, KEY_X), + KEY(5, 1, KEY_ENTER), + KEY(6, 1, KEY_KPMINUS), + + KEY(0, 2, KEY_PAGEUP), + KEY(1, 2, KEY_W), + KEY(2, 2, KEY_O), + KEY(3, 2, KEY_H), + KEY(4, 2, KEY_C), + KEY(5, 2, KEY_LEFTALT), + + KEY(0, 3, KEY_PAGEDOWN), + KEY(1, 3, KEY_E), + KEY(2, 3, KEY_P), + KEY(3, 3, KEY_J), + KEY(4, 3, KEY_V), + KEY(5, 3, KEY_LEFTSHIFT), + + KEY(0, 4, KEY_ESC), + KEY(1, 4, KEY_R), + KEY(2, 4, KEY_A), + KEY(3, 4, KEY_K), + KEY(4, 4, KEY_B), + KEY(5, 4, KEY_LEFTCTRL), + + KEY(0, 5, KEY_TAB), + KEY(1, 5, KEY_T), + KEY(2, 5, KEY_S), + KEY(3, 5, KEY_L), + KEY(4, 5, KEY_N), + KEY(5, 5, KEY_SPACE), + + KEY(0, 6, KEY_STOPCD), + KEY(1, 6, KEY_Y), + KEY(2, 6, KEY_D), + KEY(3, 6, KEY_BACKSPACE), + KEY(4, 6, KEY_M), + KEY(5, 6, KEY_COMMA), + + KEY(0, 7, KEY_PLAYCD), + KEY(1, 7, KEY_U), + KEY(2, 7, KEY_F), + KEY(3, 7, KEY_Z), + KEY(4, 7, KEY_SEMICOLON), + KEY(5, 7, KEY_DOT), +}; + +static struct pxa27x_keypad_platform_data z2_keypad_platform_data = { + .matrix_key_rows = 7, + .matrix_key_cols = 8, + .matrix_key_map = z2_matrix_keys, + .matrix_key_map_size = ARRAY_SIZE(z2_matrix_keys), + + .debounce_interval = 30, +}; + +static void __init z2_mkp_init(void) +{ + pxa_set_keypad_info(&z2_keypad_platform_data); +} +#else +static inline void z2_mkp_init(void) {} +#endif + +/****************************************************************************** + * GPIO keys + ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button z2_pxa_buttons[] = { + {KEY_POWER, GPIO1_ZIPITZ2_POWER_BUTTON, 0, "Power Button" }, + {KEY_CLOSE, GPIO98_ZIPITZ2_LID_BUTTON, 0, "Lid Button" }, +}; + +static struct gpio_keys_platform_data z2_pxa_keys_data = { + .buttons = z2_pxa_buttons, + .nbuttons = ARRAY_SIZE(z2_pxa_buttons), +}; + +static struct platform_device z2_pxa_keys = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &z2_pxa_keys_data, + }, +}; + +static void __init z2_keys_init(void) +{ + platform_device_register(&z2_pxa_keys); +} +#else +static inline void z2_keys_init(void) {} +#endif + +/****************************************************************************** + * SSP Devices - WiFi and LCD control + ******************************************************************************/ +#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE) +/* WiFi */ +static int z2_lbs_spi_setup(struct spi_device *spi) +{ + int ret = 0; + + ret = gpio_request(GPIO15_ZIPITZ2_WIFI_POWER, "WiFi Power"); + if (ret) + goto err; + + ret = gpio_direction_output(GPIO15_ZIPITZ2_WIFI_POWER, 1); + if (ret) + goto err2; + + ret = gpio_request(GPIO14_ZIPITZ2_WIFI_RESET, "WiFi Reset"); + if (ret) + goto err2; + + ret = gpio_direction_output(GPIO14_ZIPITZ2_WIFI_RESET, 0); + if (ret) + goto err3; + + /* Reset the card */ + mdelay(180); + gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 1); + mdelay(20); + + spi->bits_per_word = 16; + spi->mode = SPI_MODE_2, + + spi_setup(spi); + + return 0; + +err3: + gpio_free(GPIO14_ZIPITZ2_WIFI_RESET); +err2: + gpio_free(GPIO15_ZIPITZ2_WIFI_POWER); +err: + return ret; +}; + +static int z2_lbs_spi_teardown(struct spi_device *spi) +{ + gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 0); + gpio_set_value(GPIO15_ZIPITZ2_WIFI_POWER, 0); + gpio_free(GPIO14_ZIPITZ2_WIFI_RESET); + gpio_free(GPIO15_ZIPITZ2_WIFI_POWER); + return 0; + +}; + +static struct pxa2xx_spi_chip z2_lbs_chip_info = { + .rx_threshold = 8, + .tx_threshold = 8, + .timeout = 1000, + .gpio_cs = GPIO24_ZIPITZ2_WIFI_CS, +}; + +static struct libertas_spi_platform_data z2_lbs_pdata = { + .use_dummy_writes = 1, + .setup = z2_lbs_spi_setup, + .teardown = z2_lbs_spi_teardown, +}; + +/* LCD */ +static struct pxa2xx_spi_chip lms283_chip_info = { + .rx_threshold = 1, + .tx_threshold = 1, + .timeout = 64, + .gpio_cs = GPIO88_ZIPITZ2_LCD_CS, +}; + +static const struct lms283gf05_pdata lms283_pdata = { + .reset_gpio = GPIO19_ZIPITZ2_LCD_RESET, +}; + +static struct spi_board_info spi_board_info[] __initdata = { +{ + .modalias = "libertas_spi", + .platform_data = &z2_lbs_pdata, + .controller_data = &z2_lbs_chip_info, + .irq = gpio_to_irq(GPIO36_ZIPITZ2_WIFI_IRQ), + .max_speed_hz = 13000000, + .bus_num = 1, + .chip_select = 0, +}, +{ + .modalias = "lms283gf05", + .controller_data = &lms283_chip_info, + .platform_data = &lms283_pdata, + .max_speed_hz = 400000, + .bus_num = 2, + .chip_select = 0, +}, +}; + +static struct pxa2xx_spi_master pxa_ssp1_master_info = { + .clock_enable = CKEN_SSP, + .num_chipselect = 1, + .enable_dma = 1, +}; + +static struct pxa2xx_spi_master pxa_ssp2_master_info = { + .clock_enable = CKEN_SSP2, + .num_chipselect = 1, +}; + +static void __init z2_spi_init(void) +{ + pxa2xx_set_spi_info(1, &pxa_ssp1_master_info); + pxa2xx_set_spi_info(2, &pxa_ssp2_master_info); + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); +} +#else +static inline void z2_spi_init(void) {} +#endif + +/****************************************************************************** + * Machine init + ******************************************************************************/ +static void __init z2_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(z2_pin_config)); + + z2_lcd_init(); + z2_mmc_init(); + z2_mkp_init(); + + pxa_set_i2c_info(NULL); + + z2_spi_init(); + z2_nor_init(); + z2_pwm_init(); + z2_leds_init(); + z2_keys_init(); +} + +MACHINE_START(ZIPIT2, "Zipit Z2") + .phys_io = 0x40000000, + .boot_params = 0xa0000100, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = pxa27x_init_irq, + .timer = &pxa_timer, + .init_machine = z2_init, +MACHINE_END diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 39896d88358..03b9cb910e0 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -414,15 +414,13 @@ static int zeus_mcp2515_transceiver_enable(int enable) static struct mcp251x_platform_data zeus_mcp2515_pdata = { .oscillator_frequency = 16*1000*1000, - .model = CAN_MCP251X_MCP2515, .board_specific_setup = zeus_mcp2515_setup, - .transceiver_enable = zeus_mcp2515_transceiver_enable, .power_enable = zeus_mcp2515_transceiver_enable, }; static struct spi_board_info zeus_spi_board_info[] = { [0] = { - .modalias = "mcp251x", + .modalias = "mcp2515", .platform_data = &zeus_mcp2515_pdata, .irq = gpio_to_irq(ZEUS_CAN_GPIO), .max_speed_hz = 1*1000*1000, @@ -644,7 +642,7 @@ static struct pxafb_mach_info zeus_fb_info = { static struct pxamci_platform_data zeus_mci_platform_data = { .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .detect_delay = HZ/4, + .detect_delay_ms = 250, .gpio_card_detect = ZEUS_MMC_CD_GPIO, .gpio_card_ro = ZEUS_MMC_WP_GPIO, .gpio_card_ro_invert = 1, diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 2b4043c04d0..c479cbecf78 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -218,7 +218,7 @@ static inline void zylonite_init_lcd(void) {} #if defined(CONFIG_MMC) static struct pxamci_platform_data zylonite_mci_platform_data = { - .detect_delay = 20, + .detect_delay_ms= 200, .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .gpio_card_detect = EXT_GPIO(0), .gpio_card_ro = EXT_GPIO(2), @@ -226,7 +226,7 @@ static struct pxamci_platform_data zylonite_mci_platform_data = { }; static struct pxamci_platform_data zylonite_mci2_platform_data = { - .detect_delay = 20, + .detect_delay_ms= 200, .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .gpio_card_detect = EXT_GPIO(1), .gpio_card_ro = EXT_GPIO(3), @@ -234,7 +234,7 @@ static struct pxamci_platform_data zylonite_mci2_platform_data = { }; static struct pxamci_platform_data zylonite_mci3_platform_data = { - .detect_delay = 20, + .detect_delay_ms= 200, .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .gpio_card_detect = EXT_GPIO(30), .gpio_card_ro = EXT_GPIO(31), diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile index e704edb733c..a01b76b7c95 100644 --- a/arch/arm/mach-realview/Makefile +++ b/arch/arm/mach-realview/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := core.o clock.o +obj-y := core.o obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o diff --git a/arch/arm/mach-realview/clock.c b/arch/arm/mach-realview/clock.c deleted file mode 100644 index a7043115de7..00000000000 --- a/arch/arm/mach-realview/clock.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * linux/arch/arm/mach-realview/clock.c - * - * Copyright (C) 2004 ARM Limited. - * Written by Deep Blue Solutions Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/string.h> -#include <linux/clk.h> -#include <linux/mutex.h> - -#include <asm/hardware/icst307.h> - -#include "clock.h" - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - struct icst307_vco vco; - vco = icst307_khz_to_vco(clk->params, rate / 1000); - return icst307_khz(clk->params, vco) * 1000; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EIO; - - if (clk->setvco) { - struct icst307_vco vco; - - vco = icst307_khz_to_vco(clk->params, rate / 1000); - clk->rate = icst307_khz(clk->params, vco) * 1000; - clk->setvco(clk, vco); - ret = 0; - } - return ret; -} -EXPORT_SYMBOL(clk_set_rate); diff --git a/arch/arm/mach-realview/clock.h b/arch/arm/mach-realview/clock.h deleted file mode 100644 index ebbb0f06b60..00000000000 --- a/arch/arm/mach-realview/clock.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * linux/arch/arm/mach-realview/clock.h - * - * Copyright (C) 2004 ARM Limited. - * Written by Deep Blue Solutions Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -struct module; -struct icst307_params; - -struct clk { - unsigned long rate; - const struct icst307_params *params; - void *data; - void (*setvco)(struct clk *, struct icst307_vco vco); -}; diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index d5a95738f85..595be19f8ad 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -25,8 +25,6 @@ #include <linux/interrupt.h> #include <linux/amba/bus.h> #include <linux/amba/clcd.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> #include <linux/io.h> #include <linux/smsc911x.h> #include <linux/ata_platform.h> @@ -40,7 +38,7 @@ #include <asm/leds.h> #include <asm/mach-types.h> #include <asm/hardware/arm_timer.h> -#include <asm/hardware/icst307.h> +#include <asm/hardware/icst.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> @@ -49,13 +47,12 @@ #include <asm/hardware/gic.h> +#include <mach/clkdev.h> #include <mach/platform.h> #include <mach/irqs.h> +#include <plat/timer-sp.h> #include "core.h" -#include "clock.h" - -#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) /* used by entry-macro.S and platsmp.c */ void __iomem *gic_cpu_base_addr; @@ -79,20 +76,6 @@ void __init realview_adjust_zones(int node, unsigned long *size, } #endif -/* - * This is the RealView sched_clock implementation. This has - * a resolution of 41.7ns, and a maximum value of about 179s. - */ -unsigned long long sched_clock(void) -{ - unsigned long long v; - - v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125; - do_div(v, 3); - - return v; -} - #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) @@ -274,37 +257,40 @@ struct mmci_platform_data realview_mmc1_plat_data = { /* * Clock handling */ -static const struct icst307_params realview_oscvco_params = { - .ref = 24000, - .vco_max = 200000, +static const struct icst_params realview_oscvco_params = { + .ref = 24000000, + .vco_max = ICST307_VCO_MAX, + .vco_min = ICST307_VCO_MIN, .vd_min = 4 + 8, .vd_max = 511 + 8, .rd_min = 1 + 2, .rd_max = 127 + 2, + .s2div = icst307_s2div, + .idx2s = icst307_idx2s, }; -static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco) +static void realview_oscvco_set(struct clk *clk, struct icst_vco vco) { void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET; - void __iomem *sys_osc; u32 val; - if (machine_is_realview_pb1176()) - sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET; - else - sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET; - - val = readl(sys_osc) & ~0x7ffff; + val = readl(clk->vcoreg) & ~0x7ffff; val |= vco.v | (vco.r << 9) | (vco.s << 16); writel(0xa05f, sys_lock); - writel(val, sys_osc); + writel(val, clk->vcoreg); writel(0, sys_lock); } +static const struct clk_ops oscvco_clk_ops = { + .round = icst_clk_round, + .set = icst_clk_set, + .setvco = realview_oscvco_set, +}; + static struct clk oscvco_clk = { + .ops = &oscvco_clk_ops, .params = &realview_oscvco_params, - .setvco = realview_oscvco_set, }; /* @@ -347,7 +333,13 @@ static struct clk_lookup lookups[] = { static int __init clk_init(void) { + if (machine_is_realview_pb1176()) + oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET; + else + oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET; + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + return 0; } arch_initcall(clk_init); @@ -644,133 +636,6 @@ void __iomem *timer2_va_base; void __iomem *timer3_va_base; /* - * How long is the timer interval? - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) -#if TIMER_INTERVAL >= 0x100000 -#define TIMER_RELOAD (TIMER_INTERVAL >> 8) -#define TIMER_DIVISOR (TIMER_CTRL_DIV256) -#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) -#elif TIMER_INTERVAL >= 0x10000 -#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */ -#define TIMER_DIVISOR (TIMER_CTRL_DIV16) -#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) -#else -#define TIMER_RELOAD (TIMER_INTERVAL) -#define TIMER_DIVISOR (TIMER_CTRL_DIV1) -#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) -#endif - -static void timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk) -{ - unsigned long ctrl; - - switch(mode) { - case CLOCK_EVT_MODE_PERIODIC: - writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD); - - ctrl = TIMER_CTRL_PERIODIC; - ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; - break; - case CLOCK_EVT_MODE_ONESHOT: - /* period set, and timer enabled in 'next_event' hook */ - ctrl = TIMER_CTRL_ONESHOT; - ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE; - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - default: - ctrl = 0; - } - - writel(ctrl, timer0_va_base + TIMER_CTRL); -} - -static int timer_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL); - - writel(evt, timer0_va_base + TIMER_LOAD); - writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL); - - return 0; -} - -static struct clock_event_device timer0_clockevent = { - .name = "timer0", - .shift = 32, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = timer_set_mode, - .set_next_event = timer_set_next_event, - .rating = 300, - .cpumask = cpu_all_mask, -}; - -static void __init realview_clockevents_init(unsigned int timer_irq) -{ - timer0_clockevent.irq = timer_irq; - timer0_clockevent.mult = - div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); - timer0_clockevent.max_delta_ns = - clockevent_delta2ns(0xffffffff, &timer0_clockevent); - timer0_clockevent.min_delta_ns = - clockevent_delta2ns(0xf, &timer0_clockevent); - - clockevents_register_device(&timer0_clockevent); -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t realview_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &timer0_clockevent; - - /* clear the interrupt */ - writel(1, timer0_va_base + TIMER_INTCLR); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction realview_timer_irq = { - .name = "RealView Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = realview_timer_interrupt, -}; - -static cycle_t realview_get_cycles(struct clocksource *cs) -{ - return ~readl(timer3_va_base + TIMER_VALUE); -} - -static struct clocksource clocksource_realview = { - .name = "timer3", - .rating = 200, - .read = realview_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .shift = 20, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static void __init realview_clocksource_init(void) -{ - /* setup timer 0 as free-running clocksource */ - writel(0, timer3_va_base + TIMER_CTRL); - writel(0xffffffff, timer3_va_base + TIMER_LOAD); - writel(0xffffffff, timer3_va_base + TIMER_VALUE); - writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - timer3_va_base + TIMER_CTRL); - - clocksource_realview.mult = - clocksource_khz2mult(1000, clocksource_realview.shift); - clocksource_register(&clocksource_realview); -} - -/* * Set up the clock source and clock events devices */ void __init realview_timer_init(unsigned int timer_irq) @@ -797,13 +662,8 @@ void __init realview_timer_init(unsigned int timer_irq) writel(0, timer2_va_base + TIMER_CTRL); writel(0, timer3_va_base + TIMER_CTRL); - /* - * Make irqs happen for the system timer - */ - setup_irq(timer_irq, &realview_timer_irq); - - realview_clocksource_init(); - realview_clockevents_init(timer_irq); + sp804_clocksource_init(timer3_va_base); + sp804_clockevents_init(timer0_va_base, timer_irq); } /* diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c index be048e3e879..f95521a5e5c 100644 --- a/arch/arm/mach-realview/hotplug.c +++ b/arch/arm/mach-realview/hotplug.c @@ -131,7 +131,7 @@ void platform_cpu_die(unsigned int cpu) cpu_leave_lowpower(); } -int mach_cpu_disable(unsigned int cpu) +int platform_cpu_disable(unsigned int cpu) { /* * we don't allow CPU 0 to be shutdown (it is still too special diff --git a/arch/arm/mach-realview/include/mach/clkdev.h b/arch/arm/mach-realview/include/mach/clkdev.h index 04b37a89801..e58d0771b64 100644 --- a/arch/arm/mach-realview/include/mach/clkdev.h +++ b/arch/arm/mach-realview/include/mach/clkdev.h @@ -1,6 +1,15 @@ #ifndef __ASM_MACH_CLKDEV_H #define __ASM_MACH_CLKDEV_H +#include <plat/clock.h> + +struct clk { + unsigned long rate; + const struct clk_ops *ops; + const struct icst_params *params; + void __iomem *vcoreg; +}; + #define __clk_get(clk) ({ 1; }) #define __clk_put(clk) do { } while (0) diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h index 2410d4f8ddd..830055bb862 100644 --- a/arch/arm/mach-realview/include/mach/irqs-pb1176.h +++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h @@ -31,6 +31,7 @@ #define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */ #define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */ #define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_DC1176_CORE_PMU (IRQ_DC1176_GIC_START + 7) /* Core PMU interrupt */ #define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */ #define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */ #define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */ diff --git a/arch/arm/mach-realview/include/mach/irqs-pba8.h b/arch/arm/mach-realview/include/mach/irqs-pba8.h index 86792a9f2ab..4a88a4edb65 100644 --- a/arch/arm/mach-realview/include/mach/irqs-pba8.h +++ b/arch/arm/mach-realview/include/mach/irqs-pba8.h @@ -23,12 +23,6 @@ #define IRQ_PBA8_GIC_START 32 -/* L220 -#define IRQ_PBA8_L220_EVENT (IRQ_PBA8_GIC_START + 29) -#define IRQ_PBA8_L220_SLAVE (IRQ_PBA8_GIC_START + 30) -#define IRQ_PBA8_L220_DECODE (IRQ_PBA8_GIC_START + 31) -*/ - /* * PB-A8 on-board gic irq sources */ @@ -65,6 +59,8 @@ #define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */ #define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */ +#define IRQ_PBA8_PMU (IRQ_PBA8_GIC_START + 47) /* Cortex-A8 PMU */ + /* ... */ #define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50) #define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51) diff --git a/arch/arm/mach-realview/include/mach/irqs-pbx.h b/arch/arm/mach-realview/include/mach/irqs-pbx.h index deaad4302b1..206a3001f46 100644 --- a/arch/arm/mach-realview/include/mach/irqs-pbx.h +++ b/arch/arm/mach-realview/include/mach/irqs-pbx.h @@ -22,12 +22,6 @@ #define IRQ_PBX_GIC_START 32 -/* L220 -#define IRQ_PBX_L220_EVENT (IRQ_PBX_GIC_START + 29) -#define IRQ_PBX_L220_SLAVE (IRQ_PBX_GIC_START + 30) -#define IRQ_PBX_L220_DECODE (IRQ_PBX_GIC_START + 31) -*/ - /* * PBX on-board gic irq sources */ @@ -77,10 +71,10 @@ #define IRQ_PBX_TIMER4_5 (IRQ_PBX_GIC_START + 41) /* Timer 0/1 (default timer) */ #define IRQ_PBX_TIMER6_7 (IRQ_PBX_GIC_START + 42) /* Timer 2/3 */ /* ... */ -#define IRQ_PBX_PMU_CPU3 (IRQ_PBX_GIC_START + 44) /* CPU PMU Interrupts */ -#define IRQ_PBX_PMU_CPU2 (IRQ_PBX_GIC_START + 45) -#define IRQ_PBX_PMU_CPU1 (IRQ_PBX_GIC_START + 46) -#define IRQ_PBX_PMU_CPU0 (IRQ_PBX_GIC_START + 47) +#define IRQ_PBX_PMU_CPU0 (IRQ_PBX_GIC_START + 44) /* CPU PMU Interrupts */ +#define IRQ_PBX_PMU_CPU1 (IRQ_PBX_GIC_START + 45) +#define IRQ_PBX_PMU_CPU2 (IRQ_PBX_GIC_START + 46) +#define IRQ_PBX_PMU_CPU3 (IRQ_PBX_GIC_START + 47) /* ... */ #define IRQ_PBX_PCI0 (IRQ_PBX_GIC_START + 50) diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h index 86c0c4435a4..1b77a27bada 100644 --- a/arch/arm/mach-realview/include/mach/platform.h +++ b/arch/arm/mach-realview/include/mach/platform.h @@ -231,12 +231,6 @@ #define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ #define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ -/* - * Clean base - dummy - * - */ -#define CLEAN_BASE REALVIEW_BOOT_ROM_HI - /* * System controller bit assignment */ @@ -249,20 +243,6 @@ #define REALVIEW_TIMER4_EnSel 21 -#define MAX_TIMER 2 -#define MAX_PERIOD 699050 -#define TICKS_PER_uSEC 1 - -/* - * These are useconds NOT ticks. - * - */ -#define mSEC_1 1000 -#define mSEC_5 (mSEC_1 * 5) -#define mSEC_10 (mSEC_1 * 10) -#define mSEC_25 (mSEC_1 * 25) -#define SEC_1 (mSEC_1 * 1000) - #define REALVIEW_CSR_BASE 0x10000000 #define REALVIEW_CSR_SIZE 0x10000000 diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 7d857d30055..422ccd70d5f 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -31,8 +31,8 @@ #include <asm/irq.h> #include <asm/leds.h> #include <asm/mach-types.h> +#include <asm/pmu.h> #include <asm/hardware/gic.h> -#include <asm/hardware/icst307.h> #include <asm/hardware/cache-l2x0.h> #include <asm/localtimer.h> @@ -44,7 +44,6 @@ #include <mach/irqs.h> #include "core.h" -#include "clock.h" static struct map_desc realview_eb_io_desc[] __initdata = { { @@ -294,6 +293,36 @@ static struct resource realview_eb_isp1761_resources[] = { }, }; +static struct resource pmu_resources[] = { + [0] = { + .start = IRQ_EB11MP_PMU_CPU0, + .end = IRQ_EB11MP_PMU_CPU0, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = IRQ_EB11MP_PMU_CPU1, + .end = IRQ_EB11MP_PMU_CPU1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_EB11MP_PMU_CPU2, + .end = IRQ_EB11MP_PMU_CPU2, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_EB11MP_PMU_CPU3, + .end = IRQ_EB11MP_PMU_CPU3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = ARRAY_SIZE(pmu_resources), + .resource = pmu_resources, +}; + static void __init gic_init_irq(void) { if (core_tile_eb11mp() || core_tile_a9mp()) { @@ -407,6 +436,7 @@ static void __init realview_eb_init(void) * Bits: .... ...0 0111 1001 0000 .... .... .... */ l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); #endif + platform_device_register(&pmu_device); } realview_flash_register(&realview_eb_flash_resource, 1); diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index 44392e51dd5..96568ebfa2b 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -31,8 +31,8 @@ #include <asm/irq.h> #include <asm/leds.h> #include <asm/mach-types.h> +#include <asm/pmu.h> #include <asm/hardware/gic.h> -#include <asm/hardware/icst307.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> @@ -44,7 +44,6 @@ #include <mach/irqs.h> #include "core.h" -#include "clock.h" static struct map_desc realview_pb1176_io_desc[] __initdata = { { @@ -263,6 +262,19 @@ static struct resource realview_pb1176_isp1761_resources[] = { }, }; +static struct resource pmu_resource = { + .start = IRQ_DC1176_CORE_PMU, + .end = IRQ_DC1176_CORE_PMU, + .flags = IORESOURCE_IRQ, +}; + +static struct platform_device pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = 1, + .resource = &pmu_resource, +}; + static void __init gic_init_irq(void) { /* ARM1176 DevChip GIC, primary */ @@ -324,6 +336,7 @@ static void __init realview_pb1176_init(void) realview_eth_register(NULL, realview_pb1176_smsc911x_resources); platform_device_register(&realview_i2c_device); realview_usb_register(realview_pb1176_isp1761_resources); + platform_device_register(&pmu_device); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 3e02731af95..7fbefbbebaf 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -31,8 +31,8 @@ #include <asm/irq.h> #include <asm/leds.h> #include <asm/mach-types.h> +#include <asm/pmu.h> #include <asm/hardware/gic.h> -#include <asm/hardware/icst307.h> #include <asm/hardware/cache-l2x0.h> #include <asm/localtimer.h> @@ -45,7 +45,6 @@ #include <mach/irqs.h> #include "core.h" -#include "clock.h" static struct map_desc realview_pb11mp_io_desc[] __initdata = { { @@ -260,6 +259,36 @@ static struct resource realview_pb11mp_isp1761_resources[] = { }, }; +static struct resource pmu_resources[] = { + [0] = { + .start = IRQ_TC11MP_PMU_CPU0, + .end = IRQ_TC11MP_PMU_CPU0, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = IRQ_TC11MP_PMU_CPU1, + .end = IRQ_TC11MP_PMU_CPU1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_TC11MP_PMU_CPU2, + .end = IRQ_TC11MP_PMU_CPU2, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_TC11MP_PMU_CPU3, + .end = IRQ_TC11MP_PMU_CPU3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = ARRAY_SIZE(pmu_resources), + .resource = pmu_resources, +}; + static void __init gic_init_irq(void) { unsigned int pldctrl; @@ -329,6 +358,7 @@ static void __init realview_pb11mp_init(void) platform_device_register(&realview_i2c_device); platform_device_register(&realview_cf_device); realview_usb_register(realview_pb11mp_isp1761_resources); + platform_device_register(&pmu_device); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index fe4e25c4201..d3c113b3dfc 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@ -30,8 +30,8 @@ #include <asm/irq.h> #include <asm/leds.h> #include <asm/mach-types.h> +#include <asm/pmu.h> #include <asm/hardware/gic.h> -#include <asm/hardware/icst307.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -42,7 +42,6 @@ #include <mach/irqs.h> #include "core.h" -#include "clock.h" static struct map_desc realview_pba8_io_desc[] __initdata = { { @@ -250,6 +249,19 @@ static struct resource realview_pba8_isp1761_resources[] = { }, }; +static struct resource pmu_resource = { + .start = IRQ_PBA8_PMU, + .end = IRQ_PBA8_PMU, + .flags = IORESOURCE_IRQ, +}; + +static struct platform_device pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = 1, + .resource = &pmu_resource, +}; + static void __init gic_init_irq(void) { /* ARM PB-A8 on-board GIC */ @@ -296,6 +308,7 @@ static void __init realview_pba8_init(void) platform_device_register(&realview_i2c_device); platform_device_register(&realview_cf_device); realview_usb_register(realview_pba8_isp1761_resources); + platform_device_register(&pmu_device); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index d94857eb069..a235ba30996 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -29,6 +29,7 @@ #include <asm/irq.h> #include <asm/leds.h> #include <asm/mach-types.h> +#include <asm/pmu.h> #include <asm/smp_twd.h> #include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> @@ -270,6 +271,36 @@ static struct resource realview_pbx_isp1761_resources[] = { }, }; +static struct resource pmu_resources[] = { + [0] = { + .start = IRQ_PBX_PMU_CPU0, + .end = IRQ_PBX_PMU_CPU0, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = IRQ_PBX_PMU_CPU1, + .end = IRQ_PBX_PMU_CPU1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_PBX_PMU_CPU2, + .end = IRQ_PBX_PMU_CPU2, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_PBX_PMU_CPU3, + .end = IRQ_PBX_PMU_CPU3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = ARRAY_SIZE(pmu_resources), + .resource = pmu_resources, +}; + static void __init gic_init_irq(void) { /* ARM PBX on-board GIC */ @@ -354,6 +385,7 @@ static void __init realview_pbx_init(void) /* 16KB way size, 8-way associativity, parity disabled * Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */ l2x0_init(l2x0_base, 0x02520000, 0xc0000fff); + platform_device_register(&pmu_device); } #endif diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 554731868b0..7245a55795d 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -6,6 +6,7 @@ config CPU_S3C2410 bool depends on ARCH_S3C2410 select CPU_ARM920T + select S3C_GPIO_PULL_UP select S3C2410_CLOCK select S3C2410_GPIO select CPU_LLSERIAL_S3C2410 @@ -76,6 +77,7 @@ config ARCH_H1940 select PM_H1940 if PM select S3C_DEV_USB_HOST select S3C_DEV_NAND + select S3C2410_SETUP_TS help Say Y here if you are using the HP IPAQ H1940 @@ -95,12 +97,19 @@ config PM_H1940 config MACH_N30 bool "Acer N30 family" select CPU_S3C2410 + select MACH_N35 select S3C_DEV_USB_HOST select S3C_DEV_NAND help Say Y here if you want suppt for the Acer N30, Acer N35, Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. +config MACH_N35 + bool + help + Internal node in order to enable support for Acer N35 if Acer N30 is + selected. + config ARCH_BAST bool "Simtec Electronics BAST (EB2410ITX)" select CPU_S3C2410 @@ -110,6 +119,7 @@ config ARCH_BAST select MACH_BAST_IDE select S3C24XX_DCLK select ISA + select S3C_DEV_HWMON select S3C_DEV_USB_HOST select S3C_DEV_NAND help diff --git a/arch/arm/mach-s3c2410/Makefile.boot b/arch/arm/mach-s3c2410/Makefile.boot index 7dab2a0325b..58c1dd7f8e1 100644 --- a/arch/arm/mach-s3c2410/Makefile.boot +++ b/arch/arm/mach-s3c2410/Makefile.boot @@ -1,3 +1,7 @@ - zreladdr-y := 0x30008000 -params_phys-y := 0x30000100 - +ifeq ($(CONFIG_PM_H1940),y) + zreladdr-y := 0x30108000 + params_phys-y := 0x30100100 +else + zreladdr-y := 0x30008000 + params_phys-y := 0x30000100 +endif diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c index a3f3c7b1ca3..8cdeb14af59 100644 --- a/arch/arm/mach-s3c2410/h1940-bluetooth.c +++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c @@ -33,14 +33,15 @@ static void h1940bt_enable(int on) h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); /* Reset the chip */ mdelay(10); - s3c2410_gpio_setpin(S3C2410_GPH(1), 1); + + gpio_set_value(S3C2410_GPH(1), 1); mdelay(10); - s3c2410_gpio_setpin(S3C2410_GPH(1), 0); + gpio_set_value(S3C2410_GPH(1), 0); } else { - s3c2410_gpio_setpin(S3C2410_GPH(1), 1); + gpio_set_value(S3C2410_GPH(1), 1); mdelay(10); - s3c2410_gpio_setpin(S3C2410_GPH(1), 0); + gpio_set_value(S3C2410_GPH(1), 0); mdelay(10); h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); } @@ -61,15 +62,21 @@ static int __devinit h1940bt_probe(struct platform_device *pdev) struct rfkill *rfk; int ret = 0; + ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev)); + if (ret) { + dev_err(&pdev->dev, "could not get GPH1\n");\ + return ret; + } + /* Configures BT serial port GPIOs */ - s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0); - s3c2410_gpio_pullup(S3C2410_GPH(0), 1); - s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_pullup(S3C2410_GPH(1), 1); - s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0); - s3c2410_gpio_pullup(S3C2410_GPH(2), 1); - s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0); - s3c2410_gpio_pullup(S3C2410_GPH(3), 1); + s3c_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0); + s3c_gpio_cfgpull(S3C2410_GPH(0), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpull(S3C2410_GPH(1), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0); + s3c_gpio_cfgpull(S3C2410_GPH(2), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0); + s3c_gpio_cfgpull(S3C2410_GPH(3), S3C_GPIO_PULL_NONE); rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH, @@ -100,6 +107,7 @@ static int h1940bt_remove(struct platform_device *pdev) struct rfkill *rfk = platform_get_drvdata(pdev); platform_set_drvdata(pdev, NULL); + gpio_free(S3C2410_GPH(1)); if (rfk) { rfkill_unregister(rfk); diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index 08ac5f96c01..cf68136cc66 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h @@ -54,7 +54,7 @@ enum dma_ch { #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ /* we have 4 dma channels */ -#ifndef CONFIG_CPU_S3C2443 +#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416) #define S3C_DMA_CHANNELS (4) #else #define S3C_DMA_CHANNELS (6) diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h index 035a493952d..f453c4f2cb8 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h @@ -10,14 +10,28 @@ * published by the Free Software Foundation. */ +#ifndef __MACH_GPIO_FNS_H +#define __MACH_GPIO_FNS_H __FILE__ + /* These functions are in the to-be-removed category and it is strongly * encouraged not to use these in new code. They will be marked deprecated * very soon. * * Most of the functionality can be either replaced by the gpiocfg calls * for the s3c platform or by the generic GPIOlib API. + * + * As of 2.6.35-rc, these will be removed, with the few drivers using them + * either replaced or given a wrapper until the calls can be removed. */ +#include <plat/gpio-cfg.h> + +static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg) +{ + /* 1:1 mapping between cfgpin and setcfg calls at the moment */ + s3c_gpio_cfgpin(pin, cfg); +} + /* external functions for GPIO support * * These allow various different clients to access the same GPIO @@ -25,17 +39,6 @@ * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. */ -/* s3c2410_gpio_cfgpin - * - * set the configuration of the given pin to the value passed. - * - * eg: - * s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0); - * s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1); -*/ - -extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); - extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); /* s3c2410_gpio_getirq @@ -73,6 +76,14 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, /* s3c2410_gpio_pullup * + * This call should be replaced with s3c_gpio_setpull(). + * + * As a note, there is currently no distinction between pull-up and pull-down + * in the s3c24xx series devices with only an on/off configuration. + */ + +/* s3c2410_gpio_pullup + * * configure the pull-up control on the given pin * * to = 1 => disable the pull-up @@ -86,18 +97,8 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); -/* s3c2410_gpio_getpull - * - * Read the state of the pull-up on a given pin - * - * return: - * < 0 => error code - * 0 => enabled - * 1 => disabled -*/ - -extern int s3c2410_gpio_getpull(unsigned int pin); - extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); extern unsigned int s3c2410_gpio_getpin(unsigned int pin); + +#endif /* __MACH_GPIO_FNS_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h index 2edbb9c88ab..4f7bf3272e8 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h @@ -16,15 +16,28 @@ #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) -#define S3C2410_GPIO_BANKA (32*0) -#define S3C2410_GPIO_BANKB (32*1) -#define S3C2410_GPIO_BANKC (32*2) -#define S3C2410_GPIO_BANKD (32*3) -#define S3C2410_GPIO_BANKE (32*4) -#define S3C2410_GPIO_BANKF (32*5) #define S3C2410_GPIO_BANKG (32*6) #define S3C2410_GPIO_BANKH (32*7) +/* GPIO sizes for various SoCs: + * + * 2442 + * 2410 2412 2440 2443 2416 + * ---- ---- ---- ---- ---- + * A 23 22 25 16 25 + * B 11 11 11 11 9 + * C 16 15 16 16 16 + * D 16 16 16 16 16 + * E 16 16 16 16 16 + * F 8 8 8 8 8 + * G 16 16 16 16 8 + * H 11 11 9 15 15 + * J -- -- 13 16 -- + * K -- -- -- -- 16 + * L -- -- -- 15 7 + * M -- -- -- 2 2 + */ + /* GPIO bank sizes */ #define S3C2410_GPIO_A_NR (32) #define S3C2410_GPIO_B_NR (32) @@ -34,6 +47,10 @@ #define S3C2410_GPIO_F_NR (32) #define S3C2410_GPIO_G_NR (32) #define S3C2410_GPIO_H_NR (32) +#define S3C2410_GPIO_J_NR (32) /* technically 16. */ +#define S3C2410_GPIO_K_NR (32) /* technically 16. */ +#define S3C2410_GPIO_L_NR (32) /* technically 15. */ +#define S3C2410_GPIO_M_NR (32) /* technically 2. */ #if CONFIG_S3C_GPIO_SPACE != 0 #error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment @@ -53,6 +70,10 @@ enum s3c_gpio_number { S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), + S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H), + S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J), + S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K), + S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L), }; #endif /* __ASSEMBLY__ */ @@ -67,6 +88,10 @@ enum s3c_gpio_number { #define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) #define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) #define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) +#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr)) +#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr)) +#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) +#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) /* compatibility until drivers can be modified */ diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h index acb25910380..d67819dde42 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-track.h @@ -23,11 +23,11 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) { struct s3c_gpio_chip *chip; - if (pin > S3C2410_GPG(10)) + if (pin > S3C_GPIO_END) return NULL; chip = &s3c24xx_gpios[pin/32]; - return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL; + return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL; } #endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h index 15f0b3e7ce6..b649bf2ccd5 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h @@ -20,10 +20,18 @@ * devices that need GPIO. */ +#ifdef CONFIG_CPU_S3C244X +#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA) +#else #define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) +#endif #include <asm-generic/gpio.h> #include <mach/gpio-nrs.h> #include <mach/gpio-fns.h> +#ifdef CONFIG_CPU_S3C24XX +#define S3C_GPIO_END (S3C2410_GPIO_BANKJ + 32) +#else #define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) +#endif diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index 6c12c6312ad..11bb0f08fe6 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h @@ -115,6 +115,26 @@ #define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) #define IRQ_S3C2412_CF S3C2410_IRQSUB(14) + +#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5) +#define IRQ_S3C2416_DMA S3C2410_IRQ(17) +#define IRQ_S3C2416_UART3 S3C2410_IRQ(18) +#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20) +#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21) + +#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15) +#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16) +#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17) +#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18) +#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19) +#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20) +#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21) +#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22) +#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23) +#define IRQ_S32416_WDT S3C2410_IRQSUB(27) +#define IRQ_S32416_AC97 S3C2410_IRQSUB(28) + + /* extra irqs for s3c2440 */ #define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ @@ -130,7 +150,10 @@ #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ +#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */ + #define IRQ_HSMMC0 IRQ_S3C2443_HSMMC +#define IRQ_HSMMC1 IRQ_S3C2416_HSMMC0 #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) #define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) @@ -152,7 +175,7 @@ #define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) #define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) -#ifdef CONFIG_CPU_S3C2443 +#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) #define NR_IRQS (IRQ_S3C2443_AC97+1) #else #define NR_IRQS (IRQ_S3C2440_AC97+1) @@ -164,6 +187,9 @@ #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 +#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 +#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 + #ifdef CONFIG_CPU_S3C2440 #define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97 #else diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index b049e61460b..091c98a639d 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -63,9 +63,11 @@ #define S3C2440_PA_AC97 (0x5B000000) #define S3C2440_SZ_AC97 SZ_1M -/* S3C2443 High-speed SD/MMC */ +/* S3C2443/S3C2416 High-speed SD/MMC */ #define S3C2443_PA_HSMMC (0x4A800000) -#define S3C2443_SZ_HSMMC (256) +#define S3C2416_PA_HSMMC0 (0x4AC00000) + +#define S3C2443_PA_FB (0x4C800000) /* S3C2412 memory and IO controls */ #define S3C2412_PA_SSMC (0x4F000000) @@ -106,10 +108,12 @@ #define S3C24XX_PA_SDI S3C2410_PA_SDI #define S3C24XX_PA_NAND S3C2410_PA_NAND +#define S3C_PA_FB S3C2443_PA_FB #define S3C_PA_IIC S3C2410_PA_IIC #define S3C_PA_UART S3C24XX_PA_UART #define S3C_PA_USBHOST S3C2410_PA_USBHOST #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC +#define S3C_PA_HSMMC1 S3C2416_PA_HSMMC0 #define S3C_PA_NAND S3C24XX_PA_NAND #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h index 9a0d169be13..3415b60082d 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h @@ -161,4 +161,6 @@ #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ +#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28) + #endif /* __ASM_ARM_REGS_CLOCK */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h index 3c3853cd3cf..98fd4a05587 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h @@ -19,6 +19,42 @@ #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) #endif +#if defined(CONFIG_CPU_S3C2416) +#define S3C2416_DSC0 S3C2410_GPIOREG(0xc0) +#define S3C2416_DSC1 S3C2410_GPIOREG(0xc4) +#define S3C2416_DSC2 S3C2410_GPIOREG(0xc8) +#define S3C2416_DSC3 S3C2410_GPIOREG(0x110) + +#define S3C2416_SELECT_DSC0 (0 << 30) +#define S3C2416_SELECT_DSC1 (1 << 30) +#define S3C2416_SELECT_DSC2 (2 << 30) +#define S3C2416_SELECT_DSC3 (3 << 30) + +#define S3C2416_DSC_GETSHIFT(x) (x & 30) + +#define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28) +#define S3C2416_DSC0_CF_5mA (0 << 28) +#define S3C2416_DSC0_CF_10mA (1 << 28) +#define S3C2416_DSC0_CF_15mA (2 << 28) +#define S3C2416_DSC0_CF_21mA (3 << 28) +#define S3C2416_DSC0_CF_MASK (3 << 28) + +#define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26) +#define S3C2416_DSC0_nRBE_5mA (0 << 26) +#define S3C2416_DSC0_nRBE_10mA (1 << 26) +#define S3C2416_DSC0_nRBE_15mA (2 << 26) +#define S3C2416_DSC0_nRBE_21mA (3 << 26) +#define S3C2416_DSC0_nRBE_MASK (3 << 26) + +#define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24) +#define S3C2416_DSC0_nROE_5mA (0 << 24) +#define S3C2416_DSC0_nROE_10mA (1 << 24) +#define S3C2416_DSC0_nROE_15mA (2 << 24) +#define S3C2416_DSC0_nROE_21mA (3 << 24) +#define S3C2416_DSC0_nROE_MASK (3 << 24) + +#endif + #if defined(CONFIG_CPU_S3C244X) #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index fd672f330bf..a0a89d42929 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h @@ -17,29 +17,11 @@ #include <mach/gpio-nrs.h> #ifdef CONFIG_CPU_S3C2400 -#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) -#define S3C24XX_MISCCR S3C2400_MISCCR +#define S3C24XX_MISCCR S3C2400_MISCCR #else -#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) -#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) +#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) #endif /* CONFIG_CPU_S3C2400 */ - -/* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */ - -#define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32) -#define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2)) -#define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \ - (2 * (S3C2400_BANKNUM(pin)-2))) - -#define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \ - S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \ - S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO) - - -#define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO) -#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31) - /* general configuration options */ #define S3C2410_GPIO_LEAVE (0xFFFFFFFF) @@ -610,35 +592,73 @@ #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) #define S3C2410_GPH0_nCTS0 (0x02 << 0) +#define S3C2416_GPH0_TXD0 (0x02 << 0) #define S3C2410_GPH1_nRTS0 (0x02 << 2) +#define S3C2416_GPH1_RXD0 (0x02 << 2) #define S3C2410_GPH2_TXD0 (0x02 << 4) +#define S3C2416_GPH2_TXD1 (0x02 << 4) #define S3C2410_GPH3_RXD0 (0x02 << 6) +#define S3C2416_GPH3_RXD1 (0x02 << 6) #define S3C2410_GPH4_TXD1 (0x02 << 8) +#define S3C2416_GPH4_TXD2 (0x02 << 8) #define S3C2410_GPH5_RXD1 (0x02 << 10) +#define S3C2416_GPH5_RXD2 (0x02 << 10) #define S3C2410_GPH6_TXD2 (0x02 << 12) +#define S3C2416_GPH6_TXD3 (0x02 << 12) #define S3C2410_GPH6_nRTS1 (0x03 << 12) +#define S3C2416_GPH6_nRTS2 (0x03 << 12) #define S3C2410_GPH7_RXD2 (0x02 << 14) +#define S3C2416_GPH7_RXD3 (0x02 << 14) #define S3C2410_GPH7_nCTS1 (0x03 << 14) +#define S3C2416_GPH7_nCTS2 (0x03 << 14) #define S3C2410_GPH8_UCLK (0x02 << 16) +#define S3C2416_GPH8_nCTS0 (0x02 << 16) #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) #define S3C2442_GPH9_nSPICS0 (0x03 << 18) +#define S3C2416_GPH9_nRTS0 (0x02 << 18) #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) +#define S3C2416_GPH10_nCTS1 (0x02 << 20) + +#define S3C2416_GPH11_nRTS1 (0x02 << 22) + +#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24) + +#define S3C2416_GPH13_CLKOUT0 (0x02 << 26) + +#define S3C2416_GPH14_CLKOUT1 (0x02 << 28) /* The S3C2412 and S3C2413 move the GPJ register set to after * GPH, which means all registers after 0x80 are now offset by 0x10 * for the 2412/2413 from the 2410/2440/2442 */ +/* S3C2443 and above */ +#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) +#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) +#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8) + +#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0) +#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4) +#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8) + +#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0) +#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4) +#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8) + +#define S3C2443_GPMCON S3C2410_GPIOREG(0x100) +#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104) +#define S3C2443_GPMUP S3C2410_GPIOREG(0x108) + /* miscellaneous control */ #define S3C2400_MISCCR S3C2410_GPIOREG(0x54) #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) @@ -686,6 +706,7 @@ #define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) #define S3C2410_MISCCR_USBSUSPND0 (1<<12) +#define S3C2416_MISCCR_SEL_SUSPND (1<<12) #define S3C2410_MISCCR_USBSUSPND1 (1<<13) #define S3C2410_MISCCR_nRSTCON (1<<16) @@ -695,6 +716,9 @@ #define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ #define S3C2410_MISCCR_SDSLEEP (7<<17) +#define S3C2416_MISCCR_FLT_I2C (1<<24) +#define S3C2416_MISCCR_HSSPI_EN2 (1<<31) + /* external interrupt control... */ /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 @@ -762,8 +786,11 @@ #define S3C2410_GSTATUS1_IDMASK (0xffff0000) #define S3C2410_GSTATUS1_2410 (0x32410000) #define S3C2410_GSTATUS1_2412 (0x32412001) +#define S3C2410_GSTATUS1_2416 (0x32416003) #define S3C2410_GSTATUS1_2440 (0x32440000) #define S3C2410_GSTATUS1_2442 (0x32440aaa) +/* some 2416 CPUs report this value also */ +#define S3C2410_GSTATUS1_2450 (0x32450003) #define S3C2410_GSTATUS2_WTRESET (1<<2) #define S3C2410_GSTATUS2_OFFRESET (1<<1) diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h index 1202ca5e99f..19575e06111 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h @@ -22,85 +22,49 @@ * pull up works like all other ports. */ -#define S3C2440_GPIO_BANKJ (416) - -#define S3C2440_GPJCON S3C2410_GPIOREG(0xd0) -#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4) -#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8) - #define S3C2413_GPJCON S3C2410_GPIOREG(0x80) #define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) #define S3C2413_GPJUP S3C2410_GPIOREG(0x88) #define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) -#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0) -#define S3C2440_GPJ0_INP (0x00 << 0) #define S3C2440_GPJ0_OUTP (0x01 << 0) #define S3C2440_GPJ0_CAMDATA0 (0x02 << 0) -#define S3C2440_GPJ1 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 1) -#define S3C2440_GPJ1_INP (0x00 << 2) #define S3C2440_GPJ1_OUTP (0x01 << 2) #define S3C2440_GPJ1_CAMDATA1 (0x02 << 2) -#define S3C2440_GPJ2 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 2) -#define S3C2440_GPJ2_INP (0x00 << 4) #define S3C2440_GPJ2_OUTP (0x01 << 4) #define S3C2440_GPJ2_CAMDATA2 (0x02 << 4) -#define S3C2440_GPJ3 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 3) -#define S3C2440_GPJ3_INP (0x00 << 6) #define S3C2440_GPJ3_OUTP (0x01 << 6) #define S3C2440_GPJ3_CAMDATA3 (0x02 << 6) -#define S3C2440_GPJ4 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 4) -#define S3C2440_GPJ4_INP (0x00 << 8) #define S3C2440_GPJ4_OUTP (0x01 << 8) #define S3C2440_GPJ4_CAMDATA4 (0x02 << 8) -#define S3C2440_GPJ5 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 5) -#define S3C2440_GPJ5_INP (0x00 << 10) #define S3C2440_GPJ5_OUTP (0x01 << 10) #define S3C2440_GPJ5_CAMDATA5 (0x02 << 10) -#define S3C2440_GPJ6 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 6) -#define S3C2440_GPJ6_INP (0x00 << 12) #define S3C2440_GPJ6_OUTP (0x01 << 12) #define S3C2440_GPJ6_CAMDATA6 (0x02 << 12) -#define S3C2440_GPJ7 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 7) -#define S3C2440_GPJ7_INP (0x00 << 14) #define S3C2440_GPJ7_OUTP (0x01 << 14) #define S3C2440_GPJ7_CAMDATA7 (0x02 << 14) -#define S3C2440_GPJ8 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 8) -#define S3C2440_GPJ8_INP (0x00 << 16) #define S3C2440_GPJ8_OUTP (0x01 << 16) #define S3C2440_GPJ8_CAMPCLK (0x02 << 16) -#define S3C2440_GPJ9 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 9) -#define S3C2440_GPJ9_INP (0x00 << 18) #define S3C2440_GPJ9_OUTP (0x01 << 18) #define S3C2440_GPJ9_CAMVSYNC (0x02 << 18) -#define S3C2440_GPJ10 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 10) -#define S3C2440_GPJ10_INP (0x00 << 20) #define S3C2440_GPJ10_OUTP (0x01 << 20) #define S3C2440_GPJ10_CAMHREF (0x02 << 20) -#define S3C2440_GPJ11 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 11) -#define S3C2440_GPJ11_INP (0x00 << 22) #define S3C2440_GPJ11_OUTP (0x01 << 22) #define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22) -#define S3C2440_GPJ12 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 12) -#define S3C2440_GPJ12_INP (0x00 << 24) #define S3C2440_GPJ12_OUTP (0x01 << 24) #define S3C2440_GPJ12_CAMRESET (0x02 << 24) -#define S3C2443_GPJ13 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13) -#define S3C2443_GPJ14 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14) -#define S3C2443_GPJ15 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15) - #endif /* __ASM_ARCH_REGS_GPIOJ_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c2410/include/mach/regs-irq.h index de86ee8812b..0f07ba30b1f 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-irq.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-irq.h @@ -27,6 +27,16 @@ #define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018) #define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C) +#define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030) +#define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034) +#define S3C2416_SRCPND2 S3C2410_IRQREG(0x040) +#define S3C2416_INTMOD2 S3C2410_IRQREG(0x044) +#define S3C2416_INTMSK2 S3C2410_IRQREG(0x048) +#define S3C2416_INTPND2 S3C2410_IRQREG(0x050) +#define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054) +#define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070) +#define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074) + /* mask: 0=enable, 1=disable * 1 bit EINT, 4=EINT4, 23=EINT23 * EINT0,1,2,3 are not handled here. diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h new file mode 100644 index 00000000000..2f31b74974a --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h @@ -0,0 +1,30 @@ +/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h + * + * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, + * as part of OpenInkpot project + * Copyright (c) 2009 Promwad Innovation Company + * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2416 memory register definitions +*/ + +#ifndef __ASM_ARM_REGS_S3C2416_MEM +#define __ASM_ARM_REGS_S3C2416_MEM + +#ifndef S3C2416_MEMREG +#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) +#endif + +#define S3C2416_BANKCFG S3C2416_MEMREG(0x00) +#define S3C2416_BANKCON1 S3C2416_MEMREG(0x04) +#define S3C2416_BANKCON2 S3C2416_MEMREG(0x08) +#define S3C2416_BANKCON3 S3C2416_MEMREG(0x0C) + +#define S3C2416_REFRESH S3C2416_MEMREG(0x10) +#define S3C2416_TIMEOUT S3C2416_MEMREG(0x14) + +#endif /* __ASM_ARM_REGS_S3C2416_MEM */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h new file mode 100644 index 00000000000..e443167efb8 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h @@ -0,0 +1,24 @@ +/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h + * + * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, + * as part of OpenInkpot project + * Copyright (c) 2009 Promwad Innovation Company + * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2416 specific register definitions +*/ + +#ifndef __ASM_ARCH_REGS_S3C2416_H +#define __ASM_ARCH_REGS_S3C2416_H "s3c2416" + +#define S3C2416_SWRST (S3C24XX_VA_CLKPWR + 0x44) +#define S3C2416_SWRST_RESET (0x533C2416) + +/* see regs-power.h for the other registers in the power block. */ + +#endif /* __ASM_ARCH_REGS_S3C2416_H */ + diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h index d87ebe0cb62..08ab9dfb6ae 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h @@ -83,8 +83,7 @@ #define S3C2443_HCLKCON_DMA4 (1<<4) #define S3C2443_HCLKCON_DMA5 (1<<5) #define S3C2443_HCLKCON_CAMIF (1<<8) -#define S3C2443_HCLKCON_DISP (1<<9) -#define S3C2443_HCLKCON_LCDC (1<<10) +#define S3C2443_HCLKCON_LCDC (1<<9) #define S3C2443_HCLKCON_USBH (1<<11) #define S3C2443_HCLKCON_USBD (1<<12) #define S3C2443_HCLKCON_HSMMC (1<<16) diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h index 72f756c5e50..8b283f847da 100644 --- a/arch/arm/mach-s3c2410/include/mach/uncompress.h +++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h @@ -40,7 +40,9 @@ static void arch_detect_cpu(void) cpuid &= S3C2410_GSTATUS1_IDMASK; if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 || - cpuid == S3C2410_GSTATUS1_2442) { + cpuid == S3C2410_GSTATUS1_2442 || + cpuid == S3C2410_GSTATUS1_2416 || + cpuid == S3C2410_GSTATUS1_2450) { fifo_mask = S3C2440_UFSTAT_TXMASK; fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; } else { diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c index 7047317ed7f..34fc05a4244 100644 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c @@ -56,6 +56,7 @@ #include <plat/iic.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/gpio-cfg.h> #ifdef CONFIG_MTD_PARTITIONS @@ -225,8 +226,8 @@ static void amlm5900_init_pm(void) } else { enable_irq_wake(IRQ_EINT9); /* configure the suspend/resume status pin */ - s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_pullup(S3C2410_GPF(2), 0); + s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); + s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_UP); } } static void __init amlm5900_init(void) diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 02b1b6220cb..c1f90f6fab4 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -61,6 +61,7 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/cpu-freq.h> +#include <plat/gpio-cfg.h> #include <plat/audio-simtec.h> #include "usb-simtec.h" @@ -216,15 +217,13 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { static int bast_pm_suspend(struct sys_device *sd, pm_message_t state) { /* ensure that an nRESET is not generated on resume. */ - s3c2410_gpio_setpin(S3C2410_GPA(21), 1); - s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT); - + gpio_direction_output(S3C2410_GPA(21), 1); return 0; } static int bast_pm_resume(struct sys_device *sd) { - s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); + s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); return 0; } @@ -634,7 +633,7 @@ static void __init bast_map_io(void) s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); - s3c_device_hwmon.dev.platform_data = &bast_hwmon_info; + s3c_hwmon_set_platdata(&bast_hwmon_info); s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); s3c24xx_init_clocks(0); @@ -658,6 +657,8 @@ static void __init bast_init(void) nor_simtec_init(); simtec_audio_add(NULL, true, &bast_audio); + WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset")); + s3c_cpufreq_setboard(&bast_cpufreq); } diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index fbedd076094..779b45b3f80 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -46,16 +46,17 @@ #include <mach/h1940.h> #include <mach/h1940-latch.h> #include <mach/fb.h> -#include <mach/ts.h> #include <plat/udc.h> #include <plat/iic.h> +#include <plat/gpio-cfg.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> #include <plat/pll.h> #include <plat/pm.h> #include <plat/mci.h> +#include <plat/ts.h> static struct map_desc h1940_iodesc[] __initdata = { [0] = { @@ -145,6 +146,7 @@ static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = { .delay = 10000, .presc = 49, .oversampling_shift = 2, + .cfg_gpio = s3c24xx_ts_cfg_gpio, }; /** @@ -162,8 +164,8 @@ static struct s3c2410fb_display h1940_lcd __initdata = { .xres = 240, .yres = 320, .bpp = 16, - .left_margin = 20, - .right_margin = 8, + .left_margin = 8, + .right_margin = 20, .hsync_len = 4, .upper_margin = 8, .lower_margin = 7, @@ -207,16 +209,16 @@ static int h1940_backlight_init(struct device *dev) { gpio_request(S3C2410_GPB(0), "Backlight"); - s3c2410_gpio_setpin(S3C2410_GPB(0), 0); - s3c2410_gpio_pullup(S3C2410_GPB(0), 0); - s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0); + gpio_direction_output(S3C2410_GPB(0), 0); + s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0); return 0; } static void h1940_backlight_exit(struct device *dev) { - s3c2410_gpio_cfgpin(S3C2410_GPB(0), 1/*S3C2410_GPB0_OUTP*/); + gpio_direction_output(S3C2410_GPB(0), 1); } static struct platform_pwm_backlight_data backlight_data = { @@ -245,18 +247,18 @@ static void h1940_lcd_power_set(struct plat_lcd_data *pd, if (!power) { /* set to 3ec */ - s3c2410_gpio_setpin(S3C2410_GPC(0), 0); + gpio_direction_output(S3C2410_GPC(0), 0); /* wait for 3ac */ do { - value = s3c2410_gpio_getpin(S3C2410_GPC(6)); + value = gpio_get_value(S3C2410_GPC(6)); } while (value); /* set to 38c */ - s3c2410_gpio_setpin(S3C2410_GPC(5), 0); + gpio_direction_output(S3C2410_GPC(5), 0); } else { /* Set to 3ac */ - s3c2410_gpio_setpin(S3C2410_GPC(5), 1); + gpio_direction_output(S3C2410_GPC(5), 1); /* Set to 3ad */ - s3c2410_gpio_setpin(S3C2410_GPC(0), 1); + gpio_direction_output(S3C2410_GPC(0), 1); } } @@ -271,7 +273,6 @@ static struct platform_device h1940_lcd_powerdev = { }; static struct platform_device *h1940_devices[] __initdata = { - &s3c_device_ts, &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, @@ -285,6 +286,8 @@ static struct platform_device *h1940_devices[] __initdata = { &s3c_device_timer[0], &h1940_backlight, &h1940_lcd_powerdev, + &s3c_device_adc, + &s3c_device_ts, }; static void __init h1940_map_io(void) @@ -332,12 +335,13 @@ static void __init h1940_init(void) gpio_request(S3C2410_GPC(5), "LCD power"); gpio_request(S3C2410_GPC(6), "LCD power"); + gpio_direction_input(S3C2410_GPC(6)); platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); } MACHINE_START(H1940, "IPAQ-H1940") - /* Maintainer: Ben Dooks <ben@fluff.org> */ + /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ .phys_io = S3C2410_PA_UART, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 684710f8814..41f299d983e 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -26,6 +26,7 @@ #include <linux/serial_core.h> #include <linux/timer.h> #include <linux/io.h> +#include <linux/mmc/host.h> #include <mach/hardware.h> #include <asm/irq.h> @@ -46,6 +47,7 @@ #include <plat/clock.h> #include <plat/cpu.h> #include <plat/devs.h> +#include <plat/mci.h> #include <plat/s3c2410.h> #include <plat/udc.h> @@ -86,10 +88,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd) { switch (cmd) { case S3C2410_UDC_P_ENABLE : - s3c2410_gpio_setpin(S3C2410_GPB(3), 1); + gpio_set_value(S3C2410_GPB(3), 1); break; case S3C2410_UDC_P_DISABLE : - s3c2410_gpio_setpin(S3C2410_GPB(3), 0); + gpio_set_value(S3C2410_GPB(3), 0); break; case S3C2410_UDC_P_RESET : break; @@ -172,8 +174,10 @@ static struct gpio_keys_button n35_buttons[] = { { .gpio = S3C2410_GPF(0), .code = KEY_POWER, + .type = EV_PWR, .desc = "Power", .active_low = 0, + .wakeup = 1, }, { .gpio = S3C2410_GPG(9), @@ -264,6 +268,14 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = { .def_trigger = "", }; +/* This is the blue LED on the device. Originaly used to indicate GPS activity + * by flashing. */ +static struct s3c24xx_led_platdata n35_blue_led_pdata = { + .name = "blue_led", + .gpio = S3C2410_GPD(8), + .def_trigger = "", +}; + /* This LED is driven by the battery microcontroller, and is blinking * red, blinking green or solid green when the battery is low, * charging or full respectively. By driving GPD9 low, it's possible @@ -275,6 +287,13 @@ static struct s3c24xx_led_platdata n30_warning_led_pdata = { .def_trigger = "", }; +static struct s3c24xx_led_platdata n35_warning_led_pdata = { + .name = "warning_led", + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .gpio = S3C2410_GPD(9), + .def_trigger = "", +}; + static struct platform_device n30_blue_led = { .name = "s3c24xx_led", .id = 1, @@ -283,6 +302,14 @@ static struct platform_device n30_blue_led = { }, }; +static struct platform_device n35_blue_led = { + .name = "s3c24xx_led", + .id = 1, + .dev = { + .platform_data = &n35_blue_led_pdata, + }, +}; + static struct platform_device n30_warning_led = { .name = "s3c24xx_led", .id = 2, @@ -291,6 +318,14 @@ static struct platform_device n30_warning_led = { }, }; +static struct platform_device n35_warning_led = { + .name = "s3c24xx_led", + .id = 2, + .dev = { + .platform_data = &n35_warning_led_pdata, + }, +}; + static struct s3c2410fb_display n30_display __initdata = { .type = S3C2410_LCDCON1_TFT, .width = 240, @@ -317,13 +352,36 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = { .lpcsel = 0x06, }; +static void n30_sdi_set_power(unsigned char power_mode, unsigned short vdd) +{ + switch (power_mode) { + case MMC_POWER_ON: + case MMC_POWER_UP: + gpio_set_value(S3C2410_GPG(4), 1); + break; + case MMC_POWER_OFF: + default: + gpio_set_value(S3C2410_GPG(4), 0); + break; + } +} + +static struct s3c24xx_mci_pdata n30_mci_cfg __initdata = { + .gpio_detect = S3C2410_GPF(1), + .gpio_wprotect = S3C2410_GPG(10), + .ocr_avail = MMC_VDD_32_33, + .set_power = n30_sdi_set_power, +}; + static struct platform_device *n30_devices[] __initdata = { &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, &s3c_device_iis, &s3c_device_ohci, + &s3c_device_rtc, &s3c_device_usbgadget, + &s3c_device_sdi, &n30_button_device, &n30_blue_led, &n30_warning_led, @@ -334,8 +392,12 @@ static struct platform_device *n35_devices[] __initdata = { &s3c_device_wdt, &s3c_device_i2c0, &s3c_device_iis, + &s3c_device_rtc, &s3c_device_usbgadget, + &s3c_device_sdi, &n35_button_device, + &n35_blue_led, + &n35_warning_led, }; static struct s3c2410_platform_i2c __initdata n30_i2ccfg = { @@ -490,17 +552,15 @@ static void __init n30_map_io(void) s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); } -static void __init n30_init_irq(void) -{ - s3c24xx_init_irq(); -} - /* GPB3 is the line that controls the pull-up for the USB D+ line */ static void __init n30_init(void) { + WARN_ON(gpio_request(S3C2410_GPG(4), "mmc power")); + s3c24xx_fb_set_platdata(&n30_fb_info); s3c24xx_udc_set_platdata(&n30_udc_cfg); + s3c24xx_mci_set_platdata(&n30_mci_cfg); s3c_i2c0_set_platdata(&n30_i2ccfg); /* Turn off suspend on both USB ports, and switch the @@ -532,10 +592,13 @@ static void __init n30_init(void) s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | S3C2410_MISCCR_USBSUSPND0 | S3C2410_MISCCR_USBSUSPND1, - S3C2410_MISCCR_USBSUSPND1); + S3C2410_MISCCR_USBSUSPND0); platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices)); } + + WARN_ON(gpio_request(S3C2410_GPB(3), "udc pup")); + gpio_direction_output(S3C2410_GPB(3), 0); } MACHINE_START(N30, "Acer-N30") @@ -547,7 +610,7 @@ MACHINE_START(N30, "Acer-N30") .boot_params = S3C2410_SDRAM_PA + 0x100, .timer = &s3c24xx_timer, .init_machine = n30_init, - .init_irq = n30_init_irq, + .init_irq = s3c24xx_init_irq, .map_io = n30_map_io, MACHINE_END @@ -559,6 +622,6 @@ MACHINE_START(N35, "Acer-N35") .boot_params = S3C2410_SDRAM_PA + 0x100, .timer = &s3c24xx_timer, .init_machine = n30_init, - .init_irq = n30_init_irq, + .init_irq = s3c24xx_init_irq, .map_io = n30_map_io, MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index 92a4ec375d8..d0e87b6e2e0 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -58,6 +58,7 @@ #include <plat/iic.h> #include <plat/common-smdk.h> +#include <plat/gpio-cfg.h> #include <plat/devs.h> #include <plat/cpu.h> #include <plat/pm.h> @@ -219,10 +220,10 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs) { switch (cs) { case BITBANG_CS_ACTIVE: - s3c2410_gpio_setpin(S3C2410_GPB(5), 0); + gpio_set_value(S3C2410_GPB(5), 0); break; case BITBANG_CS_INACTIVE: - s3c2410_gpio_setpin(S3C2410_GPB(5), 1); + gpio_set_value(S3C2410_GPB(5), 1); break; } } @@ -347,13 +348,14 @@ static void __init qt2410_machine_init(void) } s3c24xx_fb_set_platdata(&qt2410_fb_info); - s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT); s3c2410_gpio_setpin(S3C2410_GPB(0), 1); s3c24xx_udc_set_platdata(&qt2410_udc_cfg); s3c_i2c0_set_platdata(NULL); - s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT); + WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs")); + gpio_direction_output(S3C2410_GPB(5), 1); platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); s3c_pm_init(); diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 9051f0d3112..d540d79dd26 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -357,8 +357,7 @@ static struct clk *vr1000_clocks[] __initdata = { static void vr1000_power_off(void) { - s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPB(9), 1); + gpio_direction_output(S3C2410_GPB(9), 1); } static void __init vr1000_map_io(void) @@ -395,6 +394,8 @@ static void __init vr1000_init(void) nor_simtec_init(); simtec_audio_add(NULL, true, NULL); + + WARN_ON(gpio_request(S3C2410_GPB(9), "power off")); } MACHINE_START(VR1000, "Thorcom-VR1000") diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index 966119c8efe..725636fc4dc 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c @@ -60,10 +60,10 @@ static void s3c2410_pm_prepare(void) __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); } - /* the RX3715 uses similar code and the same H1940 and the + /* RX3715 and RX1950 use similar to H1940 code and the * same offsets for resume and checksum pointers */ - if (machine_is_rx3715()) { + if (machine_is_rx3715() || machine_is_rx1950()) { void *base = phys_to_virt(H1940_SUSPEND_CHECK); unsigned long ptr; unsigned long calc = 0; @@ -79,6 +79,17 @@ static void s3c2410_pm_prepare(void) if ( machine_is_aml_m5900() ) s3c2410_gpio_setpin(S3C2410_GPF(2), 1); + if (machine_is_rx1950()) { + /* According to S3C2442 user's manual, page 7-17, + * when the system is operating in NAND boot mode, + * the hardware pin configuration - EINT[23:21] – + * must be set as input for starting up after + * wakeup from sleep mode + */ + s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT); + s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT); + s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT); + } } static int s3c2410_pm_resume(struct sys_device *dev) diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index 91ba42f688a..adc90a3c589 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -16,6 +16,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> +#include <linux/gpio.h> #include <linux/clk.h> #include <linux/sysdev.h> #include <linux/serial_core.h> @@ -40,6 +41,10 @@ #include <plat/clock.h> #include <plat/pll.h> +#include <plat/gpio-core.h> +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> + /* Initial IO mappings */ static struct map_desc s3c2410_iodesc[] __initdata = { @@ -65,6 +70,9 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no) void __init s3c2410_map_io(void) { + s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up; + s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up; + iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); } diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig index 9a8c0657ae5..cef6a65637b 100644 --- a/arch/arm/mach-s3c2412/Kconfig +++ b/arch/arm/mach-s3c2412/Kconfig @@ -16,7 +16,8 @@ config CPU_S3C2412 config CPU_S3C2412_ONLY bool depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \ - !CPU_S3C2440 && !CPU_S3C2442 && !CPU_S3C2443 && CPU_S3C2412 + !CPU_2416 && !CPU_S3C2440 && !CPU_S3C2442 && \ + !CPU_S3C2443 && CPU_S3C2412 default y if CPU_S3C2412 config S3C2412_DMA diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index e880524904e..7abecfca0b7 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c @@ -30,7 +30,6 @@ #include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <mach/regs-sdi.h> -#include <plat/regs-s3c2412-iis.h> #include <plat/regs-iis.h> #include <plat/regs-spi.h> @@ -119,13 +118,11 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { .name = "i2s-sdi", .channels = MAP(S3C2412_DMAREQSEL_I2SRX), .channels_rx = MAP(S3C2412_DMAREQSEL_I2SRX), - .hw_addr.from = S3C2410_PA_IIS + S3C2412_IISRXD, }, [DMACH_I2S_OUT] = { .name = "i2s-sdo", .channels = MAP(S3C2412_DMAREQSEL_I2STX), .channels_rx = MAP(S3C2412_DMAREQSEL_I2STX), - .hw_addr.to = S3C2410_PA_IIS + S3C2412_IISTXD, }, [DMACH_USB_EP1] = { .name = "usb-ep1", diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c index f7afece7fc3..3404a876b33 100644 --- a/arch/arm/mach-s3c2412/gpio.c +++ b/arch/arm/mach-s3c2412/gpio.c @@ -16,41 +16,43 @@ #include <linux/types.h> #include <linux/module.h> #include <linux/interrupt.h> +#include <linux/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/regs-gpio.h> - #include <mach/hardware.h> +#include <plat/gpio-core.h> + int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state) { - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long offs = S3C2410_GPIO_OFFSET(pin); + struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); + unsigned long offs = pin - chip->chip.base; unsigned long flags; unsigned long slpcon; offs *= 2; - if (pin < S3C2410_GPIO_BANKB) + if (pin < S3C2410_GPB(0)) return -EINVAL; - if (pin >= S3C2410_GPIO_BANKF && - pin <= S3C2410_GPIO_BANKG) + if (pin >= S3C2410_GPF(0) && + pin <= S3C2410_GPG(16)) return -EINVAL; - if (pin > (S3C2410_GPIO_BANKH + 32)) + if (pin > S3C2410_GPH(16)) return -EINVAL; local_irq_save(flags); - slpcon = __raw_readl(base + 0x0C); + slpcon = __raw_readl(chip->base + 0x0C); slpcon &= ~(3 << offs); slpcon |= state << offs; - __raw_writel(slpcon, base + 0x0C); + __raw_writel(slpcon, chip->base + 0x0C); local_irq_restore(flags); diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index 14f4798291a..478f4b4606c 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c @@ -48,6 +48,7 @@ #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> +#include <plat/gpio-cfg.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> @@ -357,8 +358,7 @@ static void jive_lcm_reset(unsigned int set) { printk(KERN_DEBUG "%s(%d)\n", __func__, set); - s3c2410_gpio_setpin(S3C2410_GPG(13), set); - s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT); + gpio_set_value(S3C2410_GPG(13), set); } #undef LCD_UPPER_MARGIN @@ -391,7 +391,7 @@ static struct ili9320_platdata jive_lcm_config = { static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs) { - s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1); + gpio_set_value(S3C2410_GPB(7), cs ? 0 : 1); } static struct s3c2410_spigpio_info jive_lcd_spi = { @@ -413,7 +413,7 @@ static struct platform_device jive_device_lcdspi = { static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs) { - s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1); + gpio_set_value(S3C2410_GPH(10), cs ? 0 : 1); } static struct s3c2410_spigpio_info jive_wm8750_spi = { @@ -531,7 +531,7 @@ static void jive_power_off(void) printk(KERN_INFO "powering system down...\n"); s3c2410_gpio_setpin(S3C2410_GPC(5), 1); - s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT); } static void __init jive_machine_init(void) @@ -636,22 +636,22 @@ static void __init jive_machine_init(void) /* initialise the spi */ - s3c2410_gpio_setpin(S3C2410_GPG(13), 0); - s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT); + gpio_request(S3C2410_GPG(13), "lcm reset"); + gpio_direction_output(S3C2410_GPG(13), 0); - s3c2410_gpio_setpin(S3C2410_GPB(7), 1); - s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT); + gpio_request(S3C2410_GPB(7), "jive spi"); + gpio_direction_output(S3C2410_GPB(7), 1); s3c2410_gpio_setpin(S3C2410_GPB(6), 0); - s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT); s3c2410_gpio_setpin(S3C2410_GPG(8), 1); - s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT); /* initialise the WM8750 spi */ - s3c2410_gpio_setpin(S3C2410_GPH(10), 1); - s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT); + gpio_request(S3C2410_GPH(10), "jive wm8750 spi"); + gpio_direction_output(S3C2410_GPH(10), 1); /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ @@ -674,7 +674,7 @@ static void __init jive_machine_init(void) } MACHINE_START(JIVE, "JIVE") - /* Maintainer: Ben Dooks <ben@fluff.org> */ + /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ .phys_io = S3C2410_PA_UART, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index 0392065af1a..ba93a356a83 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -85,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd) switch (cmd) { case S3C2410_UDC_P_ENABLE : - s3c2410_gpio_setpin(S3C2410_GPF(2), 1); + gpio_set_value(S3C2410_GPF(2), 1); break; case S3C2410_UDC_P_DISABLE : - s3c2410_gpio_setpin(S3C2410_GPF(2), 0); + gpio_set_value(S3C2410_GPF(2), 0); break; case S3C2410_UDC_P_RESET : break; @@ -134,8 +134,8 @@ static void __init smdk2413_machine_init(void) { /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ - s3c2410_gpio_setpin(S3C2410_GPF(2), 0); - s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); + WARN_ON(gpio_request(S3C2410_GPF(2), "udc pull")); + gpio_direction_output(S3C2410_GPF(2), 0); s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | S3C2410_MISCCR_USBSUSPND0 | @@ -150,7 +150,7 @@ static void __init smdk2413_machine_init(void) } MACHINE_START(S3C2413, "S3C2413") - /* Maintainer: Ben Dooks <ben@fluff.org> */ + /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ .phys_io = S3C2410_PA_UART, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, @@ -163,7 +163,7 @@ MACHINE_START(S3C2413, "S3C2413") MACHINE_END MACHINE_START(SMDK2412, "SMDK2412") - /* Maintainer: Ben Dooks <ben@fluff.org> */ + /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ .phys_io = S3C2410_PA_UART, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, @@ -176,7 +176,7 @@ MACHINE_START(SMDK2412, "SMDK2412") MACHINE_END MACHINE_START(SMDK2413, "SMDK2413") - /* Maintainer: Ben Dooks <ben@fluff.org> */ + /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ .phys_io = S3C2410_PA_UART, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig new file mode 100644 index 00000000000..657e4fe17f3 --- /dev/null +++ b/arch/arm/mach-s3c2416/Kconfig @@ -0,0 +1,39 @@ +# arch/arm/mach-s3c2416/Kconfig +# +# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com> +# +# Licensed under GPLv2 + +# note, this also supports the S3C2450 which is so similar it has the same +# ID code as the S3C2416. + +config CPU_S3C2416 + bool + depends on ARCH_S3C2410 + select CPU_ARM926T + select S3C2416_DMA if S3C2410_DMA + select CPU_LLSERIAL_S3C2440 + select S3C_GPIO_PULL_UPDOWN + select SAMSUNG_CLKSRC + select S3C2443_CLOCK + help + Support for the S3C2416 SoC from the S3C24XX line + +config S3C2416_DMA + bool + depends on CPU_S3C2416 + help + Internal config node for S3C2416 DMA support + +menu "S3C2416 Machines" + +config MACH_SMDK2416 + bool "SMDK2416" + select CPU_S3C2416 + select S3C_DEV_FB + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + help + Say Y here if you are using an SMDK2416 + +endmenu diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile new file mode 100644 index 00000000000..6c12c7bf40a --- /dev/null +++ b/arch/arm/mach-s3c2416/Makefile @@ -0,0 +1,19 @@ +# arch/arm/mach-s3c2416/Makefile +# +# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com> +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock.o +obj-$(CONFIG_CPU_S3C2416) += irq.o + +#obj-$(CONFIG_S3C2416_DMA) += dma.o + +# Machine support + +obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c new file mode 100644 index 00000000000..7ccf5a2a2bf --- /dev/null +++ b/arch/arm/mach-s3c2416/clock.c @@ -0,0 +1,135 @@ +/* linux/arch/arm/mach-s3c2416/clock.c + * + * Copyright (c) 2010 Simtec Electronics + * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org> + * + * S3C2416 Clock control support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/init.h> +#include <linux/clk.h> + +#include <plat/s3c2416.h> +#include <plat/s3c2443.h> +#include <plat/clock.h> +#include <plat/clock-clksrc.h> +#include <plat/cpu.h> + +#include <plat/cpu-freq.h> +#include <plat/pll6553x.h> +#include <plat/pll.h> + +#include <asm/mach/map.h> + +#include <mach/regs-clock.h> +#include <mach/regs-s3c2443-clock.h> + +static unsigned int armdiv[8] = { + [0] = 1, + [1] = 2, + [2] = 3, + [3] = 4, + [5] = 6, + [7] = 8, +}; + +/* ID to hardware numbering, 0 is HSMMC1, 1 is HSMMC0 */ +static struct clksrc_clk hsmmc_div[] = { + [0] = { + .clk = { + .name = "hsmmc-div", + .id = 1, + .parent = &clk_esysclk.clk, + }, + .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, + }, + [1] = { + .clk = { + .name = "hsmmc-div", + .id = 0, + .parent = &clk_esysclk.clk, + }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, + }, +}; + +static struct clksrc_clk hsmmc_mux[] = { + [0] = { + .clk = { + .id = 1, + .name = "hsmmc-if", + .ctrlbit = (1 << 6), + .enable = s3c2443_clkcon_enable_s, + }, + .sources = &(struct clksrc_sources) { + .nr_sources = 2, + .sources = (struct clk *[]) { + [0] = &hsmmc_div[0].clk, + [1] = NULL, /* to fix */ + }, + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 }, + }, + [1] = { + .clk = { + .id = 0, + .name = "hsmmc-if", + .ctrlbit = (1 << 12), + .enable = s3c2443_clkcon_enable_s, + }, + .sources = &(struct clksrc_sources) { + .nr_sources = 2, + .sources = (struct clk *[]) { + [0] = &hsmmc_div[1].clk, + [1] = NULL, /* to fix */ + }, + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 }, + }, +}; + + +static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0) +{ + clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT; + + return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]; +} + +void __init_or_cpufreq s3c2416_setup_clocks(void) +{ + s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div); +} + + +static struct clksrc_clk *clksrcs[] __initdata = { + &hsmmc_div[0], + &hsmmc_div[1], + &hsmmc_mux[0], + &hsmmc_mux[1], +}; + +void __init s3c2416_init_clocks(int xtal) +{ + u32 epllcon = __raw_readl(S3C2443_EPLLCON); + u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4); + int ptr; + + /* s3c2416 EPLL compatible with s3c64xx */ + clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1); + + clk_epll.parent = &clk_epllref.clk; + + s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_register_clksrc(clksrcs[ptr], 1); + + s3c_pwmclk_init(); + +} diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c new file mode 100644 index 00000000000..89f521d59d0 --- /dev/null +++ b/arch/arm/mach-s3c2416/irq.c @@ -0,0 +1,254 @@ +/* linux/arch/arm/mach-s3c2416/irq.c + * + * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, + * as part of OpenInkpot project + * Copyright (c) 2009 Promwad Innovation Company + * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/sysdev.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <asm/irq.h> + +#include <asm/mach/irq.h> + +#include <mach/regs-irq.h> +#include <mach/regs-gpio.h> + +#include <plat/cpu.h> +#include <plat/pm.h> +#include <plat/irq.h> + +#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) + +static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len) +{ + unsigned int subsrc, submsk; + unsigned int end; + + /* read the current pending interrupts, and the mask + * for what it is available */ + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + subsrc >>= (irq - S3C2410_IRQSUB(0)); + subsrc &= (1 << len)-1; + + end = len + irq; + + for (; irq < end && subsrc; irq++) { + if (subsrc & 1) + generic_handle_irq(irq); + + subsrc >>= 1; + } +} + +/* WDT/AC97 sub interrupts */ + +static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc) +{ + s3c2416_irq_demux(IRQ_S3C2443_WDT, 4); +} + +#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0)) +#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97) + +static void s3c2416_irq_wdtac97_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); +} + +static void s3c2416_irq_wdtac97_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_WDTAC97); +} + +static void s3c2416_irq_wdtac97_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); +} + +static struct irq_chip s3c2416_irq_wdtac97 = { + .mask = s3c2416_irq_wdtac97_mask, + .unmask = s3c2416_irq_wdtac97_unmask, + .ack = s3c2416_irq_wdtac97_ack, +}; + + +/* LCD sub interrupts */ + +static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) +{ + s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4); +} + +#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) +#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4) + +static void s3c2416_irq_lcd_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD); +} + +static void s3c2416_irq_lcd_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_LCD); +} + +static void s3c2416_irq_lcd_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD); +} + +static struct irq_chip s3c2416_irq_lcd = { + .mask = s3c2416_irq_lcd_mask, + .unmask = s3c2416_irq_lcd_unmask, + .ack = s3c2416_irq_lcd_ack, +}; + + +/* DMA sub interrupts */ + +static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc) +{ + s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6); +} + +#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0)) +#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5) + + +static void s3c2416_irq_dma_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA); +} + +static void s3c2416_irq_dma_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_DMA); +} + +static void s3c2416_irq_dma_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA); +} + +static struct irq_chip s3c2416_irq_dma = { + .mask = s3c2416_irq_dma_mask, + .unmask = s3c2416_irq_dma_unmask, + .ack = s3c2416_irq_dma_ack, +}; + + +/* UART3 sub interrupts */ + +static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) +{ + s3c2416_irq_demux(IRQ_S3C2443_UART3, 3); +} + +#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0)) +#define SUBMSK_UART3 (0xf << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0))) + + +static void s3c2416_irq_uart3_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3); +} + +static void s3c2416_irq_uart3_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_UART3); +} + +static void s3c2416_irq_uart3_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3); +} + +static struct irq_chip s3c2416_irq_uart3 = { + .mask = s3c2416_irq_uart3_mask, + .unmask = s3c2416_irq_uart3_unmask, + .ack = s3c2416_irq_uart3_ack, +}; + + +/* IRQ initialisation code */ + +static int __init s3c2416_add_sub(unsigned int base, + void (*demux)(unsigned int, + struct irq_desc *), + struct irq_chip *chip, + unsigned int start, unsigned int end) +{ + unsigned int irqno; + + set_irq_chip(base, &s3c_irq_level_chip); + set_irq_handler(base, handle_level_irq); + set_irq_chained_handler(base, demux); + + for (irqno = start; irqno <= end; irqno++) { + set_irq_chip(irqno, chip); + set_irq_handler(irqno, handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + return 0; +} + +static int __init s3c2416_irq_add(struct sys_device *sysdev) +{ + printk(KERN_INFO "S3C2416: IRQ Support\n"); + + s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd, + IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4); + + s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma, + &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5); + + s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3, + &s3c2416_irq_uart3, + IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3); + + s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97, + &s3c2416_irq_wdtac97, + IRQ_S3C2443_WDT, IRQ_S3C2443_AC97); + + return 0; +} + +static struct sysdev_driver s3c2416_irq_driver = { + .add = s3c2416_irq_add, +}; + +static int __init s3c2416_irq_init(void) +{ + return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_irq_driver); +} + +arch_initcall(s3c2416_irq_init); + diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c new file mode 100644 index 00000000000..5fc3f67ef26 --- /dev/null +++ b/arch/arm/mach-s3c2416/mach-smdk2416.c @@ -0,0 +1,206 @@ +/* linux/arch/arm/mach-s3c2416/mach-hanlin_v3c.c + * + * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, + * as part of OpenInkpot project + * Copyright (c) 2009 Promwad Innovation Company + * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/mtd/partitions.h> +#include <linux/gpio.h> +#include <linux/fb.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/hardware.h> +#include <asm/irq.h> +#include <asm/mach-types.h> + +#include <plat/regs-serial.h> +#include <mach/regs-gpio.h> +#include <mach/regs-lcd.h> + +#include <mach/idle.h> +#include <mach/leds-gpio.h> +#include <plat/iic.h> + +#include <plat/s3c2416.h> +#include <plat/gpio-cfg.h> +#include <plat/clock.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/nand.h> + +#include <plat/regs-fb-v4.h> +#include <plat/fb.h> + +#include <plat/common-smdk.h> + +static struct map_desc smdk2416_iodesc[] __initdata = { + /* ISA IO Space map (memory space selected by A24) */ + + { + .virtual = (u32)S3C24XX_VA_ISA_WORD, + .pfn = __phys_to_pfn(S3C2410_CS2), + .length = 0x10000, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, + .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), + .length = SZ_4M, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_BYTE, + .pfn = __phys_to_pfn(S3C2410_CS2), + .length = 0x10000, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000, + .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), + .length = SZ_4M, + .type = MT_DEVICE, + } +}; + +#define UCON (S3C2410_UCON_DEFAULT | \ + S3C2440_UCON_PCLK | \ + S3C2443_UCON_RXERR_IRQEN) + +#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) + +#define UFCON (S3C2410_UFCON_RXTRIG8 | \ + S3C2410_UFCON_FIFOMODE | \ + S3C2440_UFCON_TXTRIG16) + +static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + /* IR port */ + [2] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON | 0x50, + .ufcon = UFCON, + } +}; + +struct s3c_fb_pd_win smdk2416_fb_win[] = { + [0] = { + /* think this is the same as the smdk6410 */ + .win_mode = { + .pixclock = 41094, + .left_margin = 8, + .right_margin = 13, + .upper_margin = 7, + .lower_margin = 5, + .hsync_len = 3, + .vsync_len = 1, + .xres = 800, + .yres = 480, + }, + .default_bpp = 16, + .max_bpp = 32, + }, +}; + +static void s3c2416_fb_gpio_setup_24bpp(void) +{ + unsigned int gpio; + + for (gpio = S3C2410_GPC(1); gpio <= S3C2410_GPC(4); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + for (gpio = S3C2410_GPC(8); gpio <= S3C2410_GPC(15); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + for (gpio = S3C2410_GPD(0); gpio <= S3C2410_GPD(15); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } +} + +static struct s3c_fb_platdata smdk2416_fb_platdata = { + .win[0] = &smdk2416_fb_win[0], + .setup_gpio = s3c2416_fb_gpio_setup_24bpp, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, +}; + +static struct platform_device *smdk2416_devices[] __initdata = { + &s3c_device_fb, + &s3c_device_wdt, + &s3c_device_ohci, + &s3c_device_i2c0, + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, +}; + +static void __init smdk2416_map_io(void) +{ + s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); +} + +static void __init smdk2416_machine_init(void) +{ + s3c_i2c0_set_platdata(NULL); + s3c_fb_set_platdata(&smdk2416_fb_platdata); + + gpio_request(S3C2410_GPB(4), "USBHost Power"); + gpio_direction_output(S3C2410_GPB(4), 1); + + gpio_request(S3C2410_GPB(3), "Display Power"); + gpio_direction_output(S3C2410_GPB(3), 1); + + gpio_request(S3C2410_GPB(1), "Display Reset"); + gpio_direction_output(S3C2410_GPB(1), 1); + + platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices)); + smdk_machine_init(); +} + +MACHINE_START(SMDK2416, "SMDK2416") + /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + + .init_irq = s3c24xx_init_irq, + .map_io = smdk2416_map_io, + .init_machine = smdk2416_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c new file mode 100644 index 00000000000..35dabccd0ac --- /dev/null +++ b/arch/arm/mach-s3c2416/s3c2416.c @@ -0,0 +1,130 @@ +/* linux/arch/arm/mach-s3c2416/s3c2416.c + * + * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, + * as part of OpenInkpot project + * Copyright (c) 2009 Promwad Innovation Company + * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> + * + * Samsung S3C2416 Mobile CPU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/serial_core.h> +#include <linux/sysdev.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/hardware.h> +#include <asm/proc-fns.h> +#include <asm/irq.h> + +#include <mach/reset.h> +#include <mach/idle.h> +#include <mach/regs-s3c2443-clock.h> + +#include <plat/gpio-core.h> +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> +#include <plat/s3c2416.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +#include <plat/iic-core.h> + +static struct map_desc s3c2416_iodesc[] __initdata = { + IODESC_ENT(WATCHDOG), + IODESC_ENT(CLKPWR), + IODESC_ENT(TIMER), +}; + +struct sysdev_class s3c2416_sysclass = { + .name = "s3c2416-core", +}; + +static struct sys_device s3c2416_sysdev = { + .cls = &s3c2416_sysclass, +}; + +static void s3c2416_hard_reset(void) +{ + __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST); +} + +int __init s3c2416_init(void) +{ + printk(KERN_INFO "S3C2416: Initializing architecture\n"); + + s3c24xx_reset_hook = s3c2416_hard_reset; + /* s3c24xx_idle = s3c2416_idle; */ + + /* change WDT IRQ number */ + s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT; + s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT; + + /* the i2c devices are directly compatible with s3c2440 */ + s3c_i2c0_setname("s3c2440-i2c"); + s3c_i2c1_setname("s3c2440-i2c"); + + s3c_device_fb.name = "s3c2443-fb"; + + return sysdev_register(&s3c2416_sysdev); +} + +void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); + + s3c_device_nand.name = "s3c2416-nand"; +} + +/* s3c2416_map_io + * + * register the standard cpu IO areas, and any passed in from the + * machine specific initialisation. + */ + +void __init s3c2416_map_io(void) +{ + s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown; + s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown; + + iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc)); +} + +/* need to register class before we actually register the device, and + * we also need to ensure that it has been initialised before any of the + * drivers even try to use it (even if not on an s3c2416 based system) + * as a driver which may support both 2443 and 2440 may try and use it. +*/ + +static int __init s3c2416_core_init(void) +{ + return sysdev_class_register(&s3c2416_sysclass); +} + +core_initcall(s3c2416_core_init); diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 7f465265cf0..cd8e7de388f 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -6,6 +6,7 @@ config CPU_S3C2440 bool depends on ARCH_S3C2410 select CPU_ARM920T + select S3C_GPIO_PULL_UP select S3C2410_CLOCK select S3C2410_PM if PM select S3C2410_GPIO @@ -187,4 +188,17 @@ config MACH_MINI2440 Say Y here to select support for the MINI2440. Is a 10cm x 10cm board available via various sources. It can come with a 3.5" or 7" touch LCD. +config MACH_RX1950 + bool "HP iPAQ rx1950" + select CPU_S3C2442 + select S3C24XX_DCLK + select PM_H1940 if PM + select I2C + select S3C2410_PWM + select S3C_DEV_NAND + select S3C2410_IOTIMING if S3C2440_CPUFREQ + select S3C2440_XTAL_16934400 + help + Say Y here if you're using HP iPAQ rx1950 + endmenu diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile index c85ba32d895..d5440fa34b0 100644 --- a/arch/arm/mach-s3c2440/Makefile +++ b/arch/arm/mach-s3c2440/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o +obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o # extra machine support diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index 571b17683d9..a76bcda210a 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -53,6 +53,7 @@ #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> +#include <plat/gpio-cfg.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> @@ -102,10 +103,10 @@ static void mini2440_udc_pullup(enum s3c2410_udc_cmd_e cmd) switch (cmd) { case S3C2410_UDC_P_ENABLE : - s3c2410_gpio_setpin(S3C2410_GPC(5), 1); + gpio_set_value(S3C2410_GPC(5), 1); break; case S3C2410_UDC_P_DISABLE : - s3c2410_gpio_setpin(S3C2410_GPC(5), 0); + gpio_set_value(S3C2410_GPC(5), 0); break; case S3C2410_UDC_P_RESET : break; @@ -632,25 +633,25 @@ static void __init mini2440_init(void) mini2440_parse_features(&features, mini2440_features_str); /* turn LCD on */ - s3c2410_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND); + s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND); /* Turn the backlight early on */ - s3c2410_gpio_setpin(S3C2410_GPG(4), 1); - s3c2410_gpio_cfgpin(S3C2410_GPG(4), S3C2410_GPIO_OUTPUT); + WARN_ON(gpio_request(S3C2410_GPG(4), "backlight")); + gpio_direction_output(S3C2410_GPG(4), 1); /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */ - s3c2410_gpio_pullup(S3C2410_GPB(1), 0); + s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP); s3c2410_gpio_setpin(S3C2410_GPB(1), 0); - s3c2410_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT); + s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT); /* Make sure the D+ pullup pin is output */ - s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT); + WARN_ON(gpio_request(S3C2410_GPC(5), "udc pup")); + gpio_direction_output(S3C2410_GPC(5), 0); /* mark the key as input, without pullups (there is one on the board) */ for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) { - s3c2410_gpio_pullup(mini2440_buttons[i].gpio, 0); - s3c2410_gpio_cfgpin(mini2440_buttons[i].gpio, - S3C2410_GPIO_INPUT); + s3c_gpio_setpull(mini2440_buttons[i].gpio, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(mini2440_buttons[i].gpio, S3C2410_GPIO_INPUT); } if (features.lcd_index != -1) { int li; diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c index 342041593f2..3ff62de45fd 100644 --- a/arch/arm/mach-s3c2440/mach-nexcoder.c +++ b/arch/arm/mach-s3c2440/mach-nexcoder.c @@ -40,6 +40,7 @@ #include <plat/regs-serial.h> #include <plat/iic.h> +#include <plat/gpio-cfg.h> #include <plat/s3c2410.h> #include <plat/s3c244x.h> #include <plat/clock.h> @@ -122,15 +123,15 @@ static void __init nexcoder_sensorboard_init(void) { // Initialize SCCB bus s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL - s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT); s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA - s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT); // Power up the sensor board s3c2410_gpio_setpin(S3C2410_GPF(1), 1); - s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN + s3c_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN s3c2410_gpio_setpin(S3C2410_GPF(2), 0); - s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN + s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN } static void __init nexcoder_map_io(void) diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index f35371db33f..319458da71a 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c @@ -49,6 +49,7 @@ #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> +#include <plat/gpio-cfg.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> @@ -298,7 +299,7 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state) /* ensure that an nRESET is not generated on resume. */ s3c2410_gpio_setpin(S3C2410_GPA(21), 1); - s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT); return 0; } @@ -310,7 +311,7 @@ static int osiris_pm_resume(struct sys_device *sd) __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0); - s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); + s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); return 0; } diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c new file mode 100644 index 00000000000..8603b577a24 --- /dev/null +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -0,0 +1,582 @@ +/* linux/arch/arm/mach-s3c2440/mach-rx1950.c + * + * Copyright (c) 2006-2009 Victor Chukhantsev, Denis Grigoriev, + * Copyright (c) 2007-2010 Vasily Khoruzhick + * + * based on smdk2440 written by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/delay.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/serial_core.h> +#include <linux/input.h> +#include <linux/gpio_keys.h> +#include <linux/sysdev.h> +#include <linux/pwm_backlight.h> +#include <linux/pwm.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#include <linux/mmc/host.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach-types.h> + +#include <mach/regs-gpio.h> +#include <mach/regs-gpioj.h> +#include <mach/h1940.h> +#include <mach/fb.h> + +#include <plat/clock.h> +#include <plat/regs-serial.h> +#include <plat/regs-iic.h> +#include <plat/mci.h> +#include <plat/udc.h> +#include <plat/nand.h> +#include <plat/iic.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/pm.h> +#include <plat/irq.h> +#include <plat/ts.h> + +#define LCD_PWM_PERIOD 192960 +#define LCD_PWM_DUTY 127353 + +static struct map_desc rx1950_iodesc[] __initdata = { +}; + +static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = { + [0] = { + .name = "fclk", + .divisor = 0x0a, + .min_baud = 0, + .max_baud = 0, + }, +}; + +static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + .clocks = rx1950_serial_clocks, + .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + .clocks = rx1950_serial_clocks, + .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), + }, + /* IR port */ + [2] = { + .hwport = 2, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x43, + .ufcon = 0xf1, + .clocks = rx1950_serial_clocks, + .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), + }, +}; + +static struct s3c2410fb_display rx1950_display = { + .type = S3C2410_LCDCON1_TFT, + .width = 240, + .height = 320, + .xres = 240, + .yres = 320, + .bpp = 16, + + .pixclock = 260000, + .left_margin = 10, + .right_margin = 20, + .hsync_len = 10, + .upper_margin = 2, + .lower_margin = 2, + .vsync_len = 2, + + .lcdcon5 = S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVCLK | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_HWSWP | + (0x02 << 13) | + (0x02 << 15), + +}; + +static struct s3c2410fb_mach_info rx1950_lcd_cfg = { + .displays = &rx1950_display, + .num_displays = 1, + .default_display = 0, + + .lpcsel = 0x02, + .gpccon = 0xaa9556a9, + .gpccon_mask = 0xffc003fc, + .gpcup = 0x0000ffff, + .gpcup_mask = 0xffffffff, + + .gpdcon = 0xaa90aaa1, + .gpdcon_mask = 0xffc0fff0, + .gpdup = 0x0000fcfd, + .gpdup_mask = 0xffffffff, + +}; + +static struct pwm_device *lcd_pwm; + +void rx1950_lcd_power(int enable) +{ + int i; + static int enabled; + if (enabled == enable) + return; + if (!enable) { + + /* GPC11-GPC15->OUTPUT */ + for (i = 11; i < 16; i++) + gpio_direction_output(S3C2410_GPC(i), 1); + + /* Wait a bit here... */ + mdelay(100); + + /* GPD2-GPD7->OUTPUT */ + /* GPD11-GPD15->OUTPUT */ + /* GPD2-GPD7->1, GPD11-GPD15->1 */ + for (i = 2; i < 8; i++) + gpio_direction_output(S3C2410_GPD(i), 1); + for (i = 11; i < 16; i++) + gpio_direction_output(S3C2410_GPD(i), 1); + + /* Wait a bit here...*/ + mdelay(100); + + /* GPB0->OUTPUT, GPB0->0 */ + gpio_direction_output(S3C2410_GPB(0), 0); + + /* GPC1-GPC4->OUTPUT, GPC1-4->0 */ + for (i = 1; i < 5; i++) + gpio_direction_output(S3C2410_GPC(i), 0); + + /* GPC15-GPC11->0 */ + for (i = 11; i < 16; i++) + gpio_direction_output(S3C2410_GPC(i), 0); + + /* GPD15-GPD11->0, GPD2->GPD7->0 */ + for (i = 11; i < 16; i++) + gpio_direction_output(S3C2410_GPD(i), 0); + + for (i = 2; i < 8; i++) + gpio_direction_output(S3C2410_GPD(i), 0); + + /* GPC6->0, GPC7->0, GPC5->0 */ + gpio_direction_output(S3C2410_GPC(6), 0); + gpio_direction_output(S3C2410_GPC(7), 0); + gpio_direction_output(S3C2410_GPC(5), 0); + + /* GPB1->OUTPUT, GPB1->0 */ + gpio_direction_output(S3C2410_GPB(1), 0); + pwm_config(lcd_pwm, 0, LCD_PWM_PERIOD); + pwm_disable(lcd_pwm); + + /* GPC0->0, GPC10->0 */ + gpio_direction_output(S3C2410_GPC(0), 0); + gpio_direction_output(S3C2410_GPC(10), 0); + } else { + pwm_config(lcd_pwm, LCD_PWM_DUTY, LCD_PWM_PERIOD); + pwm_enable(lcd_pwm); + + gpio_direction_output(S3C2410_GPC(0), 1); + gpio_direction_output(S3C2410_GPC(5), 1); + + s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPB1_TOUT1); + gpio_direction_output(S3C2410_GPC(7), 1); + + for (i = 1; i < 5; i++) + s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2)); + + for (i = 11; i < 16; i++) + s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2)); + + for (i = 2; i < 8; i++) + s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2)); + + for (i = 11; i < 16; i++) + s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2)); + + gpio_direction_output(S3C2410_GPC(10), 1); + gpio_direction_output(S3C2410_GPC(6), 1); + } + enabled = enable; +} + +static void rx1950_bl_power(int enable) +{ + static int enabled; + if (enabled == enable) + return; + if (!enable) { + gpio_direction_output(S3C2410_GPB(0), 0); + } else { + /* LED driver need a "push" to power on */ + gpio_direction_output(S3C2410_GPB(0), 1); + /* Warm up backlight for one period of PWM. + * Without this trick its almost impossible to + * enable backlight with low brightness value + */ + ndelay(48000); + s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0); + } + enabled = enable; +} + +static int rx1950_backlight_init(struct device *dev) +{ + WARN_ON(gpio_request(S3C2410_GPB(0), "Backlight")); + lcd_pwm = pwm_request(1, "RX1950 LCD"); + if (IS_ERR(lcd_pwm)) { + dev_err(dev, "Unable to request PWM for LCD power!\n"); + return PTR_ERR(lcd_pwm); + } + + rx1950_lcd_power(1); + rx1950_bl_power(1); + + return 0; +} + +static void rx1950_backlight_exit(struct device *dev) +{ + rx1950_bl_power(0); + rx1950_lcd_power(0); + + pwm_free(lcd_pwm); + gpio_free(S3C2410_GPB(0)); +} + + +static int rx1950_backlight_notify(struct device *dev, int brightness) +{ + if (!brightness) { + rx1950_bl_power(0); + rx1950_lcd_power(0); + } else { + rx1950_lcd_power(1); + rx1950_bl_power(1); + } + return brightness; +} + +static struct platform_pwm_backlight_data rx1950_backlight_data = { + .pwm_id = 0, + .max_brightness = 24, + .dft_brightness = 4, + .pwm_period_ns = 48000, + .init = rx1950_backlight_init, + .notify = rx1950_backlight_notify, + .exit = rx1950_backlight_exit, +}; + +static struct platform_device rx1950_backlight = { + .name = "pwm-backlight", + .dev = { + .parent = &s3c_device_timer[0].dev, + .platform_data = &rx1950_backlight_data, + }, +}; + +static void rx1950_set_mmc_power(unsigned char power_mode, unsigned short vdd) +{ + switch (power_mode) { + case MMC_POWER_OFF: + gpio_direction_output(S3C2410_GPJ(1), 0); + break; + case MMC_POWER_UP: + case MMC_POWER_ON: + gpio_direction_output(S3C2410_GPJ(1), 1); + break; + default: + break; + } +} + +static struct s3c24xx_mci_pdata rx1950_mmc_cfg __initdata = { + .gpio_detect = S3C2410_GPF(5), + .gpio_wprotect = S3C2410_GPH(8), + .set_power = rx1950_set_mmc_power, + .ocr_avail = MMC_VDD_32_33, +}; + +static struct mtd_partition rx1950_nand_part[] = { + [0] = { + .name = "Boot0", + .offset = 0, + .size = 0x4000, + .mask_flags = MTD_WRITEABLE, + }, + [1] = { + .name = "Boot1", + .offset = MTDPART_OFS_APPEND, + .size = 0x40000, + .mask_flags = MTD_WRITEABLE, + }, + [2] = { + .name = "Kernel", + .offset = MTDPART_OFS_APPEND, + .size = 0x300000, + .mask_flags = 0, + }, + [3] = { + .name = "Filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct s3c2410_nand_set rx1950_nand_sets[] = { + [0] = { + .name = "Internal", + .nr_chips = 1, + .nr_partitions = ARRAY_SIZE(rx1950_nand_part), + .partitions = rx1950_nand_part, + }, +}; + +static struct s3c2410_platform_nand rx1950_nand_info = { + .tacls = 25, + .twrph0 = 50, + .twrph1 = 15, + .nr_sets = ARRAY_SIZE(rx1950_nand_sets), + .sets = rx1950_nand_sets, +}; + +static void rx1950_udc_pullup(enum s3c2410_udc_cmd_e cmd) +{ + switch (cmd) { + case S3C2410_UDC_P_ENABLE: + gpio_direction_output(S3C2410_GPJ(5), 1); + break; + case S3C2410_UDC_P_DISABLE: + gpio_direction_output(S3C2410_GPJ(5), 0); + break; + case S3C2410_UDC_P_RESET: + break; + default: + break; + } +} + +static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = { + .udc_command = rx1950_udc_pullup, + .vbus_pin = S3C2410_GPG(5), + .vbus_pin_inverted = 1, +}; + +static struct s3c2410_ts_mach_info rx1950_ts_cfg __initdata = { + .delay = 10000, + .presc = 49, + .oversampling_shift = 3, +}; + +static struct gpio_keys_button rx1950_gpio_keys_table[] = { + { + .code = KEY_POWER, + .gpio = S3C2410_GPF(0), + .active_low = 1, + .desc = "Power button", + .wakeup = 1, + }, + { + .code = KEY_F5, + .gpio = S3C2410_GPF(7), + .active_low = 1, + .desc = "Record button", + }, + { + .code = KEY_F1, + .gpio = S3C2410_GPG(0), + .active_low = 1, + .desc = "Calendar button", + }, + { + .code = KEY_F2, + .gpio = S3C2410_GPG(2), + .active_low = 1, + .desc = "Contacts button", + }, + { + .code = KEY_F3, + .gpio = S3C2410_GPG(3), + .active_low = 1, + .desc = "Mail button", + }, + { + .code = KEY_F4, + .gpio = S3C2410_GPG(7), + .active_low = 1, + .desc = "WLAN button", + }, + { + .code = KEY_LEFT, + .gpio = S3C2410_GPG(10), + .active_low = 1, + .desc = "Left button", + }, + { + .code = KEY_RIGHT, + .gpio = S3C2410_GPG(11), + .active_low = 1, + .desc = "Right button", + }, + { + .code = KEY_UP, + .gpio = S3C2410_GPG(4), + .active_low = 1, + .desc = "Up button", + }, + { + .code = KEY_DOWN, + .gpio = S3C2410_GPG(6), + .active_low = 1, + .desc = "Down button", + }, + { + .code = KEY_ENTER, + .gpio = S3C2410_GPG(9), + .active_low = 1, + .desc = "Ok button" + }, +}; + +static struct gpio_keys_platform_data rx1950_gpio_keys_data = { + .buttons = rx1950_gpio_keys_table, + .nbuttons = ARRAY_SIZE(rx1950_gpio_keys_table), +}; + +static struct platform_device rx1950_device_gpiokeys = { + .name = "gpio-keys", + .dev.platform_data = &rx1950_gpio_keys_data, +}; + +static struct s3c2410_platform_i2c rx1950_i2c_data = { + .flags = 0, + .slave_addr = 0x42, + .frequency = 400 * 1000, + .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, +}; + +static struct platform_device *rx1950_devices[] __initdata = { + &s3c_device_lcd, + &s3c_device_wdt, + &s3c_device_i2c0, + &s3c_device_iis, + &s3c_device_usbgadget, + &s3c_device_rtc, + &s3c_device_nand, + &s3c_device_sdi, + &s3c_device_adc, + &s3c_device_ts, + &s3c_device_timer[0], + &s3c_device_timer[1], + &rx1950_backlight, + &rx1950_device_gpiokeys, +}; + +static struct clk *rx1950_clocks[] __initdata = { + &s3c24xx_clkout0, + &s3c24xx_clkout1, +}; + +static void __init rx1950_map_io(void) +{ + s3c24xx_clkout0.parent = &clk_h; + s3c24xx_clkout1.parent = &clk_f; + + s3c24xx_register_clocks(rx1950_clocks, ARRAY_SIZE(rx1950_clocks)); + + s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc)); + s3c24xx_init_clocks(16934000); + s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs)); + + /* setup PM */ + +#ifdef CONFIG_PM_H1940 + memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 8); +#endif + + s3c_pm_init(); +} + +static void __init rx1950_init_machine(void) +{ + int i; + + s3c24xx_fb_set_platdata(&rx1950_lcd_cfg); + s3c24xx_udc_set_platdata(&rx1950_udc_cfg); + s3c24xx_ts_set_platdata(&rx1950_ts_cfg); + s3c24xx_mci_set_platdata(&rx1950_mmc_cfg); + s3c_i2c0_set_platdata(&rx1950_i2c_data); + s3c_nand_set_platdata(&rx1950_nand_info); + + /* Turn off suspend on both USB ports, and switch the + * selectable USB port to USB device mode. */ + s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | + S3C2410_MISCCR_USBSUSPND0 | + S3C2410_MISCCR_USBSUSPND1, 0x0); + + WARN_ON(gpio_request(S3C2410_GPJ(5), "UDC pullup")); + gpio_direction_output(S3C2410_GPJ(5), 0); + + /* mmc power is disabled by default */ + WARN_ON(gpio_request(S3C2410_GPJ(1), "MMC power")); + gpio_direction_output(S3C2410_GPJ(1), 0); + + for (i = 0; i < 8; i++) + WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power")); + + for (i = 10; i < 16; i++) + WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power")); + + for (i = 2; i < 8; i++) + WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power")); + + for (i = 11; i < 16; i++) + WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power")); + + WARN_ON(gpio_request(S3C2410_GPB(1), "LCD power")); + + platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices)); +} + +MACHINE_START(RX1950, "HP iPAQ RX1950") + /* Maintainers: Vasily Khoruzhick */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = rx1950_map_io, + .init_irq = s3c24xx_init_irq, + .init_machine = rx1950_init_machine, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index 1e836e506f8..d2946de3f36 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -209,7 +209,7 @@ static void __init rx3715_init_machine(void) } MACHINE_START(RX3715, "IPAQ-RX3715") - /* Maintainer: Ben Dooks <ben@fluff.org> */ + /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ .phys_io = S3C2410_PA_UART, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c index 3ac3d636d61..df83276d85a 100644 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c @@ -174,7 +174,7 @@ static void __init smdk2440_machine_init(void) } MACHINE_START(S3C2440, "SMDK2440") - /* Maintainer: Ben Dooks <ben@fluff.org> */ + /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ .phys_io = S3C2410_PA_UART, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c index 2b68f7ea45a..d50f3ae6173 100644 --- a/arch/arm/mach-s3c2440/s3c2440.c +++ b/arch/arm/mach-s3c2440/s3c2440.c @@ -19,6 +19,7 @@ #include <linux/platform_device.h> #include <linux/serial_core.h> #include <linux/sysdev.h> +#include <linux/gpio.h> #include <linux/clk.h> #include <linux/io.h> @@ -33,6 +34,10 @@ #include <plat/cpu.h> #include <plat/s3c244x.h> +#include <plat/gpio-core.h> +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> + static struct sys_device s3c2440_sysdev = { .cls = &s3c2440_sysclass, }; @@ -41,6 +46,9 @@ int __init s3c2440_init(void) { printk("S3C2440: Initialising architecture\n"); + s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up; + s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up; + /* change irq for watchdog */ s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT; diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig index 698140af247..4fef723126f 100644 --- a/arch/arm/mach-s3c2443/Kconfig +++ b/arch/arm/mach-s3c2443/Kconfig @@ -8,6 +8,7 @@ config CPU_S3C2443 select S3C2443_DMA if S3C2410_DMA select CPU_LLSERIAL_S3C2440 select SAMSUNG_CLKSRC + select S3C2443_CLOCK help Support for the S3C2443 SoC from the S3C24XX line diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 62cd4eaee01..0c3c0c884cd 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -21,6 +21,7 @@ */ #include <linux/init.h> + #include <linux/module.h> #include <linux/kernel.h> #include <linux/list.h> @@ -54,111 +55,13 @@ * set the correct muxing at initialisation */ -static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable) -{ - u32 ctrlbit = clk->ctrlbit; - u32 con = __raw_readl(reg); - - if (enable) - con |= ctrlbit; - else - con &= ~ctrlbit; - - __raw_writel(con, reg); - return 0; -} - -static int s3c2443_clkcon_enable_h(struct clk *clk, int enable) -{ - return s3c2443_gate(S3C2443_HCLKCON, clk, enable); -} - -static int s3c2443_clkcon_enable_p(struct clk *clk, int enable) -{ - return s3c2443_gate(S3C2443_PCLKCON, clk, enable); -} - -static int s3c2443_clkcon_enable_s(struct clk *clk, int enable) -{ - return s3c2443_gate(S3C2443_SCLKCON, clk, enable); -} - /* clock selections */ -/* mpllref is a direct descendant of clk_xtal by default, but it is not - * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as - * such directly equating the two source clocks is impossible. - */ -static struct clk clk_mpllref = { - .name = "mpllref", - .parent = &clk_xtal, - .id = -1, -}; - static struct clk clk_i2s_ext = { .name = "i2s-ext", .id = -1, }; -static struct clk *clk_epllref_sources[] = { - [0] = &clk_mpllref, - [1] = &clk_mpllref, - [2] = &clk_xtal, - [3] = &clk_ext, -}; - -static struct clksrc_clk clk_epllref = { - .clk = { - .name = "epllref", - .id = -1, - }, - .sources = &(struct clksrc_sources) { - .sources = clk_epllref_sources, - .nr_sources = ARRAY_SIZE(clk_epllref_sources), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 }, -}; - -static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2443_CLKDIV0); - - div &= S3C2443_CLKDIV0_EXTDIV_MASK; - div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */ - - return parent_rate / (div + 1); -} - -static struct clk clk_mdivclk = { - .name = "mdivclk", - .parent = &clk_mpllref, - .id = -1, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_getrate_mdivclk, - }, -}; - -static struct clk *clk_msysclk_sources[] = { - [0] = &clk_mpllref, - [1] = &clk_mpll, - [2] = &clk_mdivclk, - [3] = &clk_mpllref, -}; - -static struct clksrc_clk clk_msysclk = { - .clk = { - .name = "msysclk", - .parent = &clk_xtal, - .id = -1, - }, - .sources = &(struct clksrc_sources) { - .sources = clk_msysclk_sources, - .nr_sources = ARRAY_SIZE(clk_msysclk_sources), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 }, -}; - /* armdiv * * this clock is sourced from msysclk and can have a number of @@ -266,44 +169,6 @@ static struct clksrc_clk clk_arm = { .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 }, }; -/* esysclk - * - * this is sourced from either the EPLL or the EPLLref clock -*/ - -static struct clk *clk_sysclk_sources[] = { - [0] = &clk_epllref.clk, - [1] = &clk_epll, -}; - -static struct clksrc_clk clk_esysclk = { - .clk = { - .name = "esysclk", - .parent = &clk_epll, - .id = -1, - }, - .sources = &(struct clksrc_sources) { - .sources = clk_sysclk_sources, - .nr_sources = ARRAY_SIZE(clk_sysclk_sources), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 }, -}; - -/* uartclk - * - * UART baud-rate clock sourced from esysclk via a divisor -*/ - -static struct clksrc_clk clk_uart = { - .clk = { - .name = "uartclk", - .id = -1, - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, -}; - - /* hsspi * * high-speed spi clock, sourced from esysclk @@ -320,21 +185,6 @@ static struct clksrc_clk clk_hsspi = { .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, }; -/* usbhost - * - * usb host bus-clock, usually 48MHz to provide USB bus clock timing -*/ - -static struct clksrc_clk clk_usb_bus_host = { - .clk = { - .name = "usb-bus-host-parent", - .id = -1, - .parent = &clk_esysclk.clk, - .ctrlbit = S3C2443_SCLKCON_USBHOST, - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, -}; /* clk_hsmcc_div * @@ -391,7 +241,7 @@ static struct clk clk_hsmmc = { /* i2s_eplldiv * - * This clock is the output from the I2S divisor of ESYSCLK, and is seperate + * This clock is the output from the I2S divisor of ESYSCLK, and is separate * from the mux that comes after it (cannot merge into one single clock) */ @@ -433,89 +283,16 @@ static struct clksrc_clk clk_i2s = { .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 }, }; -/* cam-if - * - * camera interface bus-clock, divided down from esysclk -*/ - -static struct clksrc_clk clk_cam = { - .clk = { - .name = "camif-upll", /* same as 2440 name */ - .id = -1, - .parent = &clk_esysclk.clk, - .ctrlbit = S3C2443_SCLKCON_CAMCLK, - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 }, -}; - -/* display-if - * - * display interface clock, divided from esysclk -*/ - -static struct clksrc_clk clk_display = { - .clk = { - .name = "display-if", - .id = -1, - .parent = &clk_esysclk.clk, - .ctrlbit = S3C2443_SCLKCON_DISPCLK, - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 }, -}; - -/* prediv - * - * this divides the msysclk down to pass to h/p/etc. - */ - -static unsigned long s3c2443_prediv_getrate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); - - clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK; - clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT; - - return rate / (clkdiv0 + 1); -} - -static struct clk clk_prediv = { - .name = "prediv", - .id = -1, - .parent = &clk_msysclk.clk, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_prediv_getrate, - }, -}; - /* standard clock definitions */ -static struct clk init_clocks_disable[] = { +static struct clk init_clocks_off[] = { { - .name = "nand", - .id = -1, - .parent = &clk_h, - }, { .name = "sdi", .id = -1, .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_SDI, }, { - .name = "adc", - .id = -1, - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_ADC, - }, { - .name = "i2c", - .id = -1, - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_IIC, - }, { .name = "iis", .id = -1, .parent = &clk_p, @@ -537,179 +314,12 @@ static struct clk init_clocks_disable[] = { }; static struct clk init_clocks[] = { - { - .name = "dma", - .id = 0, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA0, - }, { - .name = "dma", - .id = 1, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA1, - }, { - .name = "dma", - .id = 2, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA2, - }, { - .name = "dma", - .id = 3, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA3, - }, { - .name = "dma", - .id = 4, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA4, - }, { - .name = "dma", - .id = 5, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA5, - }, { - .name = "lcd", - .id = -1, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_LCDC, - }, { - .name = "gpio", - .id = -1, - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_GPIO, - }, { - .name = "usb-host", - .id = -1, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_USBH, - }, { - .name = "usb-device", - .id = -1, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_USBD, - }, { - .name = "hsmmc", - .id = -1, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_HSMMC, - }, { - .name = "cfc", - .id = -1, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_CFC, - }, { - .name = "ssmc", - .id = -1, - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_SSMC, - }, { - .name = "timers", - .id = -1, - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_PWMT, - }, { - .name = "uart", - .id = 0, - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART0, - }, { - .name = "uart", - .id = 1, - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART1, - }, { - .name = "uart", - .id = 2, - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART2, - }, { - .name = "uart", - .id = 3, - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART3, - }, { - .name = "rtc", - .id = -1, - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_RTC, - }, { - .name = "watchdog", - .id = -1, - .parent = &clk_p, - .ctrlbit = S3C2443_PCLKCON_WDT, - }, { - .name = "usb-bus-host", - .id = -1, - .parent = &clk_usb_bus_host.clk, - }, { - .name = "ac97", - .id = -1, - .parent = &clk_p, - .ctrlbit = S3C2443_PCLKCON_AC97, - } -}; - -/* clocks to add where we need to check their parentage */ - -static struct clksrc_clk __initdata *init_list[] = { - &clk_epllref, /* should be first */ - &clk_esysclk, - &clk_msysclk, - &clk_arm, - &clk_i2s_eplldiv, - &clk_i2s, - &clk_cam, - &clk_uart, - &clk_display, - &clk_hsmmc_div, - &clk_usb_bus_host, }; -static void __init s3c2443_clk_initparents(void) -{ - int ptr; - - for (ptr = 0; ptr < ARRAY_SIZE(init_list); ptr++) - s3c_set_clksrc(init_list[ptr], true); -} - -static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) -{ - clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; - - return clkcon0 + 1; -} - /* clocks to add straight away */ static struct clksrc_clk *clksrcs[] __initdata = { - &clk_usb_bus_host, - &clk_epllref, - &clk_esysclk, - &clk_msysclk, &clk_arm, - &clk_uart, - &clk_display, - &clk_cam, &clk_i2s_eplldiv, &clk_i2s, &clk_hsspi, @@ -717,92 +327,32 @@ static struct clksrc_clk *clksrcs[] __initdata = { }; static struct clk *clks[] __initdata = { - &clk_ext, - &clk_epll, - &clk_usb_bus, - &clk_mpllref, &clk_hsmmc, &clk_armdiv, - &clk_prediv, }; void __init_or_cpufreq s3c2443_setup_clocks(void) { - unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); - unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); - struct clk *xtal_clk; - unsigned long xtal; - unsigned long pll; - unsigned long fclk; - unsigned long hclk; - unsigned long pclk; - - xtal_clk = clk_get(NULL, "xtal"); - xtal = clk_get_rate(xtal_clk); - clk_put(xtal_clk); - - pll = s3c2443_get_mpll(mpllcon, xtal); - clk_msysclk.clk.rate = pll; - - fclk = pll / s3c2443_fclk_div(clkdiv0); - hclk = s3c2443_prediv_getrate(&clk_prediv); - hclk /= s3c2443_get_hdiv(clkdiv0); - pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); - - s3c24xx_setup_clocks(fclk, hclk, pclk); - - printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", - (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", - print_mhz(pll), print_mhz(fclk), - print_mhz(hclk), print_mhz(pclk)); - - s3c24xx_setup_clocks(fclk, hclk, pclk); + s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div); } void __init s3c2443_init_clocks(int xtal) { - struct clk *clkp; unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); - int ret; int ptr; - /* s3c2443 parents h and p clocks from prediv */ - clk_h.parent = &clk_prediv; - clk_p.parent = &clk_prediv; + clk_epll.rate = s3c2443_get_epll(epllcon, xtal); + clk_epll.parent = &clk_epllref.clk; + + s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div); - s3c24xx_register_baseclocks(xtal); s3c2443_setup_clocks(); - s3c2443_clk_initparents(); - - for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { - clkp = clks[ptr]; - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_register_clksrc(clksrcs[ptr], 1); - clk_epll.rate = s3c2443_get_epll(epllcon, xtal); - clk_epll.parent = &clk_epllref.clk; - clk_usb_bus.parent = &clk_usb_bus_host.clk; - - /* ensure usb bus clock is within correct rate of 48MHz */ - - if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) { - printk(KERN_INFO "Warning: USB host bus not at 48MHz\n"); - clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000); - } - - printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", - (epllcon & S3C2443_PLLCON_OFF) ? "off":"on", - print_mhz(clk_get_rate(&clk_epll)), - print_mhz(clk_get_rate(&clk_usb_bus))); - /* register clocks from clock array */ s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); @@ -819,17 +369,8 @@ void __init s3c2443_init_clocks(int xtal) /* install (and disable) the clocks we do not need immediately */ - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - - (clkp->enable)(clkp, 0); - } + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c index e2e362bda9b..4c863d3a52f 100644 --- a/arch/arm/mach-s3c2443/mach-smdk2443.c +++ b/arch/arm/mach-s3c2443/mach-smdk2443.c @@ -131,7 +131,7 @@ static void __init smdk2443_machine_init(void) } MACHINE_START(SMDK2443, "SMDK2443") - /* Maintainer: Ben Dooks <ben@fluff.org> */ + /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ .phys_io = S3C2410_PA_UART, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 959df3840de..69e9fbfea91 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -85,6 +85,7 @@ config MACH_ANW6410 config MACH_SMDK6410 bool "SMDK6410" select CPU_S3C6410 + select SAMSUNG_DEV_ADC select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_I2C1 diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 3758e15086b..a10f1fc6b02 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -56,7 +56,6 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o # device support obj-y += dev-uart.o -obj-y += dev-rtc.o obj-y += dev-audio.o -obj-$(CONFIG_S3C_ADC) += dev-adc.o obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o +obj-$(CONFIG_S3C64XX_DEV_TS) += dev-ts.o diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 2ac2e7d73e5..7a4138beb66 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -88,6 +88,12 @@ struct clk clk_48m = { .enable = clk_48m_ctrl, }; +struct clk clk_xusbxti = { + .name = "xusbxti", + .id = -1, + .rate = 48000000, +}; + static int inline s3c64xx_gate(void __iomem *reg, struct clk *clk, int enable) @@ -518,6 +524,11 @@ static struct clk clk_iis_cd1 = { .id = -1, }; +static struct clk clk_iisv4_cd = { + .name = "iis_cdclk_v4", + .id = -1, +}; + static struct clk clk_pcm_cd = { .name = "pcm_cdclk", .id = -1, @@ -549,6 +560,19 @@ static struct clksrc_sources clkset_audio1 = { .nr_sources = ARRAY_SIZE(clkset_audio1_list), }; +static struct clk *clkset_audio2_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_dout_mpll, + [2] = &clk_fin_epll, + [3] = &clk_iisv4_cd, + [4] = &clk_pcm_cd, +}; + +static struct clksrc_sources clkset_audio2 = { + .sources = clkset_audio2_list, + .nr_sources = ARRAY_SIZE(clkset_audio2_list), +}; + static struct clk *clkset_camif_list[] = { &clk_h2, }; @@ -652,6 +676,16 @@ static struct clksrc_clk clksrcs[] = { .sources = &clkset_audio1, }, { .clk = { + .name = "audio-bus", + .id = -1, /* There's only one IISv4 port */ + .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 }, + .sources = &clkset_audio2, + }, { + .clk = { .name = "irda-bus", .id = 0, .ctrlbit = S3C_CLKCON_SCLK_IRDA, @@ -749,6 +783,7 @@ static struct clk *clks1[] __initdata = { &clk_ext_xtal_mux, &clk_iis_cd0, &clk_iis_cd1, + &clk_iisv4_cd, &clk_pcm_cd, &clk_mout_epll.clk, &clk_mout_mpll.clk, @@ -762,6 +797,7 @@ static struct clk *clks[] __initdata = { &clk_27m, &clk_48m, &clk_h2, + &clk_xusbxti, }; /** diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 33ccf7bf766..5567e037b0d 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -414,7 +414,7 @@ err_buff: EXPORT_SYMBOL(s3c2410_dma_enqueue); -int s3c2410_dma_devconfig(int channel, +int s3c2410_dma_devconfig(unsigned int channel, enum s3c2410_dmasrc source, unsigned long devaddr) { diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c index 66e6794481d..60c929a3cab 100644 --- a/arch/arm/mach-s3c64xx/gpiolib.c +++ b/arch/arm/mach-s3c64xx/gpiolib.c @@ -51,6 +51,7 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .get_config = s3c_gpio_getcfg_s3c64xx_4bit, .set_pull = s3c_gpio_setpull_updown, .get_pull = s3c_gpio_getpull_updown, }; @@ -58,12 +59,14 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = { .cfg_eint = 7, .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .get_config = s3c_gpio_getcfg_s3c64xx_4bit, .set_pull = s3c_gpio_setpull_updown, .get_pull = s3c_gpio_getpull_updown, }; static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { .cfg_eint = 3, + .get_config = s3c_gpio_getcfg_s3c64xx_4bit, .set_config = s3c_gpio_setcfg_s3c64xx_4bit, .set_pull = s3c_gpio_setpull_updown, .get_pull = s3c_gpio_getpull_updown, @@ -171,6 +174,7 @@ static struct s3c_gpio_chip gpio_4bit2[] = { static struct s3c_gpio_cfg gpio_2bit_cfg_noint = { .set_config = s3c_gpio_setcfg_s3c24xx, + .get_config = s3c_gpio_getcfg_s3c24xx, .set_pull = s3c_gpio_setpull_updown, .get_pull = s3c_gpio_getpull_updown, }; @@ -178,6 +182,7 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_noint = { static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = { .cfg_eint = 2, .set_config = s3c_gpio_setcfg_s3c24xx, + .get_config = s3c_gpio_getcfg_s3c24xx, .set_pull = s3c_gpio_setpull_updown, .get_pull = s3c_gpio_getpull_updown, }; @@ -185,6 +190,7 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = { static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { .cfg_eint = 3, .set_config = s3c_gpio_setcfg_s3c24xx, + .get_config = s3c_gpio_getcfg_s3c24xx, .set_pull = s3c_gpio_setpull_updown, .get_pull = s3c_gpio_getpull_updown, }; diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h index 801c1c0f3a9..9fdd50c8c76 100644 --- a/arch/arm/mach-s3c64xx/include/mach/map.h +++ b/arch/arm/mach-s3c64xx/include/mach/map.h @@ -103,5 +103,8 @@ #define S3C_PA_USBHOST S3C64XX_PA_USBHOST #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG #define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY +#define S3C_PA_RTC S3C64XX_PA_RTC + +#define SAMSUNG_PA_ADC S3C64XX_PA_ADC #endif /* __ASM_ARCH_6400_MAP_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h index 90bbd72fdc4..5ef0bb698ee 100644 --- a/arch/arm/mach-s3c64xx/include/mach/pll.h +++ b/arch/arm/mach-s3c64xx/include/mach/pll.h @@ -20,6 +20,7 @@ #define S3C6400_PLL_SDIV_SHIFT (0) #include <asm/div64.h> +#include <plat/pll6553x.h> static inline unsigned long s3c6400_get_pll(unsigned long baseclk, u32 pllcon) @@ -37,38 +38,8 @@ static inline unsigned long s3c6400_get_pll(unsigned long baseclk, return (unsigned long)fvco; } -#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1) -#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1) -#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1) -#define S3C6400_EPLL_MDIV_SHIFT (16) -#define S3C6400_EPLL_PDIV_SHIFT (8) -#define S3C6400_EPLL_SDIV_SHIFT (0) -#define S3C6400_EPLL_KDIV_MASK (0xffff) - static inline unsigned long s3c6400_get_epll(unsigned long baseclk) { - unsigned long result; - u32 epll0 = __raw_readl(S3C_EPLL_CON0); - u32 epll1 = __raw_readl(S3C_EPLL_CON1); - u32 mdiv, pdiv, sdiv, kdiv; - u64 tmp; - - mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK; - pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK; - sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK; - kdiv = epll1 & S3C6400_EPLL_KDIV_MASK; - - /* We need to multiple baseclk by mdiv (the integer part) and kdiv - * which is in 2^16ths, so shift mdiv up (does not overflow) and - * add kdiv before multiplying. The use of tmp is to avoid any - * overflows before shifting bac down into result when multipling - * by the mdiv and kdiv pair. - */ - - tmp = baseclk; - tmp *= (mdiv << 16) + kdiv; - do_div(tmp, (pdiv << sdiv)); - result = tmp >> 16; - - return result; + return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0), + __raw_readl(S3C_EPLL_CON1)); } diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 3ef62741e5d..0114eb0c1fe 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -33,6 +33,7 @@ #define S3C_PCLK_GATE S3C_CLKREG(0x34) #define S3C_SCLK_GATE S3C_CLKREG(0x38) #define S3C_MEM0_GATE S3C_CLKREG(0x3C) +#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) /* CLKDIV0 */ #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c index f7b18983950..59916676d8d 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6400.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c @@ -84,7 +84,7 @@ static void __init smdk6400_machine_init(void) } MACHINE_START(SMDK6400, "SMDK6400") - /* Maintainer: Ben Dooks <ben@fluff.org> */ + /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ .phys_io = S3C_PA_UART & 0xfff00000, .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, .boot_params = S3C64XX_PA_SDRAM + 0x100, diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 2d5afd221d7..9d51455feb3 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -656,7 +656,7 @@ static void __init smdk6410_machine_init(void) } MACHINE_START(SMDK6410, "SMDK6410") - /* Maintainer: Ben Dooks <ben@fluff.org> */ + /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ .phys_io = S3C_PA_UART & 0xfff00000, .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, .boot_params = S3C64XX_PA_SDRAM + 0x100, diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index 59635d19466..3ab695c691e 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -38,6 +38,7 @@ #include <plat/clock.h> #include <plat/sdhci.h> #include <plat/iic-core.h> +#include <plat/adc.h> #include <mach/s3c6400.h> #include <mach/s3c6410.h> @@ -52,6 +53,7 @@ void __init s3c6410_map_io(void) s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); + s3c_device_adc.name = "s3c64xx-adc"; s3c_device_nand.name = "s3c6400-nand"; } diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig index 4c29ff8b07d..77aeffd1733 100644 --- a/arch/arm/mach-s5p6440/Kconfig +++ b/arch/arm/mach-s5p6440/Kconfig @@ -9,6 +9,7 @@ if ARCH_S5P6440 config CPU_S5P6440 bool + select S3C_PL330_DMA help Enable S5P6440 CPU support diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile index 1ad894b1d3a..44facf43d59 100644 --- a/arch/arm/mach-s5p6440/Makefile +++ b/arch/arm/mach-s5p6440/Makefile @@ -12,8 +12,12 @@ obj- := # Core support for S5P6440 system -obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o +obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o dma.o +obj-$(CONFIG_CPU_S5P6440) += setup-i2c0.o # machine support obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o + +# device support +obj-y += dev-audio.o diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index b2672e16e7a..ca6e48dce77 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -134,24 +134,6 @@ static struct clksrc_clk clk_mout_mpll = { .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 }, }; -static struct clk clk_h_low = { - .name = "hclk_low", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .ops = &clk_ops_def_setrate, -}; - -static struct clk clk_p_low = { - .name = "pclk_low", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .ops = &clk_ops_def_setrate, -}; - enum perf_level { L0 = 532*1000, L1 = 266*1000, @@ -247,23 +229,70 @@ static struct clk_ops s5p6440_clkarm_ops = { .round_rate = s5p6440_armclk_round_rate, }; -static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); +static struct clksrc_clk clk_armclk = { + .clk = { + .name = "armclk", + .id = 1, + .parent = &clk_mout_apll.clk, + .ops = &s5p6440_clkarm_ops, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 }, +}; - if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK) - rate /= 2; +static struct clksrc_clk clk_dout_mpll = { + .clk = { + .name = "dout_mpll", + .id = -1, + .parent = &clk_mout_mpll.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 }, +}; - return rate; -} +static struct clksrc_clk clk_hclk = { + .clk = { + .name = "clk_hclk", + .id = -1, + .parent = &clk_armclk.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 }, +}; -static struct clk clk_dout_mpll = { - .name = "dout_mpll", - .id = -1, - .parent = &clk_mout_mpll.clk, - .ops = &(struct clk_ops) { - .get_rate = s5p6440_clk_doutmpll_get_rate, +static struct clksrc_clk clk_pclk = { + .clk = { + .name = "clk_pclk", + .id = -1, + .parent = &clk_hclk.clk, }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 }, +}; + +static struct clk *clkset_hclklow_list[] = { + &clk_mout_apll.clk, + &clk_mout_mpll.clk, +}; + +static struct clksrc_sources clkset_hclklow = { + .sources = clkset_hclklow_list, + .nr_sources = ARRAY_SIZE(clkset_hclklow_list), +}; + +static struct clksrc_clk clk_hclk_low = { + .clk = { + .name = "hclk_low", + .id = -1, + }, + .sources = &clkset_hclklow, + .reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk clk_pclk_low = { + .clk = { + .name = "pclk_low", + .id = -1, + .parent = &clk_hclk_low.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, }; int s5p6440_clk48m_ctrl(struct clk *clk, int enable) @@ -307,6 +336,11 @@ static int s5p6440_sclk_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable); } +static int s5p6440_sclk1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable); +} + static int s5p6440_mem_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable); @@ -321,37 +355,37 @@ static struct clk init_clocks_disable[] = { { .name = "nand", .id = -1, - .parent = &clk_h, + .parent = &clk_hclk.clk, .enable = s5p6440_mem_ctrl, .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON, }, { .name = "adc", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_TSADC, }, { .name = "i2c", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_IIC0, }, { .name = "i2s_v40", .id = 0, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_IIS2, }, { .name = "spi", .id = 0, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_SPI0, }, { .name = "spi", .id = 1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_SPI1, }, { @@ -387,58 +421,124 @@ static struct clk init_clocks_disable[] = { }, { .name = "otg", .id = -1, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk0_ctrl, .ctrlbit = S5P_CLKCON_HCLK0_USB }, { .name = "post", .id = -1, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk0_ctrl, .ctrlbit = S5P_CLKCON_HCLK0_POST0 }, { .name = "lcd", .id = -1, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk1_ctrl, .ctrlbit = S5P_CLKCON_HCLK1_DISPCON, }, { .name = "hsmmc", .id = 0, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk0_ctrl, .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0, }, { .name = "hsmmc", .id = 1, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk0_ctrl, .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1, }, { .name = "hsmmc", .id = 2, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk0_ctrl, .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2, }, { .name = "rtc", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_RTC, }, { .name = "watchdog", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_WDT, }, { .name = "timers", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_PWM, - } + }, { + .name = "hclk_fimgvg", + .id = -1, + .parent = &clk_hclk.clk, + .enable = s5p6440_hclk1_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "tsi", + .id = -1, + .parent = &clk_hclk_low.clk, + .enable = s5p6440_hclk1_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "pclk_fimgvg", + .id = -1, + .parent = &clk_pclk.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 31), + }, { + .name = "dmc0", + .id = -1, + .parent = &clk_pclk.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 30), + }, { + .name = "etm", + .id = -1, + .parent = &clk_pclk.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 29), + }, { + .name = "dsim", + .id = -1, + .parent = &clk_pclk_low.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 28), + }, { + .name = "gps", + .id = -1, + .parent = &clk_pclk_low.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 25), + }, { + .name = "pcm", + .id = -1, + .parent = &clk_pclk_low.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "irom", + .id = -1, + .parent = &clk_hclk.clk, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = (1 << 25), + }, { + .name = "dma", + .id = -1, + .parent = &clk_hclk_low.clk, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = (1 << 12), + }, { + .name = "2d", + .id = -1, + .parent = &clk_hclk.clk, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = (1 << 8), + }, }; /* @@ -448,34 +548,46 @@ static struct clk init_clocks[] = { { .name = "gpio", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_GPIO, }, { .name = "uart", .id = 0, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_UART0, }, { .name = "uart", .id = 1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_UART1, }, { .name = "uart", .id = 2, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_UART2, }, { .name = "uart", .id = 3, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_UART3, - } + }, { + .name = "mem", + .id = -1, + .parent = &clk_hclk.clk, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = (1 << 21), + }, { + .name = "intc", + .id = -1, + .parent = &clk_hclk.clk, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = (1 << 1), + }, }; static struct clk clk_iis_cd_v40 = { @@ -488,20 +600,20 @@ static struct clk clk_pcm_cd = { .id = -1, }; -static struct clk *clkset_spi_mmc_list[] = { +static struct clk *clkset_group1_list[] = { &clk_mout_epll.clk, - &clk_dout_mpll, + &clk_dout_mpll.clk, &clk_fin_epll, }; -static struct clksrc_sources clkset_spi_mmc = { - .sources = clkset_spi_mmc_list, - .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), +static struct clksrc_sources clkset_group1 = { + .sources = clkset_group1_list, + .nr_sources = ARRAY_SIZE(clkset_group1_list), }; static struct clk *clkset_uart_list[] = { &clk_mout_epll.clk, - &clk_dout_mpll + &clk_dout_mpll.clk, }; static struct clksrc_sources clkset_uart = { @@ -509,6 +621,19 @@ static struct clksrc_sources clkset_uart = { .nr_sources = ARRAY_SIZE(clkset_uart_list), }; +static struct clk *clkset_audio_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll.clk, + &clk_fin_epll, + &clk_iis_cd_v40, + &clk_pcm_cd, +}; + +static struct clksrc_sources clkset_audio = { + .sources = clkset_audio_list, + .nr_sources = ARRAY_SIZE(clkset_audio_list), +}; + static struct clksrc_clk clksrcs[] = { { .clk = { @@ -517,7 +642,7 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S5P_CLKCON_SCLK0_MMC0, .enable = s5p6440_sclk_ctrl, }, - .sources = &clkset_spi_mmc, + .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 }, }, { @@ -527,7 +652,7 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S5P_CLKCON_SCLK0_MMC1, .enable = s5p6440_sclk_ctrl, }, - .sources = &clkset_spi_mmc, + .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 }, }, { @@ -537,7 +662,7 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S5P_CLKCON_SCLK0_MMC2, .enable = s5p6440_sclk_ctrl, }, - .sources = &clkset_spi_mmc, + .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 }, }, { @@ -557,7 +682,7 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S5P_CLKCON_SCLK0_SPI0, .enable = s5p6440_sclk_ctrl, }, - .sources = &clkset_spi_mmc, + .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, }, { @@ -567,17 +692,63 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S5P_CLKCON_SCLK0_SPI1, .enable = s5p6440_sclk_ctrl, }, - .sources = &clkset_spi_mmc, + .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, - } + }, { + .clk = { + .name = "sclk_post", + .id = -1, + .ctrlbit = (1 << 10), + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_dispcon", + .id = -1, + .ctrlbit = (1 << 1), + .enable = s5p6440_sclk1_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimgvg", + .id = -1, + .ctrlbit = (1 << 2), + .enable = s5p6440_sclk1_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_audio2", + .id = -1, + .ctrlbit = (1 << 11), + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_audio, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 }, + }, }; /* Clock initialisation code */ -static struct clksrc_clk *init_parents[] = { +static struct clksrc_clk *sysclks[] = { &clk_mout_apll, &clk_mout_epll, &clk_mout_mpll, + &clk_dout_mpll, + &clk_armclk, + &clk_hclk, + &clk_pclk, + &clk_hclk_low, + &clk_pclk_low, }; void __init_or_cpufreq s5p6440_setup_clocks(void) @@ -593,21 +764,13 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) unsigned long apll; unsigned long mpll; unsigned int ptr; - u32 clkdiv0; - u32 clkdiv3; /* Set S5P6440 functions for clk_fout_epll */ clk_fout_epll.enable = s5p6440_epll_enable; clk_fout_epll.ops = &s5p6440_epll_ops; - /* Set S5P6440 functions for arm clock */ - clk_arm.parent = &clk_mout_apll.clk; - clk_arm.ops = &s5p6440_clkarm_ops; clk_48m.enable = s5p6440_clk48m_ctrl; - clkdiv0 = __raw_readl(S5P_CLK_DIV0); - clkdiv3 = __raw_readl(S5P_CLK_DIV3); - xtal_clk = clk_get(NULL, "ext_xtal"); BUG_ON(IS_ERR(xtal_clk)); @@ -619,41 +782,28 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502); + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + clk_fout_apll.rate = apll; + printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ " E=%ld.%ldMHz\n", print_mhz(apll), print_mhz(mpll), print_mhz(epll)); - fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM); - hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK); - pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK); - - if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) { - /* Asynchronous mode */ - hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); - } else { - /* Synchronous mode */ - hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); - } - - pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW); + fclk = clk_get_rate(&clk_armclk.clk); + hclk = clk_get_rate(&clk_hclk.clk); + pclk = clk_get_rate(&clk_pclk.clk); + hclk_low = clk_get_rate(&clk_hclk_low.clk); + pclk_low = clk_get_rate(&clk_pclk_low.clk); printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", print_mhz(hclk), print_mhz(hclk_low), print_mhz(pclk), print_mhz(pclk_low)); - clk_fout_mpll.rate = mpll; - clk_fout_epll.rate = epll; - clk_fout_apll.rate = apll; - clk_f.rate = fclk; clk_h.rate = hclk; clk_p.rate = pclk; - clk_h_low.rate = hclk_low; - clk_p_low.rate = pclk_low; - - for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s3c_set_clksrc(init_parents[ptr], true); for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); @@ -661,13 +811,8 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) static struct clk *clks[] __initdata = { &clk_ext, - &clk_mout_epll.clk, - &clk_mout_mpll.clk, - &clk_dout_mpll, &clk_iis_cd_v40, &clk_pcm_cd, - &clk_p_low, - &clk_h_low, }; void __init s5p6440_register_clocks(void) @@ -680,6 +825,9 @@ void __init s5p6440_register_clocks(void) if (ret > 0) printk(KERN_ERR "Failed to register %u clocks\n", ret); + for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) + s3c_register_clksrc(sysclks[ptr], 1); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c index 1794131aeac..ca3b3206e6f 100644 --- a/arch/arm/mach-s5p6440/cpu.c +++ b/arch/arm/mach-s5p6440/cpu.c @@ -88,7 +88,7 @@ void __init s5p6440_init_irq(void) s5p_init_irq(vic, ARRAY_SIZE(vic)); } -static struct sysdev_class s5p6440_sysclass = { +struct sysdev_class s5p6440_sysclass = { .name = "s5p6440-core", }; diff --git a/arch/arm/mach-s5p6440/dev-audio.c b/arch/arm/mach-s5p6440/dev-audio.c new file mode 100644 index 00000000000..0c536796283 --- /dev/null +++ b/arch/arm/mach-s5p6440/dev-audio.c @@ -0,0 +1,127 @@ +/* linux/arch/arm/mach-s5p6440/dev-audio.c + * + * Copyright (c) 2010 Samsung Electronics Co. Ltd + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <plat/gpio-cfg.h> +#include <plat/audio.h> + +#include <mach/gpio.h> +#include <mach/map.h> +#include <mach/dma.h> +#include <mach/irqs.h> + +static int s5p6440_cfg_i2s(struct platform_device *pdev) +{ + /* configure GPIO for i2s port */ + switch (pdev->id) { + case -1: + s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5)); + break; + + default: + printk(KERN_ERR "Invalid Device %d\n", pdev->id); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_i2s_pdata = { + .cfg_gpio = s5p6440_cfg_i2s, +}; + +static struct resource s5p6440_iis0_resource[] = { + [0] = { + .start = S5P6440_PA_I2S, + .end = S5P6440_PA_I2S + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S0_TX, + .end = DMACH_I2S0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S0_RX, + .end = DMACH_I2S0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5p6440_device_iis = { + .name = "s3c64xx-iis-v4", + .id = -1, + .num_resources = ARRAY_SIZE(s5p6440_iis0_resource), + .resource = s5p6440_iis0_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +/* PCM Controller platform_devices */ + +static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2)); + break; + + default: + printk(KERN_DEBUG "Invalid PCM Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_pcm_pdata = { + .cfg_gpio = s5p6440_pcm_cfg_gpio, +}; + +static struct resource s5p6440_pcm0_resource[] = { + [0] = { + .start = S5P6440_PA_PCM, + .end = S5P6440_PA_PCM + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM0_TX, + .end = DMACH_PCM0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM0_RX, + .end = DMACH_PCM0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5p6440_device_pcm = { + .name = "samsung-pcm", + .id = 0, + .num_resources = ARRAY_SIZE(s5p6440_pcm0_resource), + .resource = s5p6440_pcm0_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; diff --git a/arch/arm/mach-s5p6440/dma.c b/arch/arm/mach-s5p6440/dma.c new file mode 100644 index 00000000000..07606ad5751 --- /dev/null +++ b/arch/arm/mach-s5p6440/dma.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <plat/devs.h> +#include <plat/irqs.h> + +#include <mach/map.h> +#include <mach/irqs.h> + +#include <plat/s3c-pl330-pdata.h> + +static u64 dma_dmamask = DMA_BIT_MASK(32); + +static struct resource s5p6440_pdma_resource[] = { + [0] = { + .start = S5P6440_PA_PDMA, + .end = S5P6440_PA_PDMA + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DMA0, + .end = IRQ_DMA0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_pl330_platdata s5p6440_pdma_pdata = { + .peri = { + [0] = DMACH_UART0_RX, + [1] = DMACH_UART0_TX, + [2] = DMACH_UART1_RX, + [3] = DMACH_UART1_TX, + [4] = DMACH_UART2_RX, + [5] = DMACH_UART2_TX, + [6] = DMACH_UART3_RX, + [7] = DMACH_UART3_TX, + [8] = DMACH_MAX, + [9] = DMACH_MAX, + [10] = DMACH_PCM0_TX, + [11] = DMACH_PCM0_RX, + [12] = DMACH_I2S0_TX, + [13] = DMACH_I2S0_RX, + [14] = DMACH_SPI0_TX, + [15] = DMACH_SPI0_RX, + [16] = DMACH_MAX, + [17] = DMACH_MAX, + [18] = DMACH_MAX, + [19] = DMACH_MAX, + [20] = DMACH_SPI1_TX, + [21] = DMACH_SPI1_RX, + [22] = DMACH_MAX, + [23] = DMACH_MAX, + [24] = DMACH_MAX, + [25] = DMACH_MAX, + [26] = DMACH_MAX, + [27] = DMACH_MAX, + [28] = DMACH_MAX, + [29] = DMACH_PWM, + [30] = DMACH_MAX, + [31] = DMACH_MAX, + }, +}; + +static struct platform_device s5p6440_device_pdma = { + .name = "s3c-pl330", + .id = 1, + .num_resources = ARRAY_SIZE(s5p6440_pdma_resource), + .resource = s5p6440_pdma_resource, + .dev = { + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5p6440_pdma_pdata, + }, +}; + +static struct platform_device *s5p6440_dmacs[] __initdata = { + &s5p6440_device_pdma, +}; + +static int __init s5p6440_dma_init(void) +{ + platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs)); + + return 0; +} +arch_initcall(s5p6440_dma_init); diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p6440/gpio.c index b0ea741177a..262dc75d5be 100644 --- a/arch/arm/mach-s5p6440/gpio.c +++ b/arch/arm/mach-s5p6440/gpio.c @@ -161,12 +161,15 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = { }, { .cfg_eint = 0, .set_config = s3c_gpio_setcfg_s3c24xx, + .get_config = s3c_gpio_getcfg_s3c24xx, }, { .cfg_eint = 2, .set_config = s3c_gpio_setcfg_s3c24xx, + .get_config = s3c_gpio_getcfg_s3c24xx, }, { .cfg_eint = 3, .set_config = s3c_gpio_setcfg_s3c24xx, + .get_config = s3c_gpio_getcfg_s3c24xx, }, }; @@ -279,6 +282,8 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) for (; nr_chips > 0; nr_chips--, chipcfg++) { if (!chipcfg->set_config) chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit; + if (!chipcfg->get_config) + chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit; if (!chipcfg->set_pull) chipcfg->set_pull = s3c_gpio_setpull_updown; if (!chipcfg->get_pull) diff --git a/arch/arm/mach-s5p6440/include/mach/dma.h b/arch/arm/mach-s5p6440/include/mach/dma.h new file mode 100644 index 00000000000..81209eb1409 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/dma.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MACH_DMA_H +#define __MACH_DMA_H + +/* This platform uses the common S3C DMA API driver for PL330 */ +#include <plat/s3c-dma-pl330.h> + +#endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h index 8924e5a4d6a..72aedadd412 100644 --- a/arch/arm/mach-s5p6440/include/mach/map.h +++ b/arch/arm/mach-s5p6440/include/mach/map.h @@ -29,6 +29,8 @@ #define S5P6440_PA_VIC0 (0xE4000000) #define S5P_PA_VIC0 S5P6440_PA_VIC0 +#define S5P6440_PA_PDMA 0xE9000000 + #define S5P6440_PA_VIC1 (0xE4100000) #define S5P_PA_VIC1 S5P6440_PA_VIC1 @@ -61,6 +63,12 @@ #define S5P6440_PA_SDRAM (0x20000000) #define S5P_PA_SDRAM S5P6440_PA_SDRAM +/* I2S */ +#define S5P6440_PA_I2S 0xF2000000 + +/* PCM */ +#define S5P6440_PA_PCM 0xF2100000 + /* compatibiltiy defines. */ #define S3C_PA_UART S5P6440_PA_UART #define S3C_PA_IIC S5P6440_PA_IIC0 diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h index c4bb7c55547..6a2a02fdf12 100644 --- a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h +++ b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h @@ -1,11 +1,14 @@ /* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * http://armlinux.simtec.co.uk/ * - * Copyright 2009 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ + * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h * * S5P6440 - pwm clock and timer support * @@ -14,16 +17,19 @@ * published by the Free Software Foundation. */ +#ifndef __ASM_ARCH_PWMCLK_H +#define __ASM_ARCH_PWMCLK_H __FILE__ + /** * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @cfg: The timer TCFG1 register bits shifted down to 0. + * @tcfg: The timer TCFG1 register bits shifted down to 0. * * Return true if the given configuration from TCFG1 is a TCLK instead * any of the TDIV clocks. */ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) { - return tcfg == S3C2410_TCFG1_MUX_TCLK; + return 0; } /** @@ -35,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) */ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) { - return 1 << (1 + tcfg1); + return 1 << tcfg1; } /** @@ -45,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) */ static inline unsigned int pwm_tdiv_has_div1(void) { - return 0; + return 1; } /** @@ -56,7 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void) */ static inline unsigned long pwm_tdiv_div_bits(unsigned int div) { - return ilog2(div) - 1; + return ilog2(div); } -#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK +#define S3C_TCFG1_MUX_TCLK 0 + +#endif /* __ASM_ARCH_PWMCLK_H */ diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c index 3ae88f2c7c7..d7fede971ca 100644 --- a/arch/arm/mach-s5p6440/mach-smdk6440.c +++ b/arch/arm/mach-s5p6440/mach-smdk6440.c @@ -84,6 +84,7 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { }; static struct platform_device *smdk6440_devices[] __initdata = { + &s5p6440_device_iis, }; static void __init smdk6440_map_io(void) diff --git a/arch/arm/plat-s5p/setup-i2c0.c b/arch/arm/mach-s5p6440/setup-i2c0.c index 67a66e02a97..69e8a664aed 100644 --- a/arch/arm/plat-s5p/setup-i2c0.c +++ b/arch/arm/mach-s5p6440/setup-i2c0.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/setup-i2c0.c +/* linux/arch/arm/mach-s5p6440/setup-i2c0.c * * Copyright (c) 2009 Samsung Electronics Co., Ltd. * http://www.samsung.com/ diff --git a/arch/arm/mach-s5p6442/Kconfig b/arch/arm/mach-s5p6442/Kconfig index 4f3f6de6a01..0fd41b44791 100644 --- a/arch/arm/mach-s5p6442/Kconfig +++ b/arch/arm/mach-s5p6442/Kconfig @@ -12,6 +12,7 @@ if ARCH_S5P6442 config CPU_S5P6442 bool select PLAT_S5P + select S3C_PL330_DMA help Enable S5P6442 CPU support diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile index dde39a6ce6b..e30a7f76aee 100644 --- a/arch/arm/mach-s5p6442/Makefile +++ b/arch/arm/mach-s5p6442/Makefile @@ -12,8 +12,12 @@ obj- := # Core support for S5P6442 system -obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o +obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o dma.o +obj-$(CONFIG_CPU_S5P6442) += setup-i2c0.o # machine support obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o + +# device support +obj-y += dev-audio.o diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c index bc2524df89b..a48fb553fd0 100644 --- a/arch/arm/mach-s5p6442/cpu.c +++ b/arch/arm/mach-s5p6442/cpu.c @@ -95,7 +95,7 @@ void __init s5p6442_init_irq(void) s5p_init_irq(vic, ARRAY_SIZE(vic)); } -static struct sysdev_class s5p6442_sysclass = { +struct sysdev_class s5p6442_sysclass = { .name = "s5p6442-core", }; diff --git a/arch/arm/mach-s5p6442/dev-audio.c b/arch/arm/mach-s5p6442/dev-audio.c new file mode 100644 index 00000000000..cb801e1f5e2 --- /dev/null +++ b/arch/arm/mach-s5p6442/dev-audio.c @@ -0,0 +1,197 @@ +/* linux/arch/arm/mach-s5p6442/dev-audio.c + * + * Copyright (c) 2010 Samsung Electronics Co. Ltd + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <plat/gpio-cfg.h> +#include <plat/audio.h> + +#include <mach/gpio.h> +#include <mach/map.h> +#include <mach/dma.h> +#include <mach/irqs.h> + +static int s5p6442_cfg_i2s(struct platform_device *pdev) +{ + /* configure GPIO for i2s port */ + switch (pdev->id) { + case 1: + s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(2)); + break; + + case -1: + s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(2)); + break; + + default: + printk(KERN_ERR "Invalid Device %d\n", pdev->id); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_i2s_pdata = { + .cfg_gpio = s5p6442_cfg_i2s, +}; + +static struct resource s5p6442_iis0_resource[] = { + [0] = { + .start = S5P6442_PA_I2S0, + .end = S5P6442_PA_I2S0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S0_TX, + .end = DMACH_I2S0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S0_RX, + .end = DMACH_I2S0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5p6442_device_iis0 = { + .name = "s3c64xx-iis-v4", + .id = -1, + .num_resources = ARRAY_SIZE(s5p6442_iis0_resource), + .resource = s5p6442_iis0_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +static struct resource s5p6442_iis1_resource[] = { + [0] = { + .start = S5P6442_PA_I2S1, + .end = S5P6442_PA_I2S1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S1_TX, + .end = DMACH_I2S1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S1_RX, + .end = DMACH_I2S1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5p6442_device_iis1 = { + .name = "s3c64xx-iis", + .id = 1, + .num_resources = ARRAY_SIZE(s5p6442_iis1_resource), + .resource = s5p6442_iis1_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +/* PCM Controller platform_devices */ + +static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(3)); + break; + + case 1: + s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(3)); + break; + + default: + printk(KERN_DEBUG "Invalid PCM Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_pcm_pdata = { + .cfg_gpio = s5p6442_pcm_cfg_gpio, +}; + +static struct resource s5p6442_pcm0_resource[] = { + [0] = { + .start = S5P6442_PA_PCM0, + .end = S5P6442_PA_PCM0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM0_TX, + .end = DMACH_PCM0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM0_RX, + .end = DMACH_PCM0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5p6442_device_pcm0 = { + .name = "samsung-pcm", + .id = 0, + .num_resources = ARRAY_SIZE(s5p6442_pcm0_resource), + .resource = s5p6442_pcm0_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +static struct resource s5p6442_pcm1_resource[] = { + [0] = { + .start = S5P6442_PA_PCM1, + .end = S5P6442_PA_PCM1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM1_TX, + .end = DMACH_PCM1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM1_RX, + .end = DMACH_PCM1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5p6442_device_pcm1 = { + .name = "samsung-pcm", + .id = 1, + .num_resources = ARRAY_SIZE(s5p6442_pcm1_resource), + .resource = s5p6442_pcm1_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; diff --git a/arch/arm/mach-s5p6442/dma.c b/arch/arm/mach-s5p6442/dma.c new file mode 100644 index 00000000000..ad4f8704b93 --- /dev/null +++ b/arch/arm/mach-s5p6442/dma.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <plat/devs.h> +#include <plat/irqs.h> + +#include <mach/map.h> +#include <mach/irqs.h> + +#include <plat/s3c-pl330-pdata.h> + +static u64 dma_dmamask = DMA_BIT_MASK(32); + +static struct resource s5p6442_pdma_resource[] = { + [0] = { + .start = S5P6442_PA_PDMA, + .end = S5P6442_PA_PDMA + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PDMA, + .end = IRQ_PDMA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_pl330_platdata s5p6442_pdma_pdata = { + .peri = { + [0] = DMACH_UART0_RX, + [1] = DMACH_UART0_TX, + [2] = DMACH_UART1_RX, + [3] = DMACH_UART1_TX, + [4] = DMACH_UART2_RX, + [5] = DMACH_UART2_TX, + [6] = DMACH_MAX, + [7] = DMACH_MAX, + [8] = DMACH_MAX, + [9] = DMACH_I2S0_RX, + [10] = DMACH_I2S0_TX, + [11] = DMACH_I2S0S_TX, + [12] = DMACH_I2S1_RX, + [13] = DMACH_I2S1_TX, + [14] = DMACH_MAX, + [15] = DMACH_MAX, + [16] = DMACH_SPI0_RX, + [17] = DMACH_SPI0_TX, + [18] = DMACH_MAX, + [19] = DMACH_MAX, + [20] = DMACH_PCM0_RX, + [21] = DMACH_PCM0_TX, + [22] = DMACH_PCM1_RX, + [23] = DMACH_PCM1_TX, + [24] = DMACH_MAX, + [25] = DMACH_MAX, + [26] = DMACH_MAX, + [27] = DMACH_MSM_REQ0, + [28] = DMACH_MSM_REQ1, + [29] = DMACH_MSM_REQ2, + [30] = DMACH_MSM_REQ3, + [31] = DMACH_MAX, + }, +}; + +static struct platform_device s5p6442_device_pdma = { + .name = "s3c-pl330", + .id = 1, + .num_resources = ARRAY_SIZE(s5p6442_pdma_resource), + .resource = s5p6442_pdma_resource, + .dev = { + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5p6442_pdma_pdata, + }, +}; + +static struct platform_device *s5p6442_dmacs[] __initdata = { + &s5p6442_device_pdma, +}; + +static int __init s5p6442_dma_init(void) +{ + platform_add_devices(s5p6442_dmacs, ARRAY_SIZE(s5p6442_dmacs)); + + return 0; +} +arch_initcall(s5p6442_dma_init); diff --git a/arch/arm/mach-s5p6442/include/mach/dma.h b/arch/arm/mach-s5p6442/include/mach/dma.h new file mode 100644 index 00000000000..81209eb1409 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/dma.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MACH_DMA_H +#define __MACH_DMA_H + +/* This platform uses the common S3C DMA API driver for PL330 */ +#include <plat/s3c-dma-pl330.h> + +#endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h index 685277d792f..7568dc0d6be 100644 --- a/arch/arm/mach-s5p6442/include/mach/map.h +++ b/arch/arm/mach-s5p6442/include/mach/map.h @@ -34,6 +34,9 @@ #define S5P6442_PA_VIC2 (0xE4200000) #define S5P_PA_VIC2 S5P6442_PA_VIC2 +#define S5P6442_PA_MDMA 0xE8000000 +#define S5P6442_PA_PDMA 0xE9000000 + #define S5P6442_PA_TIMER (0xEA000000) #define S5P_PA_TIMER S5P6442_PA_TIMER @@ -51,6 +54,14 @@ #define S5P6442_PA_SDRAM (0x20000000) #define S5P_PA_SDRAM S5P6442_PA_SDRAM +/* I2S */ +#define S5P6442_PA_I2S0 0xC0B00000 +#define S5P6442_PA_I2S1 0xF2200000 + +/* PCM */ +#define S5P6442_PA_PCM0 0xF2400000 +#define S5P6442_PA_PCM1 0xF2500000 + /* compatibiltiy defines. */ #define S3C_PA_UART S5P6442_PA_UART #define S3C_PA_IIC S5P6442_PA_IIC0 diff --git a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h index 15e8525da0f..2724b37def3 100644 --- a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h +++ b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h @@ -1,13 +1,14 @@ /* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * http://armlinux.simtec.co.uk/ * - * Copyright 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h + * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h * * S5P6442 - pwm clock and timer support * @@ -21,14 +22,14 @@ /** * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @cfg: The timer TCFG1 register bits shifted down to 0. + * @tcfg: The timer TCFG1 register bits shifted down to 0. * * Return true if the given configuration from TCFG1 is a TCLK instead * any of the TDIV clocks. */ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) { - return tcfg == S3C2410_TCFG1_MUX_TCLK; + return tcfg == S3C64XX_TCFG1_MUX_TCLK; } /** @@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) */ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) { - return 1 << (1 + tcfg1); + return 1 << tcfg1; } /** @@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) */ static inline unsigned int pwm_tdiv_has_div1(void) { - return 0; + return 1; } /** @@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void) */ static inline unsigned long pwm_tdiv_div_bits(unsigned int div) { - return ilog2(div) - 1; + return ilog2(div); } -#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK +#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK #endif /* __ASM_ARCH_PWMCLK_H */ diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c index 0d63371ce07..ebcf9977725 100644 --- a/arch/arm/mach-s5p6442/mach-smdk6442.c +++ b/arch/arm/mach-s5p6442/mach-smdk6442.c @@ -65,6 +65,7 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = { }; static struct platform_device *smdk6442_devices[] __initdata = { + &s5p6442_device_iis0, }; static void __init smdk6442_map_io(void) diff --git a/arch/arm/mach-s5p6442/setup-i2c0.c b/arch/arm/mach-s5p6442/setup-i2c0.c new file mode 100644 index 00000000000..662695dd776 --- /dev/null +++ b/arch/arm/mach-s5p6442/setup-i2c0.c @@ -0,0 +1,25 @@ +/* linux/arch/arm/mach-s5p6442/setup-i2c0.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * I2C0 GPIO configuration. + * + * Based on plat-s3c64xx/setup-i2c0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <plat/iic.h> + +void s3c_i2c0_cfg_gpio(struct platform_device *dev) +{ + /* Will be populated later */ +} diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index 27ec167d280..8593337784e 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig @@ -12,12 +12,22 @@ config CPU_S5PC100 help Enable S5PC100 CPU support +config S5PC100_SETUP_FB_24BPP + bool + help + Common setup code for S5PC1XX with an 24bpp RGB display helper. + config S5PC100_SETUP_SDHCI bool select S5PC1XX_SETUP_SDHCI_GPIO help Internal helper functions for S5PC100 based SDHCI systems +config S5PC100_SETUP_I2C1 + bool + help + Common setup code for i2c bus 1. + config MACH_SMDKC100 bool "SMDKC100" select CPU_S5PC100 @@ -26,9 +36,8 @@ config MACH_SMDKC100 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 - select S5PC1XX_SETUP_I2C0 - select S5PC1XX_SETUP_I2C1 - select S5PC1XX_SETUP_FB_24BPP + select S5PC100_SETUP_FB_24BPP + select S5PC100_SETUP_I2C1 select S5PC100_SETUP_SDHCI help Machine support for the Samsung SMDKC100 diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile index 809ff10f768..373bc546eae 100644 --- a/arch/arm/mach-s5pc100/Makefile +++ b/arch/arm/mach-s5pc100/Makefile @@ -11,10 +11,13 @@ obj- := # Core support for S5PC100 system -obj-$(CONFIG_CPU_S5PC100) += cpu.o +obj-$(CONFIG_CPU_S5PC100) += cpu.o gpiolib.o +obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o # Helper and device support +obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o +obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o # machine support diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c new file mode 100644 index 00000000000..e3fed4cfe7a --- /dev/null +++ b/arch/arm/mach-s5pc100/clock.c @@ -0,0 +1,1358 @@ +/* linux/arch/arm/mach-s5pc100/clock.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PC100 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <mach/map.h> + +#include <plat/cpu-freq.h> +#include <mach/regs-clock.h> +#include <plat/clock.h> +#include <plat/cpu.h> +#include <plat/pll.h> +#include <plat/s5p-clock.h> +#include <plat/clock-clksrc.h> +#include <plat/s5pc100.h> + +static struct clk s5p_clk_otgphy = { + .name = "otg_phy", + .id = -1, +}; + +static struct clk *clk_src_mout_href_list[] = { + [0] = &s5p_clk_27m, + [1] = &clk_fin_hpll, +}; + +static struct clksrc_sources clk_src_mout_href = { + .sources = clk_src_mout_href_list, + .nr_sources = ARRAY_SIZE(clk_src_mout_href_list), +}; + +static struct clksrc_clk clk_mout_href = { + .clk = { + .name = "mout_href", + .id = -1, + }, + .sources = &clk_src_mout_href, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, +}; + +static struct clk *clk_src_mout_48m_list[] = { + [0] = &clk_xusbxti, + [1] = &s5p_clk_otgphy, +}; + +static struct clksrc_sources clk_src_mout_48m = { + .sources = clk_src_mout_48m_list, + .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list), +}; + +static struct clksrc_clk clk_mout_48m = { + .clk = { + .name = "mout_48m", + .id = -1, + }, + .sources = &clk_src_mout_48m, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + .id = -1, + }, + .sources = &clk_src_mpll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, +}; + + +static struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + .id = -1, + }, + .sources = &clk_src_apll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_epll = { + .clk = { + .name = "mout_epll", + .id = -1, + }, + .sources = &clk_src_epll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, +}; + +static struct clk *clk_src_mout_hpll_list[] = { + [0] = &s5p_clk_27m, +}; + +static struct clksrc_sources clk_src_mout_hpll = { + .sources = clk_src_mout_hpll_list, + .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list), +}; + +static struct clksrc_clk clk_mout_hpll = { + .clk = { + .name = "mout_hpll", + .id = -1, + }, + .sources = &clk_src_mout_hpll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, +}; + +static struct clksrc_clk clk_div_apll = { + .clk = { + .name = "div_apll", + .id = -1, + .parent = &clk_mout_apll.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, +}; + +static struct clksrc_clk clk_div_arm = { + .clk = { + .name = "div_arm", + .id = -1, + .parent = &clk_div_apll.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, +}; + +static struct clksrc_clk clk_div_d0_bus = { + .clk = { + .name = "div_d0_bus", + .id = -1, + .parent = &clk_div_arm.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, +}; + +static struct clksrc_clk clk_div_pclkd0 = { + .clk = { + .name = "div_pclkd0", + .id = -1, + .parent = &clk_div_d0_bus.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, +}; + +static struct clksrc_clk clk_div_secss = { + .clk = { + .name = "div_secss", + .id = -1, + .parent = &clk_div_d0_bus.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, +}; + +static struct clksrc_clk clk_div_apll2 = { + .clk = { + .name = "div_apll2", + .id = -1, + .parent = &clk_mout_apll.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, +}; + +static struct clk *clk_src_mout_am_list[] = { + [0] = &clk_mout_mpll.clk, + [1] = &clk_div_apll2.clk, +}; + +struct clksrc_sources clk_src_mout_am = { + .sources = clk_src_mout_am_list, + .nr_sources = ARRAY_SIZE(clk_src_mout_am_list), +}; + +static struct clksrc_clk clk_mout_am = { + .clk = { + .name = "mout_am", + .id = -1, + }, + .sources = &clk_src_mout_am, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, +}; + +static struct clksrc_clk clk_div_d1_bus = { + .clk = { + .name = "div_d1_bus", + .id = -1, + .parent = &clk_mout_am.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, +}; + +static struct clksrc_clk clk_div_mpll2 = { + .clk = { + .name = "div_mpll2", + .id = -1, + .parent = &clk_mout_am.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, +}; + +static struct clksrc_clk clk_div_mpll = { + .clk = { + .name = "div_mpll", + .id = -1, + .parent = &clk_mout_am.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, +}; + +static struct clk *clk_src_mout_onenand_list[] = { + [0] = &clk_div_d0_bus.clk, + [1] = &clk_div_d1_bus.clk, +}; + +struct clksrc_sources clk_src_mout_onenand = { + .sources = clk_src_mout_onenand_list, + .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list), +}; + +static struct clksrc_clk clk_mout_onenand = { + .clk = { + .name = "mout_onenand", + .id = -1, + }, + .sources = &clk_src_mout_onenand, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, +}; + +static struct clksrc_clk clk_div_onenand = { + .clk = { + .name = "div_onenand", + .id = -1, + .parent = &clk_mout_onenand.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, +}; + +static struct clksrc_clk clk_div_pclkd1 = { + .clk = { + .name = "div_pclkd1", + .id = -1, + .parent = &clk_div_d1_bus.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, +}; + +static struct clksrc_clk clk_div_cam = { + .clk = { + .name = "div_cam", + .id = -1, + .parent = &clk_div_mpll2.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, +}; + +static struct clksrc_clk clk_div_hdmi = { + .clk = { + .name = "div_hdmi", + .id = -1, + .parent = &clk_mout_hpll.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, +}; + +static int s5pc100_epll_enable(struct clk *clk, int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit; + + if (enable) + __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON); + else + __raw_writel(epll_con, S5P_EPLL_CON); + + return 0; +} + +static unsigned long s5pc100_epll_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static u32 epll_div[][4] = { + { 32750000, 131, 3, 4 }, + { 32768000, 131, 3, 4 }, + { 36000000, 72, 3, 3 }, + { 45000000, 90, 3, 3 }, + { 45158000, 90, 3, 3 }, + { 45158400, 90, 3, 3 }, + { 48000000, 96, 3, 3 }, + { 49125000, 131, 4, 3 }, + { 49152000, 131, 4, 3 }, + { 60000000, 120, 3, 3 }, + { 67737600, 226, 5, 3 }, + { 67738000, 226, 5, 3 }, + { 73800000, 246, 5, 3 }, + { 73728000, 246, 5, 3 }, + { 72000000, 144, 3, 3 }, + { 84000000, 168, 3, 3 }, + { 96000000, 96, 3, 2 }, + { 144000000, 144, 3, 2 }, + { 192000000, 96, 3, 1 } +}; + +static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int epll_con; + unsigned int i; + + if (clk->rate == rate) /* Return if nothing changed */ + return 0; + + epll_con = __raw_readl(S5P_EPLL_CON); + + epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK); + + for (i = 0; i < ARRAY_SIZE(epll_div); i++) { + if (epll_div[i][0] == rate) { + epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) | + (epll_div[i][2] << PLL65XX_PDIV_SHIFT) | + (epll_div[i][3] << PLL65XX_SDIV_SHIFT); + break; + } + } + + if (i == ARRAY_SIZE(epll_div)) { + printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); + return -EINVAL; + } + + __raw_writel(epll_con, S5P_EPLL_CON); + + clk->rate = rate; + + return 0; +} + +static struct clk_ops s5pc100_epll_ops = { + .get_rate = s5pc100_epll_get_rate, + .set_rate = s5pc100_epll_set_rate, +}; + +static int s5pc100_d0_0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable); +} + +static int s5pc100_d0_1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable); +} + +static int s5pc100_d0_2_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable); +} + +static int s5pc100_d1_0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable); +} + +static int s5pc100_d1_1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable); +} + +static int s5pc100_d1_2_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable); +} + +static int s5pc100_d1_3_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable); +} + +static int s5pc100_d1_4_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable); +} + +static int s5pc100_d1_5_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable); +} + +static int s5pc100_sclk0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable); +} + +static int s5pc100_sclk1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable); +} + +/* + * The following clocks will be disabled during clock initialization. It is + * recommended to keep the following clocks disabled until the driver requests + * for enabling the clock. + */ +static struct clk init_clocks_disable[] = { + { + .name = "cssys", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_0_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "secss", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_0_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "g2d", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_0_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "mdma", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_0_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "cfcon", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_0_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "nfcon", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_1_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "onenandc", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_1_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "sdm", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_2_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "seckey", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_2_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "hsmmc", + .id = 2, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "hsmmc", + .id = 1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "hsmmc", + .id = 0, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "modemif", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "otg", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "usbhost", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "pdma", + .id = 1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "pdma", + .id = 0, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "lcd", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_1_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "rotator", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_1_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "fimc", + .id = 0, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_1_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "fimc", + .id = 1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_1_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "fimc", + .id = 2, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_1_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "jpeg", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_1_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "mipi-dsim", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_1_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "mipi-csis", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_1_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "g3d", + .id = 0, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "tv", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_2_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "vp", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_2_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "mixer", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_2_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "hdmi", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_2_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "mfc", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_2_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "apc", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_3_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "iec", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_3_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "systimer", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_3_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "watchdog", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_3_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "rtc", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_3_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "i2c", + .id = 0, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "i2c", + .id = 1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "spi", + .id = 0, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "spi", + .id = 1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "spi", + .id = 2, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "irda", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "ccan", + .id = 0, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "ccan", + .id = 1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "hsitx", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 12), + }, { + .name = "hsirx", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 13), + }, { + .name = "iis", + .id = 0, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_5_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "iis", + .id = 1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_5_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "iis", + .id = 2, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_5_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "ac97", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_5_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "pcm", + .id = 0, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_5_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "pcm", + .id = 1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_5_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "spdif", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_5_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "adc", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_5_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "keyif", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_5_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "spi_48m", + .id = 0, + .parent = &clk_mout_48m.clk, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "spi_48m", + .id = 1, + .parent = &clk_mout_48m.clk, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "spi_48m", + .id = 2, + .parent = &clk_mout_48m.clk, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "mmc_48m", + .id = 0, + .parent = &clk_mout_48m.clk, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "mmc_48m", + .id = 1, + .parent = &clk_mout_48m.clk, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "mmc_48m", + .id = 2, + .parent = &clk_mout_48m.clk, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = (1 << 17), + }, +}; + +static struct clk clk_vclk54m = { + .name = "vclk_54m", + .id = -1, + .rate = 54000000, +}; + +static struct clk clk_i2scdclk0 = { + .name = "i2s_cdclk0", + .id = -1, +}; + +static struct clk clk_i2scdclk1 = { + .name = "i2s_cdclk1", + .id = -1, +}; + +static struct clk clk_i2scdclk2 = { + .name = "i2s_cdclk2", + .id = -1, +}; + +static struct clk clk_pcmcdclk0 = { + .name = "pcm_cdclk0", + .id = -1, +}; + +static struct clk clk_pcmcdclk1 = { + .name = "pcm_cdclk1", + .id = -1, +}; + +static struct clk *clk_src_group1_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_div_mpll2.clk, + [2] = &clk_fin_epll, + [3] = &clk_mout_hpll.clk, +}; + +struct clksrc_sources clk_src_group1 = { + .sources = clk_src_group1_list, + .nr_sources = ARRAY_SIZE(clk_src_group1_list), +}; + +static struct clk *clk_src_group2_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_div_mpll.clk, +}; + +struct clksrc_sources clk_src_group2 = { + .sources = clk_src_group2_list, + .nr_sources = ARRAY_SIZE(clk_src_group2_list), +}; + +static struct clk *clk_src_group3_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_div_mpll.clk, + [2] = &clk_fin_epll, + [3] = &clk_i2scdclk0, + [4] = &clk_pcmcdclk0, + [5] = &clk_mout_hpll.clk, +}; + +struct clksrc_sources clk_src_group3 = { + .sources = clk_src_group3_list, + .nr_sources = ARRAY_SIZE(clk_src_group3_list), +}; + +static struct clk *clk_src_group4_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_div_mpll.clk, + [2] = &clk_fin_epll, + [3] = &clk_i2scdclk1, + [4] = &clk_pcmcdclk1, + [5] = &clk_mout_hpll.clk, +}; + +struct clksrc_sources clk_src_group4 = { + .sources = clk_src_group4_list, + .nr_sources = ARRAY_SIZE(clk_src_group4_list), +}; + +static struct clk *clk_src_group5_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_div_mpll.clk, + [2] = &clk_fin_epll, + [3] = &clk_i2scdclk2, + [4] = &clk_mout_hpll.clk, +}; + +struct clksrc_sources clk_src_group5 = { + .sources = clk_src_group5_list, + .nr_sources = ARRAY_SIZE(clk_src_group5_list), +}; + +static struct clk *clk_src_group6_list[] = { + [0] = &s5p_clk_27m, + [1] = &clk_vclk54m, + [2] = &clk_div_hdmi.clk, +}; + +struct clksrc_sources clk_src_group6 = { + .sources = clk_src_group6_list, + .nr_sources = ARRAY_SIZE(clk_src_group6_list), +}; + +static struct clk *clk_src_group7_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_div_mpll.clk, + [2] = &clk_mout_hpll.clk, + [3] = &clk_vclk54m, +}; + +struct clksrc_sources clk_src_group7 = { + .sources = clk_src_group7_list, + .nr_sources = ARRAY_SIZE(clk_src_group7_list), +}; + +static struct clk *clk_src_mmc0_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_div_mpll.clk, + [2] = &clk_fin_epll, +}; + +struct clksrc_sources clk_src_mmc0 = { + .sources = clk_src_mmc0_list, + .nr_sources = ARRAY_SIZE(clk_src_mmc0_list), +}; + +static struct clk *clk_src_mmc12_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_div_mpll.clk, + [2] = &clk_fin_epll, + [3] = &clk_mout_hpll.clk, +}; + +struct clksrc_sources clk_src_mmc12 = { + .sources = clk_src_mmc12_list, + .nr_sources = ARRAY_SIZE(clk_src_mmc12_list), +}; + +static struct clk *clk_src_irda_usb_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_div_mpll.clk, + [2] = &clk_fin_epll, + [3] = &clk_mout_hpll.clk, +}; + +struct clksrc_sources clk_src_irda_usb = { + .sources = clk_src_irda_usb_list, + .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list), +}; + +static struct clk *clk_src_pwi_list[] = { + [0] = &clk_fin_epll, + [1] = &clk_mout_epll.clk, + [2] = &clk_div_mpll.clk, +}; + +struct clksrc_sources clk_src_pwi = { + .sources = clk_src_pwi_list, + .nr_sources = ARRAY_SIZE(clk_src_pwi_list), +}; + +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "sclk_spi", + .id = 0, + .ctrlbit = (1 << 4), + .enable = s5pc100_sclk0_ctrl, + + }, + .sources = &clk_src_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_spi", + .id = 1, + .ctrlbit = (1 << 5), + .enable = s5pc100_sclk0_ctrl, + + }, + .sources = &clk_src_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "sclk_spi", + .id = 2, + .ctrlbit = (1 << 6), + .enable = s5pc100_sclk0_ctrl, + + }, + .sources = &clk_src_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "uclk1", + .id = -1, + .ctrlbit = (1 << 3), + .enable = s5pc100_sclk0_ctrl, + + }, + .sources = &clk_src_group2, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_mixer", + .id = -1, + .ctrlbit = (1 << 6), + .enable = s5pc100_sclk0_ctrl, + + }, + .sources = &clk_src_group6, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 }, + }, { + .clk = { + .name = "sclk_audio", + .id = 0, + .ctrlbit = (1 << 8), + .enable = s5pc100_sclk1_ctrl, + + }, + .sources = &clk_src_group3, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_audio", + .id = 1, + .ctrlbit = (1 << 9), + .enable = s5pc100_sclk1_ctrl, + + }, + .sources = &clk_src_group4, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_audio", + .id = 2, + .ctrlbit = (1 << 10), + .enable = s5pc100_sclk1_ctrl, + + }, + .sources = &clk_src_group5, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_lcd", + .id = -1, + .ctrlbit = (1 << 0), + .enable = s5pc100_sclk1_ctrl, + + }, + .sources = &clk_src_group7, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 0, + .ctrlbit = (1 << 1), + .enable = s5pc100_sclk1_ctrl, + + }, + .sources = &clk_src_group7, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 1, + .ctrlbit = (1 << 2), + .enable = s5pc100_sclk1_ctrl, + + }, + .sources = &clk_src_group7, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 2, + .ctrlbit = (1 << 3), + .enable = s5pc100_sclk1_ctrl, + + }, + .sources = &clk_src_group7, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, + }, { + .clk = { + .name = "mmc_bus", + .id = 0, + .ctrlbit = (1 << 12), + .enable = s5pc100_sclk1_ctrl, + + }, + .sources = &clk_src_mmc0, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "mmc_bus", + .id = 1, + .ctrlbit = (1 << 13), + .enable = s5pc100_sclk1_ctrl, + + }, + .sources = &clk_src_mmc12, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "mmc_bus", + .id = 2, + .ctrlbit = (1 << 14), + .enable = s5pc100_sclk1_ctrl, + + }, + .sources = &clk_src_mmc12, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "sclk_irda", + .id = 2, + .ctrlbit = (1 << 10), + .enable = s5pc100_sclk0_ctrl, + + }, + .sources = &clk_src_irda_usb, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "sclk_irda", + .id = -1, + .ctrlbit = (1 << 10), + .enable = s5pc100_sclk0_ctrl, + + }, + .sources = &clk_src_mmc12, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_pwi", + .id = -1, + .ctrlbit = (1 << 1), + .enable = s5pc100_sclk0_ctrl, + + }, + .sources = &clk_src_pwi, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 }, + }, { + .clk = { + .name = "sclk_uhost", + .id = -1, + .ctrlbit = (1 << 11), + .enable = s5pc100_sclk0_ctrl, + + }, + .sources = &clk_src_irda_usb, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 }, + }, +}; + +/* Clock initialisation code */ +static struct clksrc_clk *sysclks[] = { + &clk_mout_apll, + &clk_mout_epll, + &clk_mout_mpll, + &clk_mout_hpll, + &clk_mout_href, + &clk_mout_48m, + &clk_div_apll, + &clk_div_arm, + &clk_div_d0_bus, + &clk_div_pclkd0, + &clk_div_secss, + &clk_div_apll2, + &clk_mout_am, + &clk_div_d1_bus, + &clk_div_mpll2, + &clk_div_mpll, + &clk_mout_onenand, + &clk_div_onenand, + &clk_div_pclkd1, + &clk_div_cam, + &clk_div_hdmi, +}; + +void __init_or_cpufreq s5pc100_setup_clocks(void) +{ + unsigned long xtal; + unsigned long arm; + unsigned long hclkd0; + unsigned long hclkd1; + unsigned long pclkd0; + unsigned long pclkd1; + unsigned long apll; + unsigned long mpll; + unsigned long epll; + unsigned long hpll; + unsigned int ptr; + + /* Set S5PC100 functions for clk_fout_epll */ + clk_fout_epll.enable = s5pc100_epll_enable; + clk_fout_epll.ops = &s5pc100_epll_ops; + + printk(KERN_DEBUG "%s: registering clocks\n", __func__); + + xtal = clk_get_rate(&clk_xtal); + + printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + + apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON)); + mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON)); + epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON)); + hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON)); + + printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n", + print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll)); + + clk_fout_apll.rate = apll; + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + clk_mout_hpll.clk.rate = hpll; + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_set_clksrc(&clksrcs[ptr], true); + + arm = clk_get_rate(&clk_div_arm.clk); + hclkd0 = clk_get_rate(&clk_div_d0_bus.clk); + pclkd0 = clk_get_rate(&clk_div_pclkd0.clk); + hclkd1 = clk_get_rate(&clk_div_d1_bus.clk); + pclkd1 = clk_get_rate(&clk_div_pclkd1.clk); + + printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n", + print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1)); + + clk_f.rate = arm; + clk_h.rate = hclkd1; + clk_p.rate = pclkd1; +} + +/* + * The following clocks will be enabled during clock initialization. + */ +static struct clk init_clocks[] = { + { + .name = "tzic", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_0_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "intc", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_0_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "ebi", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_1_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "intmem", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_1_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "sromc", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_1_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "dmc", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_1_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "chipid", + .id = -1, + .parent = &clk_div_d0_bus.clk, + .enable = s5pc100_d0_1_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "gpio", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_3_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "uart", + .id = 0, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "uart", + .id = 1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "uart", + .id = 2, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "uart", + .id = 3, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_4_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "timers", + .id = -1, + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_3_ctrl, + .ctrlbit = (1 << 6), + }, +}; + +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_i2scdclk0, + &clk_i2scdclk1, + &clk_i2scdclk2, + &clk_pcmcdclk0, + &clk_pcmcdclk1, +}; + +void __init s5pc100_register_clocks(void) +{ + struct clk *clkp; + int ret; + int ptr; + + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); + + for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) + s3c_register_clksrc(sysclks[ptr], 1); + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + + clkp = init_clocks_disable; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { + + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + (clkp->enable)(clkp, 0); + } + + s3c_pwmclk_init(); +} diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c index 1ffc57ac293..c8e8336a3a1 100644 --- a/arch/arm/plat-s5pc1xx/gpiolib.c +++ b/arch/arm/mach-s5pc100/gpiolib.c @@ -17,11 +17,11 @@ #include <linux/gpio.h> #include <mach/map.h> +#include <mach/regs-gpio.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> #include <plat/gpio-cfg-helpers.h> -#include <plat/regs-gpio.h> /* S5PC100 GPIO bank summary: * @@ -61,74 +61,7 @@ * L3 8 4Bit None */ -#define OFF_GPCON (0x00) -#define OFF_GPDAT (0x04) - -#define con_4bit_shift(__off) ((__off) * 4) - -#if 1 -#define gpio_dbg(x...) do { } while (0) -#else -#define gpio_dbg(x...) printk(KERN_DEBUG x) -#endif - -/* The s5pc1xx_gpiolib routines are to control the gpio banks where - * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the - * following example: - * - * base + 0x00: Control register, 4 bits per gpio - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x04: Data register, 1 bit per gpio - * bit n: data bit n - * - * Note, since the data register is one bit per gpio and is at base + 0x4 - * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of - * the output. - */ - -static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - - con = __raw_readl(base + OFF_GPCON); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, base + OFF_GPCON); - - gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); - - return 0; -} - -static int s5pc1xx_gpiolib_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - unsigned long dat; - - con = __raw_readl(base + OFF_GPCON); - con &= ~(0xf << con_4bit_shift(offset)); - con |= 0x1 << con_4bit_shift(offset); - - dat = __raw_readl(base + OFF_GPDAT); - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(dat, base + OFF_GPDAT); - __raw_writel(con, base + OFF_GPCON); - __raw_writel(dat, base + OFF_GPDAT); - - gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); - - return 0; -} - +#if 0 static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) { return S3C_IRQ_GPIO(chip->base + offset); @@ -152,7 +85,7 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) return IRQ_EINT(24 + offset); return -EINVAL; } - +#endif static struct s3c_gpio_cfg gpio_cfg = { .set_config = s3c_gpio_setcfg_s3c64xx_4bit, .set_pull = s3c_gpio_setpull_updown, @@ -452,12 +385,9 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { extern struct irq_chip s5pc1xx_gpioint; extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); -static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip) +static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) { - chip->chip.direction_input = s5pc1xx_gpiolib_input; - chip->chip.direction_output = s5pc1xx_gpiolib_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); - +#if 0 /* Interrupt */ if (chip->config == &gpio_cfg) { int i, irq; @@ -473,31 +403,26 @@ static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip) } } else if (chip->config == &gpio_cfg_eint) chip->chip.to_irq = s5pc1xx_gpiolib_to_eint; -} - -static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips, - int nr_chips, - void (*fn)(struct s3c_gpio_chip *)) -{ - for (; nr_chips > 0; nr_chips--, chips++) { - if (fn) - (fn)(chips); - s3c_gpiolib_add(chips); - } +#endif } static __init int s5pc1xx_gpiolib_init(void) { - struct s3c_gpio_chip *chips; + struct s3c_gpio_chip *chip; int nr_chips; - chips = s5pc100_gpio_chips; - nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); + chip = s5pc100_gpio_chips; + nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); + + for (; nr_chips > 0; nr_chips--, chip++) + s5pc100_gpiolib_link(chip); - s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link); + samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, + ARRAY_SIZE(s5pc100_gpio_chips)); +#if 0 /* Interrupt */ set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler); - +#endif return 0; } core_initcall(s5pc1xx_gpiolib_init); diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h index 2c4cbe8ee6b..29a8a12d9b4 100644 --- a/arch/arm/mach-s5pc100/include/mach/gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/gpio.h @@ -12,6 +12,9 @@ * published by the Free Software Foundation. */ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H __FILE__ + #define gpio_get_value __gpio_get_value #define gpio_set_value __gpio_set_value #define gpio_cansleep __gpio_cansleep @@ -52,11 +55,6 @@ #define S5PC100_GPIO_L2_NR (8) #define S5PC100_GPIO_L3_NR (8) #define S5PC100_GPIO_L4_NR (8) -#define S5PC100_GPIO_MP00_NR (8) -#define S5PC100_GPIO_MP01_NR (8) -#define S5PC100_GPIO_MP02_NR (8) -#define S5PC100_GPIO_MP03_NR (8) -#define S5PC100_GPIO_MP04_NR (5) /* GPIO bank numbes */ @@ -65,50 +63,45 @@ * change from one gpio bank to another can be caught. */ -#define S5PC1XX_GPIO_NEXT(__gpio) \ +#define S5PC100_GPIO_NEXT(__gpio) \ ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) -enum s3c_gpio_number { +enum s5p_gpio_number { S5PC100_GPIO_A0_START = 0, - S5PC100_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0), - S5PC100_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1), - S5PC100_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B), - S5PC100_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C), - S5PC100_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D), - S5PC100_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0), - S5PC100_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1), - S5PC100_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0), - S5PC100_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1), - S5PC100_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2), - S5PC100_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3), - S5PC100_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0), - S5PC100_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1), - S5PC100_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2), - S5PC100_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3), - S5PC100_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0), - S5PC100_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1), - S5PC100_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2), - S5PC100_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3), - S5PC100_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I), - S5PC100_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0), - S5PC100_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1), - S5PC100_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2), - S5PC100_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3), - S5PC100_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4), - S5PC100_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0), - S5PC100_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1), - S5PC100_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2), - S5PC100_GPIO_L0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3), - S5PC100_GPIO_L1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0), - S5PC100_GPIO_L2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1), - S5PC100_GPIO_L3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2), - S5PC100_GPIO_L4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3), - S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4), - S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00), - S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01), - S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02), - S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03), - S5PC100_GPIO_END = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04), + S5PC100_GPIO_A1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A0), + S5PC100_GPIO_B_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A1), + S5PC100_GPIO_C_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_B), + S5PC100_GPIO_D_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_C), + S5PC100_GPIO_E0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_D), + S5PC100_GPIO_E1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E0), + S5PC100_GPIO_F0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E1), + S5PC100_GPIO_F1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F0), + S5PC100_GPIO_F2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F1), + S5PC100_GPIO_F3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F2), + S5PC100_GPIO_G0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F3), + S5PC100_GPIO_G1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G0), + S5PC100_GPIO_G2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G1), + S5PC100_GPIO_G3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G2), + S5PC100_GPIO_H0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G3), + S5PC100_GPIO_H1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H0), + S5PC100_GPIO_H2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H1), + S5PC100_GPIO_H3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H2), + S5PC100_GPIO_I_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H3), + S5PC100_GPIO_J0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_I), + S5PC100_GPIO_J1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J0), + S5PC100_GPIO_J2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J1), + S5PC100_GPIO_J3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J2), + S5PC100_GPIO_J4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J3), + S5PC100_GPIO_K0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J4), + S5PC100_GPIO_K1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K0), + S5PC100_GPIO_K2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K1), + S5PC100_GPIO_K3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K2), + S5PC100_GPIO_L0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K3), + S5PC100_GPIO_L1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L0), + S5PC100_GPIO_L2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L1), + S5PC100_GPIO_L3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L2), + S5PC100_GPIO_L4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L3), + S5PC100_GPIO_END = S5PC100_GPIO_NEXT(S5PC100_GPIO_L4), }; /* S5PC100 GPIO number definitions. */ @@ -146,17 +139,13 @@ enum s3c_gpio_number { #define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr)) #define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr)) #define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr)) -#define S5PC100_MP00(_nr) (S5PC100_GPIO_MP00_START + (_nr)) -#define S5PC100_MP01(_nr) (S5PC100_GPIO_MP01_START + (_nr)) -#define S5PC100_MP02(_nr) (S5PC100_GPIO_MP02_START + (_nr)) -#define S5PC100_MP03(_nr) (S5PC100_GPIO_MP03_START + (_nr)) -#define S5PC100_MP04(_nr) (S5PC100_GPIO_MP04_START + (_nr)) -#define S5PC100_MP05(_nr) (S5PC100_GPIO_MP05_START + (_nr)) -/* It used the end of the S5PC1XX gpios */ +/* It used the end of the S5PC100 gpios */ #define S3C_GPIO_END S5PC100_GPIO_END /* define the number of gpios we need to the one after the MP04() range */ #define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) #include <asm-generic/gpio.h> + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h new file mode 100644 index 00000000000..f2283bdc941 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h @@ -0,0 +1,71 @@ +/* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PC100 - Clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_CLOCK_H +#define __ASM_ARCH_REGS_CLOCK_H __FILE__ + +#include <mach/map.h> + +#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) + +#define S5P_APLL_LOCK S5P_CLKREG(0x00) +#define S5P_MPLL_LOCK S5P_CLKREG(0x04) +#define S5P_EPLL_LOCK S5P_CLKREG(0x08) +#define S5P_HPLL_LOCK S5P_CLKREG(0x0C) + +#define S5P_APLL_CON S5P_CLKREG(0x100) +#define S5P_MPLL_CON S5P_CLKREG(0x104) +#define S5P_EPLL_CON S5P_CLKREG(0x108) +#define S5P_HPLL_CON S5P_CLKREG(0x10C) + +#define S5P_CLK_SRC0 S5P_CLKREG(0x200) +#define S5P_CLK_SRC1 S5P_CLKREG(0x204) +#define S5P_CLK_SRC2 S5P_CLKREG(0x208) +#define S5P_CLK_SRC3 S5P_CLKREG(0x20C) + +#define S5P_CLK_DIV0 S5P_CLKREG(0x300) +#define S5P_CLK_DIV1 S5P_CLKREG(0x304) +#define S5P_CLK_DIV2 S5P_CLKREG(0x308) +#define S5P_CLK_DIV3 S5P_CLKREG(0x30C) +#define S5P_CLK_DIV4 S5P_CLKREG(0x310) + +#define S5P_CLK_OUT S5P_CLKREG(0x400) + +#define S5P_CLKGATE_D00 S5P_CLKREG(0x500) +#define S5P_CLKGATE_D01 S5P_CLKREG(0x504) +#define S5P_CLKGATE_D02 S5P_CLKREG(0x508) + +#define S5P_CLKGATE_D10 S5P_CLKREG(0x520) +#define S5P_CLKGATE_D11 S5P_CLKREG(0x524) +#define S5P_CLKGATE_D12 S5P_CLKREG(0x528) +#define S5P_CLKGATE_D13 S5P_CLKREG(0x52C) +#define S5P_CLKGATE_D14 S5P_CLKREG(0x530) +#define S5P_CLKGATE_D15 S5P_CLKREG(0x534) + +#define S5P_CLKGATE_D20 S5P_CLKREG(0x540) + +#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x560) +#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x564) + +/* CLKDIV0 */ +#define S5P_CLKDIV0_D0_MASK (0x7<<8) +#define S5P_CLKDIV0_D0_SHIFT (8) +#define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12) +#define S5P_CLKDIV0_PCLKD0_SHIFT (12) + +/* CLKDIV1 */ +#define S5P_CLKDIV1_D1_MASK (0x7<<12) +#define S5P_CLKDIV1_D1_SHIFT (12) +#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) +#define S5P_CLKDIV1_PCLKD1_SHIFT (16) + +#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h index 43c7bc8bf78..68666913354 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h @@ -3,11 +3,11 @@ * Copyright 2009 Samsung Electronics Co. * Byungho Min <bhmin@samsung.com> * - * S5PC1XX - GPIO register definitions + * S5PC100 - GPIO register definitions */ -#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H -#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__ +#ifndef __ASM_MACH_S5PC100_REGS_GPIO_H +#define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__ #include <mach/map.h> @@ -66,5 +66,5 @@ #define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) #define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) -#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */ +#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index ae3c52cd0eb..bfe67db34f0 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c @@ -35,7 +35,6 @@ #include <plat/regs-serial.h> #include <plat/gpio-cfg.h> -#include <plat/regs-gpio.h> #include <plat/clock.h> #include <plat/devs.h> diff --git a/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c index 1a63768a9a2..6eba6cb8e2f 100644 --- a/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c +++ b/arch/arm/mach-s5pc100/setup-fb-24bpp.c @@ -1,9 +1,9 @@ /* - * linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c + * linux/arch/arm/mach-s5pc100/setup-fb-24bpp.c * * Copyright 2009 Samsung Electronics * - * Base S5PC1XX setup information for 24bpp LCD framebuffer + * Base S5PC100 setup information for 24bpp LCD framebuffer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -19,7 +19,6 @@ #include <mach/map.h> #include <plat/fb.h> #include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-s5pc1xx.h> #define DISR_OFFSET 0x7008 diff --git a/arch/arm/plat-s5pc1xx/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c index 5e4a7c3a231..dd3174e6ecc 100644 --- a/arch/arm/plat-s5pc1xx/setup-i2c0.c +++ b/arch/arm/mach-s5pc100/setup-i2c0.c @@ -1,9 +1,9 @@ -/* linux/arch/arm/plat-s5pc1xx/setup-i2c0.c +/* linux/arch/arm/mach-s5pc100/setup-i2c0.c * * Copyright 2009 Samsung Electronics Co. * Byungho Min <bhmin@samsung.com> * - * Base S5PC1XX I2C bus 0 gpio configuration + * Base S5PC100 I2C bus 0 gpio configuration * * Based on plat-s3c64xx/setup-i2c0.c * diff --git a/arch/arm/plat-s5pc1xx/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c index a0a8b4ae6ad..d1fec26b69e 100644 --- a/arch/arm/plat-s5pc1xx/setup-i2c1.c +++ b/arch/arm/mach-s5pc100/setup-i2c1.c @@ -1,9 +1,9 @@ -/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c +/* linux/arch/arm/mach-s5pc100/setup-i2c1.c * * Copyright 2009 Samsung Electronics Co. * Byungho Min <bhmin@samsung.com> * - * Base S5PC1XX I2C bus 1 gpio configuration + * Base S5PC100 I2C bus 1 gpio configuration * * Based on plat-s3c64xx/setup-i2c1.c * diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index af33a1a89b7..7601c28e240 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -12,6 +12,7 @@ if ARCH_S5PV210 config CPU_S5PV210 bool select PLAT_S5P + select S3C_PL330_DMA help Enable S5PV210 CPU support diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 8ebf51c52a0..99827813d29 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -12,9 +12,14 @@ obj- := # Core support for S5PV210 system -obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o +obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o gpiolib.o +obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o # machine support obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o + +# device support + +obj-y += dev-audio.o diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index ccccae26235..154bca4abc0 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -31,6 +31,128 @@ #include <plat/clock-clksrc.h> #include <plat/s5pv210.h> +static struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + .id = -1, + }, + .sources = &clk_src_apll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_epll = { + .clk = { + .name = "mout_epll", + .id = -1, + }, + .sources = &clk_src_epll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + .id = -1, + }, + .sources = &clk_src_mpll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, +}; + +static struct clk *clkset_armclk_list[] = { + [0] = &clk_mout_apll.clk, + [1] = &clk_mout_mpll.clk, +}; + +static struct clksrc_sources clkset_armclk = { + .sources = clkset_armclk_list, + .nr_sources = ARRAY_SIZE(clkset_armclk_list), +}; + +static struct clksrc_clk clk_armclk = { + .clk = { + .name = "armclk", + .id = -1, + }, + .sources = &clkset_armclk, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk clk_hclk_msys = { + .clk = { + .name = "hclk_msys", + .id = -1, + .parent = &clk_armclk.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, +}; + +static struct clksrc_clk clk_pclk_msys = { + .clk = { + .name = "pclk_msys", + .id = -1, + .parent = &clk_hclk_msys.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, +}; + +static struct clksrc_clk clk_sclk_a2m = { + .clk = { + .name = "sclk_a2m", + .id = -1, + .parent = &clk_mout_apll.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, +}; + +static struct clk *clkset_hclk_sys_list[] = { + [0] = &clk_mout_mpll.clk, + [1] = &clk_sclk_a2m.clk, +}; + +static struct clksrc_sources clkset_hclk_sys = { + .sources = clkset_hclk_sys_list, + .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list), +}; + +static struct clksrc_clk clk_hclk_dsys = { + .clk = { + .name = "hclk_dsys", + .id = -1, + }, + .sources = &clkset_hclk_sys, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk clk_pclk_dsys = { + .clk = { + .name = "pclk_dsys", + .id = -1, + .parent = &clk_hclk_dsys.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, +}; + +static struct clksrc_clk clk_hclk_psys = { + .clk = { + .name = "hclk_psys", + .id = -1, + }, + .sources = &clkset_hclk_sys, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, +}; + +static struct clksrc_clk clk_pclk_psys = { + .clk = { + .name = "pclk_psys", + .id = -1, + .parent = &clk_hclk_psys.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, +}; + static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); @@ -51,176 +173,226 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); } -static struct clk clk_h200 = { - .name = "hclk200", +static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable); +} + +static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); +} + +static struct clk clk_sclk_hdmi27m = { + .name = "sclk_hdmi27m", .id = -1, + .rate = 27000000, }; -static struct clk clk_h100 = { - .name = "hclk100", +static struct clk clk_sclk_hdmiphy = { + .name = "sclk_hdmiphy", .id = -1, }; -static struct clk clk_h166 = { - .name = "hclk166", +static struct clk clk_sclk_usbphy0 = { + .name = "sclk_usbphy0", .id = -1, }; -static struct clk clk_h133 = { - .name = "hclk133", +static struct clk clk_sclk_usbphy1 = { + .name = "sclk_usbphy1", .id = -1, }; -static struct clk clk_p100 = { - .name = "pclk100", +static struct clk clk_pcmcdclk0 = { + .name = "pcmcdclk", .id = -1, }; -static struct clk clk_p83 = { - .name = "pclk83", +static struct clk clk_pcmcdclk1 = { + .name = "pcmcdclk", .id = -1, }; -static struct clk clk_p66 = { - .name = "pclk66", +static struct clk clk_pcmcdclk2 = { + .name = "pcmcdclk", .id = -1, }; -static struct clk *sys_clks[] = { - &clk_h200, - &clk_h100, - &clk_h166, - &clk_h133, - &clk_p100, - &clk_p83, - &clk_p66 +static struct clk *clkset_vpllsrc_list[] = { + [0] = &clk_fin_vpll, + [1] = &clk_sclk_hdmi27m, +}; + +static struct clksrc_sources clkset_vpllsrc = { + .sources = clkset_vpllsrc_list, + .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), +}; + +static struct clksrc_clk clk_vpllsrc = { + .clk = { + .name = "vpll_src", + .id = -1, + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 7), + }, + .sources = &clkset_vpllsrc, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 }, +}; + +static struct clk *clkset_sclk_vpll_list[] = { + [0] = &clk_vpllsrc.clk, + [1] = &clk_fout_vpll, +}; + +static struct clksrc_sources clkset_sclk_vpll = { + .sources = clkset_sclk_vpll_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), +}; + +static struct clksrc_clk clk_sclk_vpll = { + .clk = { + .name = "sclk_vpll", + .id = -1, + }, + .sources = &clkset_sclk_vpll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, +}; + +static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 2; +} + +static struct clk_ops clk_hclk_imem_ops = { + .get_rate = s5pv210_clk_imem_get_rate, }; static struct clk init_clocks_disable[] = { { .name = "rot", .id = -1, - .parent = &clk_h166, + .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1<<29), }, { .name = "otg", .id = -1, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<16), }, { .name = "usb-host", .id = -1, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<17), }, { .name = "lcd", .id = -1, - .parent = &clk_h166, + .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<0), }, { .name = "cfcon", .id = 0, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<25), }, { .name = "hsmmc", .id = 0, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<16), }, { .name = "hsmmc", .id = 1, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<17), }, { .name = "hsmmc", .id = 2, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<18), }, { .name = "hsmmc", .id = 3, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<19), }, { .name = "systimer", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<16), }, { .name = "watchdog", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<22), }, { .name = "rtc", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<15), }, { .name = "i2c", .id = 0, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<7), }, { .name = "i2c", .id = 1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<8), }, { .name = "i2c", .id = 2, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<9), }, { .name = "spi", .id = 0, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<12), }, { .name = "spi", .id = 1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<13), }, { .name = "spi", .id = 2, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<14), }, { .name = "timers", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<23), }, { .name = "adc", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<24), }, { .name = "keypad", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<21), }, { @@ -246,106 +418,537 @@ static struct clk init_clocks_disable[] = { static struct clk init_clocks[] = { { + .name = "hclk_imem", + .id = -1, + .parent = &clk_hclk_msys.clk, + .ctrlbit = (1 << 5), + .enable = s5pv210_clk_ip0_ctrl, + .ops = &clk_hclk_imem_ops, + }, { .name = "uart", .id = 0, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<7), }, { .name = "uart", .id = 1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<8), }, { .name = "uart", .id = 2, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<9), }, { .name = "uart", .id = 3, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<10), }, }; -static struct clksrc_clk clk_mout_apll = { - .clk = { - .name = "mout_apll", +static struct clk *clkset_uart_list[] = { + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, +}; + +static struct clksrc_sources clkset_uart = { + .sources = clkset_uart_list, + .nr_sources = ARRAY_SIZE(clkset_uart_list), +}; + +static struct clk *clkset_group1_list[] = { + [0] = &clk_sclk_a2m.clk, + [1] = &clk_mout_mpll.clk, + [2] = &clk_mout_epll.clk, + [3] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_group1 = { + .sources = clkset_group1_list, + .nr_sources = ARRAY_SIZE(clkset_group1_list), +}; + +static struct clk *clkset_sclk_onenand_list[] = { + [0] = &clk_hclk_psys.clk, + [1] = &clk_hclk_dsys.clk, +}; + +static struct clksrc_sources clkset_sclk_onenand = { + .sources = clkset_sclk_onenand_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list), +}; + +static struct clk *clkset_sclk_dac_list[] = { + [0] = &clk_sclk_vpll.clk, + [1] = &clk_sclk_hdmiphy, +}; + +static struct clksrc_sources clkset_sclk_dac = { + .sources = clkset_sclk_dac_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list), +}; + +static struct clksrc_clk clk_sclk_dac = { + .clk = { + .name = "sclk_dac", .id = -1, + .ctrlbit = (1 << 10), + .enable = s5pv210_clk_ip1_ctrl, }, - .sources = &clk_src_apll, - .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, + .sources = &clkset_sclk_dac, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 }, }; -static struct clksrc_clk clk_mout_epll = { - .clk = { - .name = "mout_epll", +static struct clksrc_clk clk_sclk_pixel = { + .clk = { + .name = "sclk_pixel", .id = -1, + .parent = &clk_sclk_vpll.clk, }, - .sources = &clk_src_epll, - .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, }; -static struct clksrc_clk clk_mout_mpll = { - .clk = { - .name = "mout_mpll", +static struct clk *clkset_sclk_hdmi_list[] = { + [0] = &clk_sclk_pixel.clk, + [1] = &clk_sclk_hdmiphy, +}; + +static struct clksrc_sources clkset_sclk_hdmi = { + .sources = clkset_sclk_hdmi_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list), +}; + +static struct clksrc_clk clk_sclk_hdmi = { + .clk = { + .name = "sclk_hdmi", .id = -1, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 11), }, - .sources = &clk_src_mpll, - .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, + .sources = &clkset_sclk_hdmi, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, }; -static struct clk *clkset_uart_list[] = { +static struct clk *clkset_sclk_mixer_list[] = { + [0] = &clk_sclk_dac.clk, + [1] = &clk_sclk_hdmi.clk, +}; + +static struct clksrc_sources clkset_sclk_mixer = { + .sources = clkset_sclk_mixer_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), +}; + +static struct clk *clkset_sclk_audio0_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &clk_pcmcdclk0, + [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_usbphy1, + [5] = &clk_sclk_hdmiphy, [6] = &clk_mout_mpll.clk, [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, }; -static struct clksrc_sources clkset_uart = { - .sources = clkset_uart_list, - .nr_sources = ARRAY_SIZE(clkset_uart_list), +static struct clksrc_sources clkset_sclk_audio0 = { + .sources = clkset_sclk_audio0_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list), +}; + +static struct clksrc_clk clk_sclk_audio0 = { + .clk = { + .name = "sclk_audio", + .id = 0, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &clkset_sclk_audio0, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 }, +}; + +static struct clk *clkset_sclk_audio1_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &clk_pcmcdclk1, + [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_usbphy1, + [5] = &clk_sclk_hdmiphy, + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_sclk_audio1 = { + .sources = clkset_sclk_audio1_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list), +}; + +static struct clksrc_clk clk_sclk_audio1 = { + .clk = { + .name = "sclk_audio", + .id = 1, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 5), + }, + .sources = &clkset_sclk_audio1, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 }, +}; + +static struct clk *clkset_sclk_audio2_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &clk_pcmcdclk0, + [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_usbphy1, + [5] = &clk_sclk_hdmiphy, + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_sclk_audio2 = { + .sources = clkset_sclk_audio2_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list), +}; + +static struct clksrc_clk clk_sclk_audio2 = { + .clk = { + .name = "sclk_audio", + .id = 2, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 6), + }, + .sources = &clkset_sclk_audio2, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 }, +}; + +static struct clk *clkset_sclk_spdif_list[] = { + [0] = &clk_sclk_audio0.clk, + [1] = &clk_sclk_audio1.clk, + [2] = &clk_sclk_audio2.clk, +}; + +static struct clksrc_sources clkset_sclk_spdif = { + .sources = clkset_sclk_spdif_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), +}; + +static struct clk *clkset_group2_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &clk_xusbxti, + [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_usbphy1, + [5] = &clk_sclk_hdmiphy, + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_group2 = { + .sources = clkset_group2_list, + .nr_sources = ARRAY_SIZE(clkset_group2_list), }; static struct clksrc_clk clksrcs[] = { { .clk = { - .name = "uclk1", + .name = "sclk_dmc", .id = -1, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, + }, { + .clk = { + .name = "sclk_onenand", + .id = -1, + }, + .sources = &clkset_sclk_onenand, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, + }, { + .clk = { + .name = "uclk1", + .id = 0, .ctrlbit = (1<<17), .enable = s5pv210_clk_ip3_ctrl, }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, - } + }, { + .clk = { + .name = "uclk1", + .id = 1, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 18), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "uclk1", + .id = 2, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 19), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, + }, { + .clk = { + .name = "uclk1", + .id = 3, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 20), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, + }, { + .clk = { + .name = "sclk_mixer", + .id = -1, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 9), + }, + .sources = &clkset_sclk_mixer, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, + }, { + .clk = { + .name = "sclk_spdif", + .id = -1, + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 27), + }, + .sources = &clkset_sclk_spdif, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 0, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 1, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 25), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 2, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 26), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam", + .id = 0, + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam", + .id = 1, + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimd", + .id = -1, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 0, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 1, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 17), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 2, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 18), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 3, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 19), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_mfc", + .id = -1, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_g2d", + .id = -1, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "sclk_g3d", + .id = -1, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_csis", + .id = -1, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 31), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, + }, { + .clk = { + .name = "sclk_spi", + .id = 0, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_spi", + .id = 1, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 13), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_pwi", + .id = -1, + .enable = &s5pv210_clk_ip4_ctrl, + .ctrlbit = (1 << 2), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 }, + }, { + .clk = { + .name = "sclk_pwm", + .id = -1, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 23), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 }, + }, }; /* Clock initialisation code */ -static struct clksrc_clk *init_parents[] = { +static struct clksrc_clk *sysclks[] = { &clk_mout_apll, &clk_mout_epll, &clk_mout_mpll, + &clk_armclk, + &clk_hclk_msys, + &clk_sclk_a2m, + &clk_hclk_dsys, + &clk_hclk_psys, + &clk_pclk_msys, + &clk_pclk_dsys, + &clk_pclk_psys, + &clk_vpllsrc, + &clk_sclk_vpll, + &clk_sclk_dac, + &clk_sclk_pixel, + &clk_sclk_hdmi, }; -#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) - void __init_or_cpufreq s5pv210_setup_clocks(void) { struct clk *xtal_clk; unsigned long xtal; + unsigned long vpllsrc; unsigned long armclk; - unsigned long hclk200; - unsigned long hclk166; - unsigned long hclk133; - unsigned long pclk100; - unsigned long pclk83; - unsigned long pclk66; + unsigned long hclk_msys; + unsigned long hclk_dsys; + unsigned long hclk_psys; + unsigned long pclk_msys; + unsigned long pclk_dsys; + unsigned long pclk_psys; unsigned long apll; unsigned long mpll; unsigned long epll; + unsigned long vpll; unsigned int ptr; u32 clkdiv0, clkdiv1; @@ -368,59 +971,46 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); - - printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld", - apll, mpll, epll); - - armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL); - if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK) - hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200); - else - hclk200 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200); - - if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) { - hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M); - hclk166 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166); - } else - hclk166 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166); - - if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) { - hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M); - hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133); - } else - hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133); - - pclk100 = hclk200 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100); - pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83); - pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66); - - printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \ - HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", - armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66); + vpllsrc = clk_get_rate(&clk_vpllsrc.clk); + vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); clk_fout_apll.rate = apll; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; + clk_fout_vpll.rate = vpll; - clk_f.rate = armclk; - clk_h.rate = hclk133; - clk_p.rate = pclk66; - clk_p66.rate = pclk66; - clk_p83.rate = pclk83; - clk_h133.rate = hclk133; - clk_h166.rate = hclk166; - clk_h200.rate = hclk200; + printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", + apll, mpll, epll, vpll); + + armclk = clk_get_rate(&clk_armclk.clk); + hclk_msys = clk_get_rate(&clk_hclk_msys.clk); + hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk); + hclk_psys = clk_get_rate(&clk_hclk_psys.clk); + pclk_msys = clk_get_rate(&clk_pclk_msys.clk); + pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk); + pclk_psys = clk_get_rate(&clk_pclk_psys.clk); + + printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n" + "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", + armclk, hclk_msys, hclk_dsys, hclk_psys, + pclk_msys, pclk_dsys, pclk_psys); - for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s3c_set_clksrc(init_parents[ptr], true); + clk_f.rate = armclk; + clk_h.rate = hclk_psys; + clk_p.rate = pclk_psys; for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); } static struct clk *clks[] __initdata = { - &clk_mout_epll.clk, - &clk_mout_mpll.clk, + &clk_sclk_hdmi27m, + &clk_sclk_hdmiphy, + &clk_sclk_usbphy0, + &clk_sclk_usbphy1, + &clk_pcmcdclk0, + &clk_pcmcdclk1, + &clk_pcmcdclk2, }; void __init s5pv210_register_clocks(void) @@ -433,13 +1023,12 @@ void __init s5pv210_register_clocks(void) if (ret > 0) printk(KERN_ERR "Failed to register %u clocks\n", ret); + for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) + s3c_register_clksrc(sysclks[ptr], 1); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks)); - if (ret > 0) - printk(KERN_ERR "Failed to register system clocks\n"); - clkp = init_clocks_disable; for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { ret = s3c24xx_register_clock(clkp); diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 0e0f8fde2aa..2b776eb5d15 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -100,7 +100,7 @@ void __init s5pv210_init_irq(void) s5p_init_irq(vic, ARRAY_SIZE(vic)); } -static struct sysdev_class s5pv210_sysclass = { +struct sysdev_class s5pv210_sysclass = { .name = "s5pv210-core", }; diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c new file mode 100644 index 00000000000..6e215330a1b --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-audio.c @@ -0,0 +1,327 @@ +/* linux/arch/arm/mach-s5pv210/dev-audio.c + * + * Copyright (c) 2010 Samsung Electronics Co. Ltd + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <plat/gpio-cfg.h> +#include <plat/audio.h> + +#include <mach/gpio.h> +#include <mach/map.h> +#include <mach/dma.h> +#include <mach/irqs.h> + +static int s5pv210_cfg_i2s(struct platform_device *pdev) +{ + /* configure GPIO for i2s port */ + switch (pdev->id) { + case 1: + s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(2)); + break; + + case 2: + s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(4)); + break; + + case -1: + s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(5), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(6), S3C_GPIO_SFN(2)); + break; + + default: + printk(KERN_ERR "Invalid Device %d\n", pdev->id); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_i2s_pdata = { + .cfg_gpio = s5pv210_cfg_i2s, +}; + +static struct resource s5pv210_iis0_resource[] = { + [0] = { + .start = S5PV210_PA_IIS0, + .end = S5PV210_PA_IIS0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S0_TX, + .end = DMACH_I2S0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S0_RX, + .end = DMACH_I2S0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_iis0 = { + .name = "s3c64xx-iis-v4", + .id = -1, + .num_resources = ARRAY_SIZE(s5pv210_iis0_resource), + .resource = s5pv210_iis0_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +static struct resource s5pv210_iis1_resource[] = { + [0] = { + .start = S5PV210_PA_IIS1, + .end = S5PV210_PA_IIS1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S1_TX, + .end = DMACH_I2S1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S1_RX, + .end = DMACH_I2S1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_iis1 = { + .name = "s3c64xx-iis", + .id = 1, + .num_resources = ARRAY_SIZE(s5pv210_iis1_resource), + .resource = s5pv210_iis1_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +static struct resource s5pv210_iis2_resource[] = { + [0] = { + .start = S5PV210_PA_IIS2, + .end = S5PV210_PA_IIS2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S2_TX, + .end = DMACH_I2S2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S2_RX, + .end = DMACH_I2S2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_iis2 = { + .name = "s3c64xx-iis", + .id = 2, + .num_resources = ARRAY_SIZE(s5pv210_iis2_resource), + .resource = s5pv210_iis2_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +/* PCM Controller platform_devices */ + +static int s5pv210_pcm_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(3)); + break; + case 1: + s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(3)); + break; + case 2: + s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(2)); + break; + default: + printk(KERN_DEBUG "Invalid PCM Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_pcm_pdata = { + .cfg_gpio = s5pv210_pcm_cfg_gpio, +}; + +static struct resource s5pv210_pcm0_resource[] = { + [0] = { + .start = S5PV210_PA_PCM0, + .end = S5PV210_PA_PCM0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM0_TX, + .end = DMACH_PCM0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM0_RX, + .end = DMACH_PCM0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_pcm0 = { + .name = "samsung-pcm", + .id = 0, + .num_resources = ARRAY_SIZE(s5pv210_pcm0_resource), + .resource = s5pv210_pcm0_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +static struct resource s5pv210_pcm1_resource[] = { + [0] = { + .start = S5PV210_PA_PCM1, + .end = S5PV210_PA_PCM1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM1_TX, + .end = DMACH_PCM1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM1_RX, + .end = DMACH_PCM1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_pcm1 = { + .name = "samsung-pcm", + .id = 1, + .num_resources = ARRAY_SIZE(s5pv210_pcm1_resource), + .resource = s5pv210_pcm1_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +static struct resource s5pv210_pcm2_resource[] = { + [0] = { + .start = S5PV210_PA_PCM2, + .end = S5PV210_PA_PCM2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM2_TX, + .end = DMACH_PCM2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM2_RX, + .end = DMACH_PCM2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_pcm2 = { + .name = "samsung-pcm", + .id = 2, + .num_resources = ARRAY_SIZE(s5pv210_pcm2_resource), + .resource = s5pv210_pcm2_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +/* AC97 Controller platform devices */ + +static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev) +{ + s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(4)); + + return 0; +} + +static struct resource s5pv210_ac97_resource[] = { + [0] = { + .start = S5PV210_PA_AC97, + .end = S5PV210_PA_AC97 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_AC97_PCMOUT, + .end = DMACH_AC97_PCMOUT, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_AC97_PCMIN, + .end = DMACH_AC97_PCMIN, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DMACH_AC97_MICIN, + .end = DMACH_AC97_MICIN, + .flags = IORESOURCE_DMA, + }, + [4] = { + .start = IRQ_AC97, + .end = IRQ_AC97, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_audio_pdata s3c_ac97_pdata = { + .cfg_gpio = s5pv210_ac97_cfg_gpio, +}; + +static u64 s5pv210_ac97_dmamask = DMA_BIT_MASK(32); + +struct platform_device s5pv210_device_ac97 = { + .name = "s3c-ac97", + .id = -1, + .num_resources = ARRAY_SIZE(s5pv210_ac97_resource), + .resource = s5pv210_ac97_resource, + .dev = { + .platform_data = &s3c_ac97_pdata, + .dma_mask = &s5pv210_ac97_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c new file mode 100644 index 00000000000..778ad5fe231 --- /dev/null +++ b/arch/arm/mach-s5pv210/dma.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <plat/devs.h> +#include <plat/irqs.h> + +#include <mach/map.h> +#include <mach/irqs.h> + +#include <plat/s3c-pl330-pdata.h> + +static u64 dma_dmamask = DMA_BIT_MASK(32); + +static struct resource s5pv210_pdma0_resource[] = { + [0] = { + .start = S5PV210_PA_PDMA0, + .end = S5PV210_PA_PDMA0 + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PDMA0, + .end = IRQ_PDMA0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_pl330_platdata s5pv210_pdma0_pdata = { + .peri = { + [0] = DMACH_UART0_RX, + [1] = DMACH_UART0_TX, + [2] = DMACH_UART1_RX, + [3] = DMACH_UART1_TX, + [4] = DMACH_UART2_RX, + [5] = DMACH_UART2_TX, + [6] = DMACH_UART3_RX, + [7] = DMACH_UART3_TX, + [8] = DMACH_MAX, + [9] = DMACH_I2S0_RX, + [10] = DMACH_I2S0_TX, + [11] = DMACH_I2S0S_TX, + [12] = DMACH_I2S1_RX, + [13] = DMACH_I2S1_TX, + [14] = DMACH_MAX, + [15] = DMACH_MAX, + [16] = DMACH_SPI0_RX, + [17] = DMACH_SPI0_TX, + [18] = DMACH_SPI1_RX, + [19] = DMACH_SPI1_TX, + [20] = DMACH_MAX, + [21] = DMACH_MAX, + [22] = DMACH_AC97_MICIN, + [23] = DMACH_AC97_PCMIN, + [24] = DMACH_AC97_PCMOUT, + [25] = DMACH_MAX, + [26] = DMACH_PWM, + [27] = DMACH_SPDIF, + [28] = DMACH_MAX, + [29] = DMACH_MAX, + [30] = DMACH_MAX, + [31] = DMACH_MAX, + }, +}; + +static struct platform_device s5pv210_device_pdma0 = { + .name = "s3c-pl330", + .id = 1, + .num_resources = ARRAY_SIZE(s5pv210_pdma0_resource), + .resource = s5pv210_pdma0_resource, + .dev = { + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pv210_pdma0_pdata, + }, +}; + +static struct resource s5pv210_pdma1_resource[] = { + [0] = { + .start = S5PV210_PA_PDMA1, + .end = S5PV210_PA_PDMA1 + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PDMA1, + .end = IRQ_PDMA1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_pl330_platdata s5pv210_pdma1_pdata = { + .peri = { + [0] = DMACH_UART0_RX, + [1] = DMACH_UART0_TX, + [2] = DMACH_UART1_RX, + [3] = DMACH_UART1_TX, + [4] = DMACH_UART2_RX, + [5] = DMACH_UART2_TX, + [6] = DMACH_UART3_RX, + [7] = DMACH_UART3_TX, + [8] = DMACH_MAX, + [9] = DMACH_I2S0_RX, + [10] = DMACH_I2S0_TX, + [11] = DMACH_I2S0S_TX, + [12] = DMACH_I2S1_RX, + [13] = DMACH_I2S1_TX, + [14] = DMACH_I2S2_RX, + [15] = DMACH_I2S2_TX, + [16] = DMACH_SPI0_RX, + [17] = DMACH_SPI0_TX, + [18] = DMACH_SPI1_RX, + [19] = DMACH_SPI1_TX, + [20] = DMACH_MAX, + [21] = DMACH_MAX, + [22] = DMACH_PCM0_RX, + [23] = DMACH_PCM0_TX, + [24] = DMACH_PCM1_RX, + [25] = DMACH_PCM1_TX, + [26] = DMACH_MSM_REQ0, + [27] = DMACH_MSM_REQ1, + [28] = DMACH_MSM_REQ2, + [29] = DMACH_MSM_REQ3, + [30] = DMACH_PCM2_RX, + [31] = DMACH_PCM2_TX, + }, +}; + +static struct platform_device s5pv210_device_pdma1 = { + .name = "s3c-pl330", + .id = 2, + .num_resources = ARRAY_SIZE(s5pv210_pdma1_resource), + .resource = s5pv210_pdma1_resource, + .dev = { + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pv210_pdma1_pdata, + }, +}; + +static struct platform_device *s5pv210_dmacs[] __initdata = { + &s5pv210_device_pdma0, + &s5pv210_device_pdma1, +}; + +static int __init s5pv210_dma_init(void) +{ + platform_add_devices(s5pv210_dmacs, ARRAY_SIZE(s5pv210_dmacs)); + + return 0; +} +arch_initcall(s5pv210_dma_init); diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c new file mode 100644 index 00000000000..9ea8972e023 --- /dev/null +++ b/arch/arm/mach-s5pv210/gpiolib.c @@ -0,0 +1,261 @@ +/* linux/arch/arm/mach-s5pv210/gpiolib.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <plat/gpio-core.h> +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> +#include <mach/map.h> + +static struct s3c_gpio_cfg gpio_cfg = { + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_cfg_noint = { + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +/* GPIO bank's base address given the index of the bank in the + * list of all gpio banks. + */ +#define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20)) + +/* + * Following are the gpio banks in v210. + * + * The 'config' member when left to NULL, is initialized to the default + * structure gpio_cfg in the init function below. + * + * The 'base' member is also initialized in the init function below. + * Note: The initialization of 'base' member of s3c_gpio_chip structure + * uses the above macro and depends on the banks being listed in order here. + */ +static struct s3c_gpio_chip s5pv210_gpio_4bit[] = { + { + .chip = { + .base = S5PV210_GPA0(0), + .ngpio = S5PV210_GPIO_A0_NR, + .label = "GPA0", + }, + }, { + .chip = { + .base = S5PV210_GPA1(0), + .ngpio = S5PV210_GPIO_A1_NR, + .label = "GPA1", + }, + }, { + .chip = { + .base = S5PV210_GPB(0), + .ngpio = S5PV210_GPIO_B_NR, + .label = "GPB", + }, + }, { + .chip = { + .base = S5PV210_GPC0(0), + .ngpio = S5PV210_GPIO_C0_NR, + .label = "GPC0", + }, + }, { + .chip = { + .base = S5PV210_GPC1(0), + .ngpio = S5PV210_GPIO_C1_NR, + .label = "GPC1", + }, + }, { + .chip = { + .base = S5PV210_GPD0(0), + .ngpio = S5PV210_GPIO_D0_NR, + .label = "GPD0", + }, + }, { + .chip = { + .base = S5PV210_GPD1(0), + .ngpio = S5PV210_GPIO_D1_NR, + .label = "GPD1", + }, + }, { + .chip = { + .base = S5PV210_GPE0(0), + .ngpio = S5PV210_GPIO_E0_NR, + .label = "GPE0", + }, + }, { + .chip = { + .base = S5PV210_GPE1(0), + .ngpio = S5PV210_GPIO_E1_NR, + .label = "GPE1", + }, + }, { + .chip = { + .base = S5PV210_GPF0(0), + .ngpio = S5PV210_GPIO_F0_NR, + .label = "GPF0", + }, + }, { + .chip = { + .base = S5PV210_GPF1(0), + .ngpio = S5PV210_GPIO_F1_NR, + .label = "GPF1", + }, + }, { + .chip = { + .base = S5PV210_GPF2(0), + .ngpio = S5PV210_GPIO_F2_NR, + .label = "GPF2", + }, + }, { + .chip = { + .base = S5PV210_GPF3(0), + .ngpio = S5PV210_GPIO_F3_NR, + .label = "GPF3", + }, + }, { + .chip = { + .base = S5PV210_GPG0(0), + .ngpio = S5PV210_GPIO_G0_NR, + .label = "GPG0", + }, + }, { + .chip = { + .base = S5PV210_GPG1(0), + .ngpio = S5PV210_GPIO_G1_NR, + .label = "GPG1", + }, + }, { + .chip = { + .base = S5PV210_GPG2(0), + .ngpio = S5PV210_GPIO_G2_NR, + .label = "GPG2", + }, + }, { + .chip = { + .base = S5PV210_GPG3(0), + .ngpio = S5PV210_GPIO_G3_NR, + .label = "GPG3", + }, + }, { + .chip = { + .base = S5PV210_GPI(0), + .ngpio = S5PV210_GPIO_I_NR, + .label = "GPI", + }, + }, { + .chip = { + .base = S5PV210_GPJ0(0), + .ngpio = S5PV210_GPIO_J0_NR, + .label = "GPJ0", + }, + }, { + .chip = { + .base = S5PV210_GPJ1(0), + .ngpio = S5PV210_GPIO_J1_NR, + .label = "GPJ1", + }, + }, { + .chip = { + .base = S5PV210_GPJ2(0), + .ngpio = S5PV210_GPIO_J2_NR, + .label = "GPJ2", + }, + }, { + .chip = { + .base = S5PV210_GPJ3(0), + .ngpio = S5PV210_GPIO_J3_NR, + .label = "GPJ3", + }, + }, { + .chip = { + .base = S5PV210_GPJ4(0), + .ngpio = S5PV210_GPIO_J4_NR, + .label = "GPJ4", + }, + }, { + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_MP01(0), + .ngpio = S5PV210_GPIO_MP01_NR, + .label = "MP01", + }, + }, { + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_MP02(0), + .ngpio = S5PV210_GPIO_MP02_NR, + .label = "MP02", + }, + }, { + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_MP03(0), + .ngpio = S5PV210_GPIO_MP03_NR, + .label = "MP03", + }, + }, { + .base = (S5P_VA_GPIO + 0xC00), + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_GPH0(0), + .ngpio = S5PV210_GPIO_H0_NR, + .label = "GPH0", + }, + }, { + .base = (S5P_VA_GPIO + 0xC20), + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_GPH1(0), + .ngpio = S5PV210_GPIO_H1_NR, + .label = "GPH1", + }, + }, { + .base = (S5P_VA_GPIO + 0xC40), + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_GPH2(0), + .ngpio = S5PV210_GPIO_H2_NR, + .label = "GPH2", + }, + }, { + .base = (S5P_VA_GPIO + 0xC60), + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_GPH3(0), + .ngpio = S5PV210_GPIO_H3_NR, + .label = "GPH3", + }, + }, +}; + +static __init int s5pv210_gpiolib_init(void) +{ + struct s3c_gpio_chip *chip = s5pv210_gpio_4bit; + int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit); + int i = 0; + + for (i = 0; i < nr_chips; i++, chip++) { + if (chip->config == NULL) + chip->config = &gpio_cfg; + if (chip->base == NULL) + chip->base = S5PV210_BANK_BASE(i); + } + + samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips); + + return 0; +} +core_initcall(s5pv210_gpiolib_init); diff --git a/arch/arm/mach-s5pv210/include/mach/dma.h b/arch/arm/mach-s5pv210/include/mach/dma.h new file mode 100644 index 00000000000..81209eb1409 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/dma.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MACH_DMA_H +#define __MACH_DMA_H + +/* This platform uses the common S3C DMA API driver for PL330 */ +#include <plat/s3c-dma-pl330.h> + +#endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h index 533b020e21e..d6461ba2b71 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h @@ -18,6 +18,8 @@ #define gpio_cansleep __gpio_cansleep #define gpio_to_irq __gpio_to_irq +/* Practically, GPIO banks upto MP03 are the configurable gpio banks */ + /* GPIO bank sizes */ #define S5PV210_GPIO_A0_NR (8) #define S5PV210_GPIO_A1_NR (4) @@ -47,6 +49,10 @@ #define S5PV210_GPIO_J3_NR (8) #define S5PV210_GPIO_J4_NR (5) +#define S5PV210_GPIO_MP01_NR (8) +#define S5PV210_GPIO_MP02_NR (4) +#define S5PV210_GPIO_MP03_NR (8) + /* GPIO bank numbers */ /* CONFIG_S3C_GPIO_SPACE allows the user to select extra @@ -85,6 +91,9 @@ enum s5p_gpio_number { S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1), S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2), S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3), + S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4), + S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01), + S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02), }; /* S5PV210 GPIO number definitions */ @@ -115,13 +124,16 @@ enum s5p_gpio_number { #define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr)) #define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr)) #define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr)) +#define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr)) +#define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr)) +#define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr)) /* the end of the S5PV210 specific gpios */ -#define S5PV210_GPIO_END (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + 1) +#define S5PV210_GPIO_END (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1) #define S3C_GPIO_END S5PV210_GPIO_END -/* define the number of gpios we need to the one after the GPJ4() range */ -#define ARCH_NR_GPIOS (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + \ +/* define the number of gpios we need to the one after the MP03() range */ +#define ARCH_NR_GPIOS (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + \ CONFIG_SAMSUNG_GPIO_EXTRA + 1) #include <asm-generic/gpio.h> diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index c22694c8231..5adcb9f26e4 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -43,6 +43,10 @@ #define S5PV210_PA_SROMC (0xE8000000) +#define S5PV210_PA_MDMA 0xFA200000 +#define S5PV210_PA_PDMA0 0xE0900000 +#define S5PV210_PA_PDMA1 0xE0A00000 + #define S5PV210_PA_VIC0 (0xF2000000) #define S5P_PA_VIC0 S5PV210_PA_VIC0 @@ -58,6 +62,19 @@ #define S5PV210_PA_SDRAM (0x20000000) #define S5P_PA_SDRAM S5PV210_PA_SDRAM +/* I2S */ +#define S5PV210_PA_IIS0 0xEEE30000 +#define S5PV210_PA_IIS1 0xE2100000 +#define S5PV210_PA_IIS2 0xE2A00000 + +/* PCM */ +#define S5PV210_PA_PCM0 0xE2300000 +#define S5PV210_PA_PCM1 0xE1200000 +#define S5PV210_PA_PCM2 0xE2B00000 + +/* AC97 */ +#define S5PV210_PA_AC97 0xE2200000 + /* compatibiltiy defines. */ #define S3C_PA_UART S5PV210_PA_UART #define S3C_PA_IIC S5PV210_PA_IIC0 diff --git a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h index 69027fea987..f8a9f1b330e 100644 --- a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h @@ -1,13 +1,14 @@ /* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * http://armlinux.simtec.co.uk/ * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h + * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h * * S5PV210 - pwm clock and timer support * @@ -21,14 +22,14 @@ /** * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @cfg: The timer TCFG1 register bits shifted down to 0. + * @tcfg: The timer TCFG1 register bits shifted down to 0. * * Return true if the given configuration from TCFG1 is a TCLK instead * any of the TDIV clocks. */ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) { - return tcfg == S3C2410_TCFG1_MUX_TCLK; + return tcfg == S3C64XX_TCFG1_MUX_TCLK; } /** @@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) */ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) { - return 1 << (1 + tcfg1); + return 1 << tcfg1; } /** @@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) */ static inline unsigned int pwm_tdiv_has_div1(void) { - return 0; + return 1; } /** @@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void) */ static inline unsigned long pwm_tdiv_div_bits(unsigned int div) { - return ilog2(div) - 1; + return ilog2(div); } -#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK +#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK #endif /* __ASM_ARCH_PWMCLK_H */ diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c index ab4869df30c..6f9fd3274e2 100644 --- a/arch/arm/mach-s5pv210/mach-smdkc110.c +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c @@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { }; static struct platform_device *smdkc110_devices[] __initdata = { + &s5pv210_device_iis0, + &s5pv210_device_ac97, }; static void __init smdkc110_map_io(void) diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index a2788325320..3c29e18528a 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { }; static struct platform_device *smdkv210_devices[] __initdata = { + &s5pv210_device_iis0, + &s5pv210_device_ac97, }; static void __init smdkv210_map_io(void) diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c new file mode 100644 index 00000000000..9ec6845840e --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-i2c0.c @@ -0,0 +1,25 @@ +/* linux/arch/arm/mach-s5pv210/setup-i2c0.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * I2C0 GPIO configuration. + * + * Based on plat-s3c64xx/setup-i2c0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <plat/iic.h> + +void s3c_i2c0_cfg_gpio(struct platform_device *dev) +{ + /* Will be populated later */ +} diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index aeceb9b92ae..f2b88c5fe14 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -7,7 +7,6 @@ config ARCH_SH7367 select CPU_V6 select HAVE_CLK select COMMON_CLKDEV - select GENERIC_TIME select GENERIC_CLOCKEVENTS config ARCH_SH7377 @@ -15,7 +14,6 @@ config ARCH_SH7377 select CPU_V7 select HAVE_CLK select COMMON_CLKDEV - select GENERIC_TIME select GENERIC_CLOCKEVENTS config ARCH_SH7372 @@ -23,7 +21,6 @@ config ARCH_SH7372 select CPU_V7 select HAVE_CLK select COMMON_CLKDEV - select GENERIC_TIME select GENERIC_CLOCKEVENTS comment "SH-Mobile Board Type" diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig new file mode 100644 index 00000000000..20d1317cc48 --- /dev/null +++ b/arch/arm/mach-spear3xx/Kconfig @@ -0,0 +1,33 @@ +# +# SPEAr3XX Machine configuration file +# + +if ARCH_SPEAR3XX + +choice + prompt "SPEAr3XX Family" + default MACH_SPEAR300 + +config MACH_SPEAR300 + bool "SPEAr300" + help + Supports ST SPEAr300 Machine + +config MACH_SPEAR310 + bool "SPEAr310" + help + Supports ST SPEAr310 Machine + +config MACH_SPEAR320 + bool "SPEAr320" + help + Supports ST SPEAr320 Machine + +endchoice + +# Adding SPEAr3XX machine specific configuration files +source "arch/arm/mach-spear3xx/Kconfig300" +source "arch/arm/mach-spear3xx/Kconfig310" +source "arch/arm/mach-spear3xx/Kconfig320" + +endif #ARCH_SPEAR3XX diff --git a/arch/arm/mach-spear3xx/Kconfig300 b/arch/arm/mach-spear3xx/Kconfig300 new file mode 100644 index 00000000000..c519a05b4ab --- /dev/null +++ b/arch/arm/mach-spear3xx/Kconfig300 @@ -0,0 +1,17 @@ +# +# SPEAr300 machine configuration file +# + +if MACH_SPEAR300 + +choice + prompt "SPEAr300 Boards" + default BOARD_SPEAR300_EVB + +config BOARD_SPEAR300_EVB + bool "SPEAr300 Evaluation Board" + help + Supports ST SPEAr300 Evaluation Board +endchoice + +endif #MACH_SPEAR300 diff --git a/arch/arm/mach-spear3xx/Kconfig310 b/arch/arm/mach-spear3xx/Kconfig310 new file mode 100644 index 00000000000..60e7442d75b --- /dev/null +++ b/arch/arm/mach-spear3xx/Kconfig310 @@ -0,0 +1,17 @@ +# +# SPEAr310 machine configuration file +# + +if MACH_SPEAR310 + +choice + prompt "SPEAr310 Boards" + default BOARD_SPEAR310_EVB + +config BOARD_SPEAR310_EVB + bool "SPEAr310 Evaluation Board" + help + Supports ST SPEAr310 Evaluation Board +endchoice + +endif #MACH_SPEAR310 diff --git a/arch/arm/mach-spear3xx/Kconfig320 b/arch/arm/mach-spear3xx/Kconfig320 new file mode 100644 index 00000000000..1c1d438399b --- /dev/null +++ b/arch/arm/mach-spear3xx/Kconfig320 @@ -0,0 +1,17 @@ +# +# SPEAr320 machine configuration file +# + +if MACH_SPEAR320 + +choice + prompt "SPEAr320 Boards" + default BOARD_SPEAR320_EVB + +config BOARD_SPEAR320_EVB + bool "SPEAr320 Evaluation Board" + help + Supports ST SPEAr320 Evaluation Board +endchoice + +endif #MACH_SPEAR320 diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile new file mode 100644 index 00000000000..b2486248970 --- /dev/null +++ b/arch/arm/mach-spear3xx/Makefile @@ -0,0 +1,26 @@ +# +# Makefile for SPEAr3XX machine series +# + +# common files +obj-y += spear3xx.o clock.o + +# spear300 specific files +obj-$(CONFIG_MACH_SPEAR300) += spear300.o + +# spear300 boards files +obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o + + +# spear310 specific files +obj-$(CONFIG_MACH_SPEAR310) += spear310.o + +# spear310 boards files +obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o + + +# spear320 specific files +obj-$(CONFIG_MACH_SPEAR320) += spear320.o + +# spear320 boards files +obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot new file mode 100644 index 00000000000..7a1f3c0eadb --- /dev/null +++ b/arch/arm/mach-spear3xx/Makefile.boot @@ -0,0 +1,3 @@ +zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c new file mode 100644 index 00000000000..39f6ccf2229 --- /dev/null +++ b/arch/arm/mach-spear3xx/clock.c @@ -0,0 +1,389 @@ +/* + * arch/arm/mach-spear3xx/clock.c + * + * SPEAr3xx machines clock framework source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <mach/misc_regs.h> +#include <plat/clock.h> + +/* root clks */ +/* 32 KHz oscillator clock */ +static struct clk osc_32k_clk = { + .flags = ALWAYS_ENABLED, + .rate = 32000, +}; + +/* 24 MHz oscillator clock */ +static struct clk osc_24m_clk = { + .flags = ALWAYS_ENABLED, + .rate = 24000000, +}; + +/* clock derived from 32 KHz osc clk */ +/* rtc clock */ +static struct clk rtc_clk = { + .pclk = &osc_32k_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = RTC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clock derived from 24 MHz osc clk */ +/* pll1 configuration structure */ +static struct pll_clk_config pll1_config = { + .mode_reg = PLL1_CTR, + .cfg_reg = PLL1_FRQ, +}; + +/* PLL1 clock */ +static struct clk pll1_clk = { + .pclk = &osc_24m_clk, + .en_reg = PLL1_CTR, + .en_reg_bit = PLL_ENABLE, + .recalc = &pll1_clk_recalc, + .private_data = &pll1_config, +}; + +/* PLL3 48 MHz clock */ +static struct clk pll3_48m_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_24m_clk, + .rate = 48000000, +}; + +/* watch dog timer clock */ +static struct clk wdt_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_24m_clk, + .recalc = &follow_parent, +}; + +/* clock derived from pll1 clk */ +/* cpu clock */ +static struct clk cpu_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .recalc = &follow_parent, +}; + +/* ahb configuration structure */ +static struct bus_clk_config ahb_config = { + .reg = CORE_CLK_CFG, + .mask = PLL_HCLK_RATIO_MASK, + .shift = PLL_HCLK_RATIO_SHIFT, +}; + +/* ahb clock */ +static struct clk ahb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .recalc = &bus_clk_recalc, + .private_data = &ahb_config, +}; + +/* uart configurations */ +static struct aux_clk_config uart_config = { + .synth_reg = UART_CLK_SYNT, +}; + +/* uart parents */ +static struct pclk_info uart_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* uart parent select structure */ +static struct pclk_sel uart_pclk_sel = { + .pclk_info = uart_pclk_info, + .pclk_count = ARRAY_SIZE(uart_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = UART_CLK_MASK, +}; + +/* uart clock */ +static struct clk uart_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = UART_CLK_ENB, + .pclk_sel = &uart_pclk_sel, + .pclk_sel_shift = UART_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &uart_config, +}; + +/* firda configurations */ +static struct aux_clk_config firda_config = { + .synth_reg = FIRDA_CLK_SYNT, +}; + +/* firda parents */ +static struct pclk_info firda_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* firda parent select structure */ +static struct pclk_sel firda_pclk_sel = { + .pclk_info = firda_pclk_info, + .pclk_count = ARRAY_SIZE(firda_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = FIRDA_CLK_MASK, +}; + +/* firda clock */ +static struct clk firda_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = FIRDA_CLK_ENB, + .pclk_sel = &firda_pclk_sel, + .pclk_sel_shift = FIRDA_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &firda_config, +}; + +/* gpt parents */ +static struct pclk_info gpt_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt_pclk_sel = { + .pclk_info = gpt_pclk_info, + .pclk_count = ARRAY_SIZE(gpt_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, +}; + +/* gpt0 configurations */ +static struct aux_clk_config gpt0_config = { + .synth_reg = PRSC1_CLK_CFG, +}; + +/* gpt0 timer clock */ +static struct clk gpt0_clk = { + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT0_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt0_config, +}; + +/* gpt1 configurations */ +static struct aux_clk_config gpt1_config = { + .synth_reg = PRSC2_CLK_CFG, +}; + +/* gpt1 timer clock */ +static struct clk gpt1_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPT1_CLK_ENB, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT1_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt1_config, +}; + +/* gpt2 configurations */ +static struct aux_clk_config gpt2_config = { + .synth_reg = PRSC3_CLK_CFG, +}; + +/* gpt2 timer clock */ +static struct clk gpt2_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPT2_CLK_ENB, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT2_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt2_config, +}; + +/* clock derived from pll3 clk */ +/* usbh clock */ +static struct clk usbh_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBH_CLK_ENB, + .recalc = &follow_parent, +}; + +/* usbd clock */ +static struct clk usbd_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBD_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clcd clock */ +static struct clk clcd_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll3_48m_clk, + .recalc = &follow_parent, +}; + +/* clock derived from ahb clk */ +/* apb configuration structure */ +static struct bus_clk_config apb_config = { + .reg = CORE_CLK_CFG, + .mask = HCLK_PCLK_RATIO_MASK, + .shift = HCLK_PCLK_RATIO_SHIFT, +}; + +/* apb clock */ +static struct clk apb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &bus_clk_recalc, + .private_data = &apb_config, +}; + +/* i2c clock */ +static struct clk i2c_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = I2C_CLK_ENB, + .recalc = &follow_parent, +}; + +/* dma clock */ +static struct clk dma_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = DMA_CLK_ENB, + .recalc = &follow_parent, +}; + +/* jpeg clock */ +static struct clk jpeg_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = JPEG_CLK_ENB, + .recalc = &follow_parent, +}; + +/* gmac clock */ +static struct clk gmac_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GMAC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* smi clock */ +static struct clk smi_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SMI_CLK_ENB, + .recalc = &follow_parent, +}; + +/* c3 clock */ +static struct clk c3_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = C3_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clock derived from apb clk */ +/* adc clock */ +static struct clk adc_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = ADC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* ssp clock */ +static struct clk ssp_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP_CLK_ENB, + .recalc = &follow_parent, +}; + +/* gpio clock */ +static struct clk gpio_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPIO_CLK_ENB, + .recalc = &follow_parent, +}; + +/* array of all spear 3xx clock lookups */ +static struct clk_lookup spear_clk_lookups[] = { + /* root clks */ + { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, + { .con_id = "osc_24m_clk", .clk = &osc_24m_clk}, + /* clock derived from 32 KHz osc clk */ + { .dev_id = "rtc", .clk = &rtc_clk}, + /* clock derived from 24 MHz osc clk */ + { .con_id = "pll1_clk", .clk = &pll1_clk}, + { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, + { .dev_id = "wdt", .clk = &wdt_clk}, + /* clock derived from pll1 clk */ + { .con_id = "cpu_clk", .clk = &cpu_clk}, + { .con_id = "ahb_clk", .clk = &ahb_clk}, + { .dev_id = "uart", .clk = &uart_clk}, + { .dev_id = "firda", .clk = &firda_clk}, + { .dev_id = "gpt0", .clk = &gpt0_clk}, + { .dev_id = "gpt1", .clk = &gpt1_clk}, + { .dev_id = "gpt2", .clk = &gpt2_clk}, + /* clock derived from pll3 clk */ + { .dev_id = "usbh", .clk = &usbh_clk}, + { .dev_id = "usbd", .clk = &usbd_clk}, + { .dev_id = "clcd", .clk = &clcd_clk}, + /* clock derived from ahb clk */ + { .con_id = "apb_clk", .clk = &apb_clk}, + { .dev_id = "i2c", .clk = &i2c_clk}, + { .dev_id = "dma", .clk = &dma_clk}, + { .dev_id = "jpeg", .clk = &jpeg_clk}, + { .dev_id = "gmac", .clk = &gmac_clk}, + { .dev_id = "smi", .clk = &smi_clk}, + { .dev_id = "c3", .clk = &c3_clk}, + /* clock derived from apb clk */ + { .dev_id = "adc", .clk = &adc_clk}, + { .dev_id = "ssp", .clk = &ssp_clk}, + { .dev_id = "gpio", .clk = &gpio_clk}, +}; + +void __init clk_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) + clk_register(&spear_clk_lookups[i]); + + recalc_root_clocks(); +} diff --git a/arch/arm/mach-spear3xx/include/mach/clkdev.h b/arch/arm/mach-spear3xx/include/mach/clkdev.h new file mode 100644 index 00000000000..a3d07339d9f --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/clkdev.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear3xx/include/mach/clkdev.h + * + * Clock Dev framework definitions for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_CLKDEV_H +#define __MACH_CLKDEV_H + +#include <plat/clkdev.h> + +#endif /* __MACH_CLKDEV_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/debug-macro.S b/arch/arm/mach-spear3xx/include/mach/debug-macro.S new file mode 100644 index 00000000000..590519f10d6 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/debug-macro.S @@ -0,0 +1,14 @@ +/* + * arch/arm/mach-spear3xx/include/mach/debug-macro.S + * + * Debugging macro include header spear3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <plat/debug-macro.S> diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S new file mode 100644 index 00000000000..947625d6b48 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S @@ -0,0 +1,46 @@ +/* + * arch/arm/mach-spear3xx/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/hardware.h> +#include <mach/spear.h> +#include <asm/hardware/vic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =VA_SPEAR3XX_ML1_VIC_BASE + ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status + teq \irqstat, #0 + beq 1001f @ this will set/reset + @ zero register + /* + * Following code will find bit position of least significang + * bit set in irqstat, using following equation + * least significant bit set in n = (n & ~(n-1)) + */ + sub \tmp, \irqstat, #1 @ tmp = irqstat - 1 + mvn \tmp, \tmp @ tmp = ~tmp + and \irqstat, \irqstat, \tmp @ irqstat &= tmp + /* Now, irqstat is = bit no. of 1st bit set in vic irq status */ + clz \tmp, \irqstat @ tmp = leading zeros + rsb \irqnr, \tmp, #0x1F @ irqnr = 32 - tmp - 1 + +1001: /* EQ will be set if no irqs pending */ + .endm diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h new file mode 100644 index 00000000000..af7e02c909a --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -0,0 +1,205 @@ +/* + * arch/arm/mach-spear3xx/generic.h + * + * SPEAr3XX machine family generic header file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_GENERIC_H +#define __MACH_GENERIC_H + +#include <asm/mach/time.h> +#include <asm/mach/map.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/amba/bus.h> +#include <plat/padmux.h> + +/* spear3xx declarations */ +/* + * Each GPT has 2 timer channels + * Following GPT channels will be used as clock source and clockevent + */ +#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE +#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 +#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 + +/* Add spear3xx family device structure declarations here */ +extern struct amba_device gpio_device; +extern struct amba_device uart_device; +extern struct sys_timer spear_sys_timer; + +/* Add spear3xx family function declarations here */ +void __init clk_init(void); +void __init spear3xx_map_io(void); +void __init spear3xx_init_irq(void); +void __init spear3xx_init(void); +void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size); + +/* pad mux declarations */ +#define PMX_FIRDA_MASK (1 << 14) +#define PMX_I2C_MASK (1 << 13) +#define PMX_SSP_CS_MASK (1 << 12) +#define PMX_SSP_MASK (1 << 11) +#define PMX_MII_MASK (1 << 10) +#define PMX_GPIO_PIN0_MASK (1 << 9) +#define PMX_GPIO_PIN1_MASK (1 << 8) +#define PMX_GPIO_PIN2_MASK (1 << 7) +#define PMX_GPIO_PIN3_MASK (1 << 6) +#define PMX_GPIO_PIN4_MASK (1 << 5) +#define PMX_GPIO_PIN5_MASK (1 << 4) +#define PMX_UART0_MODEM_MASK (1 << 3) +#define PMX_UART0_MASK (1 << 2) +#define PMX_TIMER_3_4_MASK (1 << 1) +#define PMX_TIMER_1_2_MASK (1 << 0) + +/* pad mux devices */ +extern struct pmx_dev pmx_firda; +extern struct pmx_dev pmx_i2c; +extern struct pmx_dev pmx_ssp_cs; +extern struct pmx_dev pmx_ssp; +extern struct pmx_dev pmx_mii; +extern struct pmx_dev pmx_gpio_pin0; +extern struct pmx_dev pmx_gpio_pin1; +extern struct pmx_dev pmx_gpio_pin2; +extern struct pmx_dev pmx_gpio_pin3; +extern struct pmx_dev pmx_gpio_pin4; +extern struct pmx_dev pmx_gpio_pin5; +extern struct pmx_dev pmx_uart0_modem; +extern struct pmx_dev pmx_uart0; +extern struct pmx_dev pmx_timer_3_4; +extern struct pmx_dev pmx_timer_1_2; + +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +/* padmux plgpio devices */ +extern struct pmx_dev pmx_plgpio_0_1; +extern struct pmx_dev pmx_plgpio_2_3; +extern struct pmx_dev pmx_plgpio_4_5; +extern struct pmx_dev pmx_plgpio_6_9; +extern struct pmx_dev pmx_plgpio_10_27; +extern struct pmx_dev pmx_plgpio_28; +extern struct pmx_dev pmx_plgpio_29; +extern struct pmx_dev pmx_plgpio_30; +extern struct pmx_dev pmx_plgpio_31; +extern struct pmx_dev pmx_plgpio_32; +extern struct pmx_dev pmx_plgpio_33; +extern struct pmx_dev pmx_plgpio_34_36; +extern struct pmx_dev pmx_plgpio_37_42; +extern struct pmx_dev pmx_plgpio_43_44_47_48; +extern struct pmx_dev pmx_plgpio_45_46_49_50; +#endif + +extern struct pmx_driver pmx_driver; + +/* spear300 declarations */ +#ifdef CONFIG_MACH_SPEAR300 +/* Add spear300 machine device structure declarations here */ +extern struct amba_device gpio1_device; + +/* pad mux modes */ +extern struct pmx_mode nand_mode; +extern struct pmx_mode nor_mode; +extern struct pmx_mode photo_frame_mode; +extern struct pmx_mode lend_ip_phone_mode; +extern struct pmx_mode hend_ip_phone_mode; +extern struct pmx_mode lend_wifi_phone_mode; +extern struct pmx_mode hend_wifi_phone_mode; +extern struct pmx_mode ata_pabx_wi2s_mode; +extern struct pmx_mode ata_pabx_i2s_mode; +extern struct pmx_mode caml_lcdw_mode; +extern struct pmx_mode camu_lcd_mode; +extern struct pmx_mode camu_wlcd_mode; +extern struct pmx_mode caml_lcd_mode; + +/* pad mux devices */ +extern struct pmx_dev pmx_fsmc_2_chips; +extern struct pmx_dev pmx_fsmc_4_chips; +extern struct pmx_dev pmx_keyboard; +extern struct pmx_dev pmx_clcd; +extern struct pmx_dev pmx_telecom_gpio; +extern struct pmx_dev pmx_telecom_tdm; +extern struct pmx_dev pmx_telecom_spi_cs_i2c_clk; +extern struct pmx_dev pmx_telecom_camera; +extern struct pmx_dev pmx_telecom_dac; +extern struct pmx_dev pmx_telecom_i2s; +extern struct pmx_dev pmx_telecom_boot_pins; +extern struct pmx_dev pmx_telecom_sdio_4bit; +extern struct pmx_dev pmx_telecom_sdio_8bit; +extern struct pmx_dev pmx_gpio1; + +void spear300_pmx_init(void); + +/* Add spear300 machine function declarations here */ +void __init spear300_init(void); + +#endif /* CONFIG_MACH_SPEAR300 */ + +/* spear310 declarations */ +#ifdef CONFIG_MACH_SPEAR310 +/* Add spear310 machine device structure declarations here */ + +/* pad mux devices */ +extern struct pmx_dev pmx_emi_cs_0_1_4_5; +extern struct pmx_dev pmx_emi_cs_2_3; +extern struct pmx_dev pmx_uart1; +extern struct pmx_dev pmx_uart2; +extern struct pmx_dev pmx_uart3_4_5; +extern struct pmx_dev pmx_fsmc; +extern struct pmx_dev pmx_rs485_0_1; +extern struct pmx_dev pmx_tdm0; + +void spear310_pmx_init(void); + +/* Add spear310 machine function declarations here */ +void __init spear310_init(void); + +#endif /* CONFIG_MACH_SPEAR310 */ + +/* spear320 declarations */ +#ifdef CONFIG_MACH_SPEAR320 +/* Add spear320 machine device structure declarations here */ + +/* pad mux modes */ +extern struct pmx_mode auto_net_smii_mode; +extern struct pmx_mode auto_net_mii_mode; +extern struct pmx_mode auto_exp_mode; +extern struct pmx_mode small_printers_mode; + +/* pad mux devices */ +extern struct pmx_dev pmx_clcd; +extern struct pmx_dev pmx_emi; +extern struct pmx_dev pmx_fsmc; +extern struct pmx_dev pmx_spp; +extern struct pmx_dev pmx_sdio; +extern struct pmx_dev pmx_i2s; +extern struct pmx_dev pmx_uart1; +extern struct pmx_dev pmx_uart1_modem; +extern struct pmx_dev pmx_uart2; +extern struct pmx_dev pmx_touchscreen; +extern struct pmx_dev pmx_can; +extern struct pmx_dev pmx_sdio_led; +extern struct pmx_dev pmx_pwm0; +extern struct pmx_dev pmx_pwm1; +extern struct pmx_dev pmx_pwm2; +extern struct pmx_dev pmx_pwm3; +extern struct pmx_dev pmx_ssp1; +extern struct pmx_dev pmx_ssp2; +extern struct pmx_dev pmx_mii1; +extern struct pmx_dev pmx_smii0; +extern struct pmx_dev pmx_smii1; +extern struct pmx_dev pmx_i2c1; + +void spear320_pmx_init(void); + +/* Add spear320 machine function declarations here */ +void __init spear320_init(void); + +#endif /* CONFIG_MACH_SPEAR320 */ + +#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h new file mode 100644 index 00000000000..451b2081bfc --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/gpio.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear3xx/include/mach/gpio.h + * + * GPIO macros for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_GPIO_H +#define __MACH_GPIO_H + +#include <plat/gpio.h> + +#endif /* __MACH_GPIO_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h new file mode 100644 index 00000000000..4a86e6a3c44 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/hardware.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-spear3xx/include/mach/hardware.h + * + * Hardware definitions for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H + +/* Vitual to physical translation of statically mapped space */ +#define IO_ADDRESS(x) (x | 0xF0000000) + +#endif /* __MACH_HARDWARE_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/io.h b/arch/arm/mach-spear3xx/include/mach/io.h new file mode 100644 index 00000000000..30cff8a1f6b --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/io.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear3xx/include/mach/io.h + * + * IO definitions for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_IO_H +#define __MACH_IO_H + +#include <plat/io.h> + +#endif /* __MACH_IO_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h new file mode 100644 index 00000000000..7f940b81847 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/irqs.h @@ -0,0 +1,152 @@ +/* + * arch/arm/mach-spear3xx/include/mach/irqs.h + * + * IRQ helper macros for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +/* SPEAr3xx IRQ definitions */ +#define IRQ_HW_ACCEL_MOD_0 0 +#define IRQ_INTRCOMM_RAS_ARM 1 +#define IRQ_CPU_GPT1_1 2 +#define IRQ_CPU_GPT1_2 3 +#define IRQ_BASIC_GPT1_1 4 +#define IRQ_BASIC_GPT1_2 5 +#define IRQ_BASIC_GPT2_1 6 +#define IRQ_BASIC_GPT2_2 7 +#define IRQ_BASIC_DMA 8 +#define IRQ_BASIC_SMI 9 +#define IRQ_BASIC_RTC 10 +#define IRQ_BASIC_GPIO 11 +#define IRQ_BASIC_WDT 12 +#define IRQ_DDR_CONTROLLER 13 +#define IRQ_SYS_ERROR 14 +#define IRQ_WAKEUP_RCV 15 +#define IRQ_JPEG 16 +#define IRQ_IRDA 17 +#define IRQ_ADC 18 +#define IRQ_UART 19 +#define IRQ_SSP 20 +#define IRQ_I2C 21 +#define IRQ_MAC_1 22 +#define IRQ_MAC_2 23 +#define IRQ_USB_DEV 24 +#define IRQ_USB_H_OHCI_0 25 +#define IRQ_USB_H_EHCI_0 26 +#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0 +#define IRQ_USB_H_OHCI_1 27 +#define IRQ_GEN_RAS_1 28 +#define IRQ_GEN_RAS_2 29 +#define IRQ_GEN_RAS_3 30 +#define IRQ_HW_ACCEL_MOD_1 31 +#define IRQ_VIC_END 32 + +#define VIRQ_START IRQ_VIC_END + +/* SPEAr300 Virtual irq definitions */ +#ifdef CONFIG_MACH_SPEAR300 +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define VIRQ_IT_PERS_S (VIRQ_START + 0) +#define VIRQ_IT_CHANGE_S (VIRQ_START + 1) +#define VIRQ_I2S (VIRQ_START + 2) +#define VIRQ_TDM (VIRQ_START + 3) +#define VIRQ_CAMERA_L (VIRQ_START + 4) +#define VIRQ_CAMERA_F (VIRQ_START + 5) +#define VIRQ_CAMERA_V (VIRQ_START + 6) +#define VIRQ_KEYBOARD (VIRQ_START + 7) +#define VIRQ_GPIO1 (VIRQ_START + 8) + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define IRQ_CLCD IRQ_GEN_RAS_3 + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define IRQ_SDIO IRQ_INTRCOMM_RAS_ARM + +/* GPIO pins virtual irqs */ +#define SPEAR_GPIO_INT_BASE (VIRQ_START + 9) +#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO_INT_BASE + 8) +#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8) + +/* SPEAr310 Virtual irq definitions */ +#elif defined(CONFIG_MACH_SPEAR310) +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define VIRQ_SMII0 (VIRQ_START + 0) +#define VIRQ_SMII1 (VIRQ_START + 1) +#define VIRQ_SMII2 (VIRQ_START + 2) +#define VIRQ_SMII3 (VIRQ_START + 3) +#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 4) +#define VIRQ_WAKEUP_SMII1 (VIRQ_START + 5) +#define VIRQ_WAKEUP_SMII2 (VIRQ_START + 6) +#define VIRQ_WAKEUP_SMII3 (VIRQ_START + 7) + +/* IRQs sharing IRQ_GEN_RAS_2 */ +#define VIRQ_UART1 (VIRQ_START + 8) +#define VIRQ_UART2 (VIRQ_START + 9) +#define VIRQ_UART3 (VIRQ_START + 10) +#define VIRQ_UART4 (VIRQ_START + 11) +#define VIRQ_UART5 (VIRQ_START + 12) + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define VIRQ_EMI (VIRQ_START + 13) +#define VIRQ_PLGPIO (VIRQ_START + 14) + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define VIRQ_TDM_HDLC (VIRQ_START + 15) +#define VIRQ_RS485_0 (VIRQ_START + 16) +#define VIRQ_RS485_1 (VIRQ_START + 17) + +/* GPIO pins virtual irqs */ +#define SPEAR_GPIO_INT_BASE (VIRQ_START + 18) + +/* SPEAr320 Virtual irq definitions */ +#else +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define VIRQ_EMI (VIRQ_START + 0) +#define VIRQ_CLCD (VIRQ_START + 1) +#define VIRQ_SPP (VIRQ_START + 2) + +/* IRQs sharing IRQ_GEN_RAS_2 */ +#define IRQ_SDIO IRQ_GEN_RAS_2 + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define VIRQ_PLGPIO (VIRQ_START + 3) +#define VIRQ_I2S_PLAY (VIRQ_START + 4) +#define VIRQ_I2S_REC (VIRQ_START + 5) + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define VIRQ_CANU (VIRQ_START + 6) +#define VIRQ_CANL (VIRQ_START + 7) +#define VIRQ_UART1 (VIRQ_START + 8) +#define VIRQ_UART2 (VIRQ_START + 9) +#define VIRQ_SSP1 (VIRQ_START + 10) +#define VIRQ_SSP2 (VIRQ_START + 11) +#define VIRQ_SMII0 (VIRQ_START + 12) +#define VIRQ_MII1_SMII1 (VIRQ_START + 13) +#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 14) +#define VIRQ_WAKEUP_MII1_SMII1 (VIRQ_START + 15) +#define VIRQ_I2C (VIRQ_START + 16) + +/* GPIO pins virtual irqs */ +#define SPEAR_GPIO_INT_BASE (VIRQ_START + 17) + +#endif + +/* PLGPIO Virtual IRQs */ +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +#define SPEAR_PLGPIO_INT_BASE (SPEAR_GPIO_INT_BASE + 8) +#define SPEAR_GPIO_INT_END (SPEAR_PLGPIO_INT_BASE + 102) +#endif + +#define VIRQ_END SPEAR_GPIO_INT_END +#define NR_IRQS VIRQ_END + +#endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/memory.h b/arch/arm/mach-spear3xx/include/mach/memory.h new file mode 100644 index 00000000000..51735221ea1 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/memory.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear3xx/include/mach/memory.h + * + * Memory map for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_MEMORY_H +#define __MACH_MEMORY_H + +#include <plat/memory.h> + +#endif /* __MACH_MEMORY_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h new file mode 100644 index 00000000000..38d767a1aba --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -0,0 +1,163 @@ +/* + * arch/arm/mach-spear3xx/include/mach/misc_regs.h + * + * Miscellaneous registers definitions for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_MISC_REGS_H +#define __MACH_MISC_REGS_H + +#include <mach/spear.h> + +#define MISC_BASE VA_SPEAR3XX_ICM3_MISC_REG_BASE + +#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) +#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) +#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) +#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) +#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) +#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) +/* PLL_CTR register masks */ +#define PLL_ENABLE 2 +#define PLL_MODE_SHIFT 4 +#define PLL_MODE_MASK 0x3 +#define PLL_MODE_NORMAL 0 +#define PLL_MODE_FRACTION 1 +#define PLL_MODE_DITH_DSB 2 +#define PLL_MODE_DITH_SSB 3 + +#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) +/* PLL FRQ register masks */ +#define PLL_DIV_N_SHIFT 0 +#define PLL_DIV_N_MASK 0xFF +#define PLL_DIV_P_SHIFT 8 +#define PLL_DIV_P_MASK 0x7 +#define PLL_NORM_FDBK_M_SHIFT 24 +#define PLL_NORM_FDBK_M_MASK 0xFF +#define PLL_DITH_FDBK_M_SHIFT 16 +#define PLL_DITH_FDBK_M_MASK 0xFFFF + +#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) +#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) +#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) +/* CORE CLK CFG register masks */ +#define PLL_HCLK_RATIO_SHIFT 10 +#define PLL_HCLK_RATIO_MASK 0x3 +#define HCLK_PCLK_RATIO_SHIFT 8 +#define HCLK_PCLK_RATIO_MASK 0x3 + +#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) +/* PERIP_CLK_CFG register masks */ +#define UART_CLK_SHIFT 4 +#define UART_CLK_MASK 0x1 +#define FIRDA_CLK_SHIFT 5 +#define FIRDA_CLK_MASK 0x3 +#define GPT0_CLK_SHIFT 8 +#define GPT1_CLK_SHIFT 11 +#define GPT2_CLK_SHIFT 12 +#define GPT_CLK_MASK 0x1 +#define AUX_CLK_PLL3_MASK 0 +#define AUX_CLK_PLL1_MASK 1 + +#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) +/* PERIP1_CLK_ENB register masks */ +#define UART_CLK_ENB 3 +#define SSP_CLK_ENB 5 +#define I2C_CLK_ENB 7 +#define JPEG_CLK_ENB 8 +#define FIRDA_CLK_ENB 10 +#define GPT1_CLK_ENB 11 +#define GPT2_CLK_ENB 12 +#define ADC_CLK_ENB 15 +#define RTC_CLK_ENB 17 +#define GPIO_CLK_ENB 18 +#define DMA_CLK_ENB 19 +#define SMI_CLK_ENB 21 +#define GMAC_CLK_ENB 23 +#define USBD_CLK_ENB 24 +#define USBH_CLK_ENB 25 +#define C3_CLK_ENB 31 + +#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) +#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) +#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) +/* PERIP1_SOF_RST register masks */ +#define JPEG_SOF_RST 8 + +#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) +#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) +#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) +#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) +#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) +/* gpt synthesizer register masks */ +#define GPT_MSCALE_SHIFT 0 +#define GPT_MSCALE_MASK 0xFFF +#define GPT_NSCALE_SHIFT 12 +#define GPT_NSCALE_MASK 0xF + +#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) +#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) +#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) +#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) +#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) +#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) +#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) +#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) +#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) +#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) +/* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_EQ_SEL_SHIFT 30 +#define AUX_EQ_SEL_MASK 1 +#define AUX_EQ1_SEL 0 +#define AUX_EQ2_SEL 1 +#define AUX_XSCALE_SHIFT 16 +#define AUX_XSCALE_MASK 0xFFF +#define AUX_YSCALE_SHIFT 0 +#define AUX_YSCALE_MASK 0xFFF + +#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) +#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) +#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) +#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) +#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) +#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) +#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) +#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) +#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) +#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) +#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) +#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) +#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) +#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) +#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) +#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) +#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) +#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) +#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) +#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) +#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) +#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) +#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) +#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) +#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) +#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) +#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) +#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) +#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) +#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) +#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) +#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) +#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) +#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) +#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) +#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) +#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) + +#endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h new file mode 100644 index 00000000000..dcca8568a48 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/spear.h @@ -0,0 +1,144 @@ +/* + * arch/arm/mach-spear3xx/include/mach/spear.h + * + * SPEAr3xx Machine family specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_SPEAR3XX_H +#define __MACH_SPEAR3XX_H + +#include <mach/hardware.h> +#include <mach/spear300.h> +#include <mach/spear310.h> +#include <mach/spear320.h> + +#define SPEAR3XX_ML_SDRAM_BASE 0x00000000 +#define SPEAR3XX_ML_SDRAM_SIZE 0x40000000 + +#define SPEAR3XX_ICM9_BASE 0xC0000000 +#define SPEAR3XX_ICM9_SIZE 0x10000000 + +/* ICM1 - Low speed connection */ +#define SPEAR3XX_ICM1_2_BASE 0xD0000000 +#define SPEAR3XX_ICM1_2_SIZE 0x10000000 + +#define SPEAR3XX_ICM1_UART_BASE 0xD0000000 +#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) +#define SPEAR3XX_ICM1_UART_SIZE 0x00080000 + +#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000 +#define SPEAR3XX_ICM1_ADC_SIZE 0x00080000 + +#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000 +#define SPEAR3XX_ICM1_SSP_SIZE 0x00080000 + +#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000 +#define SPEAR3XX_ICM1_I2C_SIZE 0x00080000 + +#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000 +#define SPEAR3XX_ICM1_JPEG_SIZE 0x00800000 + +#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000 +#define SPEAR3XX_ICM1_IRDA_SIZE 0x00080000 + +#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000 +#define SPEAR3XX_ICM1_SRAM_SIZE 0x05800000 + +/* ICM2 - Application Subsystem */ +#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000 +#define SPEAR3XX_ICM2_HWACCEL0_SIZE 0x00800000 + +#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000 +#define SPEAR3XX_ICM2_HWACCEL1_SIZE 0x00800000 + +/* ICM4 - High Speed Connection */ +#define SPEAR3XX_ICM4_BASE 0xE0000000 +#define SPEAR3XX_ICM4_SIZE 0x08000000 + +#define SPEAR3XX_ICM4_MII_BASE 0xE0800000 +#define SPEAR3XX_ICM4_MII_SIZE 0x00800000 + +#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000 +#define SPEAR3XX_ICM4_USBD_FIFO_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000 +#define SPEAR3XX_ICM4_USBD_CSR_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000 +#define SPEAR3XX_ICM4_USBD_PLDT_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000 +#define SPEAR3XX_ICM4_USB_EHCI0_1_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000 +#define SPEAR3XX_ICM4_USB_OHCI0_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000 +#define SPEAR3XX_ICM4_USB_OHCI1_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000 +#define SPEAR3XX_ICM4_USB_ARB_SIZE 0x00010000 + +/* ML1 - Multi Layer CPU Subsystem */ +#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000 +#define SPEAR3XX_ICM3_ML1_2_SIZE 0x0F000000 + +#define SPEAR3XX_ML1_TMR_BASE 0xF0000000 +#define SPEAR3XX_ML1_TMR_SIZE 0x00100000 + +#define SPEAR3XX_ML1_VIC_BASE 0xF1100000 +#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE) +#define SPEAR3XX_ML1_VIC_SIZE 0x00100000 + +/* ICM3 - Basic Subsystem */ +#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000 +#define SPEAR3XX_ICM3_SMEM_SIZE 0x04000000 + +#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000 +#define SPEAR3XX_ICM3_SMI_CTRL_SIZE 0x00200000 + +#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000 +#define SPEAR3XX_ICM3_DMA_SIZE 0x00200000 + +#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 +#define SPEAR3XX_ICM3_SDRAM_CTRL_SIZE 0x00200000 + +#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000 +#define SPEAR3XX_ICM3_TMR0_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000 +#define SPEAR3XX_ICM3_WDT_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000 +#define SPEAR3XX_ICM3_RTC_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000 +#define SPEAR3XX_ICM3_GPIO_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000 +#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) +#define SPEAR3XX_ICM3_SYS_CTRL_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000 +#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) +#define SPEAR3XX_ICM3_MISC_REG_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000 +#define SPEAR3XX_ICM3_TMR1_SIZE 0x00080000 + +/* Debug uart for linux, will be used for debug and uncompress messages */ +#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE +#define VA_SPEAR_DBG_UART_BASE VA_SPEAR3XX_ICM1_UART_BASE + +/* Sysctl base for spear platform */ +#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE +#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE + +#endif /* __MACH_SPEAR3XX_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h new file mode 100644 index 00000000000..ccaa76522ee --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/spear300.h @@ -0,0 +1,83 @@ +/* + * arch/arm/mach-spear3xx/include/mach/spear300.h + * + * SPEAr300 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR300 + +#ifndef __MACH_SPEAR300_H +#define __MACH_SPEAR300_H + +/* Base address of various IPs */ +#define SPEAR300_TELECOM_BASE 0x50000000 +#define SPEAR300_TELECOM_SIZE 0x10000000 + +/* Interrupt registers offsets and masks */ +#define SPEAR300_TELECOM_REG_SIZE 0x00010000 +#define INT_ENB_MASK_REG 0x54 +#define INT_STS_MASK_REG 0x58 +#define IT_PERS_S_IRQ_MASK (1 << 0) +#define IT_CHANGE_S_IRQ_MASK (1 << 1) +#define I2S_IRQ_MASK (1 << 2) +#define TDM_IRQ_MASK (1 << 3) +#define CAMERA_L_IRQ_MASK (1 << 4) +#define CAMERA_F_IRQ_MASK (1 << 5) +#define CAMERA_V_IRQ_MASK (1 << 6) +#define KEYBOARD_IRQ_MASK (1 << 7) +#define GPIO1_IRQ_MASK (1 << 8) + +#define SHIRQ_RAS1_MASK 0x1FF + +#define SPEAR300_CLCD_BASE 0x60000000 +#define SPEAR300_CLCD_SIZE 0x10000000 + +#define SPEAR300_SDIO_BASE 0x70000000 +#define SPEAR300_SDIO_SIZE 0x10000000 + +#define SPEAR300_NAND_0_BASE 0x80000000 +#define SPEAR300_NAND_0_SIZE 0x04000000 + +#define SPEAR300_NAND_1_BASE 0x84000000 +#define SPEAR300_NAND_1_SIZE 0x04000000 + +#define SPEAR300_NAND_2_BASE 0x88000000 +#define SPEAR300_NAND_2_SIZE 0x04000000 + +#define SPEAR300_NAND_3_BASE 0x8c000000 +#define SPEAR300_NAND_3_SIZE 0x04000000 + +#define SPEAR300_NOR_0_BASE 0x90000000 +#define SPEAR300_NOR_0_SIZE 0x01000000 + +#define SPEAR300_NOR_1_BASE 0x91000000 +#define SPEAR300_NOR_1_SIZE 0x01000000 + +#define SPEAR300_NOR_2_BASE 0x92000000 +#define SPEAR300_NOR_2_SIZE 0x01000000 + +#define SPEAR300_NOR_3_BASE 0x93000000 +#define SPEAR300_NOR_3_SIZE 0x01000000 + +#define SPEAR300_FSMC_BASE 0x94000000 +#define SPEAR300_FSMC_SIZE 0x05000000 + +#define SPEAR300_SOC_CONFIG_BASE 0x99000000 +#define SPEAR300_SOC_CONFIG_SIZE 0x00000008 + +#define SPEAR300_KEYBOARD_BASE 0xA0000000 +#define SPEAR300_KEYBOARD_SIZE 0x09000000 + +#define SPEAR300_GPIO_BASE 0xA9000000 +#define SPEAR300_GPIO_SIZE 0x07000000 + +#endif /* __MACH_SPEAR300_H */ + +#endif /* CONFIG_MACH_SPEAR300 */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h new file mode 100644 index 00000000000..b27bb8af330 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/spear310.h @@ -0,0 +1,70 @@ +/* + * arch/arm/mach-spear3xx/include/mach/spear310.h + * + * SPEAr310 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR310 + +#ifndef __MACH_SPEAR310_H +#define __MACH_SPEAR310_H + +#define SPEAR310_NAND_BASE 0x40000000 +#define SPEAR310_NAND_SIZE 0x04000000 + +#define SPEAR310_FSMC_BASE 0x44000000 +#define SPEAR310_FSMC_SIZE 0x01000000 + +#define SPEAR310_UART1_BASE 0xB2000000 +#define SPEAR310_UART2_BASE 0xB2080000 +#define SPEAR310_UART3_BASE 0xB2100000 +#define SPEAR310_UART4_BASE 0xB2180000 +#define SPEAR310_UART5_BASE 0xB2200000 +#define SPEAR310_UART_SIZE 0x00080000 + +#define SPEAR310_HDLC_BASE 0xB2800000 +#define SPEAR310_HDLC_SIZE 0x00800000 + +#define SPEAR310_RS485_0_BASE 0xB3000000 +#define SPEAR310_RS485_0_SIZE 0x00800000 + +#define SPEAR310_RS485_1_BASE 0xB3800000 +#define SPEAR310_RS485_1_SIZE 0x00800000 + +#define SPEAR310_SOC_CONFIG_BASE 0xB4000000 +#define SPEAR310_SOC_CONFIG_SIZE 0x00000070 +/* Interrupt registers offsets and masks */ +#define INT_STS_MASK_REG 0x04 +#define SMII0_IRQ_MASK (1 << 0) +#define SMII1_IRQ_MASK (1 << 1) +#define SMII2_IRQ_MASK (1 << 2) +#define SMII3_IRQ_MASK (1 << 3) +#define WAKEUP_SMII0_IRQ_MASK (1 << 4) +#define WAKEUP_SMII1_IRQ_MASK (1 << 5) +#define WAKEUP_SMII2_IRQ_MASK (1 << 6) +#define WAKEUP_SMII3_IRQ_MASK (1 << 7) +#define UART1_IRQ_MASK (1 << 8) +#define UART2_IRQ_MASK (1 << 9) +#define UART3_IRQ_MASK (1 << 10) +#define UART4_IRQ_MASK (1 << 11) +#define UART5_IRQ_MASK (1 << 12) +#define EMI_IRQ_MASK (1 << 13) +#define TDM_HDLC_IRQ_MASK (1 << 14) +#define RS485_0_IRQ_MASK (1 << 15) +#define RS485_1_IRQ_MASK (1 << 16) + +#define SHIRQ_RAS1_MASK 0x000FF +#define SHIRQ_RAS2_MASK 0x01F00 +#define SHIRQ_RAS3_MASK 0x02000 +#define SHIRQ_INTRCOMM_RAS_MASK 0x1C000 + +#endif /* __MACH_SPEAR310_H */ + +#endif /* CONFIG_MACH_SPEAR310 */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h new file mode 100644 index 00000000000..cacf17a958c --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/spear320.h @@ -0,0 +1,96 @@ +/* + * arch/arm/mach-spear3xx/include/mach/spear320.h + * + * SPEAr320 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR320 + +#ifndef __MACH_SPEAR320_H +#define __MACH_SPEAR320_H + +#define SPEAR320_EMI_CTRL_BASE 0x40000000 +#define SPEAR320_EMI_CTRL_SIZE 0x08000000 + +#define SPEAR320_FSMC_BASE 0x4C000000 +#define SPEAR320_FSMC_SIZE 0x01000000 + +#define SPEAR320_I2S_BASE 0x60000000 +#define SPEAR320_I2S_SIZE 0x10000000 + +#define SPEAR320_SDIO_BASE 0x70000000 +#define SPEAR320_SDIO_SIZE 0x10000000 + +#define SPEAR320_CLCD_BASE 0x90000000 +#define SPEAR320_CLCD_SIZE 0x10000000 + +#define SPEAR320_PAR_PORT_BASE 0xA0000000 +#define SPEAR320_PAR_PORT_SIZE 0x01000000 + +#define SPEAR320_CAN0_BASE 0xA1000000 +#define SPEAR320_CAN0_SIZE 0x01000000 + +#define SPEAR320_CAN1_BASE 0xA2000000 +#define SPEAR320_CAN1_SIZE 0x01000000 + +#define SPEAR320_UART1_BASE 0xA3000000 +#define SPEAR320_UART2_BASE 0xA4000000 +#define SPEAR320_UART_SIZE 0x01000000 + +#define SPEAR320_SSP0_BASE 0xA5000000 +#define SPEAR320_SSP0_SIZE 0x01000000 + +#define SPEAR320_SSP1_BASE 0xA6000000 +#define SPEAR320_SSP1_SIZE 0x01000000 + +#define SPEAR320_I2C_BASE 0xA7000000 +#define SPEAR320_I2C_SIZE 0x01000000 + +#define SPEAR320_PWM_BASE 0xA8000000 +#define SPEAR320_PWM_SIZE 0x01000000 + +#define SPEAR320_SMII0_BASE 0xAA000000 +#define SPEAR320_SMII0_SIZE 0x01000000 + +#define SPEAR320_SMII1_BASE 0xAB000000 +#define SPEAR320_SMII1_SIZE 0x01000000 + +#define SPEAR320_SOC_CONFIG_BASE 0xB4000000 +#define SPEAR320_SOC_CONFIG_SIZE 0x00000070 +/* Interrupt registers offsets and masks */ +#define INT_STS_MASK_REG 0x04 +#define INT_CLR_MASK_REG 0x04 +#define INT_ENB_MASK_REG 0x08 +#define GPIO_IRQ_MASK (1 << 0) +#define I2S_PLAY_IRQ_MASK (1 << 1) +#define I2S_REC_IRQ_MASK (1 << 2) +#define EMI_IRQ_MASK (1 << 7) +#define CLCD_IRQ_MASK (1 << 8) +#define SPP_IRQ_MASK (1 << 9) +#define SDIO_IRQ_MASK (1 << 10) +#define CAN_U_IRQ_MASK (1 << 11) +#define CAN_L_IRQ_MASK (1 << 12) +#define UART1_IRQ_MASK (1 << 13) +#define UART2_IRQ_MASK (1 << 14) +#define SSP1_IRQ_MASK (1 << 15) +#define SSP2_IRQ_MASK (1 << 16) +#define SMII0_IRQ_MASK (1 << 17) +#define MII1_SMII1_IRQ_MASK (1 << 18) +#define WAKEUP_SMII0_IRQ_MASK (1 << 19) +#define WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) +#define I2C1_IRQ_MASK (1 << 21) + +#define SHIRQ_RAS1_MASK 0x000380 +#define SHIRQ_RAS3_MASK 0x000007 +#define SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 + +#endif /* __MACH_SPEAR320_H */ + +#endif /* CONFIG_MACH_SPEAR320 */ diff --git a/arch/arm/mach-spear3xx/include/mach/system.h b/arch/arm/mach-spear3xx/include/mach/system.h new file mode 100644 index 00000000000..92cee6335c9 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/system.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear3xx/include/mach/system.h + * + * SPEAr3xx Machine family specific architecture functions + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_SYSTEM_H +#define __MACH_SYSTEM_H + +#include <plat/system.h> + +#endif /* __MACH_SYSTEM_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/timex.h b/arch/arm/mach-spear3xx/include/mach/timex.h new file mode 100644 index 00000000000..a38cc9de876 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/timex.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear3xx/include/mach/timex.h + * + * SPEAr3XX machine family specific timex definitions + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_TIMEX_H +#define __MACH_TIMEX_H + +#include <plat/timex.h> + +#endif /* __MACH_TIMEX_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/uncompress.h b/arch/arm/mach-spear3xx/include/mach/uncompress.h new file mode 100644 index 00000000000..53ba8bbc0df --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/uncompress.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear3xx/include/mach/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_UNCOMPRESS_H +#define __MACH_UNCOMPRESS_H + +#include <plat/uncompress.h> + +#endif /* __MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h new file mode 100644 index 00000000000..df977b3c9a6 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/vmalloc.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear3xx/include/mach/vmalloc.h + * + * Defining Vmalloc area for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_VMALLOC_H +#define __MACH_VMALLOC_H + +#include <plat/vmalloc.h> + +#endif /* __MACH_VMALLOC_H */ diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c new file mode 100644 index 00000000000..3560f8c1e72 --- /dev/null +++ b/arch/arm/mach-spear3xx/spear300.c @@ -0,0 +1,468 @@ +/* + * arch/arm/mach-spear3xx/spear300.c + * + * SPEAr300 machine source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/types.h> +#include <linux/amba/pl061.h> +#include <linux/ptrace.h> +#include <asm/irq.h> +#include <mach/generic.h> +#include <mach/spear.h> +#include <plat/shirq.h> + +/* pad multiplexing support */ +/* muxing registers */ +#define PAD_MUX_CONFIG_REG 0x00 +#define MODE_CONFIG_REG 0x04 + +/* modes */ +#define NAND_MODE (1 << 0) +#define NOR_MODE (1 << 1) +#define PHOTO_FRAME_MODE (1 << 2) +#define LEND_IP_PHONE_MODE (1 << 3) +#define HEND_IP_PHONE_MODE (1 << 4) +#define LEND_WIFI_PHONE_MODE (1 << 5) +#define HEND_WIFI_PHONE_MODE (1 << 6) +#define ATA_PABX_WI2S_MODE (1 << 7) +#define ATA_PABX_I2S_MODE (1 << 8) +#define CAML_LCDW_MODE (1 << 9) +#define CAMU_LCD_MODE (1 << 10) +#define CAMU_WLCD_MODE (1 << 11) +#define CAML_LCD_MODE (1 << 12) +#define ALL_MODES 0x1FFF + +struct pmx_mode nand_mode = { + .id = NAND_MODE, + .name = "nand mode", + .mask = 0x00, +}; + +struct pmx_mode nor_mode = { + .id = NOR_MODE, + .name = "nor mode", + .mask = 0x01, +}; + +struct pmx_mode photo_frame_mode = { + .id = PHOTO_FRAME_MODE, + .name = "photo frame mode", + .mask = 0x02, +}; + +struct pmx_mode lend_ip_phone_mode = { + .id = LEND_IP_PHONE_MODE, + .name = "lend ip phone mode", + .mask = 0x03, +}; + +struct pmx_mode hend_ip_phone_mode = { + .id = HEND_IP_PHONE_MODE, + .name = "hend ip phone mode", + .mask = 0x04, +}; + +struct pmx_mode lend_wifi_phone_mode = { + .id = LEND_WIFI_PHONE_MODE, + .name = "lend wifi phone mode", + .mask = 0x05, +}; + +struct pmx_mode hend_wifi_phone_mode = { + .id = HEND_WIFI_PHONE_MODE, + .name = "hend wifi phone mode", + .mask = 0x06, +}; + +struct pmx_mode ata_pabx_wi2s_mode = { + .id = ATA_PABX_WI2S_MODE, + .name = "ata pabx wi2s mode", + .mask = 0x07, +}; + +struct pmx_mode ata_pabx_i2s_mode = { + .id = ATA_PABX_I2S_MODE, + .name = "ata pabx i2s mode", + .mask = 0x08, +}; + +struct pmx_mode caml_lcdw_mode = { + .id = CAML_LCDW_MODE, + .name = "caml lcdw mode", + .mask = 0x0C, +}; + +struct pmx_mode camu_lcd_mode = { + .id = CAMU_LCD_MODE, + .name = "camu lcd mode", + .mask = 0x0D, +}; + +struct pmx_mode camu_wlcd_mode = { + .id = CAMU_WLCD_MODE, + .name = "camu wlcd mode", + .mask = 0x0E, +}; + +struct pmx_mode caml_lcd_mode = { + .id = CAML_LCD_MODE, + .name = "caml lcd mode", + .mask = 0x0F, +}; + +/* devices */ +struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { + { + .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev pmx_fsmc_2_chips = { + .name = "fsmc_2_chips", + .modes = pmx_fsmc_2_chips_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { + { + .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, + .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, + }, +}; + +struct pmx_dev pmx_fsmc_4_chips = { + .name = "fsmc_4_chips", + .modes = pmx_fsmc_4_chips_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_keyboard_modes[] = { + { + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | + LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | + CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE | + CAML_LCD_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev pmx_keyboard = { + .name = "keyboard", + .modes = pmx_keyboard_modes, + .mode_count = ARRAY_SIZE(pmx_keyboard_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_clcd_modes[] = { + { + .ids = PHOTO_FRAME_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK , + }, { + .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | + CAMU_LCD_MODE | CAML_LCD_MODE, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev pmx_clcd = { + .name = "clcd", + .modes = pmx_clcd_modes, + .mode_count = ARRAY_SIZE(pmx_clcd_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_telecom_gpio_modes[] = { + { + .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE, + .mask = PMX_MII_MASK, + }, { + .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, { + .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK, + }, { + .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK, + }, { + .ids = ATA_PABX_WI2S_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK + | PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev pmx_telecom_gpio = { + .name = "telecom_gpio", + .modes = pmx_telecom_gpio_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_telecom_tdm_modes[] = { + { + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE + | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE + | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev pmx_telecom_tdm = { + .name = "telecom_tdm", + .modes = pmx_telecom_tdm_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { + { + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | + LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE + | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | + CAML_LCDW_MODE | CAML_LCD_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev pmx_telecom_spi_cs_i2c_clk = { + .name = "telecom_spi_cs_i2c_clk", + .modes = pmx_telecom_spi_cs_i2c_clk_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_telecom_camera_modes[] = { + { + .ids = CAML_LCDW_MODE | CAML_LCD_MODE, + .mask = PMX_MII_MASK, + }, { + .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_telecom_camera = { + .name = "telecom_camera", + .modes = pmx_telecom_camera_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_telecom_dac_modes[] = { + { + .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev pmx_telecom_dac = { + .name = "telecom_dac", + .modes = pmx_telecom_dac_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_telecom_i2s_modes[] = { + { + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE + | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | + ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev pmx_telecom_i2s = { + .name = "telecom_i2s", + .modes = pmx_telecom_i2s_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { + { + .ids = NAND_MODE | NOR_MODE, + .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | + PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev pmx_telecom_boot_pins = { + .name = "telecom_boot_pins", + .modes = pmx_telecom_boot_pins_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = { + { + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | + CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE | + ATA_PABX_I2S_MODE, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev pmx_telecom_sdio_4bit = { + .name = "telecom_sdio_4bit", + .modes = pmx_telecom_sdio_4bit_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_sdio_4bit_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = { + { + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | + CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_telecom_sdio_8bit = { + .name = "telecom_sdio_8bit", + .modes = pmx_telecom_sdio_8bit_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_sdio_8bit_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_gpio1_modes[] = { + { + .ids = PHOTO_FRAME_MODE, + .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | + PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev pmx_gpio1 = { + .name = "arm gpio1", + .modes = pmx_gpio1_modes, + .mode_count = ARRAY_SIZE(pmx_gpio1_modes), + .enb_on_reset = 1, +}; + +/* pmx driver structure */ +struct pmx_driver pmx_driver = { + .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f}, + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, +}; + +/* Add spear300 specific devices here */ +/* arm gpio1 device registeration */ +static struct pl061_platform_data gpio1_plat_data = { + .gpio_base = 8, + .irq_base = SPEAR_GPIO1_INT_BASE, +}; + +struct amba_device gpio1_device = { + .dev = { + .init_name = "gpio1", + .platform_data = &gpio1_plat_data, + }, + .res = { + .start = SPEAR300_GPIO_BASE, + .end = SPEAR300_GPIO_BASE + SPEAR300_GPIO_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {VIRQ_GPIO1, NO_IRQ}, +}; + +/* spear3xx shared irq */ +struct shirq_dev_config shirq_ras1_config[] = { + { + .virq = VIRQ_IT_PERS_S, + .enb_mask = IT_PERS_S_IRQ_MASK, + .status_mask = IT_PERS_S_IRQ_MASK, + }, { + .virq = VIRQ_IT_CHANGE_S, + .enb_mask = IT_CHANGE_S_IRQ_MASK, + .status_mask = IT_CHANGE_S_IRQ_MASK, + }, { + .virq = VIRQ_I2S, + .enb_mask = I2S_IRQ_MASK, + .status_mask = I2S_IRQ_MASK, + }, { + .virq = VIRQ_TDM, + .enb_mask = TDM_IRQ_MASK, + .status_mask = TDM_IRQ_MASK, + }, { + .virq = VIRQ_CAMERA_L, + .enb_mask = CAMERA_L_IRQ_MASK, + .status_mask = CAMERA_L_IRQ_MASK, + }, { + .virq = VIRQ_CAMERA_F, + .enb_mask = CAMERA_F_IRQ_MASK, + .status_mask = CAMERA_F_IRQ_MASK, + }, { + .virq = VIRQ_CAMERA_V, + .enb_mask = CAMERA_V_IRQ_MASK, + .status_mask = CAMERA_V_IRQ_MASK, + }, { + .virq = VIRQ_KEYBOARD, + .enb_mask = KEYBOARD_IRQ_MASK, + .status_mask = KEYBOARD_IRQ_MASK, + }, { + .virq = VIRQ_GPIO1, + .enb_mask = GPIO1_IRQ_MASK, + .status_mask = GPIO1_IRQ_MASK, + }, +}; + +struct spear_shirq shirq_ras1 = { + .irq = IRQ_GEN_RAS_1, + .dev_config = shirq_ras1_config, + .dev_count = ARRAY_SIZE(shirq_ras1_config), + .regs = { + .enb_reg = INT_ENB_MASK_REG, + .status_reg = INT_STS_MASK_REG, + .status_reg_mask = SHIRQ_RAS1_MASK, + .clear_reg = -1, + }, +}; + +/* spear300 routines */ +void __init spear300_init(void) +{ + int ret = 0; + + /* call spear3xx family common init function */ + spear3xx_init(); + + /* shared irq registeration */ + shirq_ras1.regs.base = + ioremap(SPEAR300_TELECOM_BASE, SPEAR300_TELECOM_REG_SIZE); + if (shirq_ras1.regs.base) { + ret = spear_shirq_register(&shirq_ras1); + if (ret) + printk(KERN_ERR "Error registering Shared IRQ\n"); + } +} + +void spear300_pmx_init(void) +{ + spear_pmx_init(&pmx_driver, SPEAR300_SOC_CONFIG_BASE, + SPEAR300_SOC_CONFIG_SIZE); +} diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c new file mode 100644 index 00000000000..bb21db152a2 --- /dev/null +++ b/arch/arm/mach-spear3xx/spear300_evb.c @@ -0,0 +1,77 @@ +/* + * arch/arm/mach-spear3xx/spear300_evb.c + * + * SPEAr300 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <mach/generic.h> +#include <mach/spear.h> + +/* padmux devices to enable */ +static struct pmx_dev *pmx_devs[] = { + /* spear3xx specific devices */ + &pmx_i2c, + &pmx_ssp_cs, + &pmx_ssp, + &pmx_mii, + &pmx_uart0, + + /* spear300 specific devices */ + &pmx_fsmc_2_chips, + &pmx_clcd, + &pmx_telecom_sdio_4bit, + &pmx_gpio1, +}; + +static struct amba_device *amba_devs[] __initdata = { + /* spear3xx specific devices */ + &gpio_device, + &uart_device, + + /* spear300 specific devices */ + &gpio1_device, +}; + +static struct platform_device *plat_devs[] __initdata = { + /* spear3xx specific devices */ + + /* spear300 specific devices */ +}; + +static void __init spear300_evb_init(void) +{ + unsigned int i; + + /* call spear300 machine init function */ + spear300_init(); + + /* padmux initialization */ + pmx_driver.mode = &photo_frame_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); + spear300_pmx_init(); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR300, "ST-SPEAR300-EVB") + .boot_params = 0x00000100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .timer = &spear_sys_timer, + .init_machine = spear300_evb_init, +MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c new file mode 100644 index 00000000000..96a1ab824ba --- /dev/null +++ b/arch/arm/mach-spear3xx/spear310.c @@ -0,0 +1,302 @@ +/* + * arch/arm/mach-spear3xx/spear310.c + * + * SPEAr310 machine source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/ptrace.h> +#include <asm/irq.h> +#include <mach/generic.h> +#include <mach/spear.h> +#include <plat/shirq.h> + +/* pad multiplexing support */ +/* muxing registers */ +#define PAD_MUX_CONFIG_REG 0x08 + +/* devices */ +struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev pmx_emi_cs_0_1_4_5 = { + .name = "emi_cs_0_1_4_5", + .modes = pmx_emi_cs_0_1_4_5_modes, + .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev pmx_emi_cs_2_3 = { + .name = "emi_cs_2_3", + .modes = pmx_emi_cs_2_3_modes, + .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_uart1_modes[] = { + { + .ids = 0x00, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev pmx_uart1 = { + .name = "uart1", + .modes = pmx_uart1_modes, + .mode_count = ARRAY_SIZE(pmx_uart1_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_uart2_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev pmx_uart2 = { + .name = "uart2", + .modes = pmx_uart2_modes, + .mode_count = ARRAY_SIZE(pmx_uart2_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_uart3_4_5_modes[] = { + { + .ids = 0x00, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev pmx_uart3_4_5 = { + .name = "uart3_4_5", + .modes = pmx_uart3_4_5_modes, + .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_fsmc_modes[] = { + { + .ids = 0x00, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev pmx_fsmc = { + .name = "fsmc", + .modes = pmx_fsmc_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_rs485_0_1_modes[] = { + { + .ids = 0x00, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_rs485_0_1 = { + .name = "rs485_0_1", + .modes = pmx_rs485_0_1_modes, + .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_tdm0_modes[] = { + { + .ids = 0x00, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_tdm0 = { + .name = "tdm0", + .modes = pmx_tdm0_modes, + .mode_count = ARRAY_SIZE(pmx_tdm0_modes), + .enb_on_reset = 1, +}; + +/* pmx driver structure */ +struct pmx_driver pmx_driver = { + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, +}; + +/* Add spear310 specific devices here */ + +/* spear3xx shared irq */ +struct shirq_dev_config shirq_ras1_config[] = { + { + .virq = VIRQ_SMII0, + .status_mask = SMII0_IRQ_MASK, + }, { + .virq = VIRQ_SMII1, + .status_mask = SMII1_IRQ_MASK, + }, { + .virq = VIRQ_SMII2, + .status_mask = SMII2_IRQ_MASK, + }, { + .virq = VIRQ_SMII3, + .status_mask = SMII3_IRQ_MASK, + }, { + .virq = VIRQ_WAKEUP_SMII0, + .status_mask = WAKEUP_SMII0_IRQ_MASK, + }, { + .virq = VIRQ_WAKEUP_SMII1, + .status_mask = WAKEUP_SMII1_IRQ_MASK, + }, { + .virq = VIRQ_WAKEUP_SMII2, + .status_mask = WAKEUP_SMII2_IRQ_MASK, + }, { + .virq = VIRQ_WAKEUP_SMII3, + .status_mask = WAKEUP_SMII3_IRQ_MASK, + }, +}; + +struct spear_shirq shirq_ras1 = { + .irq = IRQ_GEN_RAS_1, + .dev_config = shirq_ras1_config, + .dev_count = ARRAY_SIZE(shirq_ras1_config), + .regs = { + .enb_reg = -1, + .status_reg = INT_STS_MASK_REG, + .status_reg_mask = SHIRQ_RAS1_MASK, + .clear_reg = -1, + }, +}; + +struct shirq_dev_config shirq_ras2_config[] = { + { + .virq = VIRQ_UART1, + .status_mask = UART1_IRQ_MASK, + }, { + .virq = VIRQ_UART2, + .status_mask = UART2_IRQ_MASK, + }, { + .virq = VIRQ_UART3, + .status_mask = UART3_IRQ_MASK, + }, { + .virq = VIRQ_UART4, + .status_mask = UART4_IRQ_MASK, + }, { + .virq = VIRQ_UART5, + .status_mask = UART5_IRQ_MASK, + }, +}; + +struct spear_shirq shirq_ras2 = { + .irq = IRQ_GEN_RAS_2, + .dev_config = shirq_ras2_config, + .dev_count = ARRAY_SIZE(shirq_ras2_config), + .regs = { + .enb_reg = -1, + .status_reg = INT_STS_MASK_REG, + .status_reg_mask = SHIRQ_RAS2_MASK, + .clear_reg = -1, + }, +}; + +struct shirq_dev_config shirq_ras3_config[] = { + { + .virq = VIRQ_EMI, + .status_mask = EMI_IRQ_MASK, + }, +}; + +struct spear_shirq shirq_ras3 = { + .irq = IRQ_GEN_RAS_3, + .dev_config = shirq_ras3_config, + .dev_count = ARRAY_SIZE(shirq_ras3_config), + .regs = { + .enb_reg = -1, + .status_reg = INT_STS_MASK_REG, + .status_reg_mask = SHIRQ_RAS3_MASK, + .clear_reg = -1, + }, +}; + +struct shirq_dev_config shirq_intrcomm_ras_config[] = { + { + .virq = VIRQ_TDM_HDLC, + .status_mask = TDM_HDLC_IRQ_MASK, + }, { + .virq = VIRQ_RS485_0, + .status_mask = RS485_0_IRQ_MASK, + }, { + .virq = VIRQ_RS485_1, + .status_mask = RS485_1_IRQ_MASK, + }, +}; + +struct spear_shirq shirq_intrcomm_ras = { + .irq = IRQ_INTRCOMM_RAS_ARM, + .dev_config = shirq_intrcomm_ras_config, + .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), + .regs = { + .enb_reg = -1, + .status_reg = INT_STS_MASK_REG, + .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, + .clear_reg = -1, + }, +}; + +/* spear310 routines */ +void __init spear310_init(void) +{ + void __iomem *base; + int ret = 0; + + /* call spear3xx family common init function */ + spear3xx_init(); + + /* shared irq registeration */ + base = ioremap(SPEAR310_SOC_CONFIG_BASE, SPEAR310_SOC_CONFIG_SIZE); + if (base) { + /* shirq 1 */ + shirq_ras1.regs.base = base; + ret = spear_shirq_register(&shirq_ras1); + if (ret) + printk(KERN_ERR "Error registering Shared IRQ 1\n"); + + /* shirq 2 */ + shirq_ras2.regs.base = base; + ret = spear_shirq_register(&shirq_ras2); + if (ret) + printk(KERN_ERR "Error registering Shared IRQ 2\n"); + + /* shirq 3 */ + shirq_ras3.regs.base = base; + ret = spear_shirq_register(&shirq_ras3); + if (ret) + printk(KERN_ERR "Error registering Shared IRQ 3\n"); + + /* shirq 4 */ + shirq_intrcomm_ras.regs.base = base; + ret = spear_shirq_register(&shirq_intrcomm_ras); + if (ret) + printk(KERN_ERR "Error registering Shared IRQ 4\n"); + } +} + +void spear310_pmx_init(void) +{ + spear_pmx_init(&pmx_driver, SPEAR310_SOC_CONFIG_BASE, + SPEAR310_SOC_CONFIG_SIZE); +} diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c new file mode 100644 index 00000000000..7facf664319 --- /dev/null +++ b/arch/arm/mach-spear3xx/spear310_evb.c @@ -0,0 +1,84 @@ +/* + * arch/arm/mach-spear3xx/spear310_evb.c + * + * SPEAr310 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <mach/generic.h> +#include <mach/spear.h> + +/* padmux devices to enable */ +static struct pmx_dev *pmx_devs[] = { + /* spear3xx specific devices */ + &pmx_i2c, + &pmx_ssp, + &pmx_gpio_pin0, + &pmx_gpio_pin1, + &pmx_gpio_pin2, + &pmx_gpio_pin3, + &pmx_gpio_pin4, + &pmx_gpio_pin5, + &pmx_uart0, + + /* spear310 specific devices */ + &pmx_emi_cs_0_1_4_5, + &pmx_emi_cs_2_3, + &pmx_uart1, + &pmx_uart2, + &pmx_uart3_4_5, + &pmx_fsmc, + &pmx_rs485_0_1, + &pmx_tdm0, +}; + +static struct amba_device *amba_devs[] __initdata = { + /* spear3xx specific devices */ + &gpio_device, + &uart_device, + + /* spear310 specific devices */ +}; + +static struct platform_device *plat_devs[] __initdata = { + /* spear3xx specific devices */ + + /* spear310 specific devices */ +}; + +static void __init spear310_evb_init(void) +{ + unsigned int i; + + /* call spear310 machine init function */ + spear310_init(); + + /* padmux initialization */ + pmx_driver.mode = NULL; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); + spear310_pmx_init(); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR310, "ST-SPEAR310-EVB") + .boot_params = 0x00000100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .timer = &spear_sys_timer, + .init_machine = spear310_evb_init, +MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c new file mode 100644 index 00000000000..6a121954936 --- /dev/null +++ b/arch/arm/mach-spear3xx/spear320.c @@ -0,0 +1,549 @@ +/* + * arch/arm/mach-spear3xx/spear320.c + * + * SPEAr320 machine source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/ptrace.h> +#include <asm/irq.h> +#include <mach/generic.h> +#include <mach/spear.h> +#include <plat/shirq.h> + +/* pad multiplexing support */ +/* muxing registers */ +#define PAD_MUX_CONFIG_REG 0x0C +#define MODE_CONFIG_REG 0x10 + +/* modes */ +#define AUTO_NET_SMII_MODE (1 << 0) +#define AUTO_NET_MII_MODE (1 << 1) +#define AUTO_EXP_MODE (1 << 2) +#define SMALL_PRINTERS_MODE (1 << 3) +#define ALL_MODES 0xF + +struct pmx_mode auto_net_smii_mode = { + .id = AUTO_NET_SMII_MODE, + .name = "Automation Networking SMII Mode", + .mask = 0x00, +}; + +struct pmx_mode auto_net_mii_mode = { + .id = AUTO_NET_MII_MODE, + .name = "Automation Networking MII Mode", + .mask = 0x01, +}; + +struct pmx_mode auto_exp_mode = { + .id = AUTO_EXP_MODE, + .name = "Automation Expanded Mode", + .mask = 0x02, +}; + +struct pmx_mode small_printers_mode = { + .id = SMALL_PRINTERS_MODE, + .name = "Small Printers Mode", + .mask = 0x03, +}; + +/* devices */ +struct pmx_dev_mode pmx_clcd_modes[] = { + { + .ids = AUTO_NET_SMII_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev pmx_clcd = { + .name = "clcd", + .modes = pmx_clcd_modes, + .mode_count = ARRAY_SIZE(pmx_clcd_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_emi_modes[] = { + { + .ids = AUTO_EXP_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev pmx_emi = { + .name = "emi", + .modes = pmx_emi_modes, + .mode_count = ARRAY_SIZE(pmx_emi_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_fsmc_modes[] = { + { + .ids = ALL_MODES, + .mask = 0x0, + }, +}; + +struct pmx_dev pmx_fsmc = { + .name = "fsmc", + .modes = pmx_fsmc_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_spp_modes[] = { + { + .ids = SMALL_PRINTERS_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev pmx_spp = { + .name = "spp", + .modes = pmx_spp_modes, + .mode_count = ARRAY_SIZE(pmx_spp_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_sdio_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | + SMALL_PRINTERS_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev pmx_sdio = { + .name = "sdio", + .modes = pmx_sdio_modes, + .mode_count = ARRAY_SIZE(pmx_sdio_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_i2s_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev pmx_i2s = { + .name = "i2s", + .modes = pmx_i2s_modes, + .mode_count = ARRAY_SIZE(pmx_i2s_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_uart1_modes[] = { + { + .ids = ALL_MODES, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, + }, +}; + +struct pmx_dev pmx_uart1 = { + .name = "uart1", + .modes = pmx_uart1_modes, + .mode_count = ARRAY_SIZE(pmx_uart1_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_uart1_modem_modes[] = { + { + .ids = AUTO_EXP_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | + PMX_SSP_CS_MASK, + }, { + .ids = SMALL_PRINTERS_MODE, + .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | + PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev pmx_uart1_modem = { + .name = "uart1_modem", + .modes = pmx_uart1_modem_modes, + .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_uart2_modes[] = { + { + .ids = ALL_MODES, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev pmx_uart2 = { + .name = "uart2", + .modes = pmx_uart2_modes, + .mode_count = ARRAY_SIZE(pmx_uart2_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_touchscreen_modes[] = { + { + .ids = AUTO_NET_SMII_MODE, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev pmx_touchscreen = { + .name = "touchscreen", + .modes = pmx_touchscreen_modes, + .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_can_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, + .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev pmx_can = { + .name = "can", + .modes = pmx_can_modes, + .mode_count = ARRAY_SIZE(pmx_can_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_sdio_led_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev pmx_sdio_led = { + .name = "sdio_led", + .modes = pmx_sdio_led_modes, + .mode_count = ARRAY_SIZE(pmx_sdio_led_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_pwm0_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_pwm0 = { + .name = "pwm0", + .modes = pmx_pwm0_modes, + .mode_count = ARRAY_SIZE(pmx_pwm0_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_pwm1_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_pwm1 = { + .name = "pwm1", + .modes = pmx_pwm1_modes, + .mode_count = ARRAY_SIZE(pmx_pwm1_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_pwm2_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_SSP_CS_MASK, + }, { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_pwm2 = { + .name = "pwm2", + .modes = pmx_pwm2_modes, + .mode_count = ARRAY_SIZE(pmx_pwm2_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_pwm3_modes[] = { + { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_pwm3 = { + .name = "pwm3", + .modes = pmx_pwm3_modes, + .mode_count = ARRAY_SIZE(pmx_pwm3_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_ssp1_modes[] = { + { + .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_ssp1 = { + .name = "ssp1", + .modes = pmx_ssp1_modes, + .mode_count = ARRAY_SIZE(pmx_ssp1_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_ssp2_modes[] = { + { + .ids = AUTO_NET_SMII_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_ssp2 = { + .name = "ssp2", + .modes = pmx_ssp2_modes, + .mode_count = ARRAY_SIZE(pmx_ssp2_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_mii1_modes[] = { + { + .ids = AUTO_NET_MII_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev pmx_mii1 = { + .name = "mii1", + .modes = pmx_mii1_modes, + .mode_count = ARRAY_SIZE(pmx_mii1_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_smii0_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_smii0 = { + .name = "smii0", + .modes = pmx_smii0_modes, + .mode_count = ARRAY_SIZE(pmx_smii0_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_smii1_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_smii1 = { + .name = "smii1", + .modes = pmx_smii1_modes, + .mode_count = ARRAY_SIZE(pmx_smii1_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_i2c1_modes[] = { + { + .ids = AUTO_EXP_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev pmx_i2c1 = { + .name = "i2c1", + .modes = pmx_i2c1_modes, + .mode_count = ARRAY_SIZE(pmx_i2c1_modes), + .enb_on_reset = 1, +}; + +/* pmx driver structure */ +struct pmx_driver pmx_driver = { + .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, +}; + +/* Add spear320 specific devices here */ + +/* spear3xx shared irq */ +struct shirq_dev_config shirq_ras1_config[] = { + { + .virq = VIRQ_EMI, + .status_mask = EMI_IRQ_MASK, + .clear_mask = EMI_IRQ_MASK, + }, { + .virq = VIRQ_CLCD, + .status_mask = CLCD_IRQ_MASK, + .clear_mask = CLCD_IRQ_MASK, + }, { + .virq = VIRQ_SPP, + .status_mask = SPP_IRQ_MASK, + .clear_mask = SPP_IRQ_MASK, + }, +}; + +struct spear_shirq shirq_ras1 = { + .irq = IRQ_GEN_RAS_1, + .dev_config = shirq_ras1_config, + .dev_count = ARRAY_SIZE(shirq_ras1_config), + .regs = { + .enb_reg = -1, + .status_reg = INT_STS_MASK_REG, + .status_reg_mask = SHIRQ_RAS1_MASK, + .clear_reg = INT_CLR_MASK_REG, + .reset_to_clear = 1, + }, +}; + +struct shirq_dev_config shirq_ras3_config[] = { + { + .virq = VIRQ_PLGPIO, + .enb_mask = GPIO_IRQ_MASK, + .status_mask = GPIO_IRQ_MASK, + .clear_mask = GPIO_IRQ_MASK, + }, { + .virq = VIRQ_I2S_PLAY, + .enb_mask = I2S_PLAY_IRQ_MASK, + .status_mask = I2S_PLAY_IRQ_MASK, + .clear_mask = I2S_PLAY_IRQ_MASK, + }, { + .virq = VIRQ_I2S_REC, + .enb_mask = I2S_REC_IRQ_MASK, + .status_mask = I2S_REC_IRQ_MASK, + .clear_mask = I2S_REC_IRQ_MASK, + }, +}; + +struct spear_shirq shirq_ras3 = { + .irq = IRQ_GEN_RAS_3, + .dev_config = shirq_ras3_config, + .dev_count = ARRAY_SIZE(shirq_ras3_config), + .regs = { + .enb_reg = INT_ENB_MASK_REG, + .reset_to_enb = 1, + .status_reg = INT_STS_MASK_REG, + .status_reg_mask = SHIRQ_RAS3_MASK, + .clear_reg = INT_CLR_MASK_REG, + .reset_to_clear = 1, + }, +}; + +struct shirq_dev_config shirq_intrcomm_ras_config[] = { + { + .virq = VIRQ_CANU, + .status_mask = CAN_U_IRQ_MASK, + .clear_mask = CAN_U_IRQ_MASK, + }, { + .virq = VIRQ_CANL, + .status_mask = CAN_L_IRQ_MASK, + .clear_mask = CAN_L_IRQ_MASK, + }, { + .virq = VIRQ_UART1, + .status_mask = UART1_IRQ_MASK, + .clear_mask = UART1_IRQ_MASK, + }, { + .virq = VIRQ_UART2, + .status_mask = UART2_IRQ_MASK, + .clear_mask = UART2_IRQ_MASK, + }, { + .virq = VIRQ_SSP1, + .status_mask = SSP1_IRQ_MASK, + .clear_mask = SSP1_IRQ_MASK, + }, { + .virq = VIRQ_SSP2, + .status_mask = SSP2_IRQ_MASK, + .clear_mask = SSP2_IRQ_MASK, + }, { + .virq = VIRQ_SMII0, + .status_mask = SMII0_IRQ_MASK, + .clear_mask = SMII0_IRQ_MASK, + }, { + .virq = VIRQ_MII1_SMII1, + .status_mask = MII1_SMII1_IRQ_MASK, + .clear_mask = MII1_SMII1_IRQ_MASK, + }, { + .virq = VIRQ_WAKEUP_SMII0, + .status_mask = WAKEUP_SMII0_IRQ_MASK, + .clear_mask = WAKEUP_SMII0_IRQ_MASK, + }, { + .virq = VIRQ_WAKEUP_MII1_SMII1, + .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK, + .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK, + }, { + .virq = VIRQ_I2C, + .status_mask = I2C1_IRQ_MASK, + .clear_mask = I2C1_IRQ_MASK, + }, +}; + +struct spear_shirq shirq_intrcomm_ras = { + .irq = IRQ_INTRCOMM_RAS_ARM, + .dev_config = shirq_intrcomm_ras_config, + .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), + .regs = { + .enb_reg = -1, + .status_reg = INT_STS_MASK_REG, + .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, + .clear_reg = INT_CLR_MASK_REG, + .reset_to_clear = 1, + }, +}; + +/* spear320 routines */ +void __init spear320_init(void) +{ + void __iomem *base; + int ret = 0; + + /* call spear3xx family common init function */ + spear3xx_init(); + + /* shared irq registeration */ + base = ioremap(SPEAR320_SOC_CONFIG_BASE, SPEAR320_SOC_CONFIG_SIZE); + if (base) { + /* shirq 1 */ + shirq_ras1.regs.base = base; + ret = spear_shirq_register(&shirq_ras1); + if (ret) + printk(KERN_ERR "Error registering Shared IRQ 1\n"); + + /* shirq 3 */ + shirq_ras3.regs.base = base; + ret = spear_shirq_register(&shirq_ras3); + if (ret) + printk(KERN_ERR "Error registering Shared IRQ 3\n"); + + /* shirq 4 */ + shirq_intrcomm_ras.regs.base = base; + ret = spear_shirq_register(&shirq_intrcomm_ras); + if (ret) + printk(KERN_ERR "Error registering Shared IRQ 4\n"); + } +} + +void spear320_pmx_init(void) +{ + spear_pmx_init(&pmx_driver, SPEAR320_SOC_CONFIG_BASE, + SPEAR320_SOC_CONFIG_SIZE); +} diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c new file mode 100644 index 00000000000..62ac685a413 --- /dev/null +++ b/arch/arm/mach-spear3xx/spear320_evb.c @@ -0,0 +1,81 @@ +/* + * arch/arm/mach-spear3xx/spear320_evb.c + * + * SPEAr320 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <mach/generic.h> +#include <mach/spear.h> + +/* padmux devices to enable */ +static struct pmx_dev *pmx_devs[] = { + /* spear3xx specific devices */ + &pmx_i2c, + &pmx_ssp, + &pmx_mii, + &pmx_uart0, + + /* spear320 specific devices */ + &pmx_fsmc, + &pmx_sdio, + &pmx_i2s, + &pmx_uart1, + &pmx_uart2, + &pmx_can, + &pmx_pwm0, + &pmx_pwm1, + &pmx_pwm2, + &pmx_mii1, +}; + +static struct amba_device *amba_devs[] __initdata = { + /* spear3xx specific devices */ + &gpio_device, + &uart_device, + + /* spear320 specific devices */ +}; + +static struct platform_device *plat_devs[] __initdata = { + /* spear3xx specific devices */ + + /* spear320 specific devices */ +}; + +static void __init spear320_evb_init(void) +{ + unsigned int i; + + /* call spear320 machine init function */ + spear320_init(); + + /* padmux initialization */ + pmx_driver.mode = &auto_net_mii_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); + spear320_pmx_init(); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR320, "ST-SPEAR320-EVB") + .boot_params = 0x00000100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .timer = &spear_sys_timer, + .init_machine = spear320_evb_init, +MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c new file mode 100644 index 00000000000..e87313aeae2 --- /dev/null +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -0,0 +1,548 @@ +/* + * arch/arm/mach-spear3xx/spear3xx.c + * + * SPEAr3XX machines common source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/types.h> +#include <linux/amba/pl061.h> +#include <linux/ptrace.h> +#include <linux/io.h> +#include <asm/hardware/vic.h> +#include <asm/irq.h> +#include <asm/mach/arch.h> +#include <mach/generic.h> +#include <mach/spear.h> + +/* Add spear3xx machines common devices here */ +/* gpio device registeration */ +static struct pl061_platform_data gpio_plat_data = { + .gpio_base = 0, + .irq_base = SPEAR_GPIO_INT_BASE, +}; + +struct amba_device gpio_device = { + .dev = { + .init_name = "gpio", + .platform_data = &gpio_plat_data, + }, + .res = { + .start = SPEAR3XX_ICM3_GPIO_BASE, + .end = SPEAR3XX_ICM3_GPIO_BASE + SPEAR3XX_ICM3_GPIO_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_BASIC_GPIO, NO_IRQ}, +}; + +/* uart device registeration */ +struct amba_device uart_device = { + .dev = { + .init_name = "uart", + }, + .res = { + .start = SPEAR3XX_ICM1_UART_BASE, + .end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_UART, NO_IRQ}, +}; + +/* Do spear3xx familiy common initialization part here */ +void __init spear3xx_init(void) +{ + /* nothing to do for now */ +} + +/* This will initialize vic */ +void __init spear3xx_init_irq(void) +{ + vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0); +} + +/* Following will create static virtual/physical mappings */ +struct map_desc spear3xx_io_desc[] __initdata = { + { + .virtual = VA_SPEAR3XX_ICM1_UART_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), + .length = SPEAR3XX_ICM1_UART_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR3XX_ML1_VIC_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE), + .length = SPEAR3XX_ML1_VIC_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE), + .length = SPEAR3XX_ICM3_SYS_CTRL_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE), + .length = SPEAR3XX_ICM3_MISC_REG_SIZE, + .type = MT_DEVICE + }, +}; + +/* This will create static memory mapping for selected devices */ +void __init spear3xx_map_io(void) +{ + iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); + + /* This will initialize clock framework */ + clk_init(); +} + +/* pad multiplexing support */ +/* devices */ +struct pmx_dev_mode pmx_firda_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev pmx_firda = { + .name = "firda", + .modes = pmx_firda_modes, + .mode_count = ARRAY_SIZE(pmx_firda_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_i2c_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_I2C_MASK, + }, +}; + +struct pmx_dev pmx_i2c = { + .name = "i2c", + .modes = pmx_i2c_modes, + .mode_count = ARRAY_SIZE(pmx_i2c_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_ssp_cs_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev pmx_ssp_cs = { + .name = "ssp_chip_selects", + .modes = pmx_ssp_cs_modes, + .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_ssp_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_SSP_MASK, + }, +}; + +struct pmx_dev pmx_ssp = { + .name = "ssp", + .modes = pmx_ssp_modes, + .mode_count = ARRAY_SIZE(pmx_ssp_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_mii_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_mii = { + .name = "mii", + .modes = pmx_mii_modes, + .mode_count = ARRAY_SIZE(pmx_mii_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_gpio_pin0_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN0_MASK, + }, +}; + +struct pmx_dev pmx_gpio_pin0 = { + .name = "gpio_pin0", + .modes = pmx_gpio_pin0_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_gpio_pin1_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN1_MASK, + }, +}; + +struct pmx_dev pmx_gpio_pin1 = { + .name = "gpio_pin1", + .modes = pmx_gpio_pin1_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_gpio_pin2_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN2_MASK, + }, +}; + +struct pmx_dev pmx_gpio_pin2 = { + .name = "gpio_pin2", + .modes = pmx_gpio_pin2_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_gpio_pin3_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN3_MASK, + }, +}; + +struct pmx_dev pmx_gpio_pin3 = { + .name = "gpio_pin3", + .modes = pmx_gpio_pin3_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_gpio_pin4_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN4_MASK, + }, +}; + +struct pmx_dev pmx_gpio_pin4 = { + .name = "gpio_pin4", + .modes = pmx_gpio_pin4_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_gpio_pin5_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev pmx_gpio_pin5 = { + .name = "gpio_pin5", + .modes = pmx_gpio_pin5_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_uart0_modem_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev pmx_uart0_modem = { + .name = "uart0_modem", + .modes = pmx_uart0_modem_modes, + .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_uart0_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_UART0_MASK, + }, +}; + +struct pmx_dev pmx_uart0 = { + .name = "uart0", + .modes = pmx_uart0_modes, + .mode_count = ARRAY_SIZE(pmx_uart0_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_timer_3_4_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev pmx_timer_3_4 = { + .name = "timer_3_4", + .modes = pmx_timer_3_4_modes, + .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), + .enb_on_reset = 0, +}; + +struct pmx_dev_mode pmx_timer_1_2_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev pmx_timer_1_2 = { + .name = "timer_1_2", + .modes = pmx_timer_1_2_modes, + .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), + .enb_on_reset = 0, +}; + +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +/* plgpios devices */ +struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { + { + .ids = 0x00, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_0_1 = { + .name = "plgpio 0 and 1", + .modes = pmx_plgpio_0_1_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { + { + .ids = 0x00, + .mask = PMX_UART0_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_2_3 = { + .name = "plgpio 2 and 3", + .modes = pmx_plgpio_2_3_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { + { + .ids = 0x00, + .mask = PMX_I2C_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_4_5 = { + .name = "plgpio 4 and 5", + .modes = pmx_plgpio_4_5_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { + { + .ids = 0x00, + .mask = PMX_SSP_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_6_9 = { + .name = "plgpio 6 to 9", + .modes = pmx_plgpio_6_9_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { + { + .ids = 0x00, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_10_27 = { + .name = "plgpio 10 to 27", + .modes = pmx_plgpio_10_27_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_28_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN0_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_28 = { + .name = "plgpio 28", + .modes = pmx_plgpio_28_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_29_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN1_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_29 = { + .name = "plgpio 29", + .modes = pmx_plgpio_29_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_30_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN2_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_30 = { + .name = "plgpio 30", + .modes = pmx_plgpio_30_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_31_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN3_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_31 = { + .name = "plgpio 31", + .modes = pmx_plgpio_31_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_32_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN4_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_32 = { + .name = "plgpio 32", + .modes = pmx_plgpio_32_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_33_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_33 = { + .name = "plgpio 33", + .modes = pmx_plgpio_33_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { + { + .ids = 0x00, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_34_36 = { + .name = "plgpio 34 to 36", + .modes = pmx_plgpio_34_36_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { + { + .ids = 0x00, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_37_42 = { + .name = "plgpio 37 to 42", + .modes = pmx_plgpio_37_42_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_43_44_47_48 = { + .name = "plgpio 43, 44, 47 and 48", + .modes = pmx_plgpio_43_44_47_48_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), + .enb_on_reset = 1, +}; + +struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev pmx_plgpio_45_46_49_50 = { + .name = "plgpio 45, 46, 49 and 50", + .modes = pmx_plgpio_45_46_49_50_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), + .enb_on_reset = 1, +}; + +#endif + +/* spear padmux initialization function */ +void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size) +{ + int ret = 0; + + /* pad mux initialization */ + pmx_driver->base = ioremap(base, size); + if (!pmx_driver->base) { + ret = -ENOMEM; + goto pmx_fail; + } + + ret = pmx_register(pmx_driver); + iounmap(pmx_driver->base); + +pmx_fail: + if (ret) + printk(KERN_ERR "padmux: registeration failed. err no: %d\n", + ret); +} diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig new file mode 100644 index 00000000000..bddba034f86 --- /dev/null +++ b/arch/arm/mach-spear6xx/Kconfig @@ -0,0 +1,20 @@ +# +# SPEAr6XX Machine configuration file +# + +if ARCH_SPEAR6XX + +choice + prompt "SPEAr6XX Family" + default MACH_SPEAR600 + +config MACH_SPEAR600 + bool "SPEAr600" + help + Supports ST SPEAr600 Machine +endchoice + +# Adding SPEAr6XX machine specific configuration files +source "arch/arm/mach-spear6xx/Kconfig600" + +endif #ARCH_SPEAR6XX diff --git a/arch/arm/mach-spear6xx/Kconfig600 b/arch/arm/mach-spear6xx/Kconfig600 new file mode 100644 index 00000000000..9e19f65eb78 --- /dev/null +++ b/arch/arm/mach-spear6xx/Kconfig600 @@ -0,0 +1,17 @@ +# +# SPEAr600 machine configuration file +# + +if MACH_SPEAR600 + +choice + prompt "SPEAr600 Boards" + default BOARD_SPEAR600_EVB + +config BOARD_SPEAR600_EVB + bool "SPEAr600 Evaluation Board" + help + Supports ST SPEAr600 Evaluation Board +endchoice + +endif #MACH_SPEAR600 diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile new file mode 100644 index 00000000000..cc1a4d82d45 --- /dev/null +++ b/arch/arm/mach-spear6xx/Makefile @@ -0,0 +1,12 @@ +# +# Makefile for SPEAr6XX machine series +# + +# common files +obj-y += clock.o spear6xx.o + +# spear600 specific files +obj-$(CONFIG_MACH_SPEAR600) += spear600.o + +# spear600 boards files +obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot new file mode 100644 index 00000000000..7a1f3c0eadb --- /dev/null +++ b/arch/arm/mach-spear6xx/Makefile.boot @@ -0,0 +1,3 @@ +zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c new file mode 100644 index 00000000000..13e27c76968 --- /dev/null +++ b/arch/arm/mach-spear6xx/clock.c @@ -0,0 +1,483 @@ +/* + * arch/arm/mach-spear6xx/clock.c + * + * SPEAr6xx machines clock framework source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <mach/misc_regs.h> +#include <plat/clock.h> + +/* root clks */ +/* 32 KHz oscillator clock */ +static struct clk osc_32k_clk = { + .flags = ALWAYS_ENABLED, + .rate = 32000, +}; + +/* 30 MHz oscillator clock */ +static struct clk osc_30m_clk = { + .flags = ALWAYS_ENABLED, + .rate = 30000000, +}; + +/* clock derived from 32 KHz osc clk */ +/* rtc clock */ +static struct clk rtc_clk = { + .pclk = &osc_32k_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = RTC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clock derived from 30 MHz osc clk */ +/* pll1 configuration structure */ +static struct pll_clk_config pll1_config = { + .mode_reg = PLL1_CTR, + .cfg_reg = PLL1_FRQ, +}; + +/* PLL1 clock */ +static struct clk pll1_clk = { + .pclk = &osc_30m_clk, + .en_reg = PLL1_CTR, + .en_reg_bit = PLL_ENABLE, + .recalc = &pll1_clk_recalc, + .private_data = &pll1_config, +}; + +/* PLL3 48 MHz clock */ +static struct clk pll3_48m_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_30m_clk, + .rate = 48000000, +}; + +/* watch dog timer clock */ +static struct clk wdt_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_30m_clk, + .recalc = &follow_parent, +}; + +/* clock derived from pll1 clk */ +/* cpu clock */ +static struct clk cpu_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .recalc = &follow_parent, +}; + +/* ahb configuration structure */ +static struct bus_clk_config ahb_config = { + .reg = CORE_CLK_CFG, + .mask = PLL_HCLK_RATIO_MASK, + .shift = PLL_HCLK_RATIO_SHIFT, +}; + +/* ahb clock */ +static struct clk ahb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .recalc = &bus_clk_recalc, + .private_data = &ahb_config, +}; + +/* uart parents */ +static struct pclk_info uart_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* uart parent select structure */ +static struct pclk_sel uart_pclk_sel = { + .pclk_info = uart_pclk_info, + .pclk_count = ARRAY_SIZE(uart_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = UART_CLK_MASK, +}; + +/* uart configurations */ +static struct aux_clk_config uart_config = { + .synth_reg = UART_CLK_SYNT, +}; + +/* uart0 clock */ +static struct clk uart0_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = UART0_CLK_ENB, + .pclk_sel = &uart_pclk_sel, + .pclk_sel_shift = UART_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &uart_config, +}; + +/* uart1 clock */ +static struct clk uart1_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = UART1_CLK_ENB, + .pclk_sel = &uart_pclk_sel, + .pclk_sel_shift = UART_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &uart_config, +}; + +/* firda configurations */ +static struct aux_clk_config firda_config = { + .synth_reg = FIRDA_CLK_SYNT, +}; + +/* firda parents */ +static struct pclk_info firda_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* firda parent select structure */ +static struct pclk_sel firda_pclk_sel = { + .pclk_info = firda_pclk_info, + .pclk_count = ARRAY_SIZE(firda_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = FIRDA_CLK_MASK, +}; + +/* firda clock */ +static struct clk firda_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = FIRDA_CLK_ENB, + .pclk_sel = &firda_pclk_sel, + .pclk_sel_shift = FIRDA_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &firda_config, +}; + +/* clcd configurations */ +static struct aux_clk_config clcd_config = { + .synth_reg = CLCD_CLK_SYNT, +}; + +/* clcd parents */ +static struct pclk_info clcd_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* clcd parent select structure */ +static struct pclk_sel clcd_pclk_sel = { + .pclk_info = clcd_pclk_info, + .pclk_count = ARRAY_SIZE(clcd_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = CLCD_CLK_MASK, +}; + +/* clcd clock */ +static struct clk clcd_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = CLCD_CLK_ENB, + .pclk_sel = &clcd_pclk_sel, + .pclk_sel_shift = CLCD_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &clcd_config, +}; + +/* gpt parents */ +static struct pclk_info gpt_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt_pclk_sel = { + .pclk_info = gpt_pclk_info, + .pclk_count = ARRAY_SIZE(gpt_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, +}; + +/* gpt0_1 configurations */ +static struct aux_clk_config gpt0_1_config = { + .synth_reg = PRSC1_CLK_CFG, +}; + +/* gpt0 ARM1 subsystem timer clock */ +static struct clk gpt0_clk = { + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT0_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt0_1_config, +}; + +/* gpt1 timer clock */ +static struct clk gpt1_clk = { + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT1_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt0_1_config, +}; + +/* gpt2 configurations */ +static struct aux_clk_config gpt2_config = { + .synth_reg = PRSC2_CLK_CFG, +}; + +/* gpt2 timer clock */ +static struct clk gpt2_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPT2_CLK_ENB, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT2_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt2_config, +}; + +/* gpt3 configurations */ +static struct aux_clk_config gpt3_config = { + .synth_reg = PRSC3_CLK_CFG, +}; + +/* gpt3 timer clock */ +static struct clk gpt3_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPT3_CLK_ENB, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT3_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt3_config, +}; + +/* clock derived from pll3 clk */ +/* usbh0 clock */ +static struct clk usbh0_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBH0_CLK_ENB, + .recalc = &follow_parent, +}; + +/* usbh1 clock */ +static struct clk usbh1_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBH1_CLK_ENB, + .recalc = &follow_parent, +}; + +/* usbd clock */ +static struct clk usbd_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBD_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clock derived from ahb clk */ +/* apb configuration structure */ +static struct bus_clk_config apb_config = { + .reg = CORE_CLK_CFG, + .mask = HCLK_PCLK_RATIO_MASK, + .shift = HCLK_PCLK_RATIO_SHIFT, +}; + +/* apb clock */ +static struct clk apb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &bus_clk_recalc, + .private_data = &apb_config, +}; + +/* i2c clock */ +static struct clk i2c_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = I2C_CLK_ENB, + .recalc = &follow_parent, +}; + +/* dma clock */ +static struct clk dma_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = DMA_CLK_ENB, + .recalc = &follow_parent, +}; + +/* jpeg clock */ +static struct clk jpeg_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = JPEG_CLK_ENB, + .recalc = &follow_parent, +}; + +/* gmac clock */ +static struct clk gmac_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GMAC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* smi clock */ +static struct clk smi_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SMI_CLK_ENB, + .recalc = &follow_parent, +}; + +/* fsmc clock */ +static struct clk fsmc_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = FSMC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clock derived from apb clk */ +/* adc clock */ +static struct clk adc_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = ADC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* ssp0 clock */ +static struct clk ssp0_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP0_CLK_ENB, + .recalc = &follow_parent, +}; + +/* ssp1 clock */ +static struct clk ssp1_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP1_CLK_ENB, + .recalc = &follow_parent, +}; + +/* ssp2 clock */ +static struct clk ssp2_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP2_CLK_ENB, + .recalc = &follow_parent, +}; + +/* gpio0 ARM subsystem clock */ +static struct clk gpio0_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* gpio1 clock */ +static struct clk gpio1_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPIO1_CLK_ENB, + .recalc = &follow_parent, +}; + +/* gpio2 clock */ +static struct clk gpio2_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPIO2_CLK_ENB, + .recalc = &follow_parent, +}; + +/* array of all spear 6xx clock lookups */ +static struct clk_lookup spear_clk_lookups[] = { + /* root clks */ + { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, + { .con_id = "osc_30m_clk", .clk = &osc_30m_clk}, + /* clock derived from 32 KHz os clk */ + { .dev_id = "rtc", .clk = &rtc_clk}, + /* clock derived from 30 MHz os clk */ + { .con_id = "pll1_clk", .clk = &pll1_clk}, + { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, + { .dev_id = "wdt", .clk = &wdt_clk}, + /* clock derived from pll1 clk */ + { .con_id = "cpu_clk", .clk = &cpu_clk}, + { .con_id = "ahb_clk", .clk = &ahb_clk}, + { .dev_id = "uart0", .clk = &uart0_clk}, + { .dev_id = "uart1", .clk = &uart1_clk}, + { .dev_id = "firda", .clk = &firda_clk}, + { .dev_id = "clcd", .clk = &clcd_clk}, + { .dev_id = "gpt0", .clk = &gpt0_clk}, + { .dev_id = "gpt1", .clk = &gpt1_clk}, + { .dev_id = "gpt2", .clk = &gpt2_clk}, + { .dev_id = "gpt3", .clk = &gpt3_clk}, + /* clock derived from pll3 clk */ + { .dev_id = "usbh0", .clk = &usbh0_clk}, + { .dev_id = "usbh1", .clk = &usbh1_clk}, + { .dev_id = "usbd", .clk = &usbd_clk}, + /* clock derived from ahb clk */ + { .con_id = "apb_clk", .clk = &apb_clk}, + { .dev_id = "i2c", .clk = &i2c_clk}, + { .dev_id = "dma", .clk = &dma_clk}, + { .dev_id = "jpeg", .clk = &jpeg_clk}, + { .dev_id = "gmac", .clk = &gmac_clk}, + { .dev_id = "smi", .clk = &smi_clk}, + { .dev_id = "fsmc", .clk = &fsmc_clk}, + /* clock derived from apb clk */ + { .dev_id = "adc", .clk = &adc_clk}, + { .dev_id = "ssp0", .clk = &ssp0_clk}, + { .dev_id = "ssp1", .clk = &ssp1_clk}, + { .dev_id = "ssp2", .clk = &ssp2_clk}, + { .dev_id = "gpio0", .clk = &gpio0_clk}, + { .dev_id = "gpio1", .clk = &gpio1_clk}, + { .dev_id = "gpio2", .clk = &gpio2_clk}, +}; + +void __init clk_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) + clk_register(&spear_clk_lookups[i]); + + recalc_root_clocks(); +} diff --git a/arch/arm/mach-spear6xx/include/mach/clkdev.h b/arch/arm/mach-spear6xx/include/mach/clkdev.h new file mode 100644 index 00000000000..05676bf440d --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/clkdev.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear6xx/include/mach/clkdev.h + * + * Clock Dev framework definitions for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_CLKDEV_H +#define __MACH_CLKDEV_H + +#include <plat/clkdev.h> + +#endif /* __MACH_CLKDEV_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/debug-macro.S b/arch/arm/mach-spear6xx/include/mach/debug-macro.S new file mode 100644 index 00000000000..0f3ea39edd9 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/debug-macro.S @@ -0,0 +1,14 @@ +/* + * arch/arm/mach-spear6xx/include/mach/debug-macro.S + * + * Debugging macro include header for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <plat/debug-macro.S> diff --git a/arch/arm/mach-spear6xx/include/mach/entry-macro.S b/arch/arm/mach-spear6xx/include/mach/entry-macro.S new file mode 100644 index 00000000000..9eaecaeafcf --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/entry-macro.S @@ -0,0 +1,55 @@ +/* + * arch/arm/mach-spear6xx/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/hardware.h> +#include <mach/spear.h> +#include <asm/hardware/vic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =VA_SPEAR6XX_CPU_VIC_PRI_BASE + ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status + mov \irqnr, #0 + teq \irqstat, #0 + bne 1001f + ldr \base, =VA_SPEAR6XX_CPU_VIC_SEC_BASE + ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status + teq \irqstat, #0 + beq 1002f @ this will set/reset + @ zero register + mov \irqnr, #32 +1001: + /* + * Following code will find bit position of least significang + * bit set in irqstat, using following equation + * least significant bit set in n = (n & ~(n-1)) + */ + sub \tmp, \irqstat, #1 @ tmp = irqstat - 1 + mvn \tmp, \tmp @ tmp = ~tmp + and \irqstat, \irqstat, \tmp @ irqstat &= tmp + /* Now, irqstat is = bit no. of 1st bit set in vic irq status */ + clz \tmp, \irqstat @ tmp = leading zeros + + rsb \tmp, \tmp, #0x1F @ tmp = 32 - tmp - 1 + add \irqnr, \irqnr, \tmp + +1002: /* EQ will be set if no irqs pending */ + .endm diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h new file mode 100644 index 00000000000..16205a53875 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/generic.h @@ -0,0 +1,45 @@ +/* + * arch/arm/mach-spear6xx/include/mach/generic.h + * + * SPEAr6XX machine family specific generic header file + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_GENERIC_H +#define __MACH_GENERIC_H + +#include <asm/mach/time.h> +#include <asm/mach/map.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/amba/bus.h> + +/* + * Each GPT has 2 timer channels + * Following GPT channels will be used as clock source and clockevent + */ +#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE +#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 +#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 + +/* Add spear6xx family device structure declarations here */ +extern struct amba_device gpio_device[]; +extern struct amba_device uart_device[]; +extern struct sys_timer spear_sys_timer; + +/* Add spear6xx family function declarations here */ +void __init spear6xx_map_io(void); +void __init spear6xx_init_irq(void); +void __init spear6xx_init(void); +void __init spear600_init(void); +void __init clk_init(void); + +/* Add spear600 machine device structure declarations here */ + +#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/gpio.h b/arch/arm/mach-spear6xx/include/mach/gpio.h new file mode 100644 index 00000000000..3a789dbb69f --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/gpio.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear6xx/include/mach/gpio.h + * + * GPIO macros for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_GPIO_H +#define __MACH_GPIO_H + +#include <plat/gpio.h> + +#endif /* __MACH_GPIO_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h new file mode 100644 index 00000000000..7545116deca --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/hardware.h @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-spear6xx/include/mach/hardware.h + * + * Hardware definitions for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H + +/* Vitual to physical translation of statically mapped space */ +#define IO_ADDRESS(x) (x | 0xF0000000) + +#endif /* __MACH_HARDWARE_H */ + diff --git a/arch/arm/mach-spear6xx/include/mach/io.h b/arch/arm/mach-spear6xx/include/mach/io.h new file mode 100644 index 00000000000..fb7c106cea9 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/io.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-spear6xx/include/mach/io.h + * + * IO definitions for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_IO_H +#define __MACH_IO_H + +#include <plat/io.h> + +#endif /* __MACH_IO_H */ + diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h new file mode 100644 index 00000000000..8f214b03d75 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/irqs.h @@ -0,0 +1,97 @@ +/* + * arch/arm/mach-spear6xx/include/mach/irqs.h + * + * IRQ helper macros for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +/* IRQ definitions */ +/* VIC 1 */ +#define IRQ_INTRCOMM_SW_IRQ 0 +#define IRQ_INTRCOMM_CPU_1 1 +#define IRQ_INTRCOMM_CPU_2 2 +#define IRQ_INTRCOMM_RAS2A11_1 3 +#define IRQ_INTRCOMM_RAS2A11_2 4 +#define IRQ_INTRCOMM_RAS2A12_1 5 +#define IRQ_INTRCOMM_RAS2A12_2 6 +#define IRQ_GEN_RAS_0 7 +#define IRQ_GEN_RAS_1 8 +#define IRQ_GEN_RAS_2 9 +#define IRQ_GEN_RAS_3 10 +#define IRQ_GEN_RAS_4 11 +#define IRQ_GEN_RAS_5 12 +#define IRQ_GEN_RAS_6 13 +#define IRQ_GEN_RAS_7 14 +#define IRQ_GEN_RAS_8 15 +#define IRQ_CPU_GPT1_1 16 +#define IRQ_CPU_GPT1_2 17 +#define IRQ_LOCAL_GPIO 18 +#define IRQ_PLL_UNLOCK 19 +#define IRQ_JPEG 20 +#define IRQ_FSMC 21 +#define IRQ_IRDA 22 +#define IRQ_RESERVED 23 +#define IRQ_UART_0 24 +#define IRQ_UART_1 25 +#define IRQ_SSP_1 26 +#define IRQ_SSP_2 27 +#define IRQ_I2C 28 +#define IRQ_GEN_RAS_9 29 +#define IRQ_GEN_RAS_10 30 +#define IRQ_GEN_RAS_11 31 + +/* VIC 2 */ +#define IRQ_APPL_GPT1_1 32 +#define IRQ_APPL_GPT1_2 33 +#define IRQ_APPL_GPT2_1 34 +#define IRQ_APPL_GPT2_2 35 +#define IRQ_APPL_GPIO 36 +#define IRQ_APPL_SSP 37 +#define IRQ_APPL_ADC 38 +#define IRQ_APPL_RESERVED 39 +#define IRQ_AHB_EXP_MASTER 40 +#define IRQ_DDR_CONTROLLER 41 +#define IRQ_BASIC_DMA 42 +#define IRQ_BASIC_RESERVED1 43 +#define IRQ_BASIC_SMI 44 +#define IRQ_BASIC_CLCD 45 +#define IRQ_EXP_AHB_1 46 +#define IRQ_EXP_AHB_2 47 +#define IRQ_BASIC_GPT1_1 48 +#define IRQ_BASIC_GPT1_2 49 +#define IRQ_BASIC_RTC 50 +#define IRQ_BASIC_GPIO 51 +#define IRQ_BASIC_WDT 52 +#define IRQ_BASIC_RESERVED 53 +#define IRQ_AHB_EXP_SLAVE 54 +#define IRQ_GMAC_1 55 +#define IRQ_GMAC_2 56 +#define IRQ_USB_DEV 57 +#define IRQ_USB_H_OHCI_0 58 +#define IRQ_USB_H_EHCI_0 59 +#define IRQ_USB_H_OHCI_1 60 +#define IRQ_USB_H_EHCI_1 61 +#define IRQ_EXP_AHB_3 62 +#define IRQ_EXP_AHB_4 63 + +#define IRQ_VIC_END 64 + +/* GPIO pins virtual irqs */ +#define SPEAR_GPIO_INT_BASE IRQ_VIC_END +#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE +#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8) +#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8) +#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8) +#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END) +#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) + +#endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/memory.h b/arch/arm/mach-spear6xx/include/mach/memory.h new file mode 100644 index 00000000000..781f088fc22 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/memory.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear6xx/include/mach/memory.h + * + * Memory map for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_MEMORY_H +#define __MACH_MEMORY_H + +#include <plat/memory.h> + +#endif /* __MACH_MEMORY_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h new file mode 100644 index 00000000000..03908036b0d --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h @@ -0,0 +1,173 @@ +/* + * arch/arm/mach-spear6xx/include/mach/misc_regs.h + * + * Miscellaneous registers definitions for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_MISC_REGS_H +#define __MACH_MISC_REGS_H + +#include <mach/spear.h> + +#define MISC_BASE VA_SPEAR6XX_ICM3_MISC_REG_BASE + +#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) +#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) +#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) +#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) +#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) +#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) +/* PLL_CTR register masks */ +#define PLL_ENABLE 2 +#define PLL_MODE_SHIFT 4 +#define PLL_MODE_MASK 0x3 +#define PLL_MODE_NORMAL 0 +#define PLL_MODE_FRACTION 1 +#define PLL_MODE_DITH_DSB 2 +#define PLL_MODE_DITH_SSB 3 + +#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) +/* PLL FRQ register masks */ +#define PLL_DIV_N_SHIFT 0 +#define PLL_DIV_N_MASK 0xFF +#define PLL_DIV_P_SHIFT 8 +#define PLL_DIV_P_MASK 0x7 +#define PLL_NORM_FDBK_M_SHIFT 24 +#define PLL_NORM_FDBK_M_MASK 0xFF +#define PLL_DITH_FDBK_M_SHIFT 16 +#define PLL_DITH_FDBK_M_MASK 0xFFFF + +#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) +#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) +#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) +/* CORE CLK CFG register masks */ +#define PLL_HCLK_RATIO_SHIFT 10 +#define PLL_HCLK_RATIO_MASK 0x3 +#define HCLK_PCLK_RATIO_SHIFT 8 +#define HCLK_PCLK_RATIO_MASK 0x3 + +#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) +/* PERIP_CLK_CFG register masks */ +#define CLCD_CLK_SHIFT 2 +#define CLCD_CLK_MASK 0x3 +#define UART_CLK_SHIFT 4 +#define UART_CLK_MASK 0x1 +#define FIRDA_CLK_SHIFT 5 +#define FIRDA_CLK_MASK 0x3 +#define GPT0_CLK_SHIFT 8 +#define GPT1_CLK_SHIFT 10 +#define GPT2_CLK_SHIFT 11 +#define GPT3_CLK_SHIFT 12 +#define GPT_CLK_MASK 0x1 +#define AUX_CLK_PLL3_MASK 0 +#define AUX_CLK_PLL1_MASK 1 + +#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) +/* PERIP1_CLK_ENB register masks */ +#define UART0_CLK_ENB 3 +#define UART1_CLK_ENB 4 +#define SSP0_CLK_ENB 5 +#define SSP1_CLK_ENB 6 +#define I2C_CLK_ENB 7 +#define JPEG_CLK_ENB 8 +#define FSMC_CLK_ENB 9 +#define FIRDA_CLK_ENB 10 +#define GPT2_CLK_ENB 11 +#define GPT3_CLK_ENB 12 +#define GPIO2_CLK_ENB 13 +#define SSP2_CLK_ENB 14 +#define ADC_CLK_ENB 15 +#define GPT1_CLK_ENB 11 +#define RTC_CLK_ENB 17 +#define GPIO1_CLK_ENB 18 +#define DMA_CLK_ENB 19 +#define SMI_CLK_ENB 21 +#define CLCD_CLK_ENB 22 +#define GMAC_CLK_ENB 23 +#define USBD_CLK_ENB 24 +#define USBH0_CLK_ENB 25 +#define USBH1_CLK_ENB 26 + +#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) +#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) +#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) +/* PERIP1_SOF_RST register masks */ +#define JPEG_SOF_RST 8 + +#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) +#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) +#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) +#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) +#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) +/* gpt synthesizer register masks */ +#define GPT_MSCALE_SHIFT 0 +#define GPT_MSCALE_MASK 0xFFF +#define GPT_NSCALE_SHIFT 12 +#define GPT_NSCALE_MASK 0xF + +#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) +#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) +#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) +#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) +#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) +#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) +#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) +#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) +#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) +#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) +/* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_EQ_SEL_SHIFT 30 +#define AUX_EQ_SEL_MASK 1 +#define AUX_EQ1_SEL 0 +#define AUX_EQ2_SEL 1 +#define AUX_XSCALE_SHIFT 16 +#define AUX_XSCALE_MASK 0xFFF +#define AUX_YSCALE_SHIFT 0 +#define AUX_YSCALE_MASK 0xFFF + +#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) +#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) +#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) +#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) +#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) +#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) +#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) +#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) +#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) +#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) +#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) +#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) +#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) +#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) +#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) +#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) +#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) +#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) +#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) +#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) +#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) +#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) +#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) +#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) +#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) +#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) +#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) +#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) +#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) +#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) +#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) +#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) +#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) +#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) +#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) +#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) +#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) + +#endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h new file mode 100644 index 00000000000..a835f5b6b18 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/spear.h @@ -0,0 +1,173 @@ +/* + * arch/arm/mach-spear6xx/include/mach/spear.h + * + * SPEAr6xx Machine family specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_SPEAR6XX_H +#define __MACH_SPEAR6XX_H + +#include <mach/hardware.h> +#include <mach/spear600.h> + +#define SPEAR6XX_ML_SDRAM_BASE 0x00000000 +#define SPEAR6XX_ML_SDRAM_SIZE 0x40000000 + +/* ICM1 - Low speed connection */ +#define SPEAR6XX_ICM1_BASE 0xD0000000 +#define SPEAR6XX_ICM1_SIZE 0x08000000 + +#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000 +#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) +#define SPEAR6XX_ICM1_UART0_SIZE 0x00080000 + +#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000 +#define SPEAR6XX_ICM1_UART1_SIZE 0x00080000 + +#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000 +#define SPEAR6XX_ICM1_SSP0_SIZE 0x00080000 + +#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000 +#define SPEAR6XX_ICM1_SSP1_SIZE 0x00080000 + +#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000 +#define SPEAR6XX_ICM1_I2C_SIZE 0x00080000 + +#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000 +#define SPEAR6XX_ICM1_JPEG_SIZE 0x00800000 + +#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000 +#define SPEAR6XX_ICM1_IRDA_SIZE 0x00800000 + +#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000 +#define SPEAR6XX_ICM1_FSMC_SIZE 0x00800000 + +#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000 +#define SPEAR6XX_ICM1_NAND_SIZE 0x00800000 + +#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000 +#define SPEAR6XX_ICM1_SRAM_SIZE 0x00800000 + +/* ICM2 - Application Subsystem */ +#define SPEAR6XX_ICM2_BASE 0xD8000000 +#define SPEAR6XX_ICM2_SIZE 0x08000000 + +#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000 +#define SPEAR6XX_ICM2_TMR0_SIZE 0x00080000 + +#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000 +#define SPEAR6XX_ICM2_TMR1_SIZE 0x00080000 + +#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000 +#define SPEAR6XX_ICM2_GPIO_SIZE 0x00080000 + +#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000 +#define SPEAR6XX_ICM2_SPI2_SIZE 0x00080000 + +#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000 +#define SPEAR6XX_ICM2_ADC_SIZE 0x00080000 + +/* ML-1, 2 - Multi Layer CPU Subsystem */ +#define SPEAR6XX_ML_CPU_BASE 0xF0000000 +#define SPEAR6XX_ML_CPU_SIZE 0x08000000 + +#define SPEAR6XX_CPU_TMR_BASE 0xF0000000 +#define SPEAR6XX_CPU_TMR_SIZE 0x00100000 + +#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000 +#define SPEAR6XX_CPU_GPIO_SIZE 0x00100000 + +#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000 +#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE) +#define SPEAR6XX_CPU_VIC_SEC_SIZE 0x00100000 + +#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000 +#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE) +#define SPEAR6XX_CPU_VIC_PRI_SIZE 0x00100000 + +/* ICM3 - Basic Subsystem */ +#define SPEAR6XX_ICM3_BASE 0xF8000000 +#define SPEAR6XX_ICM3_SIZE 0x08000000 + +#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000 +#define SPEAR6XX_ICM3_SMEM_SIZE 0x04000000 + +#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000 +#define SPEAR6XX_ICM3_SMI_CTRL_SIZE 0x00200000 + +#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000 +#define SPEAR6XX_ICM3_CLCD_SIZE 0x00200000 + +#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000 +#define SPEAR6XX_ICM3_DMA_SIZE 0x00200000 + +#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 +#define SPEAR6XX_ICM3_SDRAM_CTRL_SIZE 0x00200000 + +#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000 +#define SPEAR6XX_ICM3_TMR_SIZE 0x00080000 + +#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000 +#define SPEAR6XX_ICM3_WDT_SIZE 0x00080000 + +#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000 +#define SPEAR6XX_ICM3_RTC_SIZE 0x00080000 + +#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000 +#define SPEAR6XX_ICM3_GPIO_SIZE 0x00080000 + +#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000 +#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) +#define SPEAR6XX_ICM3_SYS_CTRL_SIZE 0x00080000 + +#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000 +#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) +#define SPEAR6XX_ICM3_MISC_REG_SIZE 0x00080000 + +/* ICM4 - High Speed Connection */ +#define SPEAR6XX_ICM4_BASE 0xE0000000 +#define SPEAR6XX_ICM4_SIZE 0x08000000 + +#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000 +#define SPEAR6XX_ICM4_GMAC_SIZE 0x00800000 + +#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000 +#define SPEAR6XX_ICM4_USBD_FIFO_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000 +#define SPEAR6XX_ICM4_USBD_CSR_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000 +#define SPEAR6XX_ICM4_USBD_PLDT_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000 +#define SPEAR6XX_ICM4_USB_EHCI0_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000 +#define SPEAR6XX_ICM4_USB_OHCI0_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000 +#define SPEAR6XX_ICM4_USB_EHCI1_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000 +#define SPEAR6XX_ICM4_USB_OHCI1_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000 +#define SPEAR6XX_ICM4_USB_ARB_SIZE 0x00010000 + +/* Debug uart for linux, will be used for debug and uncompress messages */ +#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE +#define VA_SPEAR_DBG_UART_BASE VA_SPEAR6XX_ICM1_UART0_BASE + +/* Sysctl base for spear platform */ +#define SPEAR_SYS_CTRL_BASE SPEAR6XX_ICM3_SYS_CTRL_BASE +#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR6XX_ICM3_SYS_CTRL_BASE + +#endif /* __MACH_SPEAR6XX_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h new file mode 100644 index 00000000000..c068cc50b0f --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/spear600.h @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-spear66xx/include/mach/spear600.h + * + * SPEAr600 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR600 + +#ifndef __MACH_SPEAR600_H +#define __MACH_SPEAR600_H + +#endif /* __MACH_SPEAR600_H */ + +#endif /* CONFIG_MACH_SPEAR600 */ diff --git a/arch/arm/mach-spear6xx/include/mach/system.h b/arch/arm/mach-spear6xx/include/mach/system.h new file mode 100644 index 00000000000..0b1d2be81cf --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/system.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear6xx/include/mach/system.h + * + * SPEAr6xx Machine family specific architecture functions + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_SYSTEM_H +#define __MACH_SYSTEM_H + +#include <plat/system.h> + +#endif /* __MACH_SYSTEM_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/timex.h b/arch/arm/mach-spear6xx/include/mach/timex.h new file mode 100644 index 00000000000..ac1c5b00569 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/timex.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear6xx/include/mach/timex.h + * + * SPEAr6XX machine family specific timex definitions + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_TIMEX_H +#define __MACH_TIMEX_H + +#include <plat/timex.h> + +#endif /* __MACH_TIMEX_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/uncompress.h b/arch/arm/mach-spear6xx/include/mach/uncompress.h new file mode 100644 index 00000000000..77f0765e21e --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/uncompress.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear6xx/include/mach/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_UNCOMPRESS_H +#define __MACH_UNCOMPRESS_H + +#include <plat/uncompress.h> + +#endif /* __MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/vmalloc.h b/arch/arm/mach-spear6xx/include/mach/vmalloc.h new file mode 100644 index 00000000000..4a0b56cb2a9 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/vmalloc.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear6xx/include/mach/vmalloc.h + * + * Defining Vmalloc area for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_VMALLOC_H +#define __MACH_VMALLOC_H + +#include <plat/vmalloc.h> + +#endif /* __MACH_VMALLOC_H */ diff --git a/arch/arm/mach-spear6xx/spear600.c b/arch/arm/mach-spear6xx/spear600.c new file mode 100644 index 00000000000..5c484c433dc --- /dev/null +++ b/arch/arm/mach-spear6xx/spear600.c @@ -0,0 +1,25 @@ +/* + * arch/arm/mach-spear6xx/spear600.c + * + * SPEAr600 machine source file + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/ptrace.h> +#include <asm/irq.h> +#include <mach/generic.h> +#include <mach/spear.h> + +/* Add spear600 specific devices here */ + +void __init spear600_init(void) +{ + /* call spear6xx family common init function */ + spear6xx_init(); +} diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c new file mode 100644 index 00000000000..daff8d04f7b --- /dev/null +++ b/arch/arm/mach-spear6xx/spear600_evb.c @@ -0,0 +1,51 @@ +/* + * arch/arm/mach-spear6xx/spear600_evb.c + * + * SPEAr600 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <mach/generic.h> +#include <mach/spear.h> + +static struct amba_device *amba_devs[] __initdata = { + &gpio_device[0], + &gpio_device[1], + &gpio_device[2], + &uart_device[0], + &uart_device[1], +}; + +static struct platform_device *plat_devs[] __initdata = { +}; + +static void __init spear600_evb_init(void) +{ + unsigned int i; + + /* call spear600 machine init function */ + spear600_init(); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR600, "ST-SPEAR600-EVB") + .boot_params = 0x00000100, + .map_io = spear6xx_map_io, + .init_irq = spear6xx_init_irq, + .timer = &spear_sys_timer, + .init_machine = spear600_evb_init, +MACHINE_END diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c new file mode 100644 index 00000000000..b67e571d4bf --- /dev/null +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -0,0 +1,158 @@ +/* + * arch/arm/mach-spear6xx/spear6xx.c + * + * SPEAr6XX machines common source file + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/types.h> +#include <linux/amba/pl061.h> +#include <linux/types.h> +#include <linux/ptrace.h> +#include <linux/io.h> +#include <asm/hardware/vic.h> +#include <asm/irq.h> +#include <asm/mach/arch.h> +#include <mach/irqs.h> +#include <mach/generic.h> +#include <mach/spear.h> + +/* Add spear6xx machines common devices here */ +/* uart device registeration */ +struct amba_device uart_device[] = { + { + .dev = { + .init_name = "uart0", + }, + .res = { + .start = SPEAR6XX_ICM1_UART0_BASE, + .end = SPEAR6XX_ICM1_UART0_BASE + + SPEAR6XX_ICM1_UART0_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_UART_0, NO_IRQ}, + }, { + .dev = { + .init_name = "uart1", + }, + .res = { + .start = SPEAR6XX_ICM1_UART1_BASE, + .end = SPEAR6XX_ICM1_UART1_BASE + + SPEAR6XX_ICM1_UART1_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_UART_1, NO_IRQ}, + } +}; + +/* gpio device registeration */ +static struct pl061_platform_data gpio_plat_data[] = { + { + .gpio_base = 0, + .irq_base = SPEAR_GPIO0_INT_BASE, + }, { + .gpio_base = 8, + .irq_base = SPEAR_GPIO1_INT_BASE, + }, { + .gpio_base = 16, + .irq_base = SPEAR_GPIO2_INT_BASE, + }, +}; + +struct amba_device gpio_device[] = { + { + .dev = { + .init_name = "gpio0", + .platform_data = &gpio_plat_data[0], + }, + .res = { + .start = SPEAR6XX_CPU_GPIO_BASE, + .end = SPEAR6XX_CPU_GPIO_BASE + + SPEAR6XX_CPU_GPIO_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_LOCAL_GPIO, NO_IRQ}, + }, { + .dev = { + .init_name = "gpio1", + .platform_data = &gpio_plat_data[1], + }, + .res = { + .start = SPEAR6XX_ICM3_GPIO_BASE, + .end = SPEAR6XX_ICM3_GPIO_BASE + + SPEAR6XX_ICM3_GPIO_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_BASIC_GPIO, NO_IRQ}, + }, { + .dev = { + .init_name = "gpio2", + .platform_data = &gpio_plat_data[2], + }, + .res = { + .start = SPEAR6XX_ICM2_GPIO_BASE, + .end = SPEAR6XX_ICM2_GPIO_BASE + + SPEAR6XX_ICM2_GPIO_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_APPL_GPIO, NO_IRQ}, + } +}; + +/* This will add devices, and do machine specific tasks */ +void __init spear6xx_init(void) +{ + /* nothing to do for now */ +} + +/* This will initialize vic */ +void __init spear6xx_init_irq(void) +{ + vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_PRI_BASE, 0, ~0, 0); + vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0, 0); +} + +/* Following will create static virtual/physical mappings */ +static struct map_desc spear6xx_io_desc[] __initdata = { + { + .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), + .length = SPEAR6XX_ICM1_UART0_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE), + .length = SPEAR6XX_CPU_VIC_PRI_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), + .length = SPEAR6XX_CPU_VIC_SEC_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE), + .length = SPEAR6XX_ICM3_MISC_REG_BASE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), + .length = SPEAR6XX_ICM3_MISC_REG_SIZE, + .type = MT_DEVICE + }, +}; + +/* This will create static memory mapping for selected devices */ +void __init spear6xx_map_io(void) +{ + iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); + + /* This will initialize clock framework */ + clk_init(); +} diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h index b8155b4e5ff..193da2df732 100644 --- a/arch/arm/mach-u300/include/mach/coh901318.h +++ b/arch/arm/mach-u300/include/mach/coh901318.h @@ -103,27 +103,6 @@ struct coh901318_platform { }; /** - * coh901318_get_bytes_left() - Get number of bytes left on a current transfer - * @chan: dma channel handle - * return number of bytes left, or negative on error - */ -u32 coh901318_get_bytes_left(struct dma_chan *chan); - -/** - * coh901318_stop() - Stops dma transfer - * @chan: dma channel handle - * return 0 on success otherwise negative value - */ -void coh901318_stop(struct dma_chan *chan); - -/** - * coh901318_continue() - Resumes a stopped dma transfer - * @chan: dma channel handle - * return 0 on success otherwise negative value - */ -void coh901318_continue(struct dma_chan *chan); - -/** * coh901318_filter_id() - DMA channel filter function * @chan: dma channel handle * @chan_id: id of dma channel to be filter out diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c index 77fbb1e0e52..88506d03059 100644 --- a/arch/arm/mach-u300/mmc.c +++ b/arch/arm/mach-u300/mmc.c @@ -102,11 +102,12 @@ int __devinit mmc_init(struct amba_device *adev) * we have a regulator we can control instead. */ /* Nominally 2.85V on our platform */ + mmci_card->mmc0_plat_data.f_max = 24000000; mmci_card->mmc0_plat_data.status = mmc_status; mmci_card->mmc0_plat_data.gpio_wp = -1; mmci_card->mmc0_plat_data.gpio_cd = -1; mmci_card->mmc0_plat_data.capabilities = MMC_CAP_MMC_HIGHSPEED | - MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA; + MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data; diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 03625d74485..6625e5bbf4d 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -1,15 +1,42 @@ -menu "ST-Ericsson platform type" - depends on ARCH_U8500 +if ARCH_U8500 -comment "ST-Ericsson Multicore Mobile Platforms" - -config MACH_U8500_MOP - bool "U8500 Early Development platform" +config UX500_SOC_COMMON + bool default y select ARM_GIC select HAS_MTU + select NOMADIK_GPIO + +config UX500_SOC_DB8500 + bool + +config UX500_SOC_DB5500 + bool + +choice + prompt "Ux500 target platform" + default MACH_U8500_MOP + +config MACH_U8500_MOP + bool "U8500 Development platform" + select UX500_SOC_DB8500 help Include support for mop500 development platform based on U8500 architecture. The platform is based on early drop silicon version of 8500. -endmenu + +config MACH_U5500 + bool "U5500 Development platform" + select UX500_SOC_DB5500 + help + Include support for the U5500 development platform. +endchoice + +config UX500_DEBUG_UART + int "Ux500 UART to use for low-level debug" + default 2 + help + Choose the UART on which kernel low-level debug messages should be + output. + +endif diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 95e6e24c004..c7bc4199e3a 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -2,7 +2,9 @@ # Makefile for the linux kernel, U8500 machine. # -obj-y := clock.o -obj-$(CONFIG_ARCH_U8500) += cpu-u8500.o +obj-y := clock.o cpu.o devices.o +obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o +obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o +obj-$(CONFIG_MACH_U5500) += board-u5500.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 803aec1d672..072196c5726 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -17,37 +17,14 @@ #include <linux/amba/pl022.h> #include <linux/spi/spi.h> -#include <asm/localtimer.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <plat/mtu.h> #include <plat/i2c.h> #include <mach/hardware.h> #include <mach/setup.h> - -#define __MEM_4K_RESOURCE(x) \ - .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM} - -/* These are active devices on this board */ -static struct amba_device uart0_device = { - .dev = { .init_name = "uart0" }, - __MEM_4K_RESOURCE(U8500_UART0_BASE), - .irq = {IRQ_UART0, NO_IRQ}, -}; - -static struct amba_device uart1_device = { - .dev = { .init_name = "uart1" }, - __MEM_4K_RESOURCE(U8500_UART1_BASE), - .irq = {IRQ_UART1, NO_IRQ}, -}; - -static struct amba_device uart2_device = { - .dev = { .init_name = "uart2" }, - __MEM_4K_RESOURCE(U8500_UART2_BASE), - .irq = {IRQ_UART2, NO_IRQ}, -}; +#include <mach/devices.h> static void ab4500_spi_cs_control(u32 command) { @@ -93,55 +70,8 @@ static struct pl022_ssp_controller ssp0_platform_data = { .num_chipselect = 5, }; -static struct amba_device pl022_device = { - .dev = { - .coherent_dma_mask = ~0, - .init_name = "pl022", - .platform_data = &ssp0_platform_data, - }, - .res = { - .start = U8500_SSP0_BASE, - .end = U8500_SSP0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .irq = {IRQ_SSP0, NO_IRQ }, - /* ST-Ericsson modified id */ - .periphid = SSP_PER_ID, -}; - -static struct amba_device pl031_device = { - .dev = { - .init_name = "pl031", - }, - .res = { - .start = U8500_RTC_BASE, - .end = U8500_RTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .irq = {IRQ_RTC_RTT, NO_IRQ}, -}; - -#define U8500_I2C_RESOURCES(id, size) \ -static struct resource u8500_i2c_resources_##id[] = { \ - [0] = { \ - .start = U8500_I2C##id##_BASE, \ - .end = U8500_I2C##id##_BASE + size - 1, \ - .flags = IORESOURCE_MEM, \ - }, \ - [1] = { \ - .start = IRQ_I2C##id, \ - .end = IRQ_I2C##id, \ - .flags = IORESOURCE_IRQ \ - } \ -} - -U8500_I2C_RESOURCES(0, SZ_4K); -U8500_I2C_RESOURCES(1, SZ_4K); -U8500_I2C_RESOURCES(2, SZ_4K); -U8500_I2C_RESOURCES(3, SZ_4K); - #define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \ -static struct nmk_i2c_controller u8500_i2c_##id = { \ +static struct nmk_i2c_controller u8500_i2c##id##_data = { \ /* \ * slave data setup time, which is \ * 250 ns,100ns,10ns which is 14,6,2 \ @@ -169,58 +99,32 @@ U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); -#define U8500_I2C_PDEVICE(cid) \ -static struct platform_device i2c_controller##cid = { \ - .name = "nmk-i2c", \ - .id = cid, \ - .num_resources = 2, \ - .resource = u8500_i2c_resources_##cid, \ - .dev = { \ - .platform_data = &u8500_i2c_##cid \ - } \ -} - -U8500_I2C_PDEVICE(0); -U8500_I2C_PDEVICE(1); -U8500_I2C_PDEVICE(2); -U8500_I2C_PDEVICE(3); - static struct amba_device *amba_devs[] __initdata = { - &uart0_device, - &uart1_device, - &uart2_device, - &pl022_device, - &pl031_device, + &ux500_uart0_device, + &ux500_uart1_device, + &ux500_uart2_device, + &u8500_ssp0_device, }; /* add any platform devices here - TODO */ static struct platform_device *platform_devs[] __initdata = { - &i2c_controller0, - &i2c_controller1, - &i2c_controller2, - &i2c_controller3, -}; - -static void __init u8500_timer_init(void) -{ -#ifdef CONFIG_LOCAL_TIMERS - /* Setup the local timer base */ - twd_base = __io_address(U8500_TWD_BASE); -#endif - /* Setup the MTU base */ - mtu_base = __io_address(U8500_MTU0_BASE); - - nmdk_timer_init(); -} - -static struct sys_timer u8500_timer = { - .init = u8500_timer_init, + &u8500_i2c0_device, + &ux500_i2c1_device, + &ux500_i2c2_device, + &ux500_i2c3_device, }; static void __init u8500_init_machine(void) { int i; + u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data; + ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data; + ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data; + ux500_i2c3_device.dev.platform_data = &u8500_i2c3_data; + + u8500_ssp0_device.dev.platform_data = &ssp0_platform_data; + /* Register the active AMBA devices on this board */ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) amba_device_register(amba_devs[i], &iomem_resource); @@ -239,8 +143,8 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform") .io_pg_offst = (IO_ADDRESS(U8500_UART2_BASE) >> 18) & 0xfffc, .boot_params = 0x100, .map_io = u8500_map_io, - .init_irq = u8500_init_irq, + .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ - .timer = &u8500_timer, + .timer = &ux500_timer, .init_machine = u8500_init_machine, MACHINE_END diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c new file mode 100644 index 00000000000..4430e69cf53 --- /dev/null +++ b/arch/arm/mach-ux500/board-u5500.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/amba/bus.h> +#include <linux/gpio.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <mach/hardware.h> +#include <mach/devices.h> +#include <mach/setup.h> + +static struct amba_device *amba_board_devs[] __initdata = { + &ux500_uart0_device, + &ux500_uart1_device, + &ux500_uart2_device, +}; + +static void __init u5500_init_machine(void) +{ + u5500_init_devices(); + + amba_add_devices(amba_board_devs, ARRAY_SIZE(amba_board_devs)); +} + +MACHINE_START(U8500, "ST-Ericsson U5500 Platform") + .phys_io = UX500_UART0_BASE, + .io_pg_offst = (IO_ADDRESS(UX500_UART0_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = u5500_map_io, + .init_irq = ux500_init_irq, + .timer = &ux500_timer, + .init_machine = u5500_init_machine, +MACHINE_END diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index 8359a73d004..1b2c9890e8b 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2009 ST-Ericsson - * heavily based on realview platform + * Copyright (C) 2009 STMicroelectronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -12,33 +12,130 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/clk.h> -#include <linux/mutex.h> +#include <linux/io.h> #include <asm/clkdev.h> -/* currently the clk structure - * just supports rate. This would - * be extended as and when new devices are - * added - TODO - */ -struct clk { - unsigned long rate; -}; +#include <mach/hardware.h> +#include "clock.h" + +#define PRCC_PCKEN 0x00 +#define PRCC_PCKDIS 0x04 +#define PRCC_KCKEN 0x08 +#define PRCC_KCKDIS 0x0C + +#define PRCM_YYCLKEN0_MGT_SET 0x510 +#define PRCM_YYCLKEN1_MGT_SET 0x514 +#define PRCM_YYCLKEN0_MGT_CLR 0x518 +#define PRCM_YYCLKEN1_MGT_CLR 0x51C +#define PRCM_YYCLKEN0_MGT_VAL 0x520 +#define PRCM_YYCLKEN1_MGT_VAL 0x524 + +#define PRCM_SVAMMDSPCLK_MGT 0x008 +#define PRCM_SIAMMDSPCLK_MGT 0x00C +#define PRCM_SGACLK_MGT 0x014 +#define PRCM_UARTCLK_MGT 0x018 +#define PRCM_MSP02CLK_MGT 0x01C +#define PRCM_MSP1CLK_MGT 0x288 +#define PRCM_I2CCLK_MGT 0x020 +#define PRCM_SDMMCCLK_MGT 0x024 +#define PRCM_SLIMCLK_MGT 0x028 +#define PRCM_PER1CLK_MGT 0x02C +#define PRCM_PER2CLK_MGT 0x030 +#define PRCM_PER3CLK_MGT 0x034 +#define PRCM_PER5CLK_MGT 0x038 +#define PRCM_PER6CLK_MGT 0x03C +#define PRCM_PER7CLK_MGT 0x040 +#define PRCM_LCDCLK_MGT 0x044 +#define PRCM_BMLCLK_MGT 0x04C +#define PRCM_HSITXCLK_MGT 0x050 +#define PRCM_HSIRXCLK_MGT 0x054 +#define PRCM_HDMICLK_MGT 0x058 +#define PRCM_APEATCLK_MGT 0x05C +#define PRCM_APETRACECLK_MGT 0x060 +#define PRCM_MCDECLK_MGT 0x064 +#define PRCM_IPI2CCLK_MGT 0x068 +#define PRCM_DSIALTCLK_MGT 0x06C +#define PRCM_DMACLK_MGT 0x074 +#define PRCM_B2R2CLK_MGT 0x078 +#define PRCM_TVCLK_MGT 0x07C +#define PRCM_UNIPROCLK_MGT 0x278 +#define PRCM_SSPCLK_MGT 0x280 +#define PRCM_RNGCLK_MGT 0x284 +#define PRCM_UICCCLK_MGT 0x27C + +#define PRCM_MGT_ENABLE (1 << 8) + +static DEFINE_SPINLOCK(clocks_lock); + +static void __clk_enable(struct clk *clk) +{ + if (clk->enabled++ == 0) { + if (clk->parent_cluster) + __clk_enable(clk->parent_cluster); + + if (clk->parent_periph) + __clk_enable(clk->parent_periph); + + if (clk->ops && clk->ops->enable) + clk->ops->enable(clk); + } +} int clk_enable(struct clk *clk) { + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + __clk_enable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); + return 0; } EXPORT_SYMBOL(clk_enable); +static void __clk_disable(struct clk *clk) +{ + if (--clk->enabled == 0) { + if (clk->ops && clk->ops->disable) + clk->ops->disable(clk); + + if (clk->parent_periph) + __clk_disable(clk->parent_periph); + + if (clk->parent_cluster) + __clk_disable(clk->parent_cluster); + } +} + void clk_disable(struct clk *clk) { + unsigned long flags; + + WARN_ON(!clk->enabled); + + spin_lock_irqsave(&clocks_lock, flags); + __clk_disable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); } EXPORT_SYMBOL(clk_disable); unsigned long clk_get_rate(struct clk *clk) { - return clk->rate; + unsigned long rate; + + if (clk->ops && clk->ops->get_rate) + return clk->ops->get_rate(clk); + + rate = clk->rate; + if (!rate) { + if (clk->parent_periph) + rate = clk_get_rate(clk->parent_periph); + else if (clk->parent_cluster) + rate = clk_get_rate(clk->parent_cluster); + } + + return rate; } EXPORT_SYMBOL(clk_get_rate); @@ -56,37 +153,373 @@ int clk_set_rate(struct clk *clk, unsigned long rate) } EXPORT_SYMBOL(clk_set_rate); -/* ssp clock */ -static struct clk ssp_clk = { - .rate = 48000000, +static void clk_prcmu_enable(struct clk *clk) +{ + void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE) + + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off; + + writel(1 << clk->prcmu_cg_bit, cg_set_reg); +} + +static void clk_prcmu_disable(struct clk *clk) +{ + void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE) + + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off; + + writel(1 << clk->prcmu_cg_bit, cg_clr_reg); +} + +/* ED doesn't have the combined set/clr registers */ +static void clk_prcmu_ed_enable(struct clk *clk) +{ + void __iomem *addr = __io_address(U8500_PRCMU_BASE) + + clk->prcmu_cg_mgt; + + writel(readl(addr) | PRCM_MGT_ENABLE, addr); +} + +static void clk_prcmu_ed_disable(struct clk *clk) +{ + void __iomem *addr = __io_address(U8500_PRCMU_BASE) + + clk->prcmu_cg_mgt; + + writel(readl(addr) & ~PRCM_MGT_ENABLE, addr); +} + +static struct clkops clk_prcmu_ops = { + .enable = clk_prcmu_enable, + .disable = clk_prcmu_disable, }; -/* fixed clock */ -static struct clk f38_clk = { - .rate = 38400000, +static unsigned int clkrst_base[] = { + [1] = U8500_CLKRST1_BASE, + [2] = U8500_CLKRST2_BASE, + [3] = U8500_CLKRST3_BASE, + [5] = U8500_CLKRST5_BASE, + [6] = U8500_CLKRST6_BASE, + [7] = U8500_CLKRST7_BASE_ED, }; -static struct clk_lookup lookups[] = { - { - /* UART0 */ - .dev_id = "uart0", - .clk = &f38_clk, - }, { /* UART1 */ - .dev_id = "uart1", - .clk = &f38_clk, - }, { /* UART2 */ - .dev_id = "uart2", - .clk = &f38_clk, - }, { /* SSP */ - .dev_id = "pl022", - .clk = &ssp_clk, - } +static void clk_prcc_enable(struct clk *clk) +{ + void __iomem *addr = __io_address(clkrst_base[clk->cluster]); + + if (clk->prcc_kernel != -1) + writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN); + + if (clk->prcc_bus != -1) + writel(1 << clk->prcc_bus, addr + PRCC_PCKEN); +} + +static void clk_prcc_disable(struct clk *clk) +{ + void __iomem *addr = __io_address(clkrst_base[clk->cluster]); + + if (clk->prcc_bus != -1) + writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS); + + if (clk->prcc_kernel != -1) + writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS); +} + +static struct clkops clk_prcc_ops = { + .enable = clk_prcc_enable, + .disable = clk_prcc_disable, +}; + +static struct clk clk_32khz = { + .rate = 32000, +}; + +/* + * PRCMU level clock gating + */ + +/* Bank 0 */ +static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK); +static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK); +static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK); +static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000); +static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK); +static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */ +static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000); +static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 50000000); +static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK); +static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK); +static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); +static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); +static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); +static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); +static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000); +static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); +static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); +static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); +static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK); +static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK); +static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK); +static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK); +static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK); +static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK); +static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */ +static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK); +static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK); +static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK); +static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */ +static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */ + +/* Bank 1 */ +static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */ +static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ + +/* + * PRCC level clock gating + * Format: per#, clk, PCKEN bit, KCKEN bit, parent + */ + +/* Peripheral Cluster #1 */ +static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); +static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); +static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); +static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); +static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); +static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); +static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); +static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); +static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); + +/* Peripheral Cluster #2 */ + +static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); +static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); +static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); +static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); +static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); +static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); +static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); +static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); +static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); + +static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL); +static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); +static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); +static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); +static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); +static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL); +static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); +static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); +static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); + +/* Peripheral Cluster #3 */ +static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); +static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); +static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); +static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); +static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); +static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); +static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); +static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); +static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); + +/* Peripheral Cluster #4 is in the always on domain */ + +/* Peripheral Cluster #5 */ +static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); +static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); +static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); + +/* Peripheral Cluster #6 */ + +static DEFINE_PRCC_CLK(6, mtu1_v1, 8, -1, NULL); +static DEFINE_PRCC_CLK(6, mtu0_v1, 7, -1, NULL); +static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); +static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); +static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); +static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); +static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); +static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); +static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); +static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); +static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); +static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); + +/* Peripheral Cluster #7 */ + +static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); +static DEFINE_PRCC_CLK(7, mtu1_ed, 3, -1, NULL); +static DEFINE_PRCC_CLK(7, mtu0_ed, 2, -1, NULL); +static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); +static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); + +static struct clk_lookup u8500_common_clks[] = { + /* Peripheral Cluster #1 */ + CLK(gpio0, "gpio.0", NULL), + CLK(gpio0, "gpio.1", NULL), + CLK(slimbus0, "slimbus0", NULL), + CLK(i2c2, "nmk-i2c.2", NULL), + CLK(sdi0, "sdi0", NULL), + CLK(msp0, "msp0", NULL), + CLK(i2c1, "nmk-i2c.1", NULL), + CLK(uart1, "uart1", NULL), + CLK(uart0, "uart0", NULL), + + /* Peripheral Cluster #3 */ + CLK(gpio2, "gpio.2", NULL), + CLK(gpio2, "gpio.3", NULL), + CLK(gpio2, "gpio.4", NULL), + CLK(gpio2, "gpio.5", NULL), + CLK(sdi5, "sdi5", NULL), + CLK(uart2, "uart2", NULL), + CLK(ske, "ske", NULL), + CLK(sdi2, "sdi2", NULL), + CLK(i2c0, "nmk-i2c.0", NULL), + CLK(fsmc, "fsmc", NULL), + + /* Peripheral Cluster #5 */ + CLK(gpio3, "gpio.8", NULL), + + /* Peripheral Cluster #6 */ + CLK(hash1, "hash1", NULL), + CLK(pka, "pka", NULL), + CLK(hash0, "hash0", NULL), + CLK(cryp0, "cryp0", NULL), + + /* PRCMU level clock gating */ + + /* Bank 0 */ + CLK(svaclk, "sva", NULL), + CLK(siaclk, "sia", NULL), + CLK(sgaclk, "sga", NULL), + CLK(slimclk, "slim", NULL), + CLK(lcdclk, "lcd", NULL), + CLK(bmlclk, "bml", NULL), + CLK(hsitxclk, "stm-hsi.0", NULL), + CLK(hsirxclk, "stm-hsi.1", NULL), + CLK(hdmiclk, "hdmi", NULL), + CLK(apeatclk, "apeat", NULL), + CLK(apetraceclk, "apetrace", NULL), + CLK(mcdeclk, "mcde", NULL), + CLK(ipi2clk, "ipi2", NULL), + CLK(dmaclk, "dma40", NULL), + CLK(b2r2clk, "b2r2", NULL), + CLK(tvclk, "tv", NULL), +}; + +static struct clk_lookup u8500_ed_clks[] = { + /* Peripheral Cluster #1 */ + CLK(spi3_ed, "spi3", NULL), + CLK(msp1_ed, "msp1", NULL), + + /* Peripheral Cluster #2 */ + CLK(gpio1_ed, "gpio.6", NULL), + CLK(gpio1_ed, "gpio.7", NULL), + CLK(ssitx_ed, "ssitx", NULL), + CLK(ssirx_ed, "ssirx", NULL), + CLK(spi0_ed, "spi0", NULL), + CLK(sdi3_ed, "sdi3", NULL), + CLK(sdi1_ed, "sdi1", NULL), + CLK(msp2_ed, "msp2", NULL), + CLK(sdi4_ed, "sdi4", NULL), + CLK(pwl_ed, "pwl", NULL), + CLK(spi1_ed, "spi1", NULL), + CLK(spi2_ed, "spi2", NULL), + CLK(i2c3_ed, "nmk-i2c.3", NULL), + + /* Peripheral Cluster #3 */ + CLK(ssp1_ed, "ssp1", NULL), + CLK(ssp0_ed, "ssp0", NULL), + + /* Peripheral Cluster #5 */ + CLK(usb_ed, "musb_hdrc.0", "usb"), + + /* Peripheral Cluster #6 */ + CLK(dmc_ed, "dmc", NULL), + CLK(cryp1_ed, "cryp1", NULL), + CLK(rng_ed, "rng", NULL), + + /* Peripheral Cluster #7 */ + CLK(tzpc0_ed, "tzpc0", NULL), + CLK(mtu1_ed, "mtu1", NULL), + CLK(mtu0_ed, "mtu0", NULL), + CLK(wdg_ed, "wdg", NULL), + CLK(cfgreg_ed, "cfgreg", NULL), +}; + +static struct clk_lookup u8500_v1_clks[] = { + /* Peripheral Cluster #1 */ + CLK(i2c4, "nmk-i2c.4", NULL), + CLK(spi3_v1, "spi3", NULL), + CLK(msp1_v1, "msp1", NULL), + + /* Peripheral Cluster #2 */ + CLK(gpio1_v1, "gpio.6", NULL), + CLK(gpio1_v1, "gpio.7", NULL), + CLK(ssitx_v1, "ssitx", NULL), + CLK(ssirx_v1, "ssirx", NULL), + CLK(spi0_v1, "spi0", NULL), + CLK(sdi3_v1, "sdi3", NULL), + CLK(sdi1_v1, "sdi1", NULL), + CLK(msp2_v1, "msp2", NULL), + CLK(sdi4_v1, "sdi4", NULL), + CLK(pwl_v1, "pwl", NULL), + CLK(spi1_v1, "spi1", NULL), + CLK(spi2_v1, "spi2", NULL), + CLK(i2c3_v1, "nmk-i2c.3", NULL), + + /* Peripheral Cluster #3 */ + CLK(ssp1_v1, "ssp1", NULL), + CLK(ssp0_v1, "ssp0", NULL), + + /* Peripheral Cluster #5 */ + CLK(usb_v1, "musb_hdrc.0", "usb"), + + /* Peripheral Cluster #6 */ + CLK(mtu1_v1, "mtu1", NULL), + CLK(mtu0_v1, "mtu0", NULL), + CLK(cfgreg_v1, "cfgreg", NULL), + CLK(hash1, "hash1", NULL), + CLK(unipro_v1, "unipro", NULL), + CLK(rng_v1, "rng", NULL), + + /* PRCMU level clock gating */ + + /* Bank 0 */ + CLK(uniproclk, "uniproclk", NULL), + CLK(dsialtclk, "dsialt", NULL), + + /* Bank 1 */ + CLK(rngclk, "rng", NULL), + CLK(uiccclk, "uicc", NULL), }; static int __init clk_init(void) { - /* register the clock lookups */ - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + if (cpu_is_u8500ed()) { + clk_prcmu_ops.enable = clk_prcmu_ed_enable; + clk_prcmu_ops.disable = clk_prcmu_ed_disable; + } else if (cpu_is_u5500()) { + /* Clock tree for U5500 not implemented yet */ + clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; + clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; + } + + clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); + if (cpu_is_u8500ed()) + clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks)); + else + clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); + return 0; } arch_initcall(clk_init); diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h new file mode 100644 index 00000000000..e4f99b65026 --- /dev/null +++ b/arch/arm/mach-ux500/clock.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * Copyright (C) 2009 STMicroelectronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/** + * struct clkops - ux500 clock operations + * @enable: function to enable the clock + * @disable: function to disable the clock + * @get_rate: function to get the current clock rate + * + * This structure contains function pointers to functions that will be used to + * control the clock. All of these functions are optional. If get_rate is + * NULL, the rate in the struct clk will be used. + */ +struct clkops { + void (*enable) (struct clk *); + void (*disable) (struct clk *); + unsigned long (*get_rate) (struct clk *); +}; + +/** + * struct clk - ux500 clock structure + * @ops: pointer to clkops struct used to control this clock + * @name: name, for debugging + * @enabled: refcount. positive if enabled, zero if disabled + * @rate: fixed rate for clocks which don't implement + * ops->getrate + * @prcmu_cg_off: address offset of the combined enable/disable register + * (used on u8500v1) + * @prcmu_cg_bit: bit in the combined enable/disable register (used on + * u8500v1) + * @prcmu_cg_mgt: address of the enable/disable register (used on + * u8500ed) + * @cluster: peripheral cluster number + * @prcc_bus: bit for the bus clock in the peripheral's CLKRST + * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST. + * -1 if no kernel clock exists. + * @parent_cluster: pointer to parent's cluster clk struct + * @parent_periph: pointer to parent's peripheral clk struct + * + * Peripherals are organised into clusters, and each cluster has an associated + * bus clock. Some peripherals also have a parent peripheral clock. + * + * In order to enable a clock for a peripheral, we need to enable: + * (1) the parent cluster (bus) clock at the PRCMU level + * (2) the parent peripheral clock (if any) at the PRCMU level + * (3) the peripheral's bus & kernel clock at the PRCC level + * + * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each + * of the cluster and peripheral clocks, and hooking these as the parents of + * the individual peripheral clocks. + * + * (3) is handled by specifying the bits in the PRCC control registers required + * to enable these clocks and modifying them in the ->enable and + * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK). + * + * This structure describes both the PRCMU-level clocks and PRCC-level clocks. + * The prcmu_* fields are only used for the PRCMU clocks, and the cluster, + * prcc, and parent pointers are only used for the PRCC-level clocks. + */ +struct clk { + const struct clkops *ops; + const char *name; + unsigned int enabled; + + unsigned long rate; + struct list_head list; + + /* These three are only for PRCMU clks */ + + unsigned int prcmu_cg_off; + unsigned int prcmu_cg_bit; + unsigned int prcmu_cg_mgt; + + /* The rest are only for PRCC clks */ + + int cluster; + unsigned int prcc_bus; + unsigned int prcc_kernel; + + struct clk *parent_cluster; + struct clk *parent_periph; +}; + +#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ +struct clk clk_##_name = { \ + .name = #_name, \ + .ops = &clk_prcmu_ops, \ + .prcmu_cg_off = _cg_off, \ + .prcmu_cg_bit = _cg_bit, \ + .prcmu_cg_mgt = PRCM_##_reg##_MGT \ + } + +#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \ +struct clk clk_##_name = { \ + .name = #_name, \ + .ops = &clk_prcmu_ops, \ + .prcmu_cg_off = _cg_off, \ + .prcmu_cg_bit = _cg_bit, \ + .rate = _rate, \ + .prcmu_cg_mgt = PRCM_##_reg##_MGT \ + } + +#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \ +struct clk clk_##_name = { \ + .name = #_name, \ + .ops = &clk_prcc_ops, \ + .cluster = _pclust, \ + .prcc_bus = _bus_en, \ + .prcc_kernel = _kernel_en, \ + .parent_cluster = &clk_per##_pclust##clk, \ + .parent_periph = _kernclk \ + } + +#define CLK(_clk, _devname, _conname) \ + { \ + .clk = &clk_##_clk, \ + .dev_id = _devname, \ + .con_id = _conname, \ + } diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c new file mode 100644 index 00000000000..6a3ac4539f1 --- /dev/null +++ b/arch/arm/mach-ux500/cpu-db5500.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/platform_device.h> +#include <linux/amba/bus.h> +#include <linux/io.h> + +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/devices.h> +#include <mach/setup.h> + +static struct map_desc u5500_io_desc[] __initdata = { + __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), + __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K), + __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K), + __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K), + __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K), +}; + +static struct platform_device *u5500_platform_devs[] __initdata = { + &u5500_gpio_devs[0], + &u5500_gpio_devs[1], + &u5500_gpio_devs[2], + &u5500_gpio_devs[3], + &u5500_gpio_devs[4], + &u5500_gpio_devs[5], + &u5500_gpio_devs[6], + &u5500_gpio_devs[7], +}; + +void __init u5500_map_io(void) +{ + ux500_map_io(); + + iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc)); +} + +void __init u5500_init_devices(void) +{ + ux500_init_devices(); + + platform_add_devices(u5500_platform_devs, + ARRAY_SIZE(u5500_platform_devs)); +} diff --git a/arch/arm/mach-ux500/cpu-u8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 397bc1f9ed9..d04299f3b6b 100644 --- a/arch/arm/mach-ux500/cpu-u8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -13,44 +13,55 @@ #include <linux/device.h> #include <linux/amba/bus.h> #include <linux/irq.h> +#include <linux/gpio.h> #include <linux/platform_device.h> +#include <linux/io.h> -#include <asm/hardware/gic.h> #include <asm/mach/map.h> #include <mach/hardware.h> +#include <mach/setup.h> +#include <mach/devices.h> -/* add any platform devices here - TODO */ static struct platform_device *platform_devs[] __initdata = { - /* yet to be added, add i2c0, gpio.. */ + &u8500_gpio_devs[0], + &u8500_gpio_devs[1], + &u8500_gpio_devs[2], + &u8500_gpio_devs[3], + &u8500_gpio_devs[4], + &u8500_gpio_devs[5], + &u8500_gpio_devs[6], + &u8500_gpio_devs[7], + &u8500_gpio_devs[8], }; -#define __IO_DEV_DESC(x, sz) { \ - .virtual = IO_ADDRESS(x), \ - .pfn = __phys_to_pfn(x), \ - .length = sz, \ - .type = MT_DEVICE, \ -} - /* minimum static i/o mapping required to boot U8500 platforms */ static struct map_desc u8500_io_desc[] __initdata = { - __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), - __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K), - __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), + __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), + __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), + __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), + __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), + __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), +}; + +static struct map_desc u8500ed_io_desc[] __initdata = { + __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K), + __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K), +}; + +static struct map_desc u8500v1_io_desc[] __initdata = { __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), - __IO_DEV_DESC(U8500_TWD_BASE, SZ_4K), - __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), - __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), }; void __init u8500_map_io(void) { + ux500_map_io(); + iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); -} -void __init u8500_init_irq(void) -{ - gic_dist_init(0, __io_address(U8500_GIC_DIST_BASE), 29); - gic_cpu_init(0, __io_address(U8500_GIC_CPU_BASE)); + if (cpu_is_u8500ed()) + iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc)); + else + iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc)); } /* @@ -58,6 +69,8 @@ void __init u8500_init_irq(void) */ void __init u8500_init_devices(void) { + ux500_init_devices(); + /* Register the platform devices */ platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c new file mode 100644 index 00000000000..d81ad023963 --- /dev/null +++ b/arch/arm/mach-ux500/cpu.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/platform_device.h> +#include <linux/amba/bus.h> +#include <linux/io.h> +#include <linux/clk.h> + +#include <asm/hardware/cache-l2x0.h> +#include <asm/hardware/gic.h> +#include <asm/mach/map.h> +#include <asm/localtimer.h> + +#include <plat/mtu.h> +#include <mach/hardware.h> +#include <mach/setup.h> +#include <mach/devices.h> + +#include "clock.h" + +static struct map_desc ux500_io_desc[] __initdata = { + __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K), + __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K), + + __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K), + __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K), + __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K), + __IO_DEV_DESC(UX500_TWD_BASE, SZ_4K), + __IO_DEV_DESC(UX500_SCU_BASE, SZ_4K), + + __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K), + __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K), + __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K), + __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K), + __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K), + + __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K), + __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K), + + __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K), +}; + +static struct amba_device *ux500_amba_devs[] __initdata = { + &ux500_pl031_device, +}; + +void __init ux500_map_io(void) +{ + iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc)); +} + +void __init ux500_init_devices(void) +{ + amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs)); +} + +void __init ux500_init_irq(void) +{ + gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29); + gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE)); +} + +#ifdef CONFIG_CACHE_L2X0 +static int ux500_l2x0_init(void) +{ + void __iomem *l2x0_base; + + l2x0_base = __io_address(UX500_L2CC_BASE); + + /* 64KB way size, 8 way associativity, force WA */ + l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); + + return 0; +} +early_initcall(ux500_l2x0_init); +#endif + +static void __init ux500_timer_init(void) +{ +#ifdef CONFIG_LOCAL_TIMERS + /* Setup the local timer base */ + twd_base = __io_address(UX500_TWD_BASE); +#endif + /* Setup the MTU base */ + if (cpu_is_u8500ed()) + mtu_base = __io_address(U8500_MTU0_BASE_ED); + else + mtu_base = __io_address(UX500_MTU0_BASE); + + nmdk_timer_init(); +} + +struct sys_timer ux500_timer = { + .init = ux500_timer_init, +}; diff --git a/arch/arm/mach-ux500/devices-db5500.c b/arch/arm/mach-ux500/devices-db5500.c new file mode 100644 index 00000000000..33e5b56bebb --- /dev/null +++ b/arch/arm/mach-ux500/devices-db5500.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/gpio.h> + +#include <mach/hardware.h> +#include <mach/devices.h> + +static struct nmk_gpio_platform_data u5500_gpio_data[] = { + GPIO_DATA("GPIO-0-31", 0), + GPIO_DATA("GPIO-32-63", 32), /* 36..63 not routed to pin */ + GPIO_DATA("GPIO-64-95", 64), /* 83..95 not routed to pin */ + GPIO_DATA("GPIO-96-127", 96), /* 102..127 not routed to pin */ + GPIO_DATA("GPIO-128-159", 128), /* 149..159 not routed to pin */ + GPIO_DATA("GPIO-160-191", 160), + GPIO_DATA("GPIO-192-223", 192), + GPIO_DATA("GPIO-224-255", 224), /* 228..255 not routed to pin */ +}; + +static struct resource u5500_gpio_resources[] = { + GPIO_RESOURCE(0), + GPIO_RESOURCE(1), + GPIO_RESOURCE(2), + GPIO_RESOURCE(3), + GPIO_RESOURCE(4), + GPIO_RESOURCE(5), + GPIO_RESOURCE(6), + GPIO_RESOURCE(7), +}; + +struct platform_device u5500_gpio_devs[] = { + GPIO_DEVICE(0), + GPIO_DEVICE(1), + GPIO_DEVICE(2), + GPIO_DEVICE(3), + GPIO_DEVICE(4), + GPIO_DEVICE(5), + GPIO_DEVICE(6), + GPIO_DEVICE(7), +}; diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c new file mode 100644 index 00000000000..20334236afc --- /dev/null +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/amba/bus.h> + +#include <mach/hardware.h> +#include <mach/setup.h> + +static struct nmk_gpio_platform_data u8500_gpio_data[] = { + GPIO_DATA("GPIO-0-31", 0), + GPIO_DATA("GPIO-32-63", 32), /* 37..63 not routed to pin */ + GPIO_DATA("GPIO-64-95", 64), + GPIO_DATA("GPIO-96-127", 96), /* 98..127 not routed to pin */ + GPIO_DATA("GPIO-128-159", 128), + GPIO_DATA("GPIO-160-191", 160), /* 172..191 not routed to pin */ + GPIO_DATA("GPIO-192-223", 192), + GPIO_DATA("GPIO-224-255", 224), /* 231..255 not routed to pin */ + GPIO_DATA("GPIO-256-288", 256), /* 268..288 not routed to pin */ +}; + +static struct resource u8500_gpio_resources[] = { + GPIO_RESOURCE(0), + GPIO_RESOURCE(1), + GPIO_RESOURCE(2), + GPIO_RESOURCE(3), + GPIO_RESOURCE(4), + GPIO_RESOURCE(5), + GPIO_RESOURCE(6), + GPIO_RESOURCE(7), + GPIO_RESOURCE(8), +}; + +struct platform_device u8500_gpio_devs[] = { + GPIO_DEVICE(0), + GPIO_DEVICE(1), + GPIO_DEVICE(2), + GPIO_DEVICE(3), + GPIO_DEVICE(4), + GPIO_DEVICE(5), + GPIO_DEVICE(6), + GPIO_DEVICE(7), + GPIO_DEVICE(8), +}; + +struct amba_device u8500_ssp0_device = { + .dev = { + .coherent_dma_mask = ~0, + .init_name = "ssp0", + }, + .res = { + .start = U8500_SSP0_BASE, + .end = U8500_SSP0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_SSP0, NO_IRQ }, + /* ST-Ericsson modified id */ + .periphid = SSP_PER_ID, +}; + +static struct resource u8500_i2c0_resources[] = { + [0] = { + .start = U8500_I2C0_BASE, + .end = U8500_I2C0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C0, + .end = IRQ_I2C0, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device u8500_i2c0_device = { + .name = "nmk-i2c", + .id = 0, + .resource = u8500_i2c0_resources, + .num_resources = ARRAY_SIZE(u8500_i2c0_resources), +}; + +static struct resource u8500_i2c4_resources[] = { + [0] = { + .start = U8500_I2C4_BASE, + .end = U8500_I2C4_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C4, + .end = IRQ_I2C4, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device u8500_i2c4_device = { + .name = "nmk-i2c", + .id = 4, + .resource = u8500_i2c4_resources, + .num_resources = ARRAY_SIZE(u8500_i2c4_resources), +}; diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c new file mode 100644 index 00000000000..8a268893cb7 --- /dev/null +++ b/arch/arm/mach-ux500/devices.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/amba/bus.h> + +#include <mach/hardware.h> +#include <mach/setup.h> + +#define __MEM_4K_RESOURCE(x) \ + .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM} + +struct amba_device ux500_pl031_device = { + .dev = { + .init_name = "pl031", + }, + .res = { + .start = UX500_RTC_BASE, + .end = UX500_RTC_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_RTC_RTT, NO_IRQ}, +}; + +struct amba_device ux500_uart0_device = { + .dev = { .init_name = "uart0" }, + __MEM_4K_RESOURCE(UX500_UART0_BASE), + .irq = {IRQ_UART0, NO_IRQ}, +}; + +struct amba_device ux500_uart1_device = { + .dev = { .init_name = "uart1" }, + __MEM_4K_RESOURCE(UX500_UART1_BASE), + .irq = {IRQ_UART1, NO_IRQ}, +}; + +struct amba_device ux500_uart2_device = { + .dev = { .init_name = "uart2" }, + __MEM_4K_RESOURCE(UX500_UART2_BASE), + .irq = {IRQ_UART2, NO_IRQ}, +}; + +#define UX500_I2C_RESOURCES(id, size) \ +static struct resource ux500_i2c##id##_resources[] = { \ + [0] = { \ + .start = UX500_I2C##id##_BASE, \ + .end = UX500_I2C##id##_BASE + size - 1, \ + .flags = IORESOURCE_MEM, \ + }, \ + [1] = { \ + .start = IRQ_I2C##id, \ + .end = IRQ_I2C##id, \ + .flags = IORESOURCE_IRQ \ + } \ +} + +UX500_I2C_RESOURCES(1, SZ_4K); +UX500_I2C_RESOURCES(2, SZ_4K); +UX500_I2C_RESOURCES(3, SZ_4K); + +#define UX500_I2C_PDEVICE(cid) \ +struct platform_device ux500_i2c##cid##_device = { \ + .name = "nmk-i2c", \ + .id = cid, \ + .num_resources = 2, \ + .resource = ux500_i2c##cid##_resources, \ +} + +UX500_I2C_PDEVICE(1); +UX500_I2C_PDEVICE(2); +UX500_I2C_PDEVICE(3); + +void __init amba_add_devices(struct amba_device *devs[], int num) +{ + int i; + + for (i = 0; i < num; i++) { + struct amba_device *d = devs[i]; + amba_device_register(d, &iomem_resource); + } +} diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h new file mode 100644 index 00000000000..545c80fc802 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h @@ -0,0 +1,103 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __MACH_DB5500_REGS_H +#define __MACH_DB5500_REGS_H + +#define U5500_PER1_BASE 0xA0020000 +#define U5500_PER2_BASE 0xA0010000 +#define U5500_PER3_BASE 0x80140000 +#define U5500_PER4_BASE 0x80150000 +#define U5500_PER5_BASE 0x80100000 +#define U5500_PER6_BASE 0x80120000 + +#define U5500_GIC_DIST_BASE 0xA0411000 +#define U5500_GIC_CPU_BASE 0xA0410100 +#define U5500_DMA_BASE 0x90030000 +#define U5500_MCDE_BASE 0xA0400000 +#define U5500_MODEM_BASE 0xB0000000 +#define U5500_L2CC_BASE 0xA0412000 +#define U5500_SCU_BASE 0xA0410000 +#define U5500_DSI1_BASE 0xA0401000 +#define U5500_DSI2_BASE 0xA0402000 +#define U5500_SIA_BASE 0xA0100000 +#define U5500_SVA_BASE 0x80200000 +#define U5500_HSEM_BASE 0xA0000000 +#define U5500_NAND0_BASE 0x60000000 +#define U5500_NAND1_BASE 0x70000000 +#define U5500_TWD_BASE 0xa0410600 +#define U5500_B2R2_BASE 0xa0200000 + +#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000) +#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000) +#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000) +#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000) +#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000) +#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000) +#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000) +#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000) + +#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000) +#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000) +#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000) + +#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000) +#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000) +#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000) +#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000) + +#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000) +#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000) +#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000) +#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000) +#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000) +#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) +#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) +#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) +#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) +#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) +#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) + +#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) +#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) +#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000) +#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000) +#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000) +#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000) +#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000) +#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000) +#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000) +#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000) +#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000) +#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000) +#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000) +#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000) +#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000) +#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000) +#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000) + +#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000) +#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000) +#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000) +#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000) +#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5000) +#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000) +#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000) +#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000) +#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000) +#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000) +#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000) + +#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE +#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80) +#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE +#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE +#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE +#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE +#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80) +#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100) + +#endif diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h new file mode 100644 index 00000000000..9169e1e382a --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __MACH_DB8500_REGS_H +#define __MACH_DB8500_REGS_H + +#define U8500_PER3_BASE 0x80000000 +#define U8500_STM_BASE 0x80100000 +#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000) +#define U8500_PER2_BASE 0x80110000 +#define U8500_PER1_BASE 0x80120000 +#define U8500_B2R2_BASE 0x80130000 +#define U8500_HSEM_BASE 0x80140000 +#define U8500_PER4_BASE 0x80150000 +#define U8500_ICN_BASE 0x81000000 + +#define U8500_BOOT_ROM_BASE 0x90000000 +/* ASIC ID is at 0xff4 offset within this region */ +#define U8500_ASIC_ID_BASE 0x9001F000 + +#define U8500_PER6_BASE 0xa03c0000 +#define U8500_PER5_BASE 0xa03e0000 +#define U8500_PER7_BASE_ED 0xa03d0000 + +#define U8500_SVA_BASE 0xa0100000 +#define U8500_SIA_BASE 0xa0200000 + +#define U8500_SGA_BASE 0xa0300000 +#define U8500_MCDE_BASE 0xa0350000 +#define U8500_DMA_BASE_ED 0xa0362000 +#define U8500_DMA_BASE 0x801C0000 /* v1 */ + +#define U8500_SBAG_BASE 0xa0390000 + +#define U8500_SCU_BASE 0xa0410000 +#define U8500_GIC_CPU_BASE 0xa0410100 +#define U8500_TWD_BASE 0xa0410600 +#define U8500_GIC_DIST_BASE 0xa0411000 +#define U8500_L2CC_BASE 0xa0412000 + +#define U8500_MODEM_I2C 0xb7e02000 + +#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) +#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000) +#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) +#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) + +/* per7 base addressess */ +#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000) +#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) +#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) +#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000) +#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000) + +#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) +#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) + +/* per6 base addressess */ +#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) +#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) +#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) +#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ +#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ +#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ +#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000) +#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) +#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) + +/* per5 base addressess */ +#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) +#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) + +/* per4 base addressess */ +#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) +#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) +#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) +#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000) +#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000) +#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) +#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) +#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) +#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000) + +/* per3 base addresses */ +#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) +#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) +#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) +#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) +#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) +#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) +#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) +#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) +#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) + +/* per2 base addressess */ +#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) +#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) +#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) +#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) +#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) +#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) +#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) +#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) +#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) +#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) +#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) +#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) + +/* per1 base addresses */ +#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) +#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) +#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) +#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) +#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) +#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) +#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000) +#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000) +#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) + +#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040 + +#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE +#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80) +#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE +#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80) +#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100) +#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180) +#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE +#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80) +#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE + +#endif diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S index 09cbfda8aee..c5203b7ea55 100644 --- a/arch/arm/mach-ux500/include/mach/debug-macro.S +++ b/arch/arm/mach-ux500/include/mach/debug-macro.S @@ -10,11 +10,19 @@ */ #include <mach/hardware.h> +#if CONFIG_UX500_DEBUG_UART > 2 +#error Invalid Ux500 debug UART +#endif + +#define __UX500_UART(n) UX500_UART##n##_BASE +#define UX500_UART(n) __UX500_UART(n) +#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - ldreq \rx, =U8500_UART2_BASE @ no, physical address - ldrne \rx, =IO_ADDRESS(U8500_UART2_BASE) @ yes, virtual address + ldreq \rx, =UART_BASE @ no, physical address + ldrne \rx, =IO_ADDRESS(UART_BASE) @ yes, virtual address .endm #include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h new file mode 100644 index 00000000000..0422af00a56 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __ASM_ARCH_DEVICES_H__ +#define __ASM_ARCH_DEVICES_H__ + +struct platform_device; +struct amba_device; + +extern struct platform_device u5500_gpio_devs[]; +extern struct platform_device u8500_gpio_devs[]; + +extern struct amba_device ux500_pl031_device; +extern struct amba_device u8500_ssp0_device; +extern struct amba_device ux500_uart0_device; +extern struct amba_device ux500_uart1_device; +extern struct amba_device ux500_uart2_device; + +extern struct platform_device ux500_i2c1_device; +extern struct platform_device ux500_i2c2_device; +extern struct platform_device ux500_i2c3_device; + +extern struct platform_device u8500_i2c0_device; +extern struct platform_device u8500_i2c4_device; + +#endif diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S index eece3301fef..60ea88db828 100644 --- a/arch/arm/mach-ux500/include/mach/entry-macro.S +++ b/arch/arm/mach-ux500/include/mach/entry-macro.S @@ -17,7 +17,7 @@ .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =IO_ADDRESS(U8500_GIC_CPU_BASE) + ldr \base, =IO_ADDRESS(UX500_GIC_CPU_BASE) .endm .macro arch_ret_to_user, tmp1, tmp2 diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h new file mode 100644 index 00000000000..d548a622e7d --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/gpio.h @@ -0,0 +1,50 @@ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +/* + * 288 (#267 is the highest one actually hooked up) onchip GPIOs, plus enough + * room for a couple of GPIO expanders. + */ +#define ARCH_NR_GPIOS 350 + +#include <plat/gpio.h> + +#define __GPIO_RESOURCE(soc, block) \ + { \ + .start = soc##_GPIOBANK##block##_BASE, \ + .end = soc##_GPIOBANK##block##_BASE + 127, \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = IRQ_GPIO##block, \ + .end = IRQ_GPIO##block, \ + .flags = IORESOURCE_IRQ, \ + } + +#define __GPIO_DEVICE(soc, block) \ + { \ + .name = "gpio", \ + .id = block, \ + .num_resources = 2, \ + .resource = &soc##_gpio_resources[block * 2], \ + .dev = { \ + .platform_data = &soc##_gpio_data[block], \ + }, \ + } + +#define GPIO_DATA(_name, first) \ + { \ + .name = _name, \ + .first_gpio = first, \ + .first_irq = NOMADIK_GPIO_TO_IRQ(first), \ + } + +#ifdef CONFIG_UX500_SOC_DB8500 +#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U8500, block) +#define GPIO_DEVICE(block) __GPIO_DEVICE(u8500, block) +#elif defined(CONFIG_UX500_SOC_DB5500) +#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U5500, block) +#define GPIO_DEVICE(block) __GPIO_DEVICE(u5500, block) +#endif + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 04ea836969b..8656379a830 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -23,109 +23,106 @@ /* typesafe io address */ #define __io_address(n) __io(IO_ADDRESS(n)) +/* used by some plat-nomadik code */ +#define io_p2v(n) __io_address(n) -/* - * Base address definitions for U8500 Onchip IPs. All the - * peripherals are contained in a single 1 Mbyte region, with - * AHB peripherals at the bottom and APB peripherals at the - * top of the region. PER stands for PERIPHERAL region which - * itself divided into sub regions. - */ -#define U8500_PER3_BASE 0x80000000 -#define U8500_PER2_BASE 0x80110000 -#define U8500_PER1_BASE 0x80120000 -#define U8500_PER4_BASE 0x80150000 - -#define U8500_PER6_BASE 0xa03c0000 -#define U8500_PER5_BASE 0xa03e0000 -#define U8500_PER7_BASE 0xa03d0000 - -#define U8500_SVA_BASE 0xa0100000 -#define U8500_SIA_BASE 0xa0200000 - -#define U8500_SGA_BASE 0xa0300000 -#define U8500_MCDE_BASE 0xa0350000 -#define U8500_DMA_BASE 0xa0362000 - -#define U8500_SCU_BASE 0xa0410000 -#define U8500_GIC_CPU_BASE 0xa0410100 -#define U8500_TWD_BASE 0xa0410600 -#define U8500_GIC_DIST_BASE 0xa0411000 -#define U8500_L2CC_BASE 0xa0412000 - -#define U8500_TWD_SIZE 0x100 - -/* per7 base addressess */ -#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000) -#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000) -#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000) -#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000) -#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000) - -/* per6 base addressess */ -#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) -#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) -#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) -#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000) -#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) -#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) - -/* per5 base addressess */ -#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) -#define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000) -#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) - -/* per4 base addressess */ -#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000) -#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000) -#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000) -#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000) -#define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000) -#define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000) -#define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000) -#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000) - -/* per3 base addressess */ -#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) -#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) -#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) -#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) -#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) -#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) -#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) -#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) -#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000) -#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) - -/* per2 base addressess */ -#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) -#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) -#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) -#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) -#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) -#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) -#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) -#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) -#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) -#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) -#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) -#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000) -#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) - -/* per1 base addresses */ -#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) -#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) -#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) -#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) -#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) -#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) -#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) -#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) -#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000) -#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000) -#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) +#include <mach/db8500-regs.h> +#include <mach/db5500-regs.h> + +#ifdef CONFIG_UX500_SOC_DB8500 +#define UX500(periph) U8500_##periph##_BASE +#elif defined(CONFIG_UX500_SOC_DB5500) +#define UX500(periph) U5500_##periph##_BASE +#endif + +#define UX500_BACKUPRAM0_BASE UX500(BACKUPRAM0) +#define UX500_BACKUPRAM1_BASE UX500(BACKUPRAM1) +#define UX500_B2R2_BASE UX500(B2R2) + +#define UX500_CLKRST1_BASE UX500(CLKRST1) +#define UX500_CLKRST2_BASE UX500(CLKRST2) +#define UX500_CLKRST3_BASE UX500(CLKRST3) +#define UX500_CLKRST5_BASE UX500(CLKRST5) +#define UX500_CLKRST6_BASE UX500(CLKRST6) + +#define UX500_DMA_BASE UX500(DMA) +#define UX500_FSMC_BASE UX500(FSMC) + +#define UX500_GIC_CPU_BASE UX500(GIC_CPU) +#define UX500_GIC_DIST_BASE UX500(GIC_DIST) + +#define UX500_I2C1_BASE UX500(I2C1) +#define UX500_I2C2_BASE UX500(I2C2) +#define UX500_I2C3_BASE UX500(I2C3) + +#define UX500_L2CC_BASE UX500(L2CC) +#define UX500_MCDE_BASE UX500(MCDE) +#define UX500_MTU0_BASE UX500(MTU0) +#define UX500_MTU1_BASE UX500(MTU1) +#define UX500_PRCMU_BASE UX500(PRCMU) + +#define UX500_RNG_BASE UX500(RNG) +#define UX500_RTC_BASE UX500(RTC) + +#define UX500_SCU_BASE UX500(SCU) + +#define UX500_SDI0_BASE UX500(SDI0) +#define UX500_SDI1_BASE UX500(SDI1) +#define UX500_SDI2_BASE UX500(SDI2) +#define UX500_SDI3_BASE UX500(SDI3) +#define UX500_SDI4_BASE UX500(SDI4) + +#define UX500_SPI0_BASE UX500(SPI0) +#define UX500_SPI1_BASE UX500(SPI1) +#define UX500_SPI2_BASE UX500(SPI2) +#define UX500_SPI3_BASE UX500(SPI3) + +#define UX500_SIA_BASE UX500(SIA) +#define UX500_SVA_BASE UX500(SVA) + +#define UX500_TWD_BASE UX500(TWD) + +#define UX500_UART0_BASE UX500(UART0) +#define UX500_UART1_BASE UX500(UART1) +#define UX500_UART2_BASE UX500(UART2) + +#define UX500_USBOTG_BASE UX500(USBOTG) /* ST-Ericsson modified pl022 id */ #define SSP_PER_ID 0x01080022 +#ifndef __ASSEMBLY__ + +#include <asm/cputype.h> + +static inline bool cpu_is_u8500(void) +{ +#ifdef CONFIG_UX500_SOC_DB8500 + return 1; +#else + return 0; +#endif +} + +static inline bool cpu_is_u8500ed(void) +{ + return cpu_is_u8500() && (read_cpuid_id() & 15) == 0; +} + +static inline bool cpu_is_u8500v1(void) +{ + return cpu_is_u8500() && (read_cpuid_id() & 15) == 1; +} + +static inline bool cpu_is_u5500(void) +{ +#ifdef CONFIG_UX500_SOC_DB5500 + return 1; +#else + return 0; +#endif +} + +#endif + #endif /* __MACH_HARDWARE_H */ diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index 394b5dd2200..7970684b1d0 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -42,6 +42,7 @@ #define IRQ_AB4500 (IRQ_SHPI_START + 40) #define IRQ_DISP (IRQ_SHPI_START + 48) #define IRQ_SiPI3 (IRQ_SHPI_START + 49) +#define IRQ_I2C4 (IRQ_SHPI_START + 51) #define IRQ_SSP1 (IRQ_SHPI_START + 52) #define IRQ_I2C2 (IRQ_SHPI_START + 55) #define IRQ_SDMMC0 (IRQ_SHPI_START + 60) @@ -66,6 +67,12 @@ /* There are 128 shared peripheral interrupts assigned to * INTID[160:32]. The first 32 interrupts are reserved. */ -#define NR_IRQS 161 +#define U8500_SOC_NR_IRQS 161 + +/* After chip-specific IRQ numbers we have the GPIO ones */ +#define NOMADIK_NR_GPIO 288 +#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + U8500_SOC_NR_IRQS) +#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - U8500_SOC_NR_IRQS) +#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) #endif /*ASM_ARCH_IRQS_H*/ diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h index cf0ce1687f2..e978dbd9e21 100644 --- a/arch/arm/mach-ux500/include/mach/setup.h +++ b/arch/arm/mach-ux500/include/mach/setup.h @@ -14,10 +14,28 @@ #include <asm/mach/time.h> #include <linux/init.h> -extern void u8500_map_io(void); -extern void u8500_init_devices(void); -extern void u8500_init_irq(void); +extern void __init ux500_map_io(void); +extern void __init u5500_map_io(void); +extern void __init u8500_map_io(void); + +extern void __init ux500_init_devices(void); +extern void __init u5500_init_devices(void); +extern void __init u8500_init_devices(void); + +extern void __init ux500_init_irq(void); /* We re-use nomadik_timer for this platform */ extern void nmdk_timer_init(void); +extern void __init amba_add_devices(struct amba_device *devs[], int num); + +struct sys_timer; +extern struct sys_timer ux500_timer; + +#define __IO_DEV_DESC(x, sz) { \ + .virtual = IO_ADDRESS(x), \ + .pfn = __phys_to_pfn(x), \ + .length = sz, \ + .type = MT_DEVICE, \ +} + #endif /* __ASM_ARCH_SETUP_H */ diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 8dfe7ca245d..438ef16aec9 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -30,7 +30,7 @@ volatile int __cpuinitdata pen_release = -1; static unsigned int __init get_core_count(void) { - return scu_get_core_count(__io_address(U8500_SCU_BASE)); + return scu_get_core_count(__io_address(UX500_SCU_BASE)); } static DEFINE_SPINLOCK(boot_lock); @@ -44,7 +44,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ - gic_cpu_init(0, __io_address(U8500_GIC_CPU_BASE)); + gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE)); /* * let the primary processor know we're out of the @@ -75,7 +75,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * that it has been released by resetting pen_release. */ pen_release = cpu; - flush_cache_all(); + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { @@ -105,12 +106,12 @@ static void __init wakeup_secondary(void) */ #define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4 __raw_writel(virt_to_phys(u8500_secondary_startup), - (void __iomem *)IO_ADDRESS(U8500_BACKUPRAM0_BASE) + + __io_address(UX500_BACKUPRAM0_BASE) + U8500_CPU1_JUMPADDR_OFFSET); #define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 __raw_writel(0xA1FEED01, - (void __iomem *)IO_ADDRESS(U8500_BACKUPRAM0_BASE) + + __io_address(UX500_BACKUPRAM0_BASE) + U8500_CPU1_WAKEMAGIC_OFFSET); /* make sure write buffer is drained */ @@ -171,7 +172,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) * boot CPU, but only if we have more than one CPU. */ percpu_timer_setup(); - scu_enable(__io_address(U8500_SCU_BASE)); + scu_enable(__io_address(UX500_SCU_BASE)); wakeup_secondary(); } } diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile index ba81e70ed81..97cf4d831b0 100644 --- a/arch/arm/mach-versatile/Makefile +++ b/arch/arm/mach-versatile/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := core.o clock.o +obj-y := core.o obj-$(CONFIG_ARCH_VERSATILE_PB) += versatile_pb.o obj-$(CONFIG_MACH_VERSATILE_AB) += versatile_ab.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/arm/mach-versatile/clock.c b/arch/arm/mach-versatile/clock.c deleted file mode 100644 index c50a44ea7ee..00000000000 --- a/arch/arm/mach-versatile/clock.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * linux/arch/arm/mach-versatile/clock.c - * - * Copyright (C) 2004 ARM Limited. - * Written by Deep Blue Solutions Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/string.h> -#include <linux/clk.h> -#include <linux/mutex.h> - -#include <asm/clkdev.h> -#include <asm/hardware/icst307.h> - -#include "clock.h" - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - struct icst307_vco vco; - vco = icst307_khz_to_vco(clk->params, rate / 1000); - return icst307_khz(clk->params, vco) * 1000; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EIO; - - if (clk->setvco) { - struct icst307_vco vco; - - vco = icst307_khz_to_vco(clk->params, rate / 1000); - clk->rate = icst307_khz(clk->params, vco) * 1000; - clk->setvco(clk, vco); - ret = 0; - } - return ret; -} -EXPORT_SYMBOL(clk_set_rate); diff --git a/arch/arm/mach-versatile/clock.h b/arch/arm/mach-versatile/clock.h deleted file mode 100644 index 03468fdc3e5..00000000000 --- a/arch/arm/mach-versatile/clock.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * linux/arch/arm/mach-versatile/clock.h - * - * Copyright (C) 2004 ARM Limited. - * Written by Deep Blue Solutions Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -struct module; -struct icst307_params; - -struct clk { - unsigned long rate; - const struct icst307_params *params; - u32 oscoff; - void *data; - void (*setvco)(struct clk *, struct icst307_vco vco); -}; diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 3b1a4ee0181..3dff8641b03 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -28,19 +28,15 @@ #include <linux/amba/clcd.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> -#include <linux/cnt32_to_63.h> #include <linux/io.h> #include <linux/gfp.h> #include <asm/clkdev.h> #include <asm/system.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/leds.h> #include <asm/hardware/arm_timer.h> -#include <asm/hardware/icst307.h> +#include <asm/hardware/icst.h> #include <asm/hardware/vic.h> #include <asm/mach-types.h> @@ -49,9 +45,12 @@ #include <asm/mach/irq.h> #include <asm/mach/time.h> #include <asm/mach/map.h> +#include <mach/clkdev.h> +#include <mach/hardware.h> +#include <mach/platform.h> +#include <plat/timer-sp.h> #include "core.h" -#include "clock.h" /* * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx @@ -59,7 +58,6 @@ * * Setup a VA for the Versatile Vectored Interrupt Controller. */ -#define __io_address(n) __io(IO_ADDRESS(n)) #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) @@ -229,27 +227,6 @@ void __init versatile_map_io(void) iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc)); } -#define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET) - -/* - * This is the Versatile sched_clock implementation. This has - * a resolution of 41.7ns, and a maximum value of about 35583 days. - * - * The return value is guaranteed to be monotonic in that range as - * long as there is always less than 89 seconds between successive - * calls to this function. - */ -unsigned long long sched_clock(void) -{ - unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER)); - - /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */ - v *= 125<<1; - do_div(v, 3<<1); - - return v; -} - #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET) @@ -380,33 +357,40 @@ static struct mmci_platform_data mmc0_plat_data = { /* * Clock handling */ -static const struct icst307_params versatile_oscvco_params = { - .ref = 24000, - .vco_max = 200000, +static const struct icst_params versatile_oscvco_params = { + .ref = 24000000, + .vco_max = ICST307_VCO_MAX, + .vco_min = ICST307_VCO_MIN, .vd_min = 4 + 8, .vd_max = 511 + 8, .rd_min = 1 + 2, .rd_max = 127 + 2, + .s2div = icst307_s2div, + .idx2s = icst307_idx2s, }; -static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco) +static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco) { - void __iomem *sys = __io_address(VERSATILE_SYS_BASE); - void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET; + void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET; u32 val; - val = readl(sys + clk->oscoff) & ~0x7ffff; + val = readl(clk->vcoreg) & ~0x7ffff; val |= vco.v | (vco.r << 9) | (vco.s << 16); writel(0xa05f, sys_lock); - writel(val, sys + clk->oscoff); + writel(val, clk->vcoreg); writel(0, sys_lock); } +static const struct clk_ops osc4_clk_ops = { + .round = icst_clk_round, + .set = icst_clk_set, + .setvco = versatile_oscvco_set, +}; + static struct clk osc4_clk = { + .ops = &osc4_clk_ops, .params = &versatile_oscvco_params, - .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET, - .setvco = versatile_oscvco_set, }; /* @@ -852,6 +836,8 @@ void __init versatile_init(void) { int i; + osc4_clk.vcoreg = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET; + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); platform_device_register(&versatile_flash_device); @@ -875,120 +861,6 @@ void __init versatile_init(void) #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20) #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE) #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20) -#define VA_IC_BASE __io_address(VERSATILE_VIC_BASE) - -/* - * How long is the timer interval? - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) -#if TIMER_INTERVAL >= 0x100000 -#define TIMER_RELOAD (TIMER_INTERVAL >> 8) -#define TIMER_DIVISOR (TIMER_CTRL_DIV256) -#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) -#elif TIMER_INTERVAL >= 0x10000 -#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */ -#define TIMER_DIVISOR (TIMER_CTRL_DIV16) -#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) -#else -#define TIMER_RELOAD (TIMER_INTERVAL) -#define TIMER_DIVISOR (TIMER_CTRL_DIV1) -#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) -#endif - -static void timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk) -{ - unsigned long ctrl; - - switch(mode) { - case CLOCK_EVT_MODE_PERIODIC: - writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); - - ctrl = TIMER_CTRL_PERIODIC; - ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; - break; - case CLOCK_EVT_MODE_ONESHOT: - /* period set, and timer enabled in 'next_event' hook */ - ctrl = TIMER_CTRL_ONESHOT; - ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE; - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - default: - ctrl = 0; - } - - writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); -} - -static int timer_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); - - writel(evt, TIMER0_VA_BASE + TIMER_LOAD); - writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); - - return 0; -} - -static struct clock_event_device timer0_clockevent = { - .name = "timer0", - .shift = 32, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = timer_set_mode, - .set_next_event = timer_set_next_event, -}; - -/* - * IRQ handler for the timer - */ -static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &timer0_clockevent; - - writel(1, TIMER0_VA_BASE + TIMER_INTCLR); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction versatile_timer_irq = { - .name = "Versatile Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = versatile_timer_interrupt, -}; - -static cycle_t versatile_get_cycles(struct clocksource *cs) -{ - return ~readl(TIMER3_VA_BASE + TIMER_VALUE); -} - -static struct clocksource clocksource_versatile = { - .name = "timer3", - .rating = 200, - .read = versatile_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .shift = 20, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int __init versatile_clocksource_init(void) -{ - /* setup timer3 as free-running clocksource */ - writel(0, TIMER3_VA_BASE + TIMER_CTRL); - writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); - writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); - writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - TIMER3_VA_BASE + TIMER_CTRL); - - clocksource_versatile.mult = - clocksource_khz2mult(1000, clocksource_versatile.shift); - clocksource_register(&clocksource_versatile); - - return 0; -} /* * Set up timer interrupt, and return the current time in seconds. @@ -1017,22 +889,8 @@ static void __init versatile_timer_init(void) writel(0, TIMER2_VA_BASE + TIMER_CTRL); writel(0, TIMER3_VA_BASE + TIMER_CTRL); - /* - * Make irqs happen for the system timer - */ - setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq); - - versatile_clocksource_init(); - - timer0_clockevent.mult = - div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); - timer0_clockevent.max_delta_ns = - clockevent_delta2ns(0xffffffff, &timer0_clockevent); - timer0_clockevent.min_delta_ns = - clockevent_delta2ns(0xf, &timer0_clockevent); - - timer0_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&timer0_clockevent); + sp804_clocksource_init(TIMER3_VA_BASE); + sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1); } struct sys_timer versatile_timer = { diff --git a/arch/arm/mach-versatile/include/mach/clkdev.h b/arch/arm/mach-versatile/include/mach/clkdev.h index 04b37a89801..e58d0771b64 100644 --- a/arch/arm/mach-versatile/include/mach/clkdev.h +++ b/arch/arm/mach-versatile/include/mach/clkdev.h @@ -1,6 +1,15 @@ #ifndef __ASM_MACH_CLKDEV_H #define __ASM_MACH_CLKDEV_H +#include <plat/clock.h> + +struct clk { + unsigned long rate; + const struct clk_ops *ops; + const struct icst_params *params; + void __iomem *vcoreg; +}; + #define __clk_get(clk) ({ 1; }) #define __clk_put(clk) do { } while (0) diff --git a/arch/arm/mach-versatile/include/mach/entry-macro.S b/arch/arm/mach-versatile/include/mach/entry-macro.S index 8c802098058..e6f7c166316 100644 --- a/arch/arm/mach-versatile/include/mach/entry-macro.S +++ b/arch/arm/mach-versatile/include/mach/entry-macro.S @@ -8,6 +8,7 @@ * warranty of any kind, whether express or implied. */ #include <mach/hardware.h> +#include <mach/platform.h> #include <asm/hardware/vic.h> .macro disable_fiq diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h index 7aa906c9315..4f8f99aac93 100644 --- a/arch/arm/mach-versatile/include/mach/hardware.h +++ b/arch/arm/mach-versatile/include/mach/hardware.h @@ -23,7 +23,6 @@ #define __ASM_ARCH_HARDWARE_H #include <asm/sizes.h> -#include <mach/platform.h> /* * PCI space virtual addresses @@ -49,4 +48,6 @@ /* macro to get at IO space when running virtually */ #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) +#define __io_address(n) __io(IO_ADDRESS(n)) + #endif diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h index 83207395191..ec087407b16 100644 --- a/arch/arm/mach-versatile/include/mach/platform.h +++ b/arch/arm/mach-versatile/include/mach/platform.h @@ -205,7 +205,7 @@ #define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */ #define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */ #define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */ -#define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */ +#define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */ /* 0x10000000 - 0x100FFFFF */ #define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */ #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ @@ -213,7 +213,7 @@ #define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */ #define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */ #define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */ -#define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */ +#define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */ #define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */ #define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */ #define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */ @@ -379,12 +379,6 @@ #define SIC_INT_PCI3 30 -/* - * Clean base - dummy - * - */ -#define CLEAN_BASE VERSATILE_BOOT_ROM_HI - /* * System controller bit assignment */ @@ -397,20 +391,6 @@ #define VERSATILE_TIMER4_EnSel 21 -#define MAX_TIMER 2 -#define MAX_PERIOD 699050 -#define TICKS_PER_uSEC 1 - -/* - * These are useconds NOT ticks. - * - */ -#define mSEC_1 1000 -#define mSEC_5 (mSEC_1 * 5) -#define mSEC_10 (mSEC_1 * 10) -#define mSEC_25 (mSEC_1 * 25) -#define SEC_1 (mSEC_1 * 1000) - #define VERSATILE_CSR_BASE 0x10000000 #define VERSATILE_CSR_SIZE 0x10000000 @@ -432,5 +412,3 @@ #endif #endif - -/* END */ diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig new file mode 100644 index 00000000000..3f19b660a16 --- /dev/null +++ b/arch/arm/mach-vexpress/Kconfig @@ -0,0 +1,9 @@ +menu "Versatile Express platform type" + depends on ARCH_VEXPRESS + +config ARCH_VEXPRESS_CA9X4 + bool "Versatile Express Cortex-A9x4 tile" + select CPU_V7 + select ARM_GIC + +endmenu diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile new file mode 100644 index 00000000000..1b71b77ade2 --- /dev/null +++ b/arch/arm/mach-vexpress/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# + +obj-y := v2m.o +obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot new file mode 100644 index 00000000000..07c2d9c457e --- /dev/null +++ b/arch/arm/mach-vexpress/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x60008000 +params_phys-y := 0x60000100 +initrd_phys-y := 0x60800000 diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h new file mode 100644 index 00000000000..57dd95ce41f --- /dev/null +++ b/arch/arm/mach-vexpress/core.h @@ -0,0 +1,26 @@ +#define __MMIO_P2V(x) (((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000) +#define MMIO_P2V(x) ((void __iomem *)__MMIO_P2V(x)) + +#define AMBA_DEVICE(name,busid,base,plat) \ +struct amba_device name##_device = { \ + .dev = { \ + .coherent_dma_mask = ~0UL, \ + .init_name = busid, \ + .platform_data = plat, \ + }, \ + .res = { \ + .start = base, \ + .end = base + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, \ + .dma_mask = ~0UL, \ + .irq = IRQ_##base, \ + /* .dma = DMA_##base,*/ \ +} + +struct map_desc; + +void v2m_map_io(struct map_desc *tile, size_t num); +extern struct sys_timer v2m_timer; + +extern void __iomem *gic_cpu_base_addr; diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c new file mode 100644 index 00000000000..e6f73030d5f --- /dev/null +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -0,0 +1,249 @@ +/* + * Versatile Express Core Tile Cortex A9x4 Support + */ +#include <linux/init.h> +#include <linux/device.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/amba/bus.h> +#include <linux/amba/clcd.h> + +#include <asm/clkdev.h> +#include <asm/hardware/arm_timer.h> +#include <asm/hardware/cache-l2x0.h> +#include <asm/hardware/gic.h> +#include <asm/mach-types.h> +#include <asm/pmu.h> + +#include <mach/clkdev.h> +#include <mach/ct-ca9x4.h> + +#include <plat/timer-sp.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> + +#include "core.h" + +#include <mach/motherboard.h> + +#define V2M_PA_CS7 0x10000000 + +static struct map_desc ct_ca9x4_io_desc[] __initdata = { + { + .virtual = __MMIO_P2V(CT_CA9X4_MPIC), + .pfn = __phys_to_pfn(CT_CA9X4_MPIC), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER), + .pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = __MMIO_P2V(CT_CA9X4_L2CC), + .pfn = __phys_to_pfn(CT_CA9X4_L2CC), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static void __init ct_ca9x4_map_io(void) +{ + v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); +} + +void __iomem *gic_cpu_base_addr; + +static void __init ct_ca9x4_init_irq(void) +{ + gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU); + gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29); + gic_cpu_init(0, gic_cpu_base_addr); +} + +#if 0 +static void ct_ca9x4_timer_init(void) +{ + writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL); + writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL); + + sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1)); + sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0); +} + +static struct sys_timer ct_ca9x4_timer = { + .init = ct_ca9x4_timer_init, +}; +#endif + +static struct clcd_panel xvga_panel = { + .mode = { + .name = "XVGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15384, + .left_margin = 168, + .right_margin = 8, + .upper_margin = 29, + .lower_margin = 3, + .hsync_len = 144, + .vsync_len = 6, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, + .width = -1, + .height = -1, + .tim2 = TIM2_BCD | TIM2_IPC, + .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), + .bpp = 16, +}; + +static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) +{ + v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0); + v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2); +} + +static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) +{ + unsigned long framesize = 1024 * 768 * 2; + dma_addr_t dma; + + fb->panel = &xvga_panel; + + fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, + &dma, GFP_KERNEL); + if (!fb->fb.screen_base) { + printk(KERN_ERR "CLCD: unable to map frame buffer\n"); + return -ENOMEM; + } + fb->fb.fix.smem_start = dma; + fb->fb.fix.smem_len = framesize; + + return 0; +} + +static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) +{ + return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base, + fb->fb.fix.smem_start, fb->fb.fix.smem_len); +} + +static void ct_ca9x4_clcd_remove(struct clcd_fb *fb) +{ + dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, + fb->fb.screen_base, fb->fb.fix.smem_start); +} + +static struct clcd_board ct_ca9x4_clcd_data = { + .name = "CT-CA9X4", + .check = clcdfb_check, + .decode = clcdfb_decode, + .enable = ct_ca9x4_clcd_enable, + .setup = ct_ca9x4_clcd_setup, + .mmap = ct_ca9x4_clcd_mmap, + .remove = ct_ca9x4_clcd_remove, +}; + +static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data); +static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL); +static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL); +static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL); + +static struct amba_device *ct_ca9x4_amba_devs[] __initdata = { + &clcd_device, + &dmc_device, + &smc_device, + &gpio_device, +}; + + +static long ct_round(struct clk *clk, unsigned long rate) +{ + return rate; +} + +static int ct_set(struct clk *clk, unsigned long rate) +{ + return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate); +} + +static const struct clk_ops osc1_clk_ops = { + .round = ct_round, + .set = ct_set, +}; + +static struct clk osc1_clk = { + .ops = &osc1_clk_ops, + .rate = 24000000, +}; + +static struct clk_lookup lookups[] = { + { /* CLCD */ + .dev_id = "ct:clcd", + .clk = &osc1_clk, + }, +}; + +static struct resource pmu_resources[] = { + [0] = { + .start = IRQ_CT_CA9X4_PMU_CPU0, + .end = IRQ_CT_CA9X4_PMU_CPU0, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = IRQ_CT_CA9X4_PMU_CPU1, + .end = IRQ_CT_CA9X4_PMU_CPU1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_CT_CA9X4_PMU_CPU2, + .end = IRQ_CT_CA9X4_PMU_CPU2, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_CT_CA9X4_PMU_CPU3, + .end = IRQ_CT_CA9X4_PMU_CPU3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = ARRAY_SIZE(pmu_resources), + .resource = pmu_resources, +}; + +static void ct_ca9x4_init(void) +{ + int i; + +#ifdef CONFIG_CACHE_L2X0 + l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00000000, 0xfe0fffff); +#endif + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) + amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); + + platform_device_register(&pmu_device); +} + +MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4") + .phys_io = V2M_UART0, + .io_pg_offst = (__MMIO_P2V(V2M_UART0) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x00000100, + .map_io = ct_ca9x4_map_io, + .init_irq = ct_ca9x4_init_irq, +#if 0 + .timer = &ct_ca9x4_timer, +#else + .timer = &v2m_timer, +#endif + .init_machine = ct_ca9x4_init, +MACHINE_END diff --git a/arch/arm/mach-vexpress/headsmp.S b/arch/arm/mach-vexpress/headsmp.S new file mode 100644 index 00000000000..8a78ff68e1e --- /dev/null +++ b/arch/arm/mach-vexpress/headsmp.S @@ -0,0 +1,39 @@ +/* + * linux/arch/arm/mach-vexpress/headsmp.S + * + * Copyright (c) 2003 ARM Limited + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <linux/init.h> + + __INIT + +/* + * Versatile Express specific entry point for secondary CPUs. This + * provides a "holding pen" into which all secondary cores are held + * until we're ready for them to initialise. + */ +ENTRY(vexpress_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + +1: .long . + .long pen_release diff --git a/arch/arm/mach-vexpress/include/mach/clkdev.h b/arch/arm/mach-vexpress/include/mach/clkdev.h new file mode 100644 index 00000000000..3f8307d73ca --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/clkdev.h @@ -0,0 +1,15 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#include <plat/clock.h> + +struct clk { + const struct clk_ops *ops; + unsigned long rate; + const struct icst_params *params; +}; + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h new file mode 100644 index 00000000000..8650f04136e --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h @@ -0,0 +1,47 @@ +#ifndef __MACH_CT_CA9X4_H +#define __MACH_CT_CA9X4_H + +/* + * Physical base addresses + */ +#define CT_CA9X4_CLCDC (0x10020000) +#define CT_CA9X4_AXIRAM (0x10060000) +#define CT_CA9X4_DMC (0x100e0000) +#define CT_CA9X4_SMC (0x100e1000) +#define CT_CA9X4_SCC (0x100e2000) +#define CT_CA9X4_SP804_TIMER (0x100e4000) +#define CT_CA9X4_SP805_WDT (0x100e5000) +#define CT_CA9X4_TZPC (0x100e6000) +#define CT_CA9X4_GPIO (0x100e8000) +#define CT_CA9X4_FASTAXI (0x100e9000) +#define CT_CA9X4_SLOWAXI (0x100ea000) +#define CT_CA9X4_TZASC (0x100ec000) +#define CT_CA9X4_CORESIGHT (0x10200000) +#define CT_CA9X4_MPIC (0x1e000000) +#define CT_CA9X4_SYSTIMER (0x1e004000) +#define CT_CA9X4_SYSWDT (0x1e007000) +#define CT_CA9X4_L2CC (0x1e00a000) + +#define CT_CA9X4_TIMER0 (CT_CA9X4_SP804_TIMER + 0x000) +#define CT_CA9X4_TIMER1 (CT_CA9X4_SP804_TIMER + 0x020) + +#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000) +#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100) +#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200) +#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000) + +/* + * Interrupts. Those in {} are for AMBA devices + */ +#define IRQ_CT_CA9X4_CLCDC { 76 } +#define IRQ_CT_CA9X4_DMC { -1 } +#define IRQ_CT_CA9X4_SMC { 77, 78 } +#define IRQ_CT_CA9X4_TIMER0 80 +#define IRQ_CT_CA9X4_TIMER1 81 +#define IRQ_CT_CA9X4_GPIO { 82 } +#define IRQ_CT_CA9X4_PMU_CPU0 92 +#define IRQ_CT_CA9X4_PMU_CPU1 93 +#define IRQ_CT_CA9X4_PMU_CPU2 94 +#define IRQ_CT_CA9X4_PMU_CPU3 95 + +#endif diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S new file mode 100644 index 00000000000..5167e2aceeb --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S @@ -0,0 +1,23 @@ +/* arch/arm/mach-realview/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define DEBUG_LL_UART_OFFSET 0x00009000 + + .macro addruart,rx,tmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x10000000 + movne \rx, #0xf8000000 @ virtual base + orr \rx, \rx, #DEBUG_LL_UART_OFFSET + .endm + +#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S new file mode 100644 index 00000000000..20e9fb514f0 --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/entry-macro.S @@ -0,0 +1,67 @@ +#include <asm/hardware/gic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =gic_cpu_base_addr + ldr \base, [\base] + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + /* + * The interrupt numbering scheme is defined in the + * interrupt controller spec. To wit: + * + * Interrupts 0-15 are IPI + * 16-28 are reserved + * 29-31 are local. We allow 30 to be used for the watchdog. + * 32-1020 are global + * 1021-1022 are reserved + * 1023 is "spurious" (no interrupt) + * + * For now, we ignore all local interrupts so only return an interrupt if it's + * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. + * + * A simple read from the controller will tell us the number of the highest + * priority enabled interrupt. We then just need to check whether it is in the + * valid range for an IRQ (30-1020 inclusive). + */ + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ + ldr \tmp, =1021 + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr + .endm + + /* We assume that irqstat (the raw value of the IRQ acknowledge + * register) is preserved from the macro above. + * If there is an IPI, we immediately signal end of interrupt on the + * controller, since this requires the original irqstat value which + * we won't easily be able to recreate later. + */ + + .macro test_for_ipi, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #16 + strcc \irqstat, [\base, #GIC_CPU_EOI] + cmpcs \irqnr, \irqnr + .endm + + /* As above, this assumes that irqstat and base are preserved.. */ + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #29 + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm + diff --git a/arch/arm/mach-vexpress/include/mach/hardware.h b/arch/arm/mach-vexpress/include/mach/hardware.h new file mode 100644 index 00000000000..40a8c178f10 --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/hardware.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-vexpress/include/mach/io.h b/arch/arm/mach-vexpress/include/mach/io.h new file mode 100644 index 00000000000..748bb524ee7 --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/io.h @@ -0,0 +1,28 @@ +/* + * arch/arm/mach-vexpress/include/mach/io.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-vexpress/include/mach/irqs.h b/arch/arm/mach-vexpress/include/mach/irqs.h new file mode 100644 index 00000000000..7054cbfc9de --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/irqs.h @@ -0,0 +1,4 @@ +#define IRQ_LOCALTIMER 29 +#define IRQ_LOCALWDOG 30 + +#define NR_IRQS 128 diff --git a/arch/arm/mach-vexpress/include/mach/memory.h b/arch/arm/mach-vexpress/include/mach/memory.h new file mode 100644 index 00000000000..be28232ae63 --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/memory.h @@ -0,0 +1,25 @@ +/* + * arch/arm/mach-vexpress/include/mach/memory.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x60000000) + +#endif diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h new file mode 100644 index 00000000000..98a8ded055b --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/motherboard.h @@ -0,0 +1,121 @@ +#ifndef __MACH_MOTHERBOARD_H +#define __MACH_MOTHERBOARD_H + +/* + * Physical addresses, offset from V2M_PA_CS0-3 + */ +#define V2M_NOR0 (V2M_PA_CS0) +#define V2M_NOR1 (V2M_PA_CS1) +#define V2M_SRAM (V2M_PA_CS2) +#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000) +#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000) +#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000) + +/* + * Physical addresses, offset from V2M_PA_CS7 + */ +#define V2M_SYSREGS (V2M_PA_CS7 + 0x00000000) +#define V2M_SYSCTL (V2M_PA_CS7 + 0x00001000) +#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + 0x00002000) + +#define V2M_AACI (V2M_PA_CS7 + 0x00004000) +#define V2M_MMCI (V2M_PA_CS7 + 0x00005000) +#define V2M_KMI0 (V2M_PA_CS7 + 0x00006000) +#define V2M_KMI1 (V2M_PA_CS7 + 0x00007000) + +#define V2M_UART0 (V2M_PA_CS7 + 0x00009000) +#define V2M_UART1 (V2M_PA_CS7 + 0x0000a000) +#define V2M_UART2 (V2M_PA_CS7 + 0x0000b000) +#define V2M_UART3 (V2M_PA_CS7 + 0x0000c000) + +#define V2M_WDT (V2M_PA_CS7 + 0x0000f000) + +#define V2M_TIMER01 (V2M_PA_CS7 + 0x00011000) +#define V2M_TIMER23 (V2M_PA_CS7 + 0x00012000) + +#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + 0x00016000) +#define V2M_RTC (V2M_PA_CS7 + 0x00017000) + +#define V2M_CF (V2M_PA_CS7 + 0x0001a000) +#define V2M_CLCD (V2M_PA_CS7 + 0x0001f000) + +#define V2M_SYS_ID (V2M_SYSREGS + 0x000) +#define V2M_SYS_SW (V2M_SYSREGS + 0x004) +#define V2M_SYS_LED (V2M_SYSREGS + 0x008) +#define V2M_SYS_100HZ (V2M_SYSREGS + 0x024) +#define V2M_SYS_FLAGS (V2M_SYSREGS + 0x030) +#define V2M_SYS_FLAGSSET (V2M_SYSREGS + 0x030) +#define V2M_SYS_FLAGSCLR (V2M_SYSREGS + 0x034) +#define V2M_SYS_NVFLAGS (V2M_SYSREGS + 0x038) +#define V2M_SYS_NVFLAGSSET (V2M_SYSREGS + 0x038) +#define V2M_SYS_NVFLAGSCLR (V2M_SYSREGS + 0x03c) +#define V2M_SYS_MCI (V2M_SYSREGS + 0x048) +#define V2M_SYS_FLASH (V2M_SYSREGS + 0x03c) +#define V2M_SYS_CFGSW (V2M_SYSREGS + 0x058) +#define V2M_SYS_24MHZ (V2M_SYSREGS + 0x05c) +#define V2M_SYS_MISC (V2M_SYSREGS + 0x060) +#define V2M_SYS_DMA (V2M_SYSREGS + 0x064) +#define V2M_SYS_PROCID0 (V2M_SYSREGS + 0x084) +#define V2M_SYS_PROCID1 (V2M_SYSREGS + 0x088) +#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) +#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) +#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) + +#define V2M_TIMER0 (V2M_TIMER01 + 0x000) +#define V2M_TIMER1 (V2M_TIMER01 + 0x020) + +#define V2M_TIMER2 (V2M_TIMER23 + 0x000) +#define V2M_TIMER3 (V2M_TIMER23 + 0x020) + + +/* + * Interrupts. Those in {} are for AMBA devices + */ +#define IRQ_V2M_WDT { (32 + 0) } +#define IRQ_V2M_TIMER0 (32 + 2) +#define IRQ_V2M_TIMER1 (32 + 2) +#define IRQ_V2M_TIMER2 (32 + 3) +#define IRQ_V2M_TIMER3 (32 + 3) +#define IRQ_V2M_RTC { (32 + 4) } +#define IRQ_V2M_UART0 { (32 + 5) } +#define IRQ_V2M_UART1 { (32 + 6) } +#define IRQ_V2M_UART2 { (32 + 7) } +#define IRQ_V2M_UART3 { (32 + 8) } +#define IRQ_V2M_MMCI { (32 + 9), (32 + 10) } +#define IRQ_V2M_AACI { (32 + 11) } +#define IRQ_V2M_KMI0 { (32 + 12) } +#define IRQ_V2M_KMI1 { (32 + 13) } +#define IRQ_V2M_CLCD { (32 + 14) } +#define IRQ_V2M_LAN9118 (32 + 15) +#define IRQ_V2M_ISP1761 (32 + 16) +#define IRQ_V2M_PCIE (32 + 17) + + +/* + * Configuration + */ +#define SYS_CFG_START (1 << 31) +#define SYS_CFG_WRITE (1 << 30) +#define SYS_CFG_OSC (1 << 20) +#define SYS_CFG_VOLT (2 << 20) +#define SYS_CFG_AMP (3 << 20) +#define SYS_CFG_TEMP (4 << 20) +#define SYS_CFG_RESET (5 << 20) +#define SYS_CFG_SCC (6 << 20) +#define SYS_CFG_MUXFPGA (7 << 20) +#define SYS_CFG_SHUTDOWN (8 << 20) +#define SYS_CFG_REBOOT (9 << 20) +#define SYS_CFG_DVIMODE (11 << 20) +#define SYS_CFG_POWER (12 << 20) +#define SYS_CFG_SITE_MB (0 << 16) +#define SYS_CFG_SITE_DB1 (1 << 16) +#define SYS_CFG_SITE_DB2 (2 << 16) +#define SYS_CFG_STACK(n) ((n) << 12) + +#define SYS_CFG_ERR (1 << 1) +#define SYS_CFG_COMPLETE (1 << 0) + +int v2m_cfg_write(u32 devfn, u32 data); +int v2m_cfg_read(u32 devfn, u32 *data); + +#endif diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h new file mode 100644 index 00000000000..72a9621ed08 --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/smp.h @@ -0,0 +1,21 @@ +#ifndef __MACH_SMP_H +#define __MACH_SMP_H + +#include <asm/hardware/gic.h> + +#define hard_smp_processor_id() \ + ({ \ + unsigned int cpunum; \ + __asm__("mrc p15, 0, %0, c0, c0, 5" \ + : "=r" (cpunum)); \ + cpunum &= 0x0F; \ + }) + +/* + * We use IRQ1 as the IPI + */ +static inline void smp_cross_call(const struct cpumask *mask) +{ + gic_raise_softirq(mask, 1); +} +#endif diff --git a/arch/arm/mach-vexpress/include/mach/system.h b/arch/arm/mach-vexpress/include/mach/system.h new file mode 100644 index 00000000000..899a4e628a4 --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/system.h @@ -0,0 +1,37 @@ +/* + * arch/arm/mach-vexpress/include/mach/system.h + * + * Copyright (C) 2003 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ +} + +#endif diff --git a/arch/arm/mach-vexpress/include/mach/timex.h b/arch/arm/mach-vexpress/include/mach/timex.h new file mode 100644 index 00000000000..00029bacd43 --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/timex.h @@ -0,0 +1,23 @@ +/* + * arch/arm/mach-vexpress/include/mach/timex.h + * + * RealView architecture timex specifications + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h new file mode 100644 index 00000000000..7972c5748d0 --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/uncompress.h @@ -0,0 +1,52 @@ +/* + * arch/arm/mach-vexpress/include/mach/uncompress.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) +#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) +#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) +#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) + +#define get_uart_base() (0x10000000 + 0x00009000) + +/* + * This does not append a newline + */ +static inline void putc(int c) +{ + unsigned long base = get_uart_base(); + + while (AMBA_UART_FR(base) & (1 << 5)) + barrier(); + + AMBA_UART_DR(base) = c; +} + +static inline void flush(void) +{ + unsigned long base = get_uart_base(); + + while (AMBA_UART_FR(base) & (1 << 3)) + barrier(); +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/arch/arm/mach-vexpress/include/mach/vmalloc.h b/arch/arm/mach-vexpress/include/mach/vmalloc.h new file mode 100644 index 00000000000..f43a36ef678 --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/vmalloc.h @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-vexpress/include/mach/vmalloc.h + * + * Copyright (C) 2003 ARM Limited + * Copyright (C) 2000 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define VMALLOC_END 0xf8000000UL diff --git a/arch/arm/mach-vexpress/localtimer.c b/arch/arm/mach-vexpress/localtimer.c new file mode 100644 index 00000000000..c0e3a59a0bf --- /dev/null +++ b/arch/arm/mach-vexpress/localtimer.c @@ -0,0 +1,26 @@ +/* + * linux/arch/arm/mach-vexpress/localtimer.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/smp.h> +#include <linux/clockchips.h> + +#include <asm/smp_twd.h> +#include <asm/localtimer.h> +#include <mach/irqs.h> + +/* + * Setup the local clock events for a CPU. + */ +void __cpuinit local_timer_setup(struct clock_event_device *evt) +{ + evt->irq = IRQ_LOCALTIMER; + twd_timer_setup(evt); +} diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c new file mode 100644 index 00000000000..670970699ba --- /dev/null +++ b/arch/arm/mach-vexpress/platsmp.c @@ -0,0 +1,190 @@ +/* + * linux/arch/arm/mach-vexpress/platsmp.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/jiffies.h> +#include <linux/smp.h> +#include <linux/io.h> + +#include <asm/cacheflush.h> +#include <asm/localtimer.h> +#include <asm/smp_scu.h> +#include <asm/unified.h> + +#include <mach/ct-ca9x4.h> +#include <mach/motherboard.h> +#define V2M_PA_CS7 0x10000000 + +#include "core.h" + +extern void vexpress_secondary_startup(void); + +/* + * control for which core is the next to come out of the secondary + * boot "holding pen" + */ +volatile int __cpuinitdata pen_release = -1; + +static void __iomem *scu_base_addr(void) +{ + return MMIO_P2V(A9_MPCORE_SCU); +} + +static DEFINE_SPINLOCK(boot_lock); + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + trace_hardirqs_off(); + + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_cpu_init(0, gic_cpu_base_addr); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + pen_release = -1; + smp_wmb(); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + + /* + * Set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * This is really belt and braces; we hold unintended secondary + * CPUs in the holding pen until we're ready for them. However, + * since we haven't sent them a soft interrupt, they shouldn't + * be there. + */ + pen_release = cpu; + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + + /* + * Send the secondary CPU a soft interrupt, thereby causing + * the boot monitor to read the system wide flags register, + * and branch to the address found there. + */ + smp_cross_call(cpumask_of(cpu)); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +void __init smp_init_cpus(void) +{ + void __iomem *scu_base = scu_base_addr(); + unsigned int i, ncores; + + ncores = scu_base ? scu_get_core_count(scu_base) : 1; + + /* sanity check */ + if (ncores == 0) { + printk(KERN_ERR + "vexpress: strange CM count of 0? Default to 1\n"); + + ncores = 1; + } + + if (ncores > NR_CPUS) { + printk(KERN_WARNING + "vexpress: no. of cores (%d) greater than configured " + "maximum of %d - clipping\n", + ncores, NR_CPUS); + ncores = NR_CPUS; + } + + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); +} + +void __init smp_prepare_cpus(unsigned int max_cpus) +{ + unsigned int ncores = num_possible_cpus(); + unsigned int cpu = smp_processor_id(); + int i; + + smp_store_cpu_info(cpu); + + /* + * are we trying to boot more cores than exist? + */ + if (max_cpus > ncores) + max_cpus = ncores; + + /* + * Initialise the present map, which describes the set of CPUs + * actually populated at the present time. + */ + for (i = 0; i < max_cpus; i++) + set_cpu_present(i, true); + + /* + * Initialise the SCU if there are more than one CPU and let + * them know where to start. + */ + if (max_cpus > 1) { + /* + * Enable the local timer or broadcast device for the + * boot CPU, but only if we have more than one CPU. + */ + percpu_timer_setup(); + + scu_enable(scu_base_addr()); + + /* + * Write the address of secondary startup into the + * system-wide flags register. The boot monitor waits + * until it receives a soft interrupt, and then the + * secondary CPU branches to this address. + */ + writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR)); + writel(BSYM(virt_to_phys(vexpress_secondary_startup)), + MMIO_P2V(V2M_SYS_FLAGSSET)); + } +} diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c new file mode 100644 index 00000000000..d250711b8c7 --- /dev/null +++ b/arch/arm/mach-vexpress/v2m.c @@ -0,0 +1,361 @@ +/* + * Versatile Express V2M Motherboard Support + */ +#include <linux/device.h> +#include <linux/amba/bus.h> +#include <linux/amba/mmci.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/smsc911x.h> +#include <linux/spinlock.h> +#include <linux/sysdev.h> +#include <linux/usb/isp1760.h> + +#include <asm/clkdev.h> +#include <asm/sizes.h> +#include <asm/mach/flash.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/hardware/arm_timer.h> + +#include <mach/clkdev.h> +#include <mach/motherboard.h> + +#include <plat/timer-sp.h> + +#include "core.h" + +#define V2M_PA_CS0 0x40000000 +#define V2M_PA_CS1 0x44000000 +#define V2M_PA_CS2 0x48000000 +#define V2M_PA_CS3 0x4c000000 +#define V2M_PA_CS7 0x10000000 + +static struct map_desc v2m_io_desc[] __initdata = { + { + .virtual = __MMIO_P2V(V2M_PA_CS7), + .pfn = __phys_to_pfn(V2M_PA_CS7), + .length = SZ_128K, + .type = MT_DEVICE, + }, +}; + +void __init v2m_map_io(struct map_desc *tile, size_t num) +{ + iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc)); + iotable_init(tile, num); +} + + +static void v2m_timer_init(void) +{ + writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL); + writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL); + + sp804_clocksource_init(MMIO_P2V(V2M_TIMER1)); + sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0); +} + +struct sys_timer v2m_timer = { + .init = v2m_timer_init, +}; + + +static DEFINE_SPINLOCK(v2m_cfg_lock); + +int v2m_cfg_write(u32 devfn, u32 data) +{ + /* Configuration interface broken? */ + u32 val; + + printk("%s: writing %08x to %08x\n", __func__, data, devfn); + + devfn |= SYS_CFG_START | SYS_CFG_WRITE; + + spin_lock(&v2m_cfg_lock); + val = readl(MMIO_P2V(V2M_SYS_CFGSTAT)); + writel(val & ~SYS_CFG_COMPLETE, MMIO_P2V(V2M_SYS_CFGSTAT)); + + writel(data, MMIO_P2V(V2M_SYS_CFGDATA)); + writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL)); + + do { + val = readl(MMIO_P2V(V2M_SYS_CFGSTAT)); + } while (val == 0); + spin_unlock(&v2m_cfg_lock); + + return !!(val & SYS_CFG_ERR); +} + +int v2m_cfg_read(u32 devfn, u32 *data) +{ + u32 val; + + devfn |= SYS_CFG_START; + + spin_lock(&v2m_cfg_lock); + writel(0, MMIO_P2V(V2M_SYS_CFGSTAT)); + writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL)); + + mb(); + + do { + cpu_relax(); + val = readl(MMIO_P2V(V2M_SYS_CFGSTAT)); + } while (val == 0); + + *data = readl(MMIO_P2V(V2M_SYS_CFGDATA)); + spin_unlock(&v2m_cfg_lock); + + return !!(val & SYS_CFG_ERR); +} + + +static struct resource v2m_pcie_i2c_resource = { + .start = V2M_SERIAL_BUS_PCI, + .end = V2M_SERIAL_BUS_PCI + SZ_4K - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device v2m_pcie_i2c_device = { + .name = "versatile-i2c", + .id = 0, + .num_resources = 1, + .resource = &v2m_pcie_i2c_resource, +}; + +static struct resource v2m_ddc_i2c_resource = { + .start = V2M_SERIAL_BUS_DVI, + .end = V2M_SERIAL_BUS_DVI + SZ_4K - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device v2m_ddc_i2c_device = { + .name = "versatile-i2c", + .id = 1, + .num_resources = 1, + .resource = &v2m_ddc_i2c_resource, +}; + +static struct resource v2m_eth_resources[] = { + { + .start = V2M_LAN9118, + .end = V2M_LAN9118 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_V2M_LAN9118, + .end = IRQ_V2M_LAN9118, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config v2m_eth_config = { + .flags = SMSC911X_USE_32BIT, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device v2m_eth_device = { + .name = "smsc911x", + .id = -1, + .resource = v2m_eth_resources, + .num_resources = ARRAY_SIZE(v2m_eth_resources), + .dev.platform_data = &v2m_eth_config, +}; + +static struct resource v2m_usb_resources[] = { + { + .start = V2M_ISP1761, + .end = V2M_ISP1761 + SZ_128K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_V2M_ISP1761, + .end = IRQ_V2M_ISP1761, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct isp1760_platform_data v2m_usb_config = { + .is_isp1761 = true, + .bus_width_16 = false, + .port1_otg = true, + .analog_oc = false, + .dack_polarity_high = false, + .dreq_polarity_high = false, +}; + +static struct platform_device v2m_usb_device = { + .name = "isp1760", + .id = -1, + .resource = v2m_usb_resources, + .num_resources = ARRAY_SIZE(v2m_usb_resources), + .dev.platform_data = &v2m_usb_config, +}; + +static int v2m_flash_init(void) +{ + writel(0, MMIO_P2V(V2M_SYS_FLASH)); + return 0; +} + +static void v2m_flash_exit(void) +{ + writel(0, MMIO_P2V(V2M_SYS_FLASH)); +} + +static void v2m_flash_set_vpp(int on) +{ + writel(on != 0, MMIO_P2V(V2M_SYS_FLASH)); +} + +static struct flash_platform_data v2m_flash_data = { + .map_name = "cfi_probe", + .width = 4, + .init = v2m_flash_init, + .exit = v2m_flash_exit, + .set_vpp = v2m_flash_set_vpp, +}; + +static struct resource v2m_flash_resources[] = { + { + .start = V2M_NOR0, + .end = V2M_NOR0 + SZ_64M - 1, + .flags = IORESOURCE_MEM, + }, { + .start = V2M_NOR1, + .end = V2M_NOR1 + SZ_64M - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device v2m_flash_device = { + .name = "armflash", + .id = -1, + .resource = v2m_flash_resources, + .num_resources = ARRAY_SIZE(v2m_flash_resources), + .dev.platform_data = &v2m_flash_data, +}; + + +static unsigned int v2m_mmci_status(struct device *dev) +{ + return !(readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0)); +} + +static struct mmci_platform_data v2m_mmci_data = { + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .status = v2m_mmci_status, +}; + +static AMBA_DEVICE(aaci, "mb:aaci", V2M_AACI, NULL); +static AMBA_DEVICE(mmci, "mb:mmci", V2M_MMCI, &v2m_mmci_data); +static AMBA_DEVICE(kmi0, "mb:kmi0", V2M_KMI0, NULL); +static AMBA_DEVICE(kmi1, "mb:kmi1", V2M_KMI1, NULL); +static AMBA_DEVICE(uart0, "mb:uart0", V2M_UART0, NULL); +static AMBA_DEVICE(uart1, "mb:uart1", V2M_UART1, NULL); +static AMBA_DEVICE(uart2, "mb:uart2", V2M_UART2, NULL); +static AMBA_DEVICE(uart3, "mb:uart3", V2M_UART3, NULL); +static AMBA_DEVICE(wdt, "mb:wdt", V2M_WDT, NULL); +static AMBA_DEVICE(rtc, "mb:rtc", V2M_RTC, NULL); + +static struct amba_device *v2m_amba_devs[] __initdata = { + &aaci_device, + &mmci_device, + &kmi0_device, + &kmi1_device, + &uart0_device, + &uart1_device, + &uart2_device, + &uart3_device, + &wdt_device, + &rtc_device, +}; + + +static long v2m_osc_round(struct clk *clk, unsigned long rate) +{ + return rate; +} + +static int v2m_osc1_set(struct clk *clk, unsigned long rate) +{ + return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate); +} + +static const struct clk_ops osc1_clk_ops = { + .round = v2m_osc_round, + .set = v2m_osc1_set, +}; + +static struct clk osc1_clk = { + .ops = &osc1_clk_ops, + .rate = 24000000, +}; + +static struct clk osc2_clk = { + .rate = 24000000, +}; + +static struct clk_lookup v2m_lookups[] = { + { /* UART0 */ + .dev_id = "mb:uart0", + .clk = &osc2_clk, + }, { /* UART1 */ + .dev_id = "mb:uart1", + .clk = &osc2_clk, + }, { /* UART2 */ + .dev_id = "mb:uart2", + .clk = &osc2_clk, + }, { /* UART3 */ + .dev_id = "mb:uart3", + .clk = &osc2_clk, + }, { /* KMI0 */ + .dev_id = "mb:kmi0", + .clk = &osc2_clk, + }, { /* KMI1 */ + .dev_id = "mb:kmi1", + .clk = &osc2_clk, + }, { /* MMC0 */ + .dev_id = "mb:mmci", + .clk = &osc2_clk, + }, { /* CLCD */ + .dev_id = "mb:clcd", + .clk = &osc1_clk, + }, +}; + +static void v2m_power_off(void) +{ + if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0)) + printk(KERN_EMERG "Unable to shutdown\n"); +} + +static void v2m_restart(char str, const char *cmd) +{ + if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) + printk(KERN_EMERG "Unable to reboot\n"); +} + +static int __init v2m_init(void) +{ + int i; + + clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups)); + + platform_device_register(&v2m_pcie_i2c_device); + platform_device_register(&v2m_ddc_i2c_device); + platform_device_register(&v2m_flash_device); + platform_device_register(&v2m_eth_device); + platform_device_register(&v2m_usb_device); + + for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++) + amba_device_register(v2m_amba_devs[i], &iomem_resource); + + pm_power_off = v2m_power_off; + arm_pm_restart = v2m_restart; + + return 0; +} +arch_initcall(v2m_init); diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 5bd7c89a604..346ae14824a 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -572,6 +572,8 @@ config CPU_TLB_V6 config CPU_TLB_V7 bool +config VERIFY_PERMISSION_FAULT + bool endif config CPU_HAS_ASID @@ -760,7 +762,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH config CACHE_L2X0 bool "Enable the L2x0 outer cache controller" depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ - REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4 + REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ + ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 default y select OUTER_CACHE select OUTER_CACHE_SYNC @@ -769,7 +772,7 @@ config CACHE_L2X0 config CACHE_TAUROS2 bool "Enable the Tauros2 L2 cache controller" - depends on ARCH_DOVE + depends on (ARCH_DOVE || ARCH_MMP) default y select OUTER_CACHE help @@ -789,6 +792,25 @@ config ARM_L1_CACHE_SHIFT default 6 if ARM_L1_CACHE_SHIFT_6 default 5 +config ARM_DMA_MEM_BUFFERABLE + bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7 + default y if CPU_V6 || CPU_V7 + help + Historically, the kernel has used strongly ordered mappings to + provide DMA coherent memory. With the advent of ARMv7, mapping + memory with differing types results in unpredictable behaviour, + so on these CPUs, this option is forced on. + + Multiple mappings with differing attributes is also unpredictable + on ARMv6 CPUs, but since they do not have aggressive speculative + prefetch, no harm appears to occur. + + However, drivers may be missing the necessary barriers for ARMv6, + and therefore turning this on may result in unpredictable driver + behaviour. Therefore, we offer this as an option. + + You are recommended say 'Y' here and debug any affected drivers. + config ARCH_HAS_BARRIERS bool help diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S index 2e6dc040c65..ec88b157d3b 100644 --- a/arch/arm/mm/abort-ev7.S +++ b/arch/arm/mm/abort-ev7.S @@ -29,5 +29,26 @@ ENTRY(v7_early_abort) * V6 code adjusts the returned DFSR. * New designs should not need to patch up faults. */ + +#if defined(CONFIG_VERIFY_PERMISSION_FAULT) + /* + * Detect erroneous permission failures and fix + */ + ldr r3, =0x40d @ On permission fault + and r3, r1, r3 + cmp r3, #0x0d + movne pc, lr + + mcr p15, 0, r0, c7, c8, 0 @ Retranslate FAR + isb + mrc p15, 0, r2, c7, c4, 0 @ Read the PAR + and r3, r2, #0x7b @ On translation fault + cmp r3, #0x0b + movne pc, lr + bic r1, r1, #0xf @ Fix up FSR FS[5:0] + and r2, r2, #0x7e + orr r1, r1, r2, LSR #1 +#endif + mov pc, lr ENDPROC(v7_early_abort) diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index a2ab51fa73e..6f98c358989 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -17,6 +17,7 @@ #include <linux/errno.h> #include <linux/string.h> #include <linux/proc_fs.h> +#include <linux/seq_file.h> #include <linux/init.h> #include <linux/sched.h> #include <linux/uaccess.h> @@ -94,36 +95,29 @@ static const char *usermode_action[] = { "signal+warn" }; -static int -proc_alignment_read(char *page, char **start, off_t off, int count, int *eof, - void *data) +static int alignment_proc_show(struct seq_file *m, void *v) { - char *p = page; - int len; - - p += sprintf(p, "User:\t\t%lu\n", ai_user); - p += sprintf(p, "System:\t\t%lu\n", ai_sys); - p += sprintf(p, "Skipped:\t%lu\n", ai_skipped); - p += sprintf(p, "Half:\t\t%lu\n", ai_half); - p += sprintf(p, "Word:\t\t%lu\n", ai_word); + seq_printf(m, "User:\t\t%lu\n", ai_user); + seq_printf(m, "System:\t\t%lu\n", ai_sys); + seq_printf(m, "Skipped:\t%lu\n", ai_skipped); + seq_printf(m, "Half:\t\t%lu\n", ai_half); + seq_printf(m, "Word:\t\t%lu\n", ai_word); if (cpu_architecture() >= CPU_ARCH_ARMv5TE) - p += sprintf(p, "DWord:\t\t%lu\n", ai_dword); - p += sprintf(p, "Multi:\t\t%lu\n", ai_multi); - p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode, + seq_printf(m, "DWord:\t\t%lu\n", ai_dword); + seq_printf(m, "Multi:\t\t%lu\n", ai_multi); + seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode, usermode_action[ai_usermode]); - len = (p - page) - off; - if (len < 0) - len = 0; - - *eof = (len <= count) ? 1 : 0; - *start = page + off; + return 0; +} - return len; +static int alignment_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, alignment_proc_show, NULL); } -static int proc_alignment_write(struct file *file, const char __user *buffer, - unsigned long count, void *data) +static ssize_t alignment_proc_write(struct file *file, const char __user *buffer, + size_t count, loff_t *pos) { char mode; @@ -136,6 +130,13 @@ static int proc_alignment_write(struct file *file, const char __user *buffer, return count; } +static const struct file_operations alignment_proc_fops = { + .open = alignment_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = alignment_proc_write, +}; #endif /* CONFIG_PROC_FS */ union offset_union { @@ -901,12 +902,10 @@ static int __init alignment_init(void) #ifdef CONFIG_PROC_FS struct proc_dir_entry *res; - res = create_proc_entry("cpu/alignment", S_IWUSR | S_IRUGO, NULL); + res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL, + &alignment_proc_fops); if (!res) return -ENOMEM; - - res->read_proc = proc_alignment_read; - res->write_proc = proc_alignment_write; #endif /* diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 21ad68ba22b..9819869d2bc 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -27,6 +27,7 @@ static void __iomem *l2x0_base; static DEFINE_SPINLOCK(l2x0_lock); +static uint32_t l2x0_way_mask; /* Bitmask of active ways */ static inline void cache_wait(void __iomem *reg, unsigned long mask) { @@ -108,8 +109,8 @@ static inline void l2x0_inv_all(void) /* invalidate all ways */ spin_lock_irqsave(&l2x0_lock, flags); - writel(0xff, l2x0_base + L2X0_INV_WAY); - cache_wait(l2x0_base + L2X0_INV_WAY, 0xff); + writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); + cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); cache_sync(); spin_unlock_irqrestore(&l2x0_lock, flags); } @@ -208,9 +209,37 @@ static void l2x0_flush_range(unsigned long start, unsigned long end) void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) { __u32 aux; + __u32 cache_id; + int ways; + const char *type; l2x0_base = base; + cache_id = readl(l2x0_base + L2X0_CACHE_ID); + aux = readl(l2x0_base + L2X0_AUX_CTRL); + + /* Determine the number of ways */ + switch (cache_id & L2X0_CACHE_ID_PART_MASK) { + case L2X0_CACHE_ID_PART_L310: + if (aux & (1 << 16)) + ways = 16; + else + ways = 8; + type = "L310"; + break; + case L2X0_CACHE_ID_PART_L210: + ways = (aux >> 13) & 0xf; + type = "L210"; + break; + default: + /* Assume unknown chips have 8 ways */ + ways = 8; + type = "L2x0 series"; + break; + } + + l2x0_way_mask = (1 << ways) - 1; + /* * Check if l2x0 controller is already enabled. * If you are booting from non-secure mode @@ -219,8 +248,6 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) if (!(readl(l2x0_base + L2X0_CTRL) & 1)) { /* l2x0 controller is disabled */ - - aux = readl(l2x0_base + L2X0_AUX_CTRL); aux &= aux_mask; aux |= aux_val; writel(aux, l2x0_base + L2X0_AUX_CTRL); @@ -236,5 +263,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) outer_cache.flush_range = l2x0_flush_range; outer_cache.sync = l2x0_cache_sync; - printk(KERN_INFO "L2X0 cache controller enabled\n"); + printk(KERN_INFO "%s cache controller enabled\n", type); + printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", + ways, cache_id, aux); } diff --git a/arch/arm/mm/copypage-fa.c b/arch/arm/mm/copypage-fa.c index b2a6008b011..d2852e1635b 100644 --- a/arch/arm/mm/copypage-fa.c +++ b/arch/arm/mm/copypage-fa.c @@ -40,7 +40,7 @@ fa_copy_user_page(void *kto, const void *kfrom) } void fa_copy_user_highpage(struct page *to, struct page *from, - unsigned long vaddr) + unsigned long vaddr, struct vm_area_struct *vma) { void *kto, *kfrom; diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index 0d414c28eb2..9b906dec1ca 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c @@ -134,8 +134,6 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, flush_dcache_mmap_unlock(mapping); if (aliases) do_adjust_pte(vma, addr, pfn, ptep); - else - flush_cache_page(vma, addr, pfn); } /* diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 9d40c341e07..92f5801f99c 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -463,7 +463,12 @@ static struct fsr_info { { do_bad, SIGILL, BUS_ADRALN, "alignment exception" }, { do_bad, SIGKILL, 0, "terminal exception" }, { do_bad, SIGILL, BUS_ADRALN, "alignment exception" }, +/* Do we need runtime check ? */ +#if __LINUX_ARM_ARCH__ < 6 { do_bad, SIGBUS, 0, "external abort on linefetch" }, +#else + { do_translation_fault, SIGSEGV, SEGV_MAPERR, "I-cache maintenance fault" }, +#endif { do_translation_fault, SIGSEGV, SEGV_MAPERR, "section translation fault" }, { do_bad, SIGBUS, 0, "external abort on linefetch" }, { do_page_fault, SIGSEGV, SEGV_MAPERR, "page translation fault" }, diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 0ed29bfeba1..1ba6cf5a2c0 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -15,7 +15,6 @@ #include <linux/mman.h> #include <linux/nodemask.h> #include <linux/initrd.h> -#include <linux/sort.h> #include <linux/highmem.h> #include <linux/gfp.h> @@ -224,20 +223,6 @@ static int __init check_initrd(struct meminfo *mi) return initrd_node; } -static inline void map_memory_bank(struct membank *bank) -{ -#ifdef CONFIG_MMU - struct map_desc map; - - map.pfn = bank_pfn_start(bank); - map.virtual = __phys_to_virt(bank_phys_start(bank)); - map.length = bank_phys_size(bank); - map.type = MT_MEMORY; - - create_mapping(&map); -#endif -} - static void __init bootmem_init_node(int node, struct meminfo *mi, unsigned long start_pfn, unsigned long end_pfn) { @@ -247,16 +232,6 @@ static void __init bootmem_init_node(int node, struct meminfo *mi, int i; /* - * Map the memory banks for this node. - */ - for_each_nodebank(i, mi, node) { - struct membank *bank = &mi->bank[i]; - - if (!bank->highmem) - map_memory_bank(bank); - } - - /* * Allocate the bootmem bitmap page. */ boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn); @@ -385,21 +360,12 @@ static void arm_memory_present(struct meminfo *mi, int node) } #endif -static int __init meminfo_cmp(const void *_a, const void *_b) -{ - const struct membank *a = _a, *b = _b; - long cmp = bank_pfn_start(a) - bank_pfn_start(b); - return cmp < 0 ? -1 : cmp > 0 ? 1 : 0; -} - void __init bootmem_init(void) { struct meminfo *mi = &meminfo; unsigned long min, max_low, max_high; int node, initrd_node; - sort(&mi->bank, mi->nr_banks, sizeof(mi->bank[0]), meminfo_cmp, NULL); - /* * Locate which node contains the ramdisk image, if any. */ diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index a888363398f..815d08eecbb 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -28,10 +28,7 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page #endif -struct map_desc; -struct meminfo; struct pglist_data; -void __init create_mapping(struct map_desc *md); void __init bootmem_init(void); void reserve_node_zero(struct pglist_data *pgdat); diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 241c24a1c18..28589417118 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -14,6 +14,7 @@ #include <linux/bootmem.h> #include <linux/mman.h> #include <linux/nodemask.h> +#include <linux/sort.h> #include <asm/cputype.h> #include <asm/mach-types.h> @@ -603,7 +604,7 @@ static void __init create_36bit_mapping(struct map_desc *md, * offsets, and we take full advantage of sections and * supersections. */ -void __init create_mapping(struct map_desc *md) +static void __init create_mapping(struct map_desc *md) { unsigned long phys, addr, length, end; const struct mem_type *type; @@ -869,9 +870,10 @@ void __init reserve_node_zero(pg_data_t *pgdat) if (machine_is_p720t()) res_size = 0x00014000; - /* H1940 and RX3715 need to reserve this for suspend */ + /* H1940, RX3715 and RX1950 need to reserve this for suspend */ - if (machine_is_h1940() || machine_is_rx3715()) { + if (machine_is_h1940() || machine_is_rx3715() + || machine_is_rx1950()) { reserve_bootmem_node(pgdat, 0x30003000, 0x1000, BOOTMEM_DEFAULT); reserve_bootmem_node(pgdat, 0x30081000, 0x1000, @@ -1017,6 +1019,39 @@ static void __init kmap_init(void) #endif } +static inline void map_memory_bank(struct membank *bank) +{ + struct map_desc map; + + map.pfn = bank_pfn_start(bank); + map.virtual = __phys_to_virt(bank_phys_start(bank)); + map.length = bank_phys_size(bank); + map.type = MT_MEMORY; + + create_mapping(&map); +} + +static void __init map_lowmem(void) +{ + struct meminfo *mi = &meminfo; + int i; + + /* Map all the lowmem memory banks. */ + for (i = 0; i < mi->nr_banks; i++) { + struct membank *bank = &mi->bank[i]; + + if (!bank->highmem) + map_memory_bank(bank); + } +} + +static int __init meminfo_cmp(const void *_a, const void *_b) +{ + const struct membank *a = _a, *b = _b; + long cmp = bank_pfn_start(a) - bank_pfn_start(b); + return cmp < 0 ? -1 : cmp > 0 ? 1 : 0; +} + /* * paging_init() sets up the page tables, initialises the zone memory * maps, and sets up the zero page, bad page and bad page tables. @@ -1025,9 +1060,12 @@ void __init paging_init(struct machine_desc *mdesc) { void *zero_page; + sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL); + build_mem_type_table(); sanity_check_meminfo(); prepare_page_table(); + map_lowmem(); bootmem_init(); devicemaps_init(mdesc); kmap_init(); diff --git a/arch/arm/nwfpe/fpmodule.c b/arch/arm/nwfpe/fpmodule.c index 4c0ab50f399..cb7658e8acc 100644 --- a/arch/arm/nwfpe/fpmodule.c +++ b/arch/arm/nwfpe/fpmodule.c @@ -24,6 +24,7 @@ #include "fpa11.h" #include <linux/module.h> +#include <linux/moduleparam.h> /* XXX */ #include <linux/errno.h> @@ -134,13 +135,17 @@ a SIGFPE exception if necessary. If not the relevant bits in the cumulative exceptions flag byte are set and we return. */ +#ifdef CONFIG_DEBUG_USER +/* By default, ignore inexact errors as there are far too many of them to log */ +static int debug = ~BIT_IXC; +#endif + void float_raise(signed char flags) { register unsigned int fpsr, cumulativeTraps; #ifdef CONFIG_DEBUG_USER - /* Ignore inexact errors as there are far too many of them to log */ - if (flags & ~BIT_IXC) + if (flags & debug) printk(KERN_DEBUG "NWFPE: %s[%d] takes exception %08x at %p from %08lx\n", current->comm, current->pid, flags, @@ -179,3 +184,7 @@ module_exit(fpe_exit); MODULE_AUTHOR("Scott Bambrough <scottb@rebel.com>"); MODULE_DESCRIPTION("NWFPE floating point emulator (" NWFPE_BITS " precision)"); MODULE_LICENSE("GPL"); + +#ifdef CONFIG_DEBUG_USER +module_param(debug, int, 0644); +#endif diff --git a/arch/arm/oprofile/Makefile b/arch/arm/oprofile/Makefile index 88e31f549f5..e666eafed15 100644 --- a/arch/arm/oprofile/Makefile +++ b/arch/arm/oprofile/Makefile @@ -6,9 +6,4 @@ DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \ oprofilefs.o oprofile_stats.o \ timer_int.o ) -oprofile-y := $(DRIVER_OBJS) common.o backtrace.o -oprofile-$(CONFIG_CPU_XSCALE) += op_model_xscale.o -oprofile-$(CONFIG_OPROFILE_ARM11_CORE) += op_model_arm11_core.o -oprofile-$(CONFIG_OPROFILE_ARMV6) += op_model_v6.o -oprofile-$(CONFIG_OPROFILE_MPCORE) += op_model_mpcore.o -oprofile-$(CONFIG_OPROFILE_ARMV7) += op_model_v7.o +oprofile-y := $(DRIVER_OBJS) common.o diff --git a/arch/arm/oprofile/backtrace.c b/arch/arm/oprofile/backtrace.c deleted file mode 100644 index d805a52b503..00000000000 --- a/arch/arm/oprofile/backtrace.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Arm specific backtracing code for oprofile - * - * Copyright 2005 Openedhand Ltd. - * - * Author: Richard Purdie <rpurdie@openedhand.com> - * - * Based on i386 oprofile backtrace code by John Levon, David Smith - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/oprofile.h> -#include <linux/sched.h> -#include <linux/mm.h> -#include <linux/uaccess.h> -#include <asm/ptrace.h> -#include <asm/stacktrace.h> - -static int report_trace(struct stackframe *frame, void *d) -{ - unsigned int *depth = d; - - if (*depth) { - oprofile_add_trace(frame->pc); - (*depth)--; - } - - return *depth == 0; -} - -/* - * The registers we're interested in are at the end of the variable - * length saved register structure. The fp points at the end of this - * structure so the address of this struct is: - * (struct frame_tail *)(xxx->fp)-1 - */ -struct frame_tail { - struct frame_tail *fp; - unsigned long sp; - unsigned long lr; -} __attribute__((packed)); - -static struct frame_tail* user_backtrace(struct frame_tail *tail) -{ - struct frame_tail buftail[2]; - - /* Also check accessibility of one struct frame_tail beyond */ - if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) - return NULL; - if (__copy_from_user_inatomic(buftail, tail, sizeof(buftail))) - return NULL; - - oprofile_add_trace(buftail[0].lr); - - /* frame pointers should strictly progress back up the stack - * (towards higher addresses) */ - if (tail >= buftail[0].fp) - return NULL; - - return buftail[0].fp-1; -} - -void arm_backtrace(struct pt_regs * const regs, unsigned int depth) -{ - struct frame_tail *tail = ((struct frame_tail *) regs->ARM_fp) - 1; - - if (!user_mode(regs)) { - struct stackframe frame; - frame.fp = regs->ARM_fp; - frame.sp = regs->ARM_sp; - frame.lr = regs->ARM_lr; - frame.pc = regs->ARM_pc; - walk_stackframe(&frame, report_trace, &depth); - return; - } - - while (depth-- && tail && !((unsigned long) tail & 3)) - tail = user_backtrace(tail); -} diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c index 3fcd752d614..0691176899f 100644 --- a/arch/arm/oprofile/common.c +++ b/arch/arm/oprofile/common.c @@ -2,32 +2,184 @@ * @file common.c * * @remark Copyright 2004 Oprofile Authors + * @remark Copyright 2010 ARM Ltd. * @remark Read the file COPYING * * @author Zwane Mwaikambo + * @author Will Deacon [move to perf] */ +#include <linux/cpumask.h> +#include <linux/err.h> +#include <linux/errno.h> #include <linux/init.h> +#include <linux/mutex.h> #include <linux/oprofile.h> -#include <linux/errno.h> +#include <linux/perf_event.h> +#include <linux/platform_device.h> #include <linux/slab.h> -#include <linux/sysdev.h> -#include <linux/mutex.h> +#include <asm/stacktrace.h> +#include <linux/uaccess.h> -#include "op_counter.h" -#include "op_arm_model.h" +#include <asm/perf_event.h> +#include <asm/ptrace.h> + +#ifdef CONFIG_HW_PERF_EVENTS +/* + * Per performance monitor configuration as set via oprofilefs. + */ +struct op_counter_config { + unsigned long count; + unsigned long enabled; + unsigned long event; + unsigned long unit_mask; + unsigned long kernel; + unsigned long user; + struct perf_event_attr attr; +}; -static struct op_arm_model_spec *op_arm_model; static int op_arm_enabled; static DEFINE_MUTEX(op_arm_mutex); -struct op_counter_config *counter_config; +static struct op_counter_config *counter_config; +static struct perf_event **perf_events[nr_cpumask_bits]; +static int perf_num_counters; + +/* + * Overflow callback for oprofile. + */ +static void op_overflow_handler(struct perf_event *event, int unused, + struct perf_sample_data *data, struct pt_regs *regs) +{ + int id; + u32 cpu = smp_processor_id(); + + for (id = 0; id < perf_num_counters; ++id) + if (perf_events[cpu][id] == event) + break; + + if (id != perf_num_counters) + oprofile_add_sample(regs, id); + else + pr_warning("oprofile: ignoring spurious overflow " + "on cpu %u\n", cpu); +} + +/* + * Called by op_arm_setup to create perf attributes to mirror the oprofile + * settings in counter_config. Attributes are created as `pinned' events and + * so are permanently scheduled on the PMU. + */ +static void op_perf_setup(void) +{ + int i; + u32 size = sizeof(struct perf_event_attr); + struct perf_event_attr *attr; + + for (i = 0; i < perf_num_counters; ++i) { + attr = &counter_config[i].attr; + memset(attr, 0, size); + attr->type = PERF_TYPE_RAW; + attr->size = size; + attr->config = counter_config[i].event; + attr->sample_period = counter_config[i].count; + attr->pinned = 1; + } +} + +static int op_create_counter(int cpu, int event) +{ + int ret = 0; + struct perf_event *pevent; + + if (!counter_config[event].enabled || (perf_events[cpu][event] != NULL)) + return ret; + + pevent = perf_event_create_kernel_counter(&counter_config[event].attr, + cpu, -1, + op_overflow_handler); + + if (IS_ERR(pevent)) { + ret = PTR_ERR(pevent); + } else if (pevent->state != PERF_EVENT_STATE_ACTIVE) { + pr_warning("oprofile: failed to enable event %d " + "on CPU %d\n", event, cpu); + ret = -EBUSY; + } else { + perf_events[cpu][event] = pevent; + } + + return ret; +} + +static void op_destroy_counter(int cpu, int event) +{ + struct perf_event *pevent = perf_events[cpu][event]; + + if (pevent) { + perf_event_release_kernel(pevent); + perf_events[cpu][event] = NULL; + } +} + +/* + * Called by op_arm_start to create active perf events based on the + * perviously configured attributes. + */ +static int op_perf_start(void) +{ + int cpu, event, ret = 0; + + for_each_online_cpu(cpu) { + for (event = 0; event < perf_num_counters; ++event) { + ret = op_create_counter(cpu, event); + if (ret) + goto out; + } + } + +out: + return ret; +} + +/* + * Called by op_arm_stop at the end of a profiling run. + */ +static void op_perf_stop(void) +{ + int cpu, event; + + for_each_online_cpu(cpu) + for (event = 0; event < perf_num_counters; ++event) + op_destroy_counter(cpu, event); +} + + +static char *op_name_from_perf_id(enum arm_perf_pmu_ids id) +{ + switch (id) { + case ARM_PERF_PMU_ID_XSCALE1: + return "arm/xscale1"; + case ARM_PERF_PMU_ID_XSCALE2: + return "arm/xscale2"; + case ARM_PERF_PMU_ID_V6: + return "arm/armv6"; + case ARM_PERF_PMU_ID_V6MP: + return "arm/mpcore"; + case ARM_PERF_PMU_ID_CA8: + return "arm/armv7"; + case ARM_PERF_PMU_ID_CA9: + return "arm/armv7-ca9"; + default: + return NULL; + } +} static int op_arm_create_files(struct super_block *sb, struct dentry *root) { unsigned int i; - for (i = 0; i < op_arm_model->num_counters; i++) { + for (i = 0; i < perf_num_counters; i++) { struct dentry *dir; char buf[4]; @@ -46,12 +198,10 @@ static int op_arm_create_files(struct super_block *sb, struct dentry *root) static int op_arm_setup(void) { - int ret; - spin_lock(&oprofilefs_lock); - ret = op_arm_model->setup_ctrs(); + op_perf_setup(); spin_unlock(&oprofilefs_lock); - return ret; + return 0; } static int op_arm_start(void) @@ -60,8 +210,9 @@ static int op_arm_start(void) mutex_lock(&op_arm_mutex); if (!op_arm_enabled) { - ret = op_arm_model->start(); - op_arm_enabled = !ret; + ret = 0; + op_perf_start(); + op_arm_enabled = 1; } mutex_unlock(&op_arm_mutex); return ret; @@ -71,113 +222,205 @@ static void op_arm_stop(void) { mutex_lock(&op_arm_mutex); if (op_arm_enabled) - op_arm_model->stop(); + op_perf_stop(); op_arm_enabled = 0; mutex_unlock(&op_arm_mutex); } #ifdef CONFIG_PM -static int op_arm_suspend(struct sys_device *dev, pm_message_t state) +static int op_arm_suspend(struct platform_device *dev, pm_message_t state) { mutex_lock(&op_arm_mutex); if (op_arm_enabled) - op_arm_model->stop(); + op_perf_stop(); mutex_unlock(&op_arm_mutex); return 0; } -static int op_arm_resume(struct sys_device *dev) +static int op_arm_resume(struct platform_device *dev) { mutex_lock(&op_arm_mutex); - if (op_arm_enabled && op_arm_model->start()) + if (op_arm_enabled && op_perf_start()) op_arm_enabled = 0; mutex_unlock(&op_arm_mutex); return 0; } -static struct sysdev_class oprofile_sysclass = { - .name = "oprofile", +static struct platform_driver oprofile_driver = { + .driver = { + .name = "arm-oprofile", + }, .resume = op_arm_resume, .suspend = op_arm_suspend, }; -static struct sys_device device_oprofile = { - .id = 0, - .cls = &oprofile_sysclass, -}; +static struct platform_device *oprofile_pdev; static int __init init_driverfs(void) { int ret; - if (!(ret = sysdev_class_register(&oprofile_sysclass))) - ret = sysdev_register(&device_oprofile); + ret = platform_driver_register(&oprofile_driver); + if (ret) + goto out; + oprofile_pdev = platform_device_register_simple( + oprofile_driver.driver.name, 0, NULL, 0); + if (IS_ERR(oprofile_pdev)) { + ret = PTR_ERR(oprofile_pdev); + platform_driver_unregister(&oprofile_driver); + } + +out: return ret; } static void exit_driverfs(void) { - sysdev_unregister(&device_oprofile); - sysdev_class_unregister(&oprofile_sysclass); + platform_device_unregister(oprofile_pdev); + platform_driver_unregister(&oprofile_driver); } #else -#define init_driverfs() do { } while (0) +static int __init init_driverfs(void) { return 0; } #define exit_driverfs() do { } while (0) #endif /* CONFIG_PM */ -int __init oprofile_arch_init(struct oprofile_operations *ops) +static int report_trace(struct stackframe *frame, void *d) { - struct op_arm_model_spec *spec = NULL; - int ret = -ENODEV; + unsigned int *depth = d; - ops->backtrace = arm_backtrace; + if (*depth) { + oprofile_add_trace(frame->pc); + (*depth)--; + } -#ifdef CONFIG_CPU_XSCALE - spec = &op_xscale_spec; -#endif + return *depth == 0; +} -#ifdef CONFIG_OPROFILE_ARMV6 - spec = &op_armv6_spec; -#endif +/* + * The registers we're interested in are at the end of the variable + * length saved register structure. The fp points at the end of this + * structure so the address of this struct is: + * (struct frame_tail *)(xxx->fp)-1 + */ +struct frame_tail { + struct frame_tail *fp; + unsigned long sp; + unsigned long lr; +} __attribute__((packed)); -#ifdef CONFIG_OPROFILE_MPCORE - spec = &op_mpcore_spec; -#endif +static struct frame_tail* user_backtrace(struct frame_tail *tail) +{ + struct frame_tail buftail[2]; -#ifdef CONFIG_OPROFILE_ARMV7 - spec = &op_armv7_spec; -#endif + /* Also check accessibility of one struct frame_tail beyond */ + if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) + return NULL; + if (__copy_from_user_inatomic(buftail, tail, sizeof(buftail))) + return NULL; - if (spec) { - ret = spec->init(); - if (ret < 0) - return ret; + oprofile_add_trace(buftail[0].lr); - counter_config = kcalloc(spec->num_counters, sizeof(struct op_counter_config), - GFP_KERNEL); - if (!counter_config) - return -ENOMEM; + /* frame pointers should strictly progress back up the stack + * (towards higher addresses) */ + if (tail >= buftail[0].fp) + return NULL; - op_arm_model = spec; - init_driverfs(); - ops->create_files = op_arm_create_files; - ops->setup = op_arm_setup; - ops->shutdown = op_arm_stop; - ops->start = op_arm_start; - ops->stop = op_arm_stop; - ops->cpu_type = op_arm_model->name; - printk(KERN_INFO "oprofile: using %s\n", spec->name); + return buftail[0].fp-1; +} + +static void arm_backtrace(struct pt_regs * const regs, unsigned int depth) +{ + struct frame_tail *tail = ((struct frame_tail *) regs->ARM_fp) - 1; + + if (!user_mode(regs)) { + struct stackframe frame; + frame.fp = regs->ARM_fp; + frame.sp = regs->ARM_sp; + frame.lr = regs->ARM_lr; + frame.pc = regs->ARM_pc; + walk_stackframe(&frame, report_trace, &depth); + return; } + while (depth-- && tail && !((unsigned long) tail & 3)) + tail = user_backtrace(tail); +} + +int __init oprofile_arch_init(struct oprofile_operations *ops) +{ + int cpu, ret = 0; + + perf_num_counters = armpmu_get_max_events(); + + counter_config = kcalloc(perf_num_counters, + sizeof(struct op_counter_config), GFP_KERNEL); + + if (!counter_config) { + pr_info("oprofile: failed to allocate %d " + "counters\n", perf_num_counters); + return -ENOMEM; + } + + ret = init_driverfs(); + if (ret) { + kfree(counter_config); + return ret; + } + + for_each_possible_cpu(cpu) { + perf_events[cpu] = kcalloc(perf_num_counters, + sizeof(struct perf_event *), GFP_KERNEL); + if (!perf_events[cpu]) { + pr_info("oprofile: failed to allocate %d perf events " + "for cpu %d\n", perf_num_counters, cpu); + while (--cpu >= 0) + kfree(perf_events[cpu]); + return -ENOMEM; + } + } + + ops->backtrace = arm_backtrace; + ops->create_files = op_arm_create_files; + ops->setup = op_arm_setup; + ops->start = op_arm_start; + ops->stop = op_arm_stop; + ops->shutdown = op_arm_stop; + ops->cpu_type = op_name_from_perf_id(armpmu_get_pmu_id()); + + if (!ops->cpu_type) + ret = -ENODEV; + else + pr_info("oprofile: using %s\n", ops->cpu_type); + return ret; } void oprofile_arch_exit(void) { - if (op_arm_model) { + int cpu, id; + struct perf_event *event; + + if (*perf_events) { exit_driverfs(); - op_arm_model = NULL; + for_each_possible_cpu(cpu) { + for (id = 0; id < perf_num_counters; ++id) { + event = perf_events[cpu][id]; + if (event != NULL) + perf_event_release_kernel(event); + } + kfree(perf_events[cpu]); + } } - kfree(counter_config); + + if (counter_config) + kfree(counter_config); +} +#else +int __init oprofile_arch_init(struct oprofile_operations *ops) +{ + pr_info("oprofile: hardware counters not available\n"); + return -ENODEV; } +void oprofile_arch_exit(void) {} +#endif /* CONFIG_HW_PERF_EVENTS */ diff --git a/arch/arm/oprofile/op_arm_model.h b/arch/arm/oprofile/op_arm_model.h deleted file mode 100644 index 8c4e4f6a1de..00000000000 --- a/arch/arm/oprofile/op_arm_model.h +++ /dev/null @@ -1,35 +0,0 @@ -/** - * @file op_arm_model.h - * interface to ARM machine specific operations - * - * @remark Copyright 2004 Oprofile Authors - * @remark Read the file COPYING - * - * @author Zwane Mwaikambo - */ - -#ifndef OP_ARM_MODEL_H -#define OP_ARM_MODEL_H - -struct op_arm_model_spec { - int (*init)(void); - unsigned int num_counters; - int (*setup_ctrs)(void); - int (*start)(void); - void (*stop)(void); - char *name; -}; - -#ifdef CONFIG_CPU_XSCALE -extern struct op_arm_model_spec op_xscale_spec; -#endif - -extern struct op_arm_model_spec op_armv6_spec; -extern struct op_arm_model_spec op_mpcore_spec; -extern struct op_arm_model_spec op_armv7_spec; - -extern void arm_backtrace(struct pt_regs * const regs, unsigned int depth); - -extern int __init op_arm_init(struct oprofile_operations *ops, struct op_arm_model_spec *spec); -extern void op_arm_exit(void); -#endif /* OP_ARM_MODEL_H */ diff --git a/arch/arm/oprofile/op_counter.h b/arch/arm/oprofile/op_counter.h deleted file mode 100644 index ca942a63b52..00000000000 --- a/arch/arm/oprofile/op_counter.h +++ /dev/null @@ -1,27 +0,0 @@ -/** - * @file op_counter.h - * - * @remark Copyright 2004 Oprofile Authors - * @remark Read the file COPYING - * - * @author Zwane Mwaikambo - */ - -#ifndef OP_COUNTER_H -#define OP_COUNTER_H - -/* Per performance monitor configuration as set via - * oprofilefs. - */ -struct op_counter_config { - unsigned long count; - unsigned long enabled; - unsigned long event; - unsigned long unit_mask; - unsigned long kernel; - unsigned long user; -}; - -extern struct op_counter_config *counter_config; - -#endif /* OP_COUNTER_H */ diff --git a/arch/arm/oprofile/op_model_arm11_core.c b/arch/arm/oprofile/op_model_arm11_core.c deleted file mode 100644 index ef3e2653b90..00000000000 --- a/arch/arm/oprofile/op_model_arm11_core.c +++ /dev/null @@ -1,162 +0,0 @@ -/** - * @file op_model_arm11_core.c - * ARM11 Event Monitor Driver - * @remark Copyright 2004 ARM SMP Development Team - */ -#include <linux/types.h> -#include <linux/errno.h> -#include <linux/oprofile.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/smp.h> - -#include "op_counter.h" -#include "op_arm_model.h" -#include "op_model_arm11_core.h" - -/* - * ARM11 PMU support - */ -static inline void arm11_write_pmnc(u32 val) -{ - /* upper 4bits and 7, 11 are write-as-0 */ - val &= 0x0ffff77f; - asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r" (val)); -} - -static inline u32 arm11_read_pmnc(void) -{ - u32 val; - asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r" (val)); - return val; -} - -static void arm11_reset_counter(unsigned int cnt) -{ - u32 val = -(u32)counter_config[CPU_COUNTER(smp_processor_id(), cnt)].count; - switch (cnt) { - case CCNT: - asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r" (val)); - break; - - case PMN0: - asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r" (val)); - break; - - case PMN1: - asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r" (val)); - break; - } -} - -int arm11_setup_pmu(void) -{ - unsigned int cnt; - u32 pmnc; - - if (arm11_read_pmnc() & PMCR_E) { - printk(KERN_ERR "oprofile: CPU%u PMU still enabled when setup new event counter.\n", smp_processor_id()); - return -EBUSY; - } - - /* initialize PMNC, reset overflow, D bit, C bit and P bit. */ - arm11_write_pmnc(PMCR_OFL_PMN0 | PMCR_OFL_PMN1 | PMCR_OFL_CCNT | - PMCR_C | PMCR_P); - - for (pmnc = 0, cnt = PMN0; cnt <= CCNT; cnt++) { - unsigned long event; - - if (!counter_config[CPU_COUNTER(smp_processor_id(), cnt)].enabled) - continue; - - event = counter_config[CPU_COUNTER(smp_processor_id(), cnt)].event & 255; - - /* - * Set event (if destined for PMNx counters) - */ - if (cnt == PMN0) { - pmnc |= event << 20; - } else if (cnt == PMN1) { - pmnc |= event << 12; - } - - /* - * We don't need to set the event if it's a cycle count - * Enable interrupt for this counter - */ - pmnc |= PMCR_IEN_PMN0 << cnt; - arm11_reset_counter(cnt); - } - arm11_write_pmnc(pmnc); - - return 0; -} - -int arm11_start_pmu(void) -{ - arm11_write_pmnc(arm11_read_pmnc() | PMCR_E); - return 0; -} - -int arm11_stop_pmu(void) -{ - unsigned int cnt; - - arm11_write_pmnc(arm11_read_pmnc() & ~PMCR_E); - - for (cnt = PMN0; cnt <= CCNT; cnt++) - arm11_reset_counter(cnt); - - return 0; -} - -/* - * CPU counters' IRQ handler (one IRQ per CPU) - */ -static irqreturn_t arm11_pmu_interrupt(int irq, void *arg) -{ - struct pt_regs *regs = get_irq_regs(); - unsigned int cnt; - u32 pmnc; - - pmnc = arm11_read_pmnc(); - - for (cnt = PMN0; cnt <= CCNT; cnt++) { - if ((pmnc & (PMCR_OFL_PMN0 << cnt)) && (pmnc & (PMCR_IEN_PMN0 << cnt))) { - arm11_reset_counter(cnt); - oprofile_add_sample(regs, CPU_COUNTER(smp_processor_id(), cnt)); - } - } - /* Clear counter flag(s) */ - arm11_write_pmnc(pmnc); - return IRQ_HANDLED; -} - -int arm11_request_interrupts(const int *irqs, int nr) -{ - unsigned int i; - int ret = 0; - - for(i = 0; i < nr; i++) { - ret = request_irq(irqs[i], arm11_pmu_interrupt, IRQF_DISABLED, "CP15 PMU", NULL); - if (ret != 0) { - printk(KERN_ERR "oprofile: unable to request IRQ%u for MPCORE-EM\n", - irqs[i]); - break; - } - } - - if (i != nr) - while (i-- != 0) - free_irq(irqs[i], NULL); - - return ret; -} - -void arm11_release_interrupts(const int *irqs, int nr) -{ - unsigned int i; - - for (i = 0; i < nr; i++) - free_irq(irqs[i], NULL); -} diff --git a/arch/arm/oprofile/op_model_arm11_core.h b/arch/arm/oprofile/op_model_arm11_core.h deleted file mode 100644 index 1902b99d9df..00000000000 --- a/arch/arm/oprofile/op_model_arm11_core.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file op_model_arm11_core.h - * ARM11 Event Monitor Driver - * @remark Copyright 2004 ARM SMP Development Team - * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com> - * @remark Copyright 2000-2004 MontaVista Software Inc - * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com> - * @remark Copyright 2004 Intel Corporation - * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk> - * @remark Copyright 2004 Oprofile Authors - * - * @remark Read the file COPYING - * - * @author Zwane Mwaikambo - */ -#ifndef OP_MODEL_ARM11_CORE_H -#define OP_MODEL_ARM11_CORE_H - -/* - * Per-CPU PMCR - */ -#define PMCR_E (1 << 0) /* Enable */ -#define PMCR_P (1 << 1) /* Count reset */ -#define PMCR_C (1 << 2) /* Cycle counter reset */ -#define PMCR_D (1 << 3) /* Cycle counter counts every 64th cpu cycle */ -#define PMCR_IEN_PMN0 (1 << 4) /* Interrupt enable count reg 0 */ -#define PMCR_IEN_PMN1 (1 << 5) /* Interrupt enable count reg 1 */ -#define PMCR_IEN_CCNT (1 << 6) /* Interrupt enable cycle counter */ -#define PMCR_OFL_PMN0 (1 << 8) /* Count reg 0 overflow */ -#define PMCR_OFL_PMN1 (1 << 9) /* Count reg 1 overflow */ -#define PMCR_OFL_CCNT (1 << 10) /* Cycle counter overflow */ - -#define PMN0 0 -#define PMN1 1 -#define CCNT 2 - -#define CPU_COUNTER(cpu, counter) ((cpu) * 3 + (counter)) - -int arm11_setup_pmu(void); -int arm11_start_pmu(void); -int arm11_stop_pmu(void); -int arm11_request_interrupts(const int *, int); -void arm11_release_interrupts(const int *, int); - -#endif diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c deleted file mode 100644 index f73ce875a39..00000000000 --- a/arch/arm/oprofile/op_model_mpcore.c +++ /dev/null @@ -1,306 +0,0 @@ -/** - * @file op_model_mpcore.c - * MPCORE Event Monitor Driver - * @remark Copyright 2004 ARM SMP Development Team - * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com> - * @remark Copyright 2000-2004 MontaVista Software Inc - * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com> - * @remark Copyright 2004 Intel Corporation - * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk> - * @remark Copyright 2004 Oprofile Authors - * - * @remark Read the file COPYING - * - * @author Zwane Mwaikambo - * - * Counters: - * 0: PMN0 on CPU0, per-cpu configurable event counter - * 1: PMN1 on CPU0, per-cpu configurable event counter - * 2: CCNT on CPU0 - * 3: PMN0 on CPU1 - * 4: PMN1 on CPU1 - * 5: CCNT on CPU1 - * 6: PMN0 on CPU1 - * 7: PMN1 on CPU1 - * 8: CCNT on CPU1 - * 9: PMN0 on CPU1 - * 10: PMN1 on CPU1 - * 11: CCNT on CPU1 - * 12-19: configurable SCU event counters - */ - -/* #define DEBUG */ -#include <linux/types.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/sched.h> -#include <linux/oprofile.h> -#include <linux/interrupt.h> -#include <linux/smp.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/board-eb.h> -#include <asm/system.h> -#include <asm/pmu.h> - -#include "op_counter.h" -#include "op_arm_model.h" -#include "op_model_arm11_core.h" -#include "op_model_mpcore.h" - -/* - * MPCore SCU event monitor support - */ -#define SCU_EVENTMONITORS_VA_BASE __io_address(REALVIEW_EB11MP_SCU_BASE + 0x10) - -/* - * Bitmask of used SCU counters - */ -static unsigned int scu_em_used; -static const struct pmu_irqs *pmu_irqs; - -/* - * 2 helper fns take a counter number from 0-7 (not the userspace-visible counter number) - */ -static inline void scu_reset_counter(struct eventmonitor __iomem *emc, unsigned int n) -{ - writel(-(u32)counter_config[SCU_COUNTER(n)].count, &emc->MC[n]); -} - -static inline void scu_set_event(struct eventmonitor __iomem *emc, unsigned int n, u32 event) -{ - event &= 0xff; - writeb(event, &emc->MCEB[n]); -} - -/* - * SCU counters' IRQ handler (one IRQ per counter => 2 IRQs per CPU) - */ -static irqreturn_t scu_em_interrupt(int irq, void *arg) -{ - struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE; - unsigned int cnt; - - cnt = irq - IRQ_EB11MP_PMU_SCU0; - oprofile_add_sample(get_irq_regs(), SCU_COUNTER(cnt)); - scu_reset_counter(emc, cnt); - - /* Clear overflow flag for this counter */ - writel(1 << (cnt + 16), &emc->PMCR); - - return IRQ_HANDLED; -} - -/* Configure just the SCU counters that the user has requested */ -static void scu_setup(void) -{ - struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE; - unsigned int i; - - scu_em_used = 0; - - for (i = 0; i < NUM_SCU_COUNTERS; i++) { - if (counter_config[SCU_COUNTER(i)].enabled && - counter_config[SCU_COUNTER(i)].event) { - scu_set_event(emc, i, 0); /* disable counter for now */ - scu_em_used |= 1 << i; - } - } -} - -static int scu_start(void) -{ - struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE; - unsigned int temp, i; - unsigned long event; - int ret = 0; - - /* - * request the SCU counter interrupts that we need - */ - for (i = 0; i < NUM_SCU_COUNTERS; i++) { - if (scu_em_used & (1 << i)) { - ret = request_irq(IRQ_EB11MP_PMU_SCU0 + i, scu_em_interrupt, IRQF_DISABLED, "SCU PMU", NULL); - if (ret) { - printk(KERN_ERR "oprofile: unable to request IRQ%u for SCU Event Monitor\n", - IRQ_EB11MP_PMU_SCU0 + i); - goto err_free_scu; - } - } - } - - /* - * clear overflow and enable interrupt for all used counters - */ - temp = readl(&emc->PMCR); - for (i = 0; i < NUM_SCU_COUNTERS; i++) { - if (scu_em_used & (1 << i)) { - scu_reset_counter(emc, i); - event = counter_config[SCU_COUNTER(i)].event; - scu_set_event(emc, i, event); - - /* clear overflow/interrupt */ - temp |= 1 << (i + 16); - /* enable interrupt*/ - temp |= 1 << (i + 8); - } - } - - /* Enable all 8 counters */ - temp |= PMCR_E; - writel(temp, &emc->PMCR); - - return 0; - - err_free_scu: - while (i--) - free_irq(IRQ_EB11MP_PMU_SCU0 + i, NULL); - return ret; -} - -static void scu_stop(void) -{ - struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE; - unsigned int temp, i; - - /* Disable counter interrupts */ - /* Don't disable all 8 counters (with the E bit) as they may be in use */ - temp = readl(&emc->PMCR); - for (i = 0; i < NUM_SCU_COUNTERS; i++) { - if (scu_em_used & (1 << i)) - temp &= ~(1 << (i + 8)); - } - writel(temp, &emc->PMCR); - - /* Free counter interrupts and reset counters */ - for (i = 0; i < NUM_SCU_COUNTERS; i++) { - if (scu_em_used & (1 << i)) { - scu_reset_counter(emc, i); - free_irq(IRQ_EB11MP_PMU_SCU0 + i, NULL); - } - } -} - -struct em_function_data { - int (*fn)(void); - int ret; -}; - -static void em_func(void *data) -{ - struct em_function_data *d = data; - int ret = d->fn(); - if (ret) - d->ret = ret; -} - -static int em_call_function(int (*fn)(void)) -{ - struct em_function_data data; - - data.fn = fn; - data.ret = 0; - - preempt_disable(); - smp_call_function(em_func, &data, 1); - em_func(&data); - preempt_enable(); - - return data.ret; -} - -/* - * Glue to stick the individual ARM11 PMUs and the SCU - * into the oprofile framework. - */ -static int em_setup_ctrs(void) -{ - int ret; - - /* Configure CPU counters by cross-calling to the other CPUs */ - ret = em_call_function(arm11_setup_pmu); - if (ret == 0) - scu_setup(); - - return 0; -} - -static int em_start(void) -{ - int ret; - - pmu_irqs = reserve_pmu(); - if (IS_ERR(pmu_irqs)) { - ret = PTR_ERR(pmu_irqs); - goto out; - } - - ret = arm11_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); - if (ret == 0) { - em_call_function(arm11_start_pmu); - - ret = scu_start(); - if (ret) { - arm11_release_interrupts(pmu_irqs->irqs, - pmu_irqs->num_irqs); - } else { - release_pmu(pmu_irqs); - pmu_irqs = NULL; - } - } - -out: - return ret; -} - -static void em_stop(void) -{ - em_call_function(arm11_stop_pmu); - arm11_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); - scu_stop(); - release_pmu(pmu_irqs); -} - -/* - * Why isn't there a function to route an IRQ to a specific CPU in - * genirq? - */ -static void em_route_irq(int irq, unsigned int cpu) -{ - struct irq_desc *desc = irq_desc + irq; - const struct cpumask *mask = cpumask_of(cpu); - - spin_lock_irq(&desc->lock); - cpumask_copy(desc->affinity, mask); - desc->chip->set_affinity(irq, mask); - spin_unlock_irq(&desc->lock); -} - -static int em_setup(void) -{ - /* - * Send SCU PMU interrupts to the "owner" CPU. - */ - em_route_irq(IRQ_EB11MP_PMU_SCU0, 0); - em_route_irq(IRQ_EB11MP_PMU_SCU1, 0); - em_route_irq(IRQ_EB11MP_PMU_SCU2, 1); - em_route_irq(IRQ_EB11MP_PMU_SCU3, 1); - em_route_irq(IRQ_EB11MP_PMU_SCU4, 2); - em_route_irq(IRQ_EB11MP_PMU_SCU5, 2); - em_route_irq(IRQ_EB11MP_PMU_SCU6, 3); - em_route_irq(IRQ_EB11MP_PMU_SCU7, 3); - - return init_pmu(); -} - -struct op_arm_model_spec op_mpcore_spec = { - .init = em_setup, - .num_counters = MPCORE_NUM_COUNTERS, - .setup_ctrs = em_setup_ctrs, - .start = em_start, - .stop = em_stop, - .name = "arm/mpcore", -}; diff --git a/arch/arm/oprofile/op_model_mpcore.h b/arch/arm/oprofile/op_model_mpcore.h deleted file mode 100644 index 73d81102368..00000000000 --- a/arch/arm/oprofile/op_model_mpcore.h +++ /dev/null @@ -1,61 +0,0 @@ -/** - * @file op_model_mpcore.c - * MPCORE Event Monitor Driver - * @remark Copyright 2004 ARM SMP Development Team - * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com> - * @remark Copyright 2000-2004 MontaVista Software Inc - * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com> - * @remark Copyright 2004 Intel Corporation - * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk> - * @remark Copyright 2004 Oprofile Authors - * - * @remark Read the file COPYING - * - * @author Zwane Mwaikambo - */ -#ifndef OP_MODEL_MPCORE_H -#define OP_MODEL_MPCORE_H - -struct eventmonitor { - unsigned long PMCR; - unsigned char MCEB[8]; - unsigned long MC[8]; -}; - -/* - * List of userspace counter numbers: note that the structure is important. - * The code relies on CPUn's counters being CPU0's counters + 3n - * and on CPU0's counters starting at 0 - */ - -#define COUNTER_CPU0_PMN0 0 -#define COUNTER_CPU0_PMN1 1 -#define COUNTER_CPU0_CCNT 2 - -#define COUNTER_CPU1_PMN0 3 -#define COUNTER_CPU1_PMN1 4 -#define COUNTER_CPU1_CCNT 5 - -#define COUNTER_CPU2_PMN0 6 -#define COUNTER_CPU2_PMN1 7 -#define COUNTER_CPU2_CCNT 8 - -#define COUNTER_CPU3_PMN0 9 -#define COUNTER_CPU3_PMN1 10 -#define COUNTER_CPU3_CCNT 11 - -#define COUNTER_SCU_MN0 12 -#define COUNTER_SCU_MN1 13 -#define COUNTER_SCU_MN2 14 -#define COUNTER_SCU_MN3 15 -#define COUNTER_SCU_MN4 16 -#define COUNTER_SCU_MN5 17 -#define COUNTER_SCU_MN6 18 -#define COUNTER_SCU_MN7 19 -#define NUM_SCU_COUNTERS 8 - -#define SCU_COUNTER(number) ((number) + COUNTER_SCU_MN0) - -#define MPCORE_NUM_COUNTERS SCU_COUNTER(NUM_SCU_COUNTERS) - -#endif diff --git a/arch/arm/oprofile/op_model_v6.c b/arch/arm/oprofile/op_model_v6.c deleted file mode 100644 index a22357a2fd0..00000000000 --- a/arch/arm/oprofile/op_model_v6.c +++ /dev/null @@ -1,78 +0,0 @@ -/** - * @file op_model_v6.c - * ARM11 Performance Monitor Driver - * - * Based on op_model_xscale.c - * - * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com> - * @remark Copyright 2000-2004 MontaVista Software Inc - * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com> - * @remark Copyright 2004 Intel Corporation - * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk> - * @remark Copyright 2004 OProfile Authors - * - * @remark Read the file COPYING - * - * @author Tony Lindgren <tony@atomide.com> - */ - -/* #define DEBUG */ -#include <linux/types.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/sched.h> -#include <linux/oprofile.h> -#include <linux/interrupt.h> -#include <asm/irq.h> -#include <asm/system.h> -#include <asm/pmu.h> - -#include "op_counter.h" -#include "op_arm_model.h" -#include "op_model_arm11_core.h" - -static const struct pmu_irqs *pmu_irqs; - -static void armv6_pmu_stop(void) -{ - arm11_stop_pmu(); - arm11_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); - release_pmu(pmu_irqs); - pmu_irqs = NULL; -} - -static int armv6_pmu_start(void) -{ - int ret; - - pmu_irqs = reserve_pmu(); - if (IS_ERR(pmu_irqs)) { - ret = PTR_ERR(pmu_irqs); - goto out; - } - - ret = arm11_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); - if (ret >= 0) { - ret = arm11_start_pmu(); - } else { - release_pmu(pmu_irqs); - pmu_irqs = NULL; - } - -out: - return ret; -} - -static int armv6_detect_pmu(void) -{ - return 0; -} - -struct op_arm_model_spec op_armv6_spec = { - .init = armv6_detect_pmu, - .num_counters = 3, - .setup_ctrs = arm11_setup_pmu, - .start = armv6_pmu_start, - .stop = armv6_pmu_stop, - .name = "arm/armv6", -}; diff --git a/arch/arm/oprofile/op_model_v7.c b/arch/arm/oprofile/op_model_v7.c deleted file mode 100644 index 8642d0891ae..00000000000 --- a/arch/arm/oprofile/op_model_v7.c +++ /dev/null @@ -1,415 +0,0 @@ -/** - * op_model_v7.c - * ARM V7 (Cortex A8) Event Monitor Driver - * - * Copyright 2008 Jean Pihet <jpihet@mvista.com> - * Copyright 2004 ARM SMP Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/types.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/oprofile.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/smp.h> - -#include <asm/pmu.h> - -#include "op_counter.h" -#include "op_arm_model.h" -#include "op_model_v7.h" - -/* #define DEBUG */ - - -/* - * ARM V7 PMNC support - */ - -static u32 cnt_en[CNTMAX]; - -static inline void armv7_pmnc_write(u32 val) -{ - val &= PMNC_MASK; - asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val)); -} - -static inline u32 armv7_pmnc_read(void) -{ - u32 val; - - asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); - return val; -} - -static inline u32 armv7_pmnc_enable_counter(unsigned int cnt) -{ - u32 val; - - if (cnt >= CNTMAX) { - printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter" - " %d\n", smp_processor_id(), cnt); - return -1; - } - - if (cnt == CCNT) - val = CNTENS_C; - else - val = (1 << (cnt - CNT0)); - - val &= CNTENS_MASK; - asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val)); - - return cnt; -} - -static inline u32 armv7_pmnc_disable_counter(unsigned int cnt) -{ - u32 val; - - if (cnt >= CNTMAX) { - printk(KERN_ERR "oprofile: CPU%u disabling wrong PMNC counter" - " %d\n", smp_processor_id(), cnt); - return -1; - } - - if (cnt == CCNT) - val = CNTENC_C; - else - val = (1 << (cnt - CNT0)); - - val &= CNTENC_MASK; - asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val)); - - return cnt; -} - -static inline u32 armv7_pmnc_enable_intens(unsigned int cnt) -{ - u32 val; - - if (cnt >= CNTMAX) { - printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter" - " interrupt enable %d\n", smp_processor_id(), cnt); - return -1; - } - - if (cnt == CCNT) - val = INTENS_C; - else - val = (1 << (cnt - CNT0)); - - val &= INTENS_MASK; - asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val)); - - return cnt; -} - -static inline u32 armv7_pmnc_getreset_flags(void) -{ - u32 val; - - /* Read */ - asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); - - /* Write to clear flags */ - val &= FLAG_MASK; - asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); - - return val; -} - -static inline int armv7_pmnc_select_counter(unsigned int cnt) -{ - u32 val; - - if ((cnt == CCNT) || (cnt >= CNTMAX)) { - printk(KERN_ERR "oprofile: CPU%u selecting wrong PMNC counteri" - " %d\n", smp_processor_id(), cnt); - return -1; - } - - val = (cnt - CNT0) & SELECT_MASK; - asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); - - return cnt; -} - -static inline void armv7_pmnc_write_evtsel(unsigned int cnt, u32 val) -{ - if (armv7_pmnc_select_counter(cnt) == cnt) { - val &= EVTSEL_MASK; - asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); - } -} - -static void armv7_pmnc_reset_counter(unsigned int cnt) -{ - u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); - u32 val = -(u32)counter_config[cpu_cnt].count; - - switch (cnt) { - case CCNT: - armv7_pmnc_disable_counter(cnt); - - asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val)); - - if (cnt_en[cnt] != 0) - armv7_pmnc_enable_counter(cnt); - - break; - - case CNT0: - case CNT1: - case CNT2: - case CNT3: - armv7_pmnc_disable_counter(cnt); - - if (armv7_pmnc_select_counter(cnt) == cnt) - asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val)); - - if (cnt_en[cnt] != 0) - armv7_pmnc_enable_counter(cnt); - - break; - - default: - printk(KERN_ERR "oprofile: CPU%u resetting wrong PMNC counter" - " %d\n", smp_processor_id(), cnt); - break; - } -} - -int armv7_setup_pmnc(void) -{ - unsigned int cnt; - - if (armv7_pmnc_read() & PMNC_E) { - printk(KERN_ERR "oprofile: CPU%u PMNC still enabled when setup" - " new event counter.\n", smp_processor_id()); - return -EBUSY; - } - - /* Initialize & Reset PMNC: C bit and P bit */ - armv7_pmnc_write(PMNC_P | PMNC_C); - - - for (cnt = CCNT; cnt < CNTMAX; cnt++) { - unsigned long event; - u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); - - /* - * Disable counter - */ - armv7_pmnc_disable_counter(cnt); - cnt_en[cnt] = 0; - - if (!counter_config[cpu_cnt].enabled) - continue; - - event = counter_config[cpu_cnt].event & 255; - - /* - * Set event (if destined for PMNx counters) - * We don't need to set the event if it's a cycle count - */ - if (cnt != CCNT) - armv7_pmnc_write_evtsel(cnt, event); - - /* - * Enable interrupt for this counter - */ - armv7_pmnc_enable_intens(cnt); - - /* - * Reset counter - */ - armv7_pmnc_reset_counter(cnt); - - /* - * Enable counter - */ - armv7_pmnc_enable_counter(cnt); - cnt_en[cnt] = 1; - } - - return 0; -} - -static inline void armv7_start_pmnc(void) -{ - armv7_pmnc_write(armv7_pmnc_read() | PMNC_E); -} - -static inline void armv7_stop_pmnc(void) -{ - armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E); -} - -/* - * CPU counters' IRQ handler (one IRQ per CPU) - */ -static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg) -{ - struct pt_regs *regs = get_irq_regs(); - unsigned int cnt; - u32 flags; - - - /* - * Stop IRQ generation - */ - armv7_stop_pmnc(); - - /* - * Get and reset overflow status flags - */ - flags = armv7_pmnc_getreset_flags(); - - /* - * Cycle counter - */ - if (flags & FLAG_C) { - u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), CCNT); - armv7_pmnc_reset_counter(CCNT); - oprofile_add_sample(regs, cpu_cnt); - } - - /* - * PMNC counters 0:3 - */ - for (cnt = CNT0; cnt < CNTMAX; cnt++) { - if (flags & (1 << (cnt - CNT0))) { - u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); - armv7_pmnc_reset_counter(cnt); - oprofile_add_sample(regs, cpu_cnt); - } - } - - /* - * Allow IRQ generation - */ - armv7_start_pmnc(); - - return IRQ_HANDLED; -} - -int armv7_request_interrupts(const int *irqs, int nr) -{ - unsigned int i; - int ret = 0; - - for (i = 0; i < nr; i++) { - ret = request_irq(irqs[i], armv7_pmnc_interrupt, - IRQF_DISABLED, "CP15 PMNC", NULL); - if (ret != 0) { - printk(KERN_ERR "oprofile: unable to request IRQ%u" - " for ARMv7\n", - irqs[i]); - break; - } - } - - if (i != nr) - while (i-- != 0) - free_irq(irqs[i], NULL); - - return ret; -} - -void armv7_release_interrupts(const int *irqs, int nr) -{ - unsigned int i; - - for (i = 0; i < nr; i++) - free_irq(irqs[i], NULL); -} - -#ifdef DEBUG -static void armv7_pmnc_dump_regs(void) -{ - u32 val; - unsigned int cnt; - - printk(KERN_INFO "PMNC registers dump:\n"); - - asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); - printk(KERN_INFO "PMNC =0x%08x\n", val); - - asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); - printk(KERN_INFO "CNTENS=0x%08x\n", val); - - asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); - printk(KERN_INFO "INTENS=0x%08x\n", val); - - asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); - printk(KERN_INFO "FLAGS =0x%08x\n", val); - - asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); - printk(KERN_INFO "SELECT=0x%08x\n", val); - - asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); - printk(KERN_INFO "CCNT =0x%08x\n", val); - - for (cnt = CNT0; cnt < CNTMAX; cnt++) { - armv7_pmnc_select_counter(cnt); - asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); - printk(KERN_INFO "CNT[%d] count =0x%08x\n", cnt-CNT0, val); - asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); - printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", cnt-CNT0, val); - } -} -#endif - -static const struct pmu_irqs *pmu_irqs; - -static void armv7_pmnc_stop(void) -{ -#ifdef DEBUG - armv7_pmnc_dump_regs(); -#endif - armv7_stop_pmnc(); - armv7_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); - release_pmu(pmu_irqs); - pmu_irqs = NULL; -} - -static int armv7_pmnc_start(void) -{ - int ret; - - pmu_irqs = reserve_pmu(); - if (IS_ERR(pmu_irqs)) - return PTR_ERR(pmu_irqs); - -#ifdef DEBUG - armv7_pmnc_dump_regs(); -#endif - ret = armv7_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); - if (ret >= 0) { - armv7_start_pmnc(); - } else { - release_pmu(pmu_irqs); - pmu_irqs = NULL; - } - - return ret; -} - -static int armv7_detect_pmnc(void) -{ - return 0; -} - -struct op_arm_model_spec op_armv7_spec = { - .init = armv7_detect_pmnc, - .num_counters = 5, - .setup_ctrs = armv7_setup_pmnc, - .start = armv7_pmnc_start, - .stop = armv7_pmnc_stop, - .name = "arm/armv7", -}; diff --git a/arch/arm/oprofile/op_model_v7.h b/arch/arm/oprofile/op_model_v7.h deleted file mode 100644 index 9ca334b39c7..00000000000 --- a/arch/arm/oprofile/op_model_v7.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * op_model_v7.h - * ARM v7 (Cortex A8) Event Monitor Driver - * - * Copyright 2008 Jean Pihet <jpihet@mvista.com> - * Copyright 2004 ARM SMP Development Team - * Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com> - * Copyright 2000-2004 MontaVista Software Inc - * Copyright 2004 Dave Jiang <dave.jiang@intel.com> - * Copyright 2004 Intel Corporation - * Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk> - * Copyright 2004 Oprofile Authors - * - * Read the file COPYING - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef OP_MODEL_V7_H -#define OP_MODEL_V7_H - -/* - * Per-CPU PMNC: config reg - */ -#define PMNC_E (1 << 0) /* Enable all counters */ -#define PMNC_P (1 << 1) /* Reset all counters */ -#define PMNC_C (1 << 2) /* Cycle counter reset */ -#define PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ -#define PMNC_X (1 << 4) /* Export to ETM */ -#define PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#define PMNC_MASK 0x3f /* Mask for writable bits */ - -/* - * Available counters - */ -#define CCNT 0 -#define CNT0 1 -#define CNT1 2 -#define CNT2 3 -#define CNT3 4 -#define CNTMAX 5 - -#define CPU_COUNTER(cpu, counter) ((cpu) * CNTMAX + (counter)) - -/* - * CNTENS: counters enable reg - */ -#define CNTENS_P0 (1 << 0) -#define CNTENS_P1 (1 << 1) -#define CNTENS_P2 (1 << 2) -#define CNTENS_P3 (1 << 3) -#define CNTENS_C (1 << 31) -#define CNTENS_MASK 0x8000000f /* Mask for writable bits */ - -/* - * CNTENC: counters disable reg - */ -#define CNTENC_P0 (1 << 0) -#define CNTENC_P1 (1 << 1) -#define CNTENC_P2 (1 << 2) -#define CNTENC_P3 (1 << 3) -#define CNTENC_C (1 << 31) -#define CNTENC_MASK 0x8000000f /* Mask for writable bits */ - -/* - * INTENS: counters overflow interrupt enable reg - */ -#define INTENS_P0 (1 << 0) -#define INTENS_P1 (1 << 1) -#define INTENS_P2 (1 << 2) -#define INTENS_P3 (1 << 3) -#define INTENS_C (1 << 31) -#define INTENS_MASK 0x8000000f /* Mask for writable bits */ - -/* - * EVTSEL: Event selection reg - */ -#define EVTSEL_MASK 0x7f /* Mask for writable bits */ - -/* - * SELECT: Counter selection reg - */ -#define SELECT_MASK 0x1f /* Mask for writable bits */ - -/* - * FLAG: counters overflow flag status reg - */ -#define FLAG_P0 (1 << 0) -#define FLAG_P1 (1 << 1) -#define FLAG_P2 (1 << 2) -#define FLAG_P3 (1 << 3) -#define FLAG_C (1 << 31) -#define FLAG_MASK 0x8000000f /* Mask for writable bits */ - - -int armv7_setup_pmu(void); -int armv7_start_pmu(void); -int armv7_stop_pmu(void); -int armv7_request_interrupts(const int *, int); -void armv7_release_interrupts(const int *, int); - -#endif diff --git a/arch/arm/oprofile/op_model_xscale.c b/arch/arm/oprofile/op_model_xscale.c deleted file mode 100644 index 1d34a02048b..00000000000 --- a/arch/arm/oprofile/op_model_xscale.c +++ /dev/null @@ -1,444 +0,0 @@ -/** - * @file op_model_xscale.c - * XScale Performance Monitor Driver - * - * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com> - * @remark Copyright 2000-2004 MontaVista Software Inc - * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com> - * @remark Copyright 2004 Intel Corporation - * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk> - * @remark Copyright 2004 OProfile Authors - * - * @remark Read the file COPYING - * - * @author Zwane Mwaikambo - */ - -/* #define DEBUG */ -#include <linux/types.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/sched.h> -#include <linux/oprofile.h> -#include <linux/interrupt.h> -#include <linux/irq.h> - -#include <asm/cputype.h> -#include <asm/pmu.h> - -#include "op_counter.h" -#include "op_arm_model.h" - -#define PMU_ENABLE 0x001 /* Enable counters */ -#define PMN_RESET 0x002 /* Reset event counters */ -#define CCNT_RESET 0x004 /* Reset clock counter */ -#define PMU_RESET (CCNT_RESET | PMN_RESET) -#define PMU_CNT64 0x008 /* Make CCNT count every 64th cycle */ - -/* - * Different types of events that can be counted by the XScale PMU - * as used by Oprofile userspace. Here primarily for documentation - * purposes. - */ - -#define EVT_ICACHE_MISS 0x00 -#define EVT_ICACHE_NO_DELIVER 0x01 -#define EVT_DATA_STALL 0x02 -#define EVT_ITLB_MISS 0x03 -#define EVT_DTLB_MISS 0x04 -#define EVT_BRANCH 0x05 -#define EVT_BRANCH_MISS 0x06 -#define EVT_INSTRUCTION 0x07 -#define EVT_DCACHE_FULL_STALL 0x08 -#define EVT_DCACHE_FULL_STALL_CONTIG 0x09 -#define EVT_DCACHE_ACCESS 0x0A -#define EVT_DCACHE_MISS 0x0B -#define EVT_DCACE_WRITE_BACK 0x0C -#define EVT_PC_CHANGED 0x0D -#define EVT_BCU_REQUEST 0x10 -#define EVT_BCU_FULL 0x11 -#define EVT_BCU_DRAIN 0x12 -#define EVT_BCU_ECC_NO_ELOG 0x14 -#define EVT_BCU_1_BIT_ERR 0x15 -#define EVT_RMW 0x16 -/* EVT_CCNT is not hardware defined */ -#define EVT_CCNT 0xFE -#define EVT_UNUSED 0xFF - -struct pmu_counter { - volatile unsigned long ovf; - unsigned long reset_counter; -}; - -enum { CCNT, PMN0, PMN1, PMN2, PMN3, MAX_COUNTERS }; - -static struct pmu_counter results[MAX_COUNTERS]; - -/* - * There are two versions of the PMU in current XScale processors - * with differing register layouts and number of performance counters. - * e.g. IOP32x is xsc1 whilst IOP33x is xsc2. - * We detect which register layout to use in xscale_detect_pmu() - */ -enum { PMU_XSC1, PMU_XSC2 }; - -struct pmu_type { - int id; - char *name; - int num_counters; - unsigned int int_enable; - unsigned int cnt_ovf[MAX_COUNTERS]; - unsigned int int_mask[MAX_COUNTERS]; -}; - -static struct pmu_type pmu_parms[] = { - { - .id = PMU_XSC1, - .name = "arm/xscale1", - .num_counters = 3, - .int_mask = { [PMN0] = 0x10, [PMN1] = 0x20, - [CCNT] = 0x40 }, - .cnt_ovf = { [CCNT] = 0x400, [PMN0] = 0x100, - [PMN1] = 0x200}, - }, - { - .id = PMU_XSC2, - .name = "arm/xscale2", - .num_counters = 5, - .int_mask = { [CCNT] = 0x01, [PMN0] = 0x02, - [PMN1] = 0x04, [PMN2] = 0x08, - [PMN3] = 0x10 }, - .cnt_ovf = { [CCNT] = 0x01, [PMN0] = 0x02, - [PMN1] = 0x04, [PMN2] = 0x08, - [PMN3] = 0x10 }, - }, -}; - -static struct pmu_type *pmu; - -static void write_pmnc(u32 val) -{ - if (pmu->id == PMU_XSC1) { - /* upper 4bits and 7, 11 are write-as-0 */ - val &= 0xffff77f; - __asm__ __volatile__ ("mcr p14, 0, %0, c0, c0, 0" : : "r" (val)); - } else { - /* bits 4-23 are write-as-0, 24-31 are write ignored */ - val &= 0xf; - __asm__ __volatile__ ("mcr p14, 0, %0, c0, c1, 0" : : "r" (val)); - } -} - -static u32 read_pmnc(void) -{ - u32 val; - - if (pmu->id == PMU_XSC1) - __asm__ __volatile__ ("mrc p14, 0, %0, c0, c0, 0" : "=r" (val)); - else { - __asm__ __volatile__ ("mrc p14, 0, %0, c0, c1, 0" : "=r" (val)); - /* bits 1-2 and 4-23 are read-unpredictable */ - val &= 0xff000009; - } - - return val; -} - -static u32 __xsc1_read_counter(int counter) -{ - u32 val = 0; - - switch (counter) { - case CCNT: - __asm__ __volatile__ ("mrc p14, 0, %0, c1, c0, 0" : "=r" (val)); - break; - case PMN0: - __asm__ __volatile__ ("mrc p14, 0, %0, c2, c0, 0" : "=r" (val)); - break; - case PMN1: - __asm__ __volatile__ ("mrc p14, 0, %0, c3, c0, 0" : "=r" (val)); - break; - } - return val; -} - -static u32 __xsc2_read_counter(int counter) -{ - u32 val = 0; - - switch (counter) { - case CCNT: - __asm__ __volatile__ ("mrc p14, 0, %0, c1, c1, 0" : "=r" (val)); - break; - case PMN0: - __asm__ __volatile__ ("mrc p14, 0, %0, c0, c2, 0" : "=r" (val)); - break; - case PMN1: - __asm__ __volatile__ ("mrc p14, 0, %0, c1, c2, 0" : "=r" (val)); - break; - case PMN2: - __asm__ __volatile__ ("mrc p14, 0, %0, c2, c2, 0" : "=r" (val)); - break; - case PMN3: - __asm__ __volatile__ ("mrc p14, 0, %0, c3, c2, 0" : "=r" (val)); - break; - } - return val; -} - -static u32 read_counter(int counter) -{ - u32 val; - - if (pmu->id == PMU_XSC1) - val = __xsc1_read_counter(counter); - else - val = __xsc2_read_counter(counter); - - return val; -} - -static void __xsc1_write_counter(int counter, u32 val) -{ - switch (counter) { - case CCNT: - __asm__ __volatile__ ("mcr p14, 0, %0, c1, c0, 0" : : "r" (val)); - break; - case PMN0: - __asm__ __volatile__ ("mcr p14, 0, %0, c2, c0, 0" : : "r" (val)); - break; - case PMN1: - __asm__ __volatile__ ("mcr p14, 0, %0, c3, c0, 0" : : "r" (val)); - break; - } -} - -static void __xsc2_write_counter(int counter, u32 val) -{ - switch (counter) { - case CCNT: - __asm__ __volatile__ ("mcr p14, 0, %0, c1, c1, 0" : : "r" (val)); - break; - case PMN0: - __asm__ __volatile__ ("mcr p14, 0, %0, c0, c2, 0" : : "r" (val)); - break; - case PMN1: - __asm__ __volatile__ ("mcr p14, 0, %0, c1, c2, 0" : : "r" (val)); - break; - case PMN2: - __asm__ __volatile__ ("mcr p14, 0, %0, c2, c2, 0" : : "r" (val)); - break; - case PMN3: - __asm__ __volatile__ ("mcr p14, 0, %0, c3, c2, 0" : : "r" (val)); - break; - } -} - -static void write_counter(int counter, u32 val) -{ - if (pmu->id == PMU_XSC1) - __xsc1_write_counter(counter, val); - else - __xsc2_write_counter(counter, val); -} - -static int xscale_setup_ctrs(void) -{ - u32 evtsel, pmnc; - int i; - - for (i = CCNT; i < MAX_COUNTERS; i++) { - if (counter_config[i].enabled) - continue; - - counter_config[i].event = EVT_UNUSED; - } - - switch (pmu->id) { - case PMU_XSC1: - pmnc = (counter_config[PMN1].event << 20) | (counter_config[PMN0].event << 12); - pr_debug("xscale_setup_ctrs: pmnc: %#08x\n", pmnc); - write_pmnc(pmnc); - break; - - case PMU_XSC2: - evtsel = counter_config[PMN0].event | (counter_config[PMN1].event << 8) | - (counter_config[PMN2].event << 16) | (counter_config[PMN3].event << 24); - - pr_debug("xscale_setup_ctrs: evtsel %#08x\n", evtsel); - __asm__ __volatile__ ("mcr p14, 0, %0, c8, c1, 0" : : "r" (evtsel)); - break; - } - - for (i = CCNT; i < MAX_COUNTERS; i++) { - if (counter_config[i].event == EVT_UNUSED) { - counter_config[i].event = 0; - pmu->int_enable &= ~pmu->int_mask[i]; - continue; - } - - results[i].reset_counter = counter_config[i].count; - write_counter(i, -(u32)counter_config[i].count); - pmu->int_enable |= pmu->int_mask[i]; - pr_debug("xscale_setup_ctrs: counter%d %#08x from %#08lx\n", i, - read_counter(i), counter_config[i].count); - } - - return 0; -} - -static void inline __xsc1_check_ctrs(void) -{ - int i; - u32 pmnc = read_pmnc(); - - /* NOTE: there's an A stepping errata that states if an overflow */ - /* bit already exists and another occurs, the previous */ - /* Overflow bit gets cleared. There's no workaround. */ - /* Fixed in B stepping or later */ - - /* Write the value back to clear the overflow flags. Overflow */ - /* flags remain in pmnc for use below */ - write_pmnc(pmnc & ~PMU_ENABLE); - - for (i = CCNT; i <= PMN1; i++) { - if (!(pmu->int_mask[i] & pmu->int_enable)) - continue; - - if (pmnc & pmu->cnt_ovf[i]) - results[i].ovf++; - } -} - -static void inline __xsc2_check_ctrs(void) -{ - int i; - u32 flag = 0, pmnc = read_pmnc(); - - pmnc &= ~PMU_ENABLE; - write_pmnc(pmnc); - - /* read overflow flag register */ - __asm__ __volatile__ ("mrc p14, 0, %0, c5, c1, 0" : "=r" (flag)); - - for (i = CCNT; i <= PMN3; i++) { - if (!(pmu->int_mask[i] & pmu->int_enable)) - continue; - - if (flag & pmu->cnt_ovf[i]) - results[i].ovf++; - } - - /* writeback clears overflow bits */ - __asm__ __volatile__ ("mcr p14, 0, %0, c5, c1, 0" : : "r" (flag)); -} - -static irqreturn_t xscale_pmu_interrupt(int irq, void *arg) -{ - int i; - u32 pmnc; - - if (pmu->id == PMU_XSC1) - __xsc1_check_ctrs(); - else - __xsc2_check_ctrs(); - - for (i = CCNT; i < MAX_COUNTERS; i++) { - if (!results[i].ovf) - continue; - - write_counter(i, -(u32)results[i].reset_counter); - oprofile_add_sample(get_irq_regs(), i); - results[i].ovf--; - } - - pmnc = read_pmnc() | PMU_ENABLE; - write_pmnc(pmnc); - - return IRQ_HANDLED; -} - -static const struct pmu_irqs *pmu_irqs; - -static void xscale_pmu_stop(void) -{ - u32 pmnc = read_pmnc(); - - pmnc &= ~PMU_ENABLE; - write_pmnc(pmnc); - - free_irq(pmu_irqs->irqs[0], results); - release_pmu(pmu_irqs); - pmu_irqs = NULL; -} - -static int xscale_pmu_start(void) -{ - int ret; - u32 pmnc; - - pmu_irqs = reserve_pmu(); - if (IS_ERR(pmu_irqs)) - return PTR_ERR(pmu_irqs); - - pmnc = read_pmnc(); - - ret = request_irq(pmu_irqs->irqs[0], xscale_pmu_interrupt, - IRQF_DISABLED, "XScale PMU", (void *)results); - - if (ret < 0) { - printk(KERN_ERR "oprofile: unable to request IRQ%d for XScale PMU\n", - pmu_irqs->irqs[0]); - release_pmu(pmu_irqs); - pmu_irqs = NULL; - return ret; - } - - if (pmu->id == PMU_XSC1) - pmnc |= pmu->int_enable; - else { - __asm__ __volatile__ ("mcr p14, 0, %0, c4, c1, 0" : : "r" (pmu->int_enable)); - pmnc &= ~PMU_CNT64; - } - - pmnc |= PMU_ENABLE; - write_pmnc(pmnc); - pr_debug("xscale_pmu_start: pmnc: %#08x mask: %08x\n", pmnc, pmu->int_enable); - return 0; -} - -static int xscale_detect_pmu(void) -{ - int ret = 0; - u32 id; - - id = (read_cpuid(CPUID_ID) >> 13) & 0x7; - - switch (id) { - case 1: - pmu = &pmu_parms[PMU_XSC1]; - break; - case 2: - pmu = &pmu_parms[PMU_XSC2]; - break; - default: - ret = -ENODEV; - break; - } - - if (!ret) { - op_xscale_spec.name = pmu->name; - op_xscale_spec.num_counters = pmu->num_counters; - pr_debug("xscale_detect_pmu: detected %s PMU\n", pmu->name); - } - - return ret; -} - -struct op_arm_model_spec op_xscale_spec = { - .init = xscale_detect_pmu, - .setup_ctrs = xscale_setup_ctrs, - .start = xscale_pmu_start, - .stop = xscale_pmu_stop, -}; - diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile index 36bff032595..69b09c1cec8 100644 --- a/arch/arm/plat-iop/Makefile +++ b/arch/arm/plat-iop/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_IOP32X) += time.o obj-$(CONFIG_ARCH_IOP32X) += io.o obj-$(CONFIG_ARCH_IOP32X) += cp6.o obj-$(CONFIG_ARCH_IOP32X) += adma.o +obj-$(CONFIG_ARCH_IOP32X) += pmu.o # IOP33X obj-$(CONFIG_ARCH_IOP33X) += gpio.o @@ -23,6 +24,7 @@ obj-$(CONFIG_ARCH_IOP33X) += time.o obj-$(CONFIG_ARCH_IOP33X) += io.o obj-$(CONFIG_ARCH_IOP33X) += cp6.o obj-$(CONFIG_ARCH_IOP33X) += adma.o +obj-$(CONFIG_ARCH_IOP33X) += pmu.o # IOP13XX obj-$(CONFIG_ARCH_IOP13XX) += cp6.o diff --git a/arch/arm/plat-iop/pmu.c b/arch/arm/plat-iop/pmu.c new file mode 100644 index 00000000000..a2024b8685a --- /dev/null +++ b/arch/arm/plat-iop/pmu.c @@ -0,0 +1,40 @@ +/* + * PMU IRQ registration for the iop3xx xscale PMU families. + * Copyright (C) 2010 Will Deacon, ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/platform_device.h> +#include <asm/pmu.h> +#include <mach/irqs.h> + +static struct resource pmu_resource = { +#ifdef CONFIG_ARCH_IOP32X + .start = IRQ_IOP32X_CORE_PMU, + .end = IRQ_IOP32X_CORE_PMU, +#endif +#ifdef CONFIG_ARCH_IOP33X + .start = IRQ_IOP33X_CORE_PMU, + .end = IRQ_IOP33X_CORE_PMU, +#endif + .flags = IORESOURCE_IRQ, +}; + +static struct platform_device pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .resource = &pmu_resource, + .num_resources = 1, +}; + +static int __init iop3xx_pmu_init(void) +{ + platform_device_register(&pmu_device); + return 0; +} + +arch_initcall(iop3xx_pmu_init); diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig index 159daf583f8..5da3f97c537 100644 --- a/arch/arm/plat-nomadik/Kconfig +++ b/arch/arm/plat-nomadik/Kconfig @@ -19,4 +19,9 @@ config HAS_MTU to multiple interrupt generating programmable 32-bit free running decrementing counters. +config NOMADIK_GPIO + bool + help + Support for the Nomadik GPIO controller. + endif diff --git a/arch/arm/plat-nomadik/Makefile b/arch/arm/plat-nomadik/Makefile index 37c7cdd0f8f..c33547361bd 100644 --- a/arch/arm/plat-nomadik/Makefile +++ b/arch/arm/plat-nomadik/Makefile @@ -3,3 +3,4 @@ # Licensed under GPLv2 obj-$(CONFIG_HAS_MTU) += timer.o +obj-$(CONFIG_NOMADIK_GPIO) += gpio.o diff --git a/arch/arm/mach-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 66b1c91ccc7..5a6ef252c38 100644 --- a/arch/arm/mach-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c @@ -13,8 +13,10 @@ #include <linux/module.h> #include <linux/init.h> #include <linux/device.h> -#include <linux/amba/bus.h> +#include <linux/platform_device.h> #include <linux/io.h> +#include <linux/clk.h> +#include <linux/err.h> #include <linux/gpio.h> #include <linux/spinlock.h> #include <linux/interrupt.h> @@ -36,8 +38,9 @@ struct nmk_gpio_chip { struct gpio_chip chip; void __iomem *addr; + struct clk *clk; unsigned int parent_irq; - spinlock_t *lock; + spinlock_t lock; /* Keep track of configured edges */ u32 edge_rising; u32 edge_falling; @@ -108,40 +111,37 @@ static void nmk_gpio_irq_ack(unsigned int irq) writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); } -static void nmk_gpio_irq_mask(unsigned int irq) +static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, + int gpio, bool enable) { - int gpio; - struct nmk_gpio_chip *nmk_chip; - unsigned long flags; - u32 bitmask, reg; - - gpio = NOMADIK_IRQ_TO_GPIO(irq); - nmk_chip = get_irq_chip_data(irq); - bitmask = nmk_gpio_get_bitmask(gpio); - if (!nmk_chip) - return; + u32 bitmask = nmk_gpio_get_bitmask(gpio); + u32 reg; - /* we must individually clear the two edges */ - spin_lock_irqsave(&nmk_chip->lock, flags); + /* we must individually set/clear the two edges */ if (nmk_chip->edge_rising & bitmask) { - reg = readl(nmk_chip->addr + NMK_GPIO_RWIMSC); - reg &= ~bitmask; - writel(reg, nmk_chip->addr + NMK_GPIO_RWIMSC); + reg = readl(nmk_chip->addr + NMK_GPIO_RIMSC); + if (enable) + reg |= bitmask; + else + reg &= ~bitmask; + writel(reg, nmk_chip->addr + NMK_GPIO_RIMSC); } if (nmk_chip->edge_falling & bitmask) { - reg = readl(nmk_chip->addr + NMK_GPIO_FWIMSC); - reg &= ~bitmask; - writel(reg, nmk_chip->addr + NMK_GPIO_FWIMSC); + reg = readl(nmk_chip->addr + NMK_GPIO_FIMSC); + if (enable) + reg |= bitmask; + else + reg &= ~bitmask; + writel(reg, nmk_chip->addr + NMK_GPIO_FIMSC); } - spin_unlock_irqrestore(&nmk_chip->lock, flags); -}; +} -static void nmk_gpio_irq_unmask(unsigned int irq) +static void nmk_gpio_irq_modify(unsigned int irq, bool enable) { int gpio; struct nmk_gpio_chip *nmk_chip; unsigned long flags; - u32 bitmask, reg; + u32 bitmask; gpio = NOMADIK_IRQ_TO_GPIO(irq); nmk_chip = get_irq_chip_data(irq); @@ -149,23 +149,24 @@ static void nmk_gpio_irq_unmask(unsigned int irq) if (!nmk_chip) return; - /* we must individually set the two edges */ spin_lock_irqsave(&nmk_chip->lock, flags); - if (nmk_chip->edge_rising & bitmask) { - reg = readl(nmk_chip->addr + NMK_GPIO_RWIMSC); - reg |= bitmask; - writel(reg, nmk_chip->addr + NMK_GPIO_RWIMSC); - } - if (nmk_chip->edge_falling & bitmask) { - reg = readl(nmk_chip->addr + NMK_GPIO_FWIMSC); - reg |= bitmask; - writel(reg, nmk_chip->addr + NMK_GPIO_FWIMSC); - } + __nmk_gpio_irq_modify(nmk_chip, gpio, enable); spin_unlock_irqrestore(&nmk_chip->lock, flags); } +static void nmk_gpio_irq_mask(unsigned int irq) +{ + nmk_gpio_irq_modify(irq, false); +}; + +static void nmk_gpio_irq_unmask(unsigned int irq) +{ + nmk_gpio_irq_modify(irq, true); +} + static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) { + bool enabled = !(irq_to_desc(irq)->status & IRQ_DISABLED); int gpio; struct nmk_gpio_chip *nmk_chip; unsigned long flags; @@ -184,19 +185,21 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) spin_lock_irqsave(&nmk_chip->lock, flags); + if (enabled) + __nmk_gpio_irq_modify(nmk_chip, gpio, false); + nmk_chip->edge_rising &= ~bitmask; if (type & IRQ_TYPE_EDGE_RISING) nmk_chip->edge_rising |= bitmask; - writel(nmk_chip->edge_rising, nmk_chip->addr + NMK_GPIO_RIMSC); nmk_chip->edge_falling &= ~bitmask; if (type & IRQ_TYPE_EDGE_FALLING) nmk_chip->edge_falling |= bitmask; - writel(nmk_chip->edge_falling, nmk_chip->addr + NMK_GPIO_FIMSC); - spin_unlock_irqrestore(&nmk_chip->lock, flags); + if (enabled) + __nmk_gpio_irq_modify(nmk_chip, gpio, true); - nmk_gpio_irq_unmask(irq); + spin_unlock_irqrestore(&nmk_chip->lock, flags); return 0; } @@ -212,21 +215,27 @@ static struct irq_chip nmk_gpio_irq_chip = { static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { struct nmk_gpio_chip *nmk_chip; - struct irq_chip *host_chip; + struct irq_chip *host_chip = get_irq_chip(irq); unsigned int gpio_irq; u32 pending; unsigned int first_irq; + if (host_chip->mask_ack) + host_chip->mask_ack(irq); + else { + host_chip->mask(irq); + if (host_chip->ack) + host_chip->ack(irq); + } + nmk_chip = get_irq_data(irq); first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); while ( (pending = readl(nmk_chip->addr + NMK_GPIO_IS)) ) { gpio_irq = first_irq + __ffs(pending); generic_handle_irq(gpio_irq); } - if (0) {/* don't ack parent irq, as ack == disable */ - host_chip = get_irq_chip(irq); - host_chip->ack(irq); - } + + host_chip->unmask(irq); } static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) @@ -240,6 +249,7 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) set_irq_handler(i, handle_edge_irq); set_irq_flags(i, IRQF_VALID); set_irq_chip_data(i, nmk_chip); + set_irq_type(i, IRQ_TYPE_EDGE_FALLING); } set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); set_irq_data(nmk_chip->parent_irq, nmk_chip); @@ -298,30 +308,59 @@ static struct gpio_chip nmk_gpio_template = { .can_sleep = 0, }; -static int __init nmk_gpio_probe(struct amba_device *dev, struct amba_id *id) +static int __init nmk_gpio_probe(struct platform_device *dev) { - struct nmk_gpio_platform_data *pdata; + struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; struct nmk_gpio_chip *nmk_chip; struct gpio_chip *chip; + struct resource *res; + struct clk *clk; + int irq; int ret; - pdata = dev->dev.platform_data; - ret = amba_request_regions(dev, pdata->name); - if (ret) - return ret; + if (!pdata) + return -ENODEV; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENOENT; + goto out; + } + + irq = platform_get_irq(dev, 0); + if (irq < 0) { + ret = irq; + goto out; + } + + if (request_mem_region(res->start, resource_size(res), + dev_name(&dev->dev)) == NULL) { + ret = -EBUSY; + goto out; + } + + clk = clk_get(&dev->dev, NULL); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto out_release; + } + + clk_enable(clk); nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); if (!nmk_chip) { ret = -ENOMEM; - goto out_amba; + goto out_clk; } /* * The virt address in nmk_chip->addr is in the nomadik register space, * so we can simply convert the resource address, without remapping */ - nmk_chip->addr = io_p2v(dev->res.start); + nmk_chip->clk = clk; + nmk_chip->addr = io_p2v(res->start); nmk_chip->chip = nmk_gpio_template; - nmk_chip->parent_irq = pdata->parent_irq; + nmk_chip->parent_irq = irq; + spin_lock_init(&nmk_chip->lock); chip = &nmk_chip->chip; chip->base = pdata->first_gpio; @@ -333,7 +372,7 @@ static int __init nmk_gpio_probe(struct amba_device *dev, struct amba_id *id) if (ret) goto out_free; - amba_set_drvdata(dev, nmk_chip); + platform_set_drvdata(dev, nmk_chip); nmk_gpio_init_irq(nmk_chip); @@ -341,51 +380,50 @@ static int __init nmk_gpio_probe(struct amba_device *dev, struct amba_id *id) nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr); return 0; - out_free: +out_free: kfree(nmk_chip); - out_amba: - amba_release_regions(dev); +out_clk: + clk_disable(clk); + clk_put(clk); +out_release: + release_mem_region(res->start, resource_size(res)); +out: dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, pdata->first_gpio, pdata->first_gpio+31); return ret; } -static int nmk_gpio_remove(struct amba_device *dev) +static int __exit nmk_gpio_remove(struct platform_device *dev) { struct nmk_gpio_chip *nmk_chip; + struct resource *res; - nmk_chip = amba_get_drvdata(dev); + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + + nmk_chip = platform_get_drvdata(dev); gpiochip_remove(&nmk_chip->chip); + clk_disable(nmk_chip->clk); + clk_put(nmk_chip->clk); kfree(nmk_chip); - amba_release_regions(dev); + release_mem_region(res->start, resource_size(res)); return 0; } -/* We have 0x1f080060 and 0x1f180060, accept both using the mask */ -static struct amba_id nmk_gpio_ids[] = { - { - .id = 0x1f080060, - .mask = 0xffefffff, - }, - {0, 0}, -}; - -static struct amba_driver nmk_gpio_driver = { - .drv = { +static struct platform_driver nmk_gpio_driver = { + .driver = { .owner = THIS_MODULE, .name = "gpio", }, .probe = nmk_gpio_probe, - .remove = nmk_gpio_remove, + .remove = __exit_p(nmk_gpio_remove), .suspend = NULL, /* to be done */ .resume = NULL, - .id_table = nmk_gpio_ids, }; static int __init nmk_gpio_init(void) { - return amba_driver_register(&nmk_gpio_driver); + return platform_driver_register(&nmk_gpio_driver); } arch_initcall(nmk_gpio_init); diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h new file mode 100644 index 00000000000..4200811249c --- /dev/null +++ b/arch/arm/plat-nomadik/include/plat/gpio.h @@ -0,0 +1,70 @@ +/* + * Structures and registers for GPIO access in the Nomadik SoC + * + * Copyright (C) 2008 STMicroelectronics + * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com> + * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PLAT_GPIO_H +#define __ASM_PLAT_GPIO_H + +#include <asm-generic/gpio.h> + +/* + * These currently cause a function call to happen, they may be optimized + * if needed by adding cpu-specific defines to identify blocks + * (see mach-pxa/include/mach/gpio.h as an example using GPLR etc) + */ +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +/* + * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving + * the "gpio" namespace for generic and cross-machine functions + */ + +/* Register in the logic block */ +#define NMK_GPIO_DAT 0x00 +#define NMK_GPIO_DATS 0x04 +#define NMK_GPIO_DATC 0x08 +#define NMK_GPIO_PDIS 0x0c +#define NMK_GPIO_DIR 0x10 +#define NMK_GPIO_DIRS 0x14 +#define NMK_GPIO_DIRC 0x18 +#define NMK_GPIO_SLPC 0x1c +#define NMK_GPIO_AFSLA 0x20 +#define NMK_GPIO_AFSLB 0x24 + +#define NMK_GPIO_RIMSC 0x40 +#define NMK_GPIO_FIMSC 0x44 +#define NMK_GPIO_IS 0x48 +#define NMK_GPIO_IC 0x4c +#define NMK_GPIO_RWIMSC 0x50 +#define NMK_GPIO_FWIMSC 0x54 +#define NMK_GPIO_WKS 0x58 + +/* Alternate functions: function C is set in hw by setting both A and B */ +#define NMK_GPIO_ALT_GPIO 0 +#define NMK_GPIO_ALT_A 1 +#define NMK_GPIO_ALT_B 2 +#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) + +extern int nmk_gpio_set_mode(int gpio, int gpio_mode); +extern int nmk_gpio_get_mode(int gpio); + +/* + * Platform data to register a block: only the initial gpio/irq number. + */ +struct nmk_gpio_platform_data { + char *name; + int first_gpio; + int first_irq; +}; + +#endif /* __ASM_PLAT_GPIO_H */ diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h new file mode 100644 index 00000000000..4d12ea4ca36 --- /dev/null +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -0,0 +1,239 @@ +/* + * arch/arm/plat-nomadik/include/plat/ste_dma40.h + * + * Copyright (C) ST-Ericsson 2007-2010 + * License terms: GNU General Public License (GPL) version 2 + * Author: Per Friden <per.friden@stericsson.com> + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> + */ + + +#ifndef STE_DMA40_H +#define STE_DMA40_H + +#include <linux/dmaengine.h> +#include <linux/workqueue.h> +#include <linux/interrupt.h> +#include <linux/dmaengine.h> + +/* dev types for memcpy */ +#define STEDMA40_DEV_DST_MEMORY (-1) +#define STEDMA40_DEV_SRC_MEMORY (-1) + +/* + * Description of bitfields of channel_type variable is available in + * the info structure. + */ + +/* Priority */ +#define STEDMA40_INFO_PRIO_TYPE_POS 2 +#define STEDMA40_HIGH_PRIORITY_CHANNEL (0x1 << STEDMA40_INFO_PRIO_TYPE_POS) +#define STEDMA40_LOW_PRIORITY_CHANNEL (0x2 << STEDMA40_INFO_PRIO_TYPE_POS) + +/* Mode */ +#define STEDMA40_INFO_CH_MODE_TYPE_POS 6 +#define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS) +#define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS) +#define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS) + +/* Mode options */ +#define STEDMA40_INFO_CH_MODE_OPT_POS 8 +#define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS) +#define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS) +#define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS) +#define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS) +#define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS) +#define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS) + +/* Interrupt */ +#define STEDMA40_INFO_TIM_POS 10 +#define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS) +#define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS) + +/* End of channel_type configuration */ + +#define STEDMA40_ESIZE_8_BIT 0x0 +#define STEDMA40_ESIZE_16_BIT 0x1 +#define STEDMA40_ESIZE_32_BIT 0x2 +#define STEDMA40_ESIZE_64_BIT 0x3 + +/* The value 4 indicates that PEN-reg shall be set to 0 */ +#define STEDMA40_PSIZE_PHY_1 0x4 +#define STEDMA40_PSIZE_PHY_2 0x0 +#define STEDMA40_PSIZE_PHY_4 0x1 +#define STEDMA40_PSIZE_PHY_8 0x2 +#define STEDMA40_PSIZE_PHY_16 0x3 + +/* + * The number of elements differ in logical and + * physical mode + */ +#define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2 +#define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4 +#define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8 +#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16 + +enum stedma40_flow_ctrl { + STEDMA40_NO_FLOW_CTRL, + STEDMA40_FLOW_CTRL, +}; + +enum stedma40_endianess { + STEDMA40_LITTLE_ENDIAN, + STEDMA40_BIG_ENDIAN +}; + +enum stedma40_periph_data_width { + STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT, + STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT, + STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT, + STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT +}; + +struct stedma40_half_channel_info { + enum stedma40_endianess endianess; + enum stedma40_periph_data_width data_width; + int psize; + enum stedma40_flow_ctrl flow_ctrl; +}; + +enum stedma40_xfer_dir { + STEDMA40_MEM_TO_MEM, + STEDMA40_MEM_TO_PERIPH, + STEDMA40_PERIPH_TO_MEM, + STEDMA40_PERIPH_TO_PERIPH +}; + + +/** + * struct stedma40_chan_cfg - Structure to be filled by client drivers. + * + * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH + * @channel_type: priority, mode, mode options and interrupt configuration. + * @src_dev_type: Src device type + * @dst_dev_type: Dst device type + * @src_info: Parameters for dst half channel + * @dst_info: Parameters for dst half channel + * @pre_transfer_data: Data to be passed on to the pre_transfer() function. + * @pre_transfer: Callback used if needed before preparation of transfer. + * Only called if device is set. size of bytes to transfer + * (in case of multiple element transfer size is size of the first element). + * + * + * This structure has to be filled by the client drivers. + * It is recommended to do all dma configurations for clients in the machine. + * + */ +struct stedma40_chan_cfg { + enum stedma40_xfer_dir dir; + unsigned int channel_type; + int src_dev_type; + int dst_dev_type; + struct stedma40_half_channel_info src_info; + struct stedma40_half_channel_info dst_info; + void *pre_transfer_data; + int (*pre_transfer) (struct dma_chan *chan, + void *data, + int size); +}; + +/** + * struct stedma40_platform_data - Configuration struct for the dma device. + * + * @dev_len: length of dev_tx and dev_rx + * @dev_tx: mapping between destination event line and io address + * @dev_rx: mapping between source event line and io address + * @memcpy: list of memcpy event lines + * @memcpy_len: length of memcpy + * @memcpy_conf_phy: default configuration of physical channel memcpy + * @memcpy_conf_log: default configuration of logical channel memcpy + * @llis_per_log: number of max linked list items per logical channel + * + */ +struct stedma40_platform_data { + u32 dev_len; + const dma_addr_t *dev_tx; + const dma_addr_t *dev_rx; + int *memcpy; + u32 memcpy_len; + struct stedma40_chan_cfg *memcpy_conf_phy; + struct stedma40_chan_cfg *memcpy_conf_log; + unsigned int llis_per_log; +}; + +/** + * setdma40_set_psize() - Used for changing the package size of an + * already configured dma channel. + * + * @chan: dmaengine handle + * @src_psize: new package side for src. (STEDMA40_PSIZE*) + * @src_psize: new package side for dst. (STEDMA40_PSIZE*) + * + * returns 0 on ok, otherwise negative error number. + */ +int stedma40_set_psize(struct dma_chan *chan, + int src_psize, + int dst_psize); + +/** + * stedma40_filter() - Provides stedma40_chan_cfg to the + * ste_dma40 dma driver via the dmaengine framework. + * does some checking of what's provided. + * + * Never directly called by client. It used by dmaengine. + * @chan: dmaengine handle. + * @data: Must be of type: struct stedma40_chan_cfg and is + * the configuration of the framework. + * + * + */ + +bool stedma40_filter(struct dma_chan *chan, void *data); + +/** + * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from + * scattergatter lists. + * + * @chan: dmaengine handle + * @sgl_dst: Destination scatter list + * @sgl_src: Source scatter list + * @sgl_len: The length of each scatterlist. Both lists must be of equal length + * and each element must match the corresponding element in the other scatter + * list. + * @flags: is actually enum dma_ctrl_flags. See dmaengine.h + */ + +struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan, + struct scatterlist *sgl_dst, + struct scatterlist *sgl_src, + unsigned int sgl_len, + unsigned long flags); + +/** + * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave + * (=device) + * + * @chan: dmaengine handle + * @addr: source or destination physicall address. + * @size: bytes to transfer + * @direction: direction of transfer + * @flags: is actually enum dma_ctrl_flags. See dmaengine.h + */ + +static inline struct +dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, + dma_addr_t addr, + unsigned int size, + enum dma_data_direction direction, + unsigned long flags) +{ + struct scatterlist sg; + sg_init_table(&sg, 1); + sg.dma_address = addr; + sg.length = size; + + return chan->device->device_prep_slave_sg(chan, &sg, 1, + direction, flags); +} + +#endif diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c index fa7cb3a57cb..0ff3798769a 100644 --- a/arch/arm/plat-nomadik/timer.c +++ b/arch/arm/plat-nomadik/timer.c @@ -2,7 +2,7 @@ * linux/arch/arm/mach-nomadik/timer.c * * Copyright (C) 2008 STMicroelectronics - * Copyright (C) 2009 Alessandro Rubini, somewhat based on at91sam926x + * Copyright (C) 2010 Alessandro Rubini * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2, as @@ -18,123 +18,150 @@ #include <plat/mtu.h> -static u32 nmdk_count; /* accumulated count */ -static u32 nmdk_cycle; /* write-once */ - -/* setup by the platform code */ -void __iomem *mtu_base; +void __iomem *mtu_base; /* ssigned by machine code */ /* - * clocksource: the MTU device is a decrementing counters, so we negate - * the value being read. + * Kernel assumes that sched_clock can be called early + * but the MTU may not yet be initialized. */ -static cycle_t nmdk_read_timer(struct clocksource *cs) +static cycle_t nmdk_read_timer_dummy(struct clocksource *cs) { - u32 count = readl(mtu_base + MTU_VAL(0)); - return nmdk_count + nmdk_cycle - count; + return 0; +} +/* clocksource: MTU decrements, so we negate the value being read. */ +static cycle_t nmdk_read_timer(struct clocksource *cs) +{ + return -readl(mtu_base + MTU_VAL(0)); } static struct clocksource nmdk_clksrc = { .name = "mtu_0", - .rating = 120, - .read = nmdk_read_timer, + .rating = 200, + .read = nmdk_read_timer_dummy, + .mask = CLOCKSOURCE_MASK(32), .shift = 20, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; /* - * Clockevent device: currently only periodic mode is supported + * Override the global weak sched_clock symbol with this + * local implementation which uses the clocksource to get some + * better resolution when scheduling the kernel. We accept that + * this wraps around for now, since it is just a relative time + * stamp. (Inspired by OMAP implementation.) */ +unsigned long long notrace sched_clock(void) +{ + return clocksource_cyc2ns(nmdk_clksrc.read( + &nmdk_clksrc), + nmdk_clksrc.mult, + nmdk_clksrc.shift); +} + +/* Clockevent device: use one-shot mode */ static void nmdk_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) { + u32 cr; + switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - /* count current value? */ - writel(readl(mtu_base + MTU_IMSC) | 1, mtu_base + MTU_IMSC); + pr_err("%s: periodic mode not supported\n", __func__); break; case CLOCK_EVT_MODE_ONESHOT: - BUG(); /* Not supported, yet */ - /* FALLTHROUGH */ + /* Load highest value, enable device, enable interrupts */ + cr = readl(mtu_base + MTU_CR(1)); + writel(0, mtu_base + MTU_LR(1)); + writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1)); + writel(0x2, mtu_base + MTU_IMSC); + break; case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_UNUSED: - writel(readl(mtu_base + MTU_IMSC) & ~1, mtu_base + MTU_IMSC); + /* disable irq */ + writel(0, mtu_base + MTU_IMSC); break; case CLOCK_EVT_MODE_RESUME: break; } } +static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev) +{ + /* writing the value has immediate effect */ + writel(evt, mtu_base + MTU_LR(1)); + return 0; +} + static struct clock_event_device nmdk_clkevt = { - .name = "mtu_0", - .features = CLOCK_EVT_FEAT_PERIODIC, + .name = "mtu_1", + .features = CLOCK_EVT_FEAT_ONESHOT, .shift = 32, - .rating = 100, + .rating = 200, .set_mode = nmdk_clkevt_mode, + .set_next_event = nmdk_clkevt_next, }; /* - * IRQ Handler for the timer 0 of the MTU block. The irq is not shared - * as we are the only users of mtu0 by now. + * IRQ Handler for timer 1 of the MTU block. */ static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id) { - /* ack: "interrupt clear register" */ - writel(1 << 0, mtu_base + MTU_ICR); - - /* we can't count lost ticks, unfortunately */ - nmdk_count += nmdk_cycle; - nmdk_clkevt.event_handler(&nmdk_clkevt); + struct clock_event_device *evdev = dev_id; + writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */ + evdev->event_handler(evdev); return IRQ_HANDLED; } -/* - * Set up timer interrupt, and return the current time in seconds. - */ static struct irqaction nmdk_timer_irq = { .name = "Nomadik Timer Tick", .flags = IRQF_DISABLED | IRQF_TIMER, .handler = nmdk_timer_interrupt, + .dev_id = &nmdk_clkevt, }; -static void nmdk_timer_reset(void) -{ - u32 cr; - - writel(0, mtu_base + MTU_CR(0)); /* off */ - - /* configure load and background-load, and fire it up */ - writel(nmdk_cycle, mtu_base + MTU_LR(0)); - writel(nmdk_cycle, mtu_base + MTU_BGLR(0)); - cr = MTU_CRn_PERIODIC | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS; - writel(cr, mtu_base + MTU_CR(0)); - writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); -} - void __init nmdk_timer_init(void) { unsigned long rate; - int bits; - - rate = CLOCK_TICK_RATE; /* 2.4MHz */ - nmdk_cycle = (rate + HZ/2) / HZ; + u32 cr = MTU_CRn_32BITS;; + + /* + * Tick rate is 2.4MHz for Nomadik and 110MHz for ux500: + * use a divide-by-16 counter if it's more than 16MHz + */ + rate = CLOCK_TICK_RATE; + if (rate > 16 << 20) { + rate /= 16; + cr |= MTU_CRn_PRESCALE_16; + } else { + cr |= MTU_CRn_PRESCALE_1; + } - /* Init the timer and register clocksource */ - nmdk_timer_reset(); + /* Timer 0 is the free running clocksource */ + writel(cr, mtu_base + MTU_CR(0)); + writel(0, mtu_base + MTU_LR(0)); + writel(0, mtu_base + MTU_BGLR(0)); + writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift); - bits = 8*sizeof(nmdk_count); - nmdk_clksrc.mask = CLOCKSOURCE_MASK(bits); + /* Now the scheduling clock is ready */ + nmdk_clksrc.read = nmdk_read_timer; if (clocksource_register(&nmdk_clksrc)) - printk(KERN_ERR "timer: failed to initialize clock " - "source %s\n", nmdk_clksrc.name); + pr_err("timer: failed to initialize clock source %s\n", + nmdk_clksrc.name); + + /* Timer 1 is used for events, fix according to rate */ + writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */ + nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift); + nmdk_clkevt.max_delta_ns = + clockevent_delta2ns(0xffffffff, &nmdk_clkevt); + nmdk_clkevt.min_delta_ns = + clockevent_delta2ns(0x00000002, &nmdk_clkevt); + nmdk_clkevt.cpumask = cpumask_of(0); /* Register irq and clockevents */ setup_irq(IRQ_MTU0, &nmdk_timer_irq); - nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift); - nmdk_clkevt.cpumask = cpumask_of(0); clockevents_register_device(&nmdk_clkevt); } diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 6da796ef82b..78b49a626d0 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -110,8 +110,13 @@ config OMAP_IOMMU tristate config OMAP_IOMMU_DEBUG - depends on OMAP_IOMMU - tristate + tristate "Export OMAP IOMMU internals in DebugFS" + depends on OMAP_IOMMU && DEBUG_FS + help + Select this to see extensive information about + the internal state of OMAP IOMMU in debugfs. + + Say N unless you know you need this. choice prompt "System timer" diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 5261a092369..7190cbd9262 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -12,14 +12,12 @@ */ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/module.h> #include <linux/list.h> #include <linux/errno.h> #include <linux/err.h> #include <linux/string.h> #include <linux/clk.h> #include <linux/mutex.h> -#include <linux/platform_device.h> #include <linux/cpufreq.h> #include <linux/debugfs.h> #include <linux/io.h> @@ -32,9 +30,9 @@ static DEFINE_SPINLOCK(clockfw_lock); static struct clk_functions *arch_clock; -/*------------------------------------------------------------------------- +/* * Standard clock functions defined in include/linux/clk.h - *-------------------------------------------------------------------------*/ + */ int clk_enable(struct clk *clk) { @@ -92,9 +90,9 @@ unsigned long clk_get_rate(struct clk *clk) } EXPORT_SYMBOL(clk_get_rate); -/*------------------------------------------------------------------------- +/* * Optional clock functions defined in include/linux/clk.h - *-------------------------------------------------------------------------*/ + */ long clk_round_rate(struct clk *clk, unsigned long rate) { @@ -140,9 +138,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent) unsigned long flags; int ret = -EINVAL; - if (cpu_is_omap44xx()) - /* OMAP4 clk framework not supported yet */ - return 0; if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) return ret; @@ -169,9 +164,9 @@ struct clk *clk_get_parent(struct clk *clk) } EXPORT_SYMBOL(clk_get_parent); -/*------------------------------------------------------------------------- +/* * OMAP specific clock functions shared between omap1 and omap2 - *-------------------------------------------------------------------------*/ + */ int __initdata mpurate; @@ -222,7 +217,7 @@ void clk_reparent(struct clk *child, struct clk *parent) } /* Propagate rate to children */ -void propagate_rate(struct clk * tclk) +void propagate_rate(struct clk *tclk) { struct clk *clkp; @@ -389,7 +384,9 @@ void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) } #endif -/*-------------------------------------------------------------------------*/ +/* + * + */ #ifdef CONFIG_OMAP_RESET_CLOCKS /* @@ -404,7 +401,7 @@ static int __init clk_disable_unused(void) if (ck->ops == &clkops_null) continue; - if (ck->usecount > 0 || ck->enable_reg == 0) + if (ck->usecount > 0 || !ck->enable_reg) continue; spin_lock_irqsave(&clockfw_lock, flags); diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index f12f0e39ddf..219c01e82bc 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -47,9 +47,6 @@ struct omap_board_config_kernel *omap_board_config; int omap_board_config_size; -/* used by omap-smp.c and board-4430sdp.c */ -void __iomem *gic_cpu_base_addr; - static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) { struct omap_board_config_kernel *kinfo = NULL; diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 1d959965ff5..f7f571e7987 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -501,7 +501,8 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) burst = 0x2; break; } - /* not supported by current hardware on OMAP1 + /* + * not supported by current hardware on OMAP1 * w |= (0x03 << 7); * fall through */ @@ -510,7 +511,8 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) burst = 0x3; break; } - /* OMAP1 don't support burst 16 + /* + * OMAP1 don't support burst 16 * fall through */ default: @@ -604,7 +606,8 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) burst = 0x3; break; } - /* OMAP1 don't support burst 16 + /* + * OMAP1 don't support burst 16 * fall through */ default: @@ -709,6 +712,21 @@ static inline void omap2_enable_irq_lch(int lch) spin_unlock_irqrestore(&dma_chan_lock, flags); } +static inline void omap2_disable_irq_lch(int lch) +{ + u32 val; + unsigned long flags; + + if (!cpu_class_is_omap2()) + return; + + spin_lock_irqsave(&dma_chan_lock, flags); + val = dma_read(IRQENABLE_L0); + val &= ~(1 << lch); + dma_write(val, IRQENABLE_L0); + spin_unlock_irqrestore(&dma_chan_lock, flags); +} + int omap_request_dma(int dev_id, const char *dev_name, void (*callback)(int lch, u16 ch_status, void *data), void *data, int *dma_ch_out) @@ -807,14 +825,7 @@ void omap_free_dma(int lch) } if (cpu_class_is_omap2()) { - u32 val; - - spin_lock_irqsave(&dma_chan_lock, flags); - /* Disable interrupts */ - val = dma_read(IRQENABLE_L0); - val &= ~(1 << lch); - dma_write(val, IRQENABLE_L0); - spin_unlock_irqrestore(&dma_chan_lock, flags); + omap2_disable_irq_lch(lch); /* Clear the CSR register and IRQ status register */ dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); @@ -1277,8 +1288,10 @@ int omap_request_dma_chain(int dev_id, const char *dev_name, return -EINVAL; } - /* Allocate a queue to maintain the status of the channels - * in the chain */ + /* + * Allocate a queue to maintain the status of the channels + * in the chain + */ channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL); if (channels == NULL) { printk(KERN_ERR "omap_dma: No memory for channel queue\n"); @@ -1907,7 +1920,8 @@ static int omap2_dma_handle_ch(int ch) printk(KERN_INFO "DMA transaction error with device %d\n", dma_chan[ch].dev_id); if (cpu_class_is_omap2()) { - /* Errata: sDMA Channel is not disabled + /* + * Errata: sDMA Channel is not disabled * after a transaction error. So we explicitely * disable the channel */ @@ -2107,6 +2121,9 @@ static int __init omap_init_dma(void) for (ch = 0; ch < dma_chan_count; ch++) { omap_clear_dma(ch); + if (cpu_class_is_omap2()) + omap2_disable_irq_lch(ch); + dma_chan[ch].dev_id = -1; dma_chan[ch].next_lch = -1; diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 4d99dfbc8be..c64875f11fa 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -264,8 +264,8 @@ static struct omap_dm_timer omap4_dm_timers[] = { { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 }, }; static const char *omap4_dm_source_names[] __initdata = { - "sys_ck", - "omap_32k_fck", + "sys_clkin_ck", + "sys_32k_ck", NULL }; static struct clk *omap4_dm_source_clocks[2]; diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 45a225d0912..dc2ac42d631 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -27,6 +27,7 @@ #include <mach/irqs.h> #include <mach/gpio.h> #include <asm/mach/irq.h> +#include <plat/powerdomain.h> /* * OMAP1510 GPIO registers @@ -137,7 +138,11 @@ #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 #define OMAP4_GPIO_IRQWAKEN0 0x0044 #define OMAP4_GPIO_IRQWAKEN1 0x0048 -#define OMAP4_GPIO_SYSSTATUS 0x0104 +#define OMAP4_GPIO_SYSSTATUS 0x0114 +#define OMAP4_GPIO_IRQENABLE1 0x011c +#define OMAP4_GPIO_WAKE_EN 0x0120 +#define OMAP4_GPIO_IRQSTATUS2 0x0128 +#define OMAP4_GPIO_IRQENABLE2 0x012c #define OMAP4_GPIO_CTRL 0x0130 #define OMAP4_GPIO_OE 0x0134 #define OMAP4_GPIO_DATAIN 0x0138 @@ -148,6 +153,10 @@ #define OMAP4_GPIO_FALLINGDETECT 0x014c #define OMAP4_GPIO_DEBOUNCENABLE 0x0150 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 +#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160 +#define OMAP4_GPIO_SETIRQENABLE1 0x0164 +#define OMAP4_GPIO_CLEARWKUENA 0x0180 +#define OMAP4_GPIO_SETWKUENA 0x0184 #define OMAP4_GPIO_CLEARDATAOUT 0x0190 #define OMAP4_GPIO_SETDATAOUT 0x0194 /* @@ -195,6 +204,7 @@ struct gpio_bank { struct gpio_chip chip; struct clk *dbck; u32 mod_usage; + u32 dbck_enable_mask; }; #define METHOD_MPUIO 0 @@ -303,8 +313,6 @@ struct omap3_gpio_regs { u32 risingdetect; u32 fallingdetect; u32 dataout; - u32 setwkuena; - u32 setdataout; }; static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; @@ -591,12 +599,16 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) reg += OMAP7XX_GPIO_DATA_OUTPUT; break; #endif -#ifdef CONFIG_ARCH_OMAP2PLUS +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) case METHOD_GPIO_24XX: - case METHOD_GPIO_44XX: reg += OMAP24XX_GPIO_DATAOUT; break; #endif +#ifdef CONFIG_ARCH_OMAP4 + case METHOD_GPIO_44XX: + reg += OMAP4_GPIO_DATAOUT; + break; +#endif default: return -EINVAL; } @@ -646,6 +658,7 @@ void omap_set_gpio_debounce(int gpio, int enable) goto done; if (cpu_is_omap34xx() || cpu_is_omap44xx()) { + bank->dbck_enable_mask = val; if (enable) clk_enable(bank->dbck); else @@ -724,15 +737,27 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, OMAP4_GPIO_IRQWAKEN0); } } else { - if (trigger != 0) + /* + * GPIO wakeup request can only be generated on edge + * transitions + */ + if (trigger & IRQ_TYPE_EDGE_BOTH) __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA); else __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA); } - } else { - if (trigger != 0) + } + /* This part needs to be executed always for OMAP34xx */ + if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) { + /* + * Log the edge gpio and manually trigger the IRQ + * after resume if the input level changes + * to avoid irq lost during PER RET/OFF mode + * Applies for omap2 non-wakeup gpio and all omap3 gpios + */ + if (trigger & IRQ_TYPE_EDGE_BOTH) bank->enabled_non_wakeup_gpios |= gpio_bit; else bank->enabled_non_wakeup_gpios &= ~gpio_bit; @@ -1200,11 +1225,17 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) #endif if (!cpu_class_is_omap1()) { if (!bank->mod_usage) { + void __iomem *reg = bank->base; u32 ctrl; - ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); - ctrl &= 0xFFFFFFFE; + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) + reg += OMAP24XX_GPIO_CTRL; + else if (cpu_is_omap44xx()) + reg += OMAP4_GPIO_CTRL; + ctrl = __raw_readl(reg); /* Module is enabled, clocks are not gated */ - __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL); + ctrl &= 0xFFFFFFFE; + __raw_writel(ctrl, reg); } bank->mod_usage |= 1 << offset; } @@ -1226,22 +1257,34 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) __raw_writel(1 << offset, reg); } #endif -#ifdef CONFIG_ARCH_OMAP2PLUS - if ((bank->method == METHOD_GPIO_24XX) || - (bank->method == METHOD_GPIO_44XX)) { +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + if (bank->method == METHOD_GPIO_24XX) { /* Disable wake-up during idle for dynamic tick */ void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; __raw_writel(1 << offset, reg); } #endif +#ifdef CONFIG_ARCH_OMAP4 + if (bank->method == METHOD_GPIO_44XX) { + /* Disable wake-up during idle for dynamic tick */ + void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; + __raw_writel(1 << offset, reg); + } +#endif if (!cpu_class_is_omap1()) { bank->mod_usage &= ~(1 << offset); if (!bank->mod_usage) { + void __iomem *reg = bank->base; u32 ctrl; - ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) + reg += OMAP24XX_GPIO_CTRL; + else if (cpu_is_omap44xx()) + reg += OMAP4_GPIO_CTRL; + ctrl = __raw_readl(reg); /* Module is disabled, clocks are gated */ ctrl |= 1; - __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL); + __raw_writel(ctrl, reg); } } _reset_gpio(bank, bank->chip.base + offset); @@ -1570,9 +1613,14 @@ static int gpio_is_input(struct gpio_bank *bank, int mask) reg += OMAP7XX_GPIO_DIR_CONTROL; break; case METHOD_GPIO_24XX: - case METHOD_GPIO_44XX: reg += OMAP24XX_GPIO_OE; break; + case METHOD_GPIO_44XX: + reg += OMAP4_GPIO_OE; + break; + default: + WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method"); + return -EINVAL; } return __raw_readl(reg) & mask; } @@ -1845,7 +1893,8 @@ static int __init _omap_gpio_init(void) __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); } - if (i < ARRAY_SIZE(non_wakeup_gpios)) + if (cpu_is_omap24xx() && + i < ARRAY_SIZE(non_wakeup_gpios)) bank->non_wakeup_gpios = non_wakeup_gpios[i]; gpio_count = 32; } @@ -2028,16 +2077,27 @@ static struct sys_device omap_gpio_device = { static int workaround_enabled; -void omap2_gpio_prepare_for_retention(void) +void omap2_gpio_prepare_for_idle(int power_state) { int i, c = 0; + int min = 0; - /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious - * IRQs will be generated. See OMAP2420 Errata item 1.101. */ - for (i = 0; i < gpio_bank_count; i++) { + if (cpu_is_omap34xx()) + min = 1; + + for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; u32 l1, l2; + if (bank->dbck_enable_mask) + clk_disable(bank->dbck); + + if (power_state > PWRDM_POWER_OFF) + continue; + + /* If going to OFF, remove triggering for all + * non-wakeup GPIOs. Otherwise spurious IRQs will be + * generated. See OMAP2420 Errata item 1.101. */ if (!(bank->enabled_non_wakeup_gpios)) continue; @@ -2085,16 +2145,23 @@ void omap2_gpio_prepare_for_retention(void) workaround_enabled = 1; } -void omap2_gpio_resume_after_retention(void) +void omap2_gpio_resume_after_idle(void) { int i; + int min = 0; - if (!workaround_enabled) - return; - for (i = 0; i < gpio_bank_count; i++) { + if (cpu_is_omap34xx()) + min = 1; + for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; u32 l, gen, gen0, gen1; + if (bank->dbck_enable_mask) + clk_enable(bank->dbck); + + if (!workaround_enabled) + continue; + if (!(bank->enabled_non_wakeup_gpios)) continue; @@ -2119,7 +2186,7 @@ void omap2_gpio_resume_after_retention(void) * horribly racy, but it's the best we can do to work around * this silicon bug. */ l ^= bank->saved_datain; - l &= bank->non_wakeup_gpios; + l &= bank->enabled_non_wakeup_gpios; /* * No need to generate IRQs for the rising edge for gpio IRQs @@ -2207,10 +2274,6 @@ void omap_gpio_save_context(void) __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); gpio_context[i].dataout = __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); - gpio_context[i].setwkuena = - __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA); - gpio_context[i].setdataout = - __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT); } } @@ -2243,10 +2306,6 @@ void omap_gpio_restore_context(void) bank->base + OMAP24XX_GPIO_FALLINGDETECT); __raw_writel(gpio_context[i].dataout, bank->base + OMAP24XX_GPIO_DATAOUT); - __raw_writel(gpio_context[i].setwkuena, - bank->base + OMAP24XX_GPIO_SETWKUENA); - __raw_writel(gpio_context[i].setdataout, - bank->base + OMAP24XX_GPIO_SETDATAOUT); } } #endif @@ -2286,110 +2345,3 @@ static int __init omap_gpio_sysinit(void) } arch_initcall(omap_gpio_sysinit); - - -#ifdef CONFIG_DEBUG_FS - -#include <linux/debugfs.h> -#include <linux/seq_file.h> - -static int dbg_gpio_show(struct seq_file *s, void *unused) -{ - unsigned i, j, gpio; - - for (i = 0, gpio = 0; i < gpio_bank_count; i++) { - struct gpio_bank *bank = gpio_bank + i; - unsigned bankwidth = 16; - u32 mask = 1; - - if (bank_is_mpuio(bank)) - gpio = OMAP_MPUIO(0); - else if (cpu_class_is_omap2() || cpu_is_omap7xx()) - bankwidth = 32; - - for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { - unsigned irq, value, is_in, irqstat; - const char *label; - - label = gpiochip_is_requested(&bank->chip, j); - if (!label) - continue; - - irq = bank->virtual_irq_start + j; - value = gpio_get_value(gpio); - is_in = gpio_is_input(bank, mask); - - if (bank_is_mpuio(bank)) - seq_printf(s, "MPUIO %2d ", j); - else - seq_printf(s, "GPIO %3d ", gpio); - seq_printf(s, "(%-20.20s): %s %s", - label, - is_in ? "in " : "out", - value ? "hi" : "lo"); - -/* FIXME for at least omap2, show pullup/pulldown state */ - - irqstat = irq_desc[irq].status; -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) - if (is_in && ((bank->suspend_wakeup & mask) - || irqstat & IRQ_TYPE_SENSE_MASK)) { - char *trigger = NULL; - - switch (irqstat & IRQ_TYPE_SENSE_MASK) { - case IRQ_TYPE_EDGE_FALLING: - trigger = "falling"; - break; - case IRQ_TYPE_EDGE_RISING: - trigger = "rising"; - break; - case IRQ_TYPE_EDGE_BOTH: - trigger = "bothedge"; - break; - case IRQ_TYPE_LEVEL_LOW: - trigger = "low"; - break; - case IRQ_TYPE_LEVEL_HIGH: - trigger = "high"; - break; - case IRQ_TYPE_NONE: - trigger = "(?)"; - break; - } - seq_printf(s, ", irq-%d %-8s%s", - irq, trigger, - (bank->suspend_wakeup & mask) - ? " wakeup" : ""); - } -#endif - seq_printf(s, "\n"); - } - - if (bank_is_mpuio(bank)) { - seq_printf(s, "\n"); - gpio = 0; - } - } - return 0; -} - -static int dbg_gpio_open(struct inode *inode, struct file *file) -{ - return single_open(file, dbg_gpio_show, &inode->i_private); -} - -static const struct file_operations debug_fops = { - .open = dbg_gpio_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init omap_gpio_debuginit(void) -{ - (void) debugfs_create_file("omap_gpio", S_IRUGO, - NULL, NULL, &debug_fops); - return 0; -} -late_initcall(omap_gpio_debuginit); -#endif diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index 624e26298fa..eec2b4993c6 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -26,15 +26,19 @@ #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/i2c.h> +#include <linux/i2c-omap.h> + #include <mach/irqs.h> #include <plat/mux.h> #include <plat/i2c.h> +#include <plat/omap-pm.h> #define OMAP_I2C_SIZE 0x3f #define OMAP1_I2C_BASE 0xfffb3800 #define OMAP2_I2C_BASE1 0x48070000 #define OMAP2_I2C_BASE2 0x48072000 #define OMAP2_I2C_BASE3 0x48060000 +#define OMAP4_I2C_BASE4 0x48350000 static const char name[] = "i2c_omap"; @@ -51,11 +55,14 @@ static const char name[] = "i2c_omap"; static struct resource i2c_resources[][2] = { { I2C_RESOURCE_BUILDER(0, 0) }, -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) }, +#if defined(CONFIG_ARCH_OMAP2PLUS) + { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) }, +#endif +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) + { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) }, #endif -#if defined(CONFIG_ARCH_OMAP3) - { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) }, +#if defined(CONFIG_ARCH_OMAP4) + { I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) }, #endif }; @@ -70,14 +77,17 @@ static struct resource i2c_resources[][2] = { }, \ } -static u32 i2c_rate[ARRAY_SIZE(i2c_resources)]; +static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)]; static struct platform_device omap_i2c_devices[] = { - I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]), -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]), + I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]), +#if defined(CONFIG_ARCH_OMAP2PLUS) + I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]), +#endif +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) + I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]), #endif -#if defined(CONFIG_ARCH_OMAP3) - I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]), +#if defined(CONFIG_ARCH_OMAP4) + I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]), #endif }; @@ -93,39 +103,89 @@ static int __init omap_i2c_nr_ports(void) ports = 2; else if (cpu_is_omap34xx()) ports = 3; + else if (cpu_is_omap44xx()) + ports = 4; return ports; } -static int __init omap_i2c_add_bus(int bus_id) +/* Shared between omap2 and 3 */ +static resource_size_t omap2_i2c_irq[3] __initdata = { + INT_24XX_I2C1_IRQ, + INT_24XX_I2C2_IRQ, + INT_34XX_I2C3_IRQ, +}; + +static resource_size_t omap4_i2c_irq[4] __initdata = { + OMAP44XX_IRQ_I2C1, + OMAP44XX_IRQ_I2C2, + OMAP44XX_IRQ_I2C3, + OMAP44XX_IRQ_I2C4, +}; + +static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id) { - struct platform_device *pdev; + struct omap_i2c_bus_platform_data *pd; struct resource *res; - resource_size_t base, irq; - pdev = &omap_i2c_devices[bus_id - 1]; + pd = pdev->dev.platform_data; + res = pdev->resource; + res[0].start = OMAP1_I2C_BASE; + res[0].end = res[0].start + OMAP_I2C_SIZE; + res[1].start = INT_I2C; + omap1_i2c_mux_pins(bus_id); + + return platform_device_register(pdev); +} + +static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) +{ + struct resource *res; + resource_size_t *irq; + + res = pdev->resource; + + if (!cpu_is_omap44xx()) + irq = omap2_i2c_irq; + else + irq = omap4_i2c_irq; + if (bus_id == 1) { - res = pdev->resource; - if (cpu_class_is_omap1()) { - base = OMAP1_I2C_BASE; - irq = INT_I2C; - } else { - base = OMAP2_I2C_BASE1; - irq = INT_24XX_I2C1_IRQ; - } - res[0].start = base; - res[0].end = base + OMAP_I2C_SIZE; - res[1].start = irq; + res[0].start = OMAP2_I2C_BASE1; + res[0].end = res[0].start + OMAP_I2C_SIZE; } - if (cpu_class_is_omap1()) - omap1_i2c_mux_pins(bus_id); - if (cpu_class_is_omap2()) - omap2_i2c_mux_pins(bus_id); + res[1].start = irq[bus_id - 1]; + omap2_i2c_mux_pins(bus_id); + + /* + * When waiting for completion of a i2c transfer, we need to + * set a wake up latency constraint for the MPU. This is to + * ensure quick enough wakeup from idle, when transfer + * completes. + */ + if (cpu_is_omap34xx()) { + struct omap_i2c_bus_platform_data *pd; + + pd = pdev->dev.platform_data; + pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat; + } return platform_device_register(pdev); } +static int __init omap_i2c_add_bus(int bus_id) +{ + struct platform_device *pdev; + + pdev = &omap_i2c_devices[bus_id - 1]; + + if (cpu_class_is_omap1()) + return omap1_i2c_add_bus(pdev, bus_id); + else + return omap2_i2c_add_bus(pdev, bus_id); +} + /** * omap_i2c_bus_setup - Process command line options for the I2C bus speed * @str: String of options @@ -146,8 +206,8 @@ static int __init omap_i2c_bus_setup(char *str) get_options(str, 3, ints); if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports) return 0; - i2c_rate[ints[1] - 1] = ints[2]; - i2c_rate[ints[1] - 1] |= OMAP_I2C_CMDLINE_SETUP; + i2c_pdata[ints[1] - 1].clkrate = ints[2]; + i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP; return 1; } @@ -161,9 +221,9 @@ static int __init omap_register_i2c_bus_cmdline(void) { int i, err = 0; - for (i = 0; i < ARRAY_SIZE(i2c_rate); i++) - if (i2c_rate[i] & OMAP_I2C_CMDLINE_SETUP) { - i2c_rate[i] &= ~OMAP_I2C_CMDLINE_SETUP; + for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++) + if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) { + i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP; err = omap_i2c_add_bus(i + 1); if (err) goto out; @@ -197,9 +257,10 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate, return err; } - if (!i2c_rate[bus_id - 1]) - i2c_rate[bus_id - 1] = clkrate; - i2c_rate[bus_id - 1] &= ~OMAP_I2C_CMDLINE_SETUP; + if (!i2c_pdata[bus_id - 1].clkrate) + i2c_pdata[bus_id - 1].clkrate = clkrate; + + i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP; return omap_i2c_add_bus(bus_id); } diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 34f7fa9ad4c..dfc472ca0cc 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -196,15 +196,15 @@ extern struct clk dummy_ck; #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ /* Clksel_rate flags */ -#define DEFAULT_RATE (1 << 0) -#define RATE_IN_242X (1 << 1) -#define RATE_IN_243X (1 << 2) -#define RATE_IN_343X (1 << 3) /* rates common to all 343X */ -#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ -#define RATE_IN_36XX (1 << 5) -#define RATE_IN_4430 (1 << 6) +#define RATE_IN_242X (1 << 0) +#define RATE_IN_243X (1 << 1) +#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */ +#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */ +#define RATE_IN_36XX (1 << 4) +#define RATE_IN_4430 (1 << 5) #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) +#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX) #endif diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 7556e271942..d265018f5e6 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -31,9 +31,6 @@ struct sys_timer; -/* used by omap-smp.c and board-4430sdp.c */ -extern void __iomem *gic_cpu_base_addr; - extern void omap_map_common_io(void); extern struct sys_timer omap_timer; diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index a56deee9767..131bf405c2f 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -207,6 +207,9 @@ /* 44xx control status register offset */ #define OMAP44XX_CONTROL_STATUS 0x2c4 +/* 44xx-only CONTROL_GENERAL register offsets */ +#define OMAP44XX_CONTROL_MMC1 0x628 +#define OMAP44XX_CONTROL_PBIAS_LITE 0x600 /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. @@ -252,6 +255,23 @@ #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) #define OMAP2_PBIASLITEVMODE0 (1 << 0) +/* CONTROL_PBIAS_LITE bits for OMAP4 */ +#define OMAP4_MMC1_PWRDNZ (1 << 26) +#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25) +#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24) +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23) +#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22) +#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21) +#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20) + +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28) +#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27) +#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26) +#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25) + /* CONTROL_PROG_IO1 bits */ #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index de7c54731cb..de1c604962e 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -72,8 +72,8 @@ IH_GPIO_BASE + (nr)) extern int omap_gpio_init(void); /* Call from board init only */ -extern void omap2_gpio_prepare_for_retention(void); -extern void omap2_gpio_resume_after_retention(void); +extern void omap2_gpio_prepare_for_idle(int power_state); +extern void omap2_gpio_resume_after_idle(void); extern void omap_set_gpio_debounce(int gpio, int enable); extern void omap_set_gpio_debounce_time(int gpio, int enable); extern void omap_gpio_save_context(void); diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index 401701977db..c01d9f08a19 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -428,4 +428,8 @@ void omap3_intc_resume_idle(void); #include <mach/hardware.h> +#ifdef CONFIG_FIQ +#define FIQ_START 1024 +#endif + #endif diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 7de903d7c1c..975744f10a5 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -149,6 +149,8 @@ #define OMAP_MCBSP_REG_WAKEUPEN 0xA8 #define OMAP_MCBSP_REG_XCCR 0xAC #define OMAP_MCBSP_REG_RCCR 0xB0 +#define OMAP_MCBSP_REG_XBUFFSTAT 0xB4 +#define OMAP_MCBSP_REG_RBUFFSTAT 0xB8 #define OMAP_MCBSP_REG_SSELCR 0xBC #define OMAP_ST_REG_REV 0x00 @@ -471,6 +473,8 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); u16 omap_mcbsp_get_max_rx_threshold(unsigned int id); +u16 omap_mcbsp_get_tx_delay(unsigned int id); +u16 omap_mcbsp_get_rx_delay(unsigned int id); int omap_mcbsp_get_dma_op_mode(unsigned int id); #else static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) @@ -479,6 +483,8 @@ static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) { } static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; } static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; } +static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; } +static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; } static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; } #endif int omap_mcbsp_request(unsigned int id); diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index a1bac07c89e..c835f1e994c 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -102,6 +102,10 @@ struct omap_mmc_platform_data { /* Regulator off remapped to sleep */ unsigned vcc_aux_disable_is_sleep:1; + /* we can put the features above into this variable */ +#define HSMMC_HAS_PBIAS (1 << 0) + unsigned features; + int switch_pin; /* gpio (card detect) */ int gpio_wp; /* gpio (write protect) */ diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h index f235d32cd94..ffd909fa528 100644 --- a/arch/arm/plat-omap/include/plat/multi.h +++ b/arch/arm/plat-omap/include/plat/multi.h @@ -61,9 +61,9 @@ # define OMAP_NAME omap16xx # endif #endif -#if (defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) +#ifdef CONFIG_ARCH_OMAP2PLUS # if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) -# error "OMAP1 and OMAP2 can't be selected at the same time" +# error "OMAP1 and OMAP2PLUS can't be selected at the same time" # endif #endif #ifdef CONFIG_ARCH_OMAP2420 @@ -82,12 +82,20 @@ # define OMAP_NAME omap2430 # endif #endif -#ifdef CONFIG_ARCH_OMAP3430 +#ifdef CONFIG_ARCH_OMAP3 # ifdef OMAP_NAME # undef MULTI_OMAP2 # define MULTI_OMAP2 # else -# define OMAP_NAME omap3430 +# define OMAP_NAME omap3 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP4 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap4 # endif #endif diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h index 2845fdc658b..98fc8b4a4cc 100644 --- a/arch/arm/plat-omap/include/plat/omap34xx.h +++ b/arch/arm/plat-omap/include/plat/omap34xx.h @@ -82,5 +82,10 @@ #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) +/* Security */ +#define OMAP34XX_SEC_BASE (L4_34XX_BASE + 0xA0000) +#define OMAP34XX_SEC_SHA1MD5_BASE (OMAP34XX_SEC_BASE + 0x23000) +#define OMAP34XX_SEC_AES_BASE (OMAP34XX_SEC_BASE + 0x25000) + #endif /* __ASM_ARCH_OMAP3_H */ diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index b3ef1a7f53c..8b3f12ff5cb 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h @@ -30,6 +30,7 @@ #define OMAP4430_CM_BASE OMAP4430_CM1_BASE #define OMAP4430_CM2_BASE 0x4a008000 #define OMAP4430_PRM_BASE 0x4a306000 +#define OMAP4430_PRCM_MPU_BASE 0x48243000 #define OMAP44XX_GPMC_BASE 0x50000000 #define OMAP443X_SCM_BASE 0x4a002000 #define OMAP443X_CTRL_BASE 0x4a100000 @@ -48,5 +49,8 @@ #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) #define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000) +#define OMAP4_MMU1_BASE 0x55082000 +#define OMAP4_MMU2_BASE 0x4A066000 + #endif /* __ASM_ARCH_OMAP44XX_H */ diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 36d6ea56ab5..0eccc09ac4a 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -176,9 +176,8 @@ struct omap_hwmod_addr_space { #define OCP_USER_SDMA (1 << 1) /* omap_hwmod_ocp_if.flags bits */ -#define OCPIF_HAS_IDLEST (1 << 0) -#define OCPIF_SWSUP_IDLE (1 << 1) -#define OCPIF_CAN_BURST (1 << 2) +#define OCPIF_SWSUP_IDLE (1 << 0) +#define OCPIF_CAN_BURST (1 << 1) /** * struct omap_hwmod_ocp_if - OCP interface data @@ -327,14 +326,12 @@ struct omap_hwmod_omap2_prcm { /** * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data - * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2 - * @device_offs: device register offset from @module_offs + * @clkctrl_reg: PRCM address of the clock control register * @submodule_wkdep_bit: bit shift of the WKDEP range */ struct omap_hwmod_omap4_prcm { - u32 module_offs; - u16 device_offs; - u8 submodule_wkdep_bit; + void __iomem *clkctrl_reg; + u8 submodule_wkdep_bit; }; @@ -353,6 +350,8 @@ struct omap_hwmod_omap4_prcm { * when module is enabled, rather than the default, which is to * enable autoidle * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup + * HWMOD_NO_IDLEST : this module does not have idle status - this is the case + * only for few initiator modules on OMAP2 & 3. */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -360,6 +359,7 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_INIT_NO_IDLE (1 << 3) #define HWMOD_NO_OCP_AUTOIDLE (1 << 4) #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) +#define HWMOD_NO_IDLEST (1 << 6) /* * omap_hwmod._int_flags definitions diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index d82b2c00d4f..fb6ec74fe39 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -31,6 +31,7 @@ #define PWRDM_MAX_PWRSTS 4 /* Powerdomain allowable state bitfields */ +#define PWRSTS_ON (1 << PWRDM_POWER_ON) #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ (1 << PWRDM_POWER_ON)) @@ -49,6 +50,12 @@ * in MEM bank 1 position. This is * true for OMAP3430 */ +#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* + * support to transition from a + * sleep state to a lower sleep + * state without waking up the + * powerdomain + */ /* * Number of memory banks that are power-controllable. On OMAP4430, the diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index 83dce4c4f7e..19145f5c32b 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -15,6 +15,20 @@ #include <linux/init.h> +/* + * Memory entry used for the DEBUG_LL UART configuration. See also + * uncompress.h and debug-macro.S. + * + * Note that using a memory location for storing the UART configuration + * has at least two limitations: + * + * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the + * uncompress code could then partially overwrite itself + * 2. We assume printascii is called at least once before paging_init, + * and addruart has a chance to read OMAP_UART_INFO + */ +#define OMAP_UART_INFO (PHYS_OFFSET + 0x3ffc) + /* OMAP1 serial ports */ #define OMAP1_UART1_BASE 0xfffb0000 #define OMAP1_UART2_BASE 0xfffb0800 @@ -39,7 +53,7 @@ /* External port on Zoom2/3 */ #define ZOOM_UART_BASE 0x10000000 -#define ZOOM_UART_VIRT 0xfb000000 +#define ZOOM_UART_VIRT 0xfa400000 #define OMAP_PORT_SHIFT 2 #define OMAP7XX_PORT_SHIFT 0 diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 81d9ec540fc..bbedd71943f 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -20,27 +20,21 @@ #include <linux/types.h> #include <linux/serial_reg.h> +#include <asm/memory.h> #include <asm/mach-types.h> #include <plat/serial.h> -static volatile u8 *uart1_base; -static int uart1_shift; - static volatile u8 *uart_base; static int uart_shift; /* - * Store the DEBUG_LL uart number into UART1 scratchpad register. + * Store the DEBUG_LL uart number into memory. * See also debug-macro.S, and serial.c for related code. - * - * Please note that we currently assume that: - * - UART1 clocks are enabled for register access - * - UART1 scratchpad register can be used */ -static void set_uart1_scratchpad(unsigned char port) +static void set_omap_uart_info(unsigned char port) { - uart1_base[UART_SCR << uart1_shift] = port; + *(volatile u32 *)OMAP_UART_INFO = port; } static void putc(int c) @@ -60,42 +54,38 @@ static inline void flush(void) /* * Macros to configure UART1 and debug UART */ -#define _DEBUG_LL_ENTRY(mach, uart1_phys, uart1_shft, \ - dbg_uart, dbg_shft, dbg_id) \ +#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \ if (machine_is_##mach()) { \ - uart1_base = (volatile u8 *)(uart1_phys); \ - uart1_shift = (uart1_shft); \ uart_base = (volatile u8 *)(dbg_uart); \ uart_shift = (dbg_shft); \ port = (dbg_id); \ - set_uart1_scratchpad(port); \ + set_omap_uart_info(port); \ break; \ } #define DEBUG_LL_OMAP7XX(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP7XX_PORT_SHIFT, \ - OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, OMAP1UART##p) + _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \ + OMAP1UART##p) #define DEBUG_LL_OMAP1(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP_PORT_SHIFT, \ - OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP1UART##p) + _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \ + OMAP1UART##p) #define DEBUG_LL_OMAP2(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ - OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP2UART##p) + _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, \ + OMAP2UART##p) #define DEBUG_LL_OMAP3(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP3_UART1_BASE, OMAP_PORT_SHIFT, \ - OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP3UART##p) + _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, \ + OMAP3UART##p) #define DEBUG_LL_OMAP4(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP4_UART1_BASE, OMAP_PORT_SHIFT, \ - OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP4UART##p) + _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \ + OMAP4UART##p) /* Zoom2/3 shift is different for UART1 and external port */ #define DEBUG_LL_ZOOM(mach) \ - _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ - ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) + _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) static inline void __arch_decomp_setup(unsigned long arch_id) { diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 876ca8d5e92..98eef5360e6 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -13,6 +13,20 @@ enum ehci_hcd_omap_mode { EHCI_HCD_OMAP_MODE_TLL, }; +enum ohci_omap3_port_mode { + OMAP_OHCI_PORT_MODE_UNUSED, + OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0, + OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM, + OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0, + OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM, + OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0, + OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM, + OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0, + OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM, + OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0, + OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM, +}; + struct ehci_hcd_omap_platform_data { enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS]; unsigned phy_reset:1; @@ -21,6 +35,13 @@ struct ehci_hcd_omap_platform_data { int reset_gpio_port[OMAP3_HS_USB_PORTS]; }; +struct ohci_hcd_omap_platform_data { + enum ohci_omap3_port_mode port_mode[OMAP3_HS_USB_PORTS]; + + /* Set this to true for ES2.x silicon */ + unsigned es2_compatibility:1; +}; + /*-------------------------------------------------------------------------*/ #define OMAP1_OTG_BASE 0xfffb0400 @@ -47,6 +68,7 @@ struct omap_musb_board_data { u8 interface_type; u8 mode; u16 power; + unsigned extvbus:1; }; enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; @@ -55,6 +77,8 @@ extern void usb_musb_init(struct omap_musb_board_data *board_data); extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata); +extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata); + #endif void omap_usb_init(struct omap_usb_config *pdata); diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 0e137663349..bc094dbacee 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -25,6 +25,11 @@ #include "iopgtable.h" +#define for_each_iotlb_cr(obj, n, __i, cr) \ + for (__i = 0; \ + (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ + __i++) + /* accommodate the difference between omap1 and omap2/3 */ static const struct iommu_functions *arch_iommu; @@ -172,15 +177,12 @@ static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l) l->base = MMU_LOCK_BASE(val); l->vict = MMU_LOCK_VICT(val); - BUG_ON(l->base != 0); /* Currently no preservation is used */ } static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l) { u32 val; - BUG_ON(l->base != 0); /* Currently no preservation is used */ - val = (l->base << MMU_LOCK_BASE_SHIFT); val |= (l->vict << MMU_LOCK_VICT_SHIFT); @@ -214,6 +216,20 @@ static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, return arch_iommu->dump_cr(obj, cr, buf); } +/* only used in iotlb iteration for-loop */ +static struct cr_regs __iotlb_read_cr(struct iommu *obj, int n) +{ + struct cr_regs cr; + struct iotlb_lock l; + + iotlb_lock_get(obj, &l); + l.vict = n; + iotlb_lock_set(obj, &l); + iotlb_read_cr(obj, &cr); + + return cr; +} + /** * load_iotlb_entry - Set an iommu tlb entry * @obj: target iommu @@ -221,7 +237,6 @@ static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, **/ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) { - int i; int err = 0; struct iotlb_lock l; struct cr_regs *cr; @@ -231,21 +246,30 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) clk_enable(obj->clk); - for (i = 0; i < obj->nr_tlb_entries; i++) { + iotlb_lock_get(obj, &l); + if (l.base == obj->nr_tlb_entries) { + dev_warn(obj->dev, "%s: preserve entries full\n", __func__); + err = -EBUSY; + goto out; + } + if (!e->prsvd) { + int i; struct cr_regs tmp; + for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) + if (!iotlb_cr_valid(&tmp)) + break; + + if (i == obj->nr_tlb_entries) { + dev_dbg(obj->dev, "%s: full: no entry\n", __func__); + err = -EBUSY; + goto out; + } + iotlb_lock_get(obj, &l); - l.vict = i; + } else { + l.vict = l.base; iotlb_lock_set(obj, &l); - iotlb_read_cr(obj, &tmp); - if (!iotlb_cr_valid(&tmp)) - break; - } - - if (i == obj->nr_tlb_entries) { - dev_dbg(obj->dev, "%s: full: no entry\n", __func__); - err = -EBUSY; - goto out; } cr = iotlb_alloc_cr(obj, e); @@ -257,9 +281,11 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) iotlb_load_cr(obj, cr); kfree(cr); + if (e->prsvd) + l.base++; /* increment victim for next tlb load */ if (++l.vict == obj->nr_tlb_entries) - l.vict = 0; + l.vict = l.base; iotlb_lock_set(obj, &l); out: clk_disable(obj->clk); @@ -276,20 +302,15 @@ EXPORT_SYMBOL_GPL(load_iotlb_entry); **/ void flush_iotlb_page(struct iommu *obj, u32 da) { - struct iotlb_lock l; int i; + struct cr_regs cr; clk_enable(obj->clk); - for (i = 0; i < obj->nr_tlb_entries; i++) { - struct cr_regs cr; + for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { u32 start; size_t bytes; - iotlb_lock_get(obj, &l); - l.vict = i; - iotlb_lock_set(obj, &l); - iotlb_read_cr(obj, &cr); if (!iotlb_cr_valid(&cr)) continue; @@ -299,7 +320,6 @@ void flush_iotlb_page(struct iommu *obj, u32 da) if ((start <= da) && (da < start + bytes)) { dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", __func__, start, da, bytes); - iotlb_load_cr(obj, &cr); iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); } } @@ -370,26 +390,19 @@ EXPORT_SYMBOL_GPL(iommu_dump_ctx); static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num) { int i; - struct iotlb_lock saved, l; + struct iotlb_lock saved; + struct cr_regs tmp; struct cr_regs *p = crs; clk_enable(obj->clk); - iotlb_lock_get(obj, &saved); - memcpy(&l, &saved, sizeof(saved)); - for (i = 0; i < num; i++) { - struct cr_regs tmp; - - iotlb_lock_get(obj, &l); - l.vict = i; - iotlb_lock_set(obj, &l); - iotlb_read_cr(obj, &tmp); + for_each_iotlb_cr(obj, num, i, tmp) { if (!iotlb_cr_valid(&tmp)) continue; - *p++ = tmp; } + iotlb_lock_set(obj, &saved); clk_disable(obj->clk); @@ -503,6 +516,12 @@ static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot) { u32 *iopgd = iopgd_offset(obj, da); + if ((da | pa) & ~IOSECTION_MASK) { + dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", + __func__, da, pa, IOSECTION_SIZE); + return -EINVAL; + } + *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; flush_iopgd_range(iopgd, iopgd); return 0; @@ -513,6 +532,12 @@ static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot) u32 *iopgd = iopgd_offset(obj, da); int i; + if ((da | pa) & ~IOSUPER_MASK) { + dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", + __func__, da, pa, IOSUPER_SIZE); + return -EINVAL; + } + for (i = 0; i < 16; i++) *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; flush_iopgd_range(iopgd, iopgd + 15); @@ -542,6 +567,12 @@ static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot) u32 *iopte = iopte_alloc(obj, iopgd, da); int i; + if ((da | pa) & ~IOLARGE_MASK) { + dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", + __func__, da, pa, IOLARGE_SIZE); + return -EINVAL; + } + if (IS_ERR(iopte)) return PTR_ERR(iopte); diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c index 65c6d1ff723..e43983ba59c 100644 --- a/arch/arm/plat-omap/iovmm.c +++ b/arch/arm/plat-omap/iovmm.c @@ -287,16 +287,19 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da, prev_end = 0; list_for_each_entry(tmp, &obj->mmap, list) { - if ((prev_end <= start) && (start + bytes < tmp->da_start)) + if (prev_end >= start) + break; + + if (start + bytes < tmp->da_start) goto found; if (flags & IOVMF_DA_ANON) - start = roundup(tmp->da_end, alignement); + start = roundup(tmp->da_end + 1, alignement); prev_end = tmp->da_end; } - if ((start >= prev_end) && (ULONG_MAX - start >= bytes)) + if ((start > prev_end) && (ULONG_MAX - start >= bytes)) goto found; dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n", diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index e1d0440fd4a..7e669c9744d 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -489,7 +489,7 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) return; if (!omap_mcbsp_check_valid_id(id)) { @@ -511,7 +511,7 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) return; if (!omap_mcbsp_check_valid_id(id)) { @@ -560,6 +560,61 @@ u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) } EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold); +#define MCBSP2_FIFO_SIZE 0x500 /* 1024 + 256 locations */ +#define MCBSP1345_FIFO_SIZE 0x80 /* 128 locations */ +/* + * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO + */ +u16 omap_mcbsp_get_tx_delay(unsigned int id) +{ + struct omap_mcbsp *mcbsp; + u16 buffstat; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); + return -ENODEV; + } + mcbsp = id_to_mcbsp_ptr(id); + + /* Returns the number of free locations in the buffer */ + buffstat = MCBSP_READ(mcbsp, XBUFFSTAT); + + /* Number of slots are different in McBSP ports */ + if (mcbsp->id == 2) + return MCBSP2_FIFO_SIZE - buffstat; + else + return MCBSP1345_FIFO_SIZE - buffstat; +} +EXPORT_SYMBOL(omap_mcbsp_get_tx_delay); + +/* + * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO + * to reach the threshold value (when the DMA will be triggered to read it) + */ +u16 omap_mcbsp_get_rx_delay(unsigned int id) +{ + struct omap_mcbsp *mcbsp; + u16 buffstat, threshold; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); + return -ENODEV; + } + mcbsp = id_to_mcbsp_ptr(id); + + /* Returns the number of used locations in the buffer */ + buffstat = MCBSP_READ(mcbsp, RBUFFSTAT); + /* RX threshold */ + threshold = MCBSP_READ(mcbsp, THRSH1); + + /* Return the number of location till we reach the threshold limit */ + if (threshold <= buffstat) + return 0; + else + return threshold - buffstat; +} +EXPORT_SYMBOL(omap_mcbsp_get_rx_delay); + /* * omap_mcbsp_get_dma_op_mode just return the current configured * operating mode for the mcbsp channel @@ -587,7 +642,7 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) * Enable wakup behavior, smart idle and all wakeups * REVISIT: some wakeups may be unnecessary */ - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { u16 syscon; syscon = MCBSP_READ(mcbsp, SYSCON); @@ -610,7 +665,7 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) /* * Disable wakup behavior, smart idle and all wakeups */ - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { u16 syscon; syscon = MCBSP_READ(mcbsp, SYSCON); @@ -724,14 +779,17 @@ int omap_mcbsp_request(unsigned int id) goto err_clk_disable; } - init_completion(&mcbsp->rx_irq_completion); - err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, + if (mcbsp->rx_irq) { + init_completion(&mcbsp->rx_irq_completion); + err = request_irq(mcbsp->rx_irq, + omap_mcbsp_rx_irq_handler, 0, "McBSP", (void *)mcbsp); - if (err != 0) { - dev_err(mcbsp->dev, "Unable to request RX IRQ %d " - "for McBSP%d\n", mcbsp->rx_irq, - mcbsp->id); - goto err_free_irq; + if (err != 0) { + dev_err(mcbsp->dev, "Unable to request RX IRQ %d " + "for McBSP%d\n", mcbsp->rx_irq, + mcbsp->id); + goto err_free_irq; + } } } @@ -781,7 +839,8 @@ void omap_mcbsp_free(unsigned int id) if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { /* Free IRQs */ - free_irq(mcbsp->rx_irq, (void *)mcbsp); + if (mcbsp->rx_irq) + free_irq(mcbsp->rx_irq, (void *)mcbsp); free_irq(mcbsp->tx_irq, (void *)mcbsp); } @@ -855,7 +914,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); } - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { /* Release the transmitter and receiver */ w = MCBSP_READ_CACHE(mcbsp, XCCR); w &= ~(tx ? XDISABLE : 0); @@ -885,7 +944,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) /* Reset transmitter */ tx &= 1; - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { w = MCBSP_READ_CACHE(mcbsp, XCCR); w |= (tx ? XDISABLE : 0); MCBSP_WRITE(mcbsp, XCCR, w); @@ -895,7 +954,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) /* Reset receiver */ rx &= 1; - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { w = MCBSP_READ_CACHE(mcbsp, RCCR); w |= (rx ? RDISABLE : 0); MCBSP_WRITE(mcbsp, RCCR, w); diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index 0f519747951..f899603051a 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -2,10 +2,10 @@ * omap_device implementation * * Copyright (C) 2009 Nokia Corporation - * Paul Walmsley + * Paul Walmsley, Kevin Hilman * * Developed in collaboration with (alphabetical order): Benoit - * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram + * Cousson, Thara Gopinath, Tony Lindgren, Rajendra Nayak, Vikram * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard * Woodruff * diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 51f4dfb82e2..226b2e858d6 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -437,6 +437,20 @@ static inline int omap34xx_sram_init(void) } #endif +#ifdef CONFIG_ARCH_OMAP4 +int __init omap44xx_sram_init(void) +{ + printk(KERN_ERR "FIXME: %s not implemented\n", __func__); + + return -ENODEV; +} +#else +static inline int omap44xx_sram_init(void) +{ + return 0; +} +#endif + int __init omap_sram_init(void) { omap_detect_sram(); @@ -451,7 +465,7 @@ int __init omap_sram_init(void) else if (cpu_is_omap34xx()) omap34xx_sram_init(); else if (cpu_is_omap44xx()) - omap34xx_sram_init(); /* FIXME: */ + omap44xx_sram_init(); return 0; } diff --git a/arch/arm/plat-orion/include/plat/orion_nand.h b/arch/arm/plat-orion/include/plat/orion_nand.h index d6a4cfa3778..9f3c180834d 100644 --- a/arch/arm/plat-orion/include/plat/orion_nand.h +++ b/arch/arm/plat-orion/include/plat/orion_nand.h @@ -14,6 +14,7 @@ */ struct orion_nand_data { struct mtd_partition *parts; + int (*dev_ready)(struct mtd_info *mtd); u32 nr_parts; u8 ale; /* address line number connected to ALE */ u8 cle; /* address line number connected to CLE */ diff --git a/arch/arm/plat-pxa/Kconfig b/arch/arm/plat-pxa/Kconfig index b158e98038e..da53395a17c 100644 --- a/arch/arm/plat-pxa/Kconfig +++ b/arch/arm/plat-pxa/Kconfig @@ -1,3 +1,8 @@ if PLAT_PXA +config PXA_SSP + tristate + help + Enable support for PXA2xx SSP ports + endif diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile index 0264bfb0ca4..6187edfbcb7 100644 --- a/arch/arm/plat-pxa/Makefile +++ b/arch/arm/plat-pxa/Makefile @@ -2,10 +2,11 @@ # Makefile for code common across different PXA processor families # -obj-y := dma.o +obj-y := dma.o pmu.o obj-$(CONFIG_GENERIC_GPIO) += gpio.o obj-$(CONFIG_PXA3xx) += mfp.o obj-$(CONFIG_ARCH_MMP) += mfp.o obj-$(CONFIG_HAVE_PWM) += pwm.o +obj-$(CONFIG_PXA_SSP) += ssp.o diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index 857a6839071..9e604c80618 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h @@ -316,6 +316,13 @@ enum { MFP_PIN_PMIC_INT, MFP_PIN_RDY, + /* additional pins on MMP2 */ + MFP_PIN_TWSI1_SCL, + MFP_PIN_TWSI1_SDA, + MFP_PIN_TWSI4_SCL, + MFP_PIN_TWSI4_SDA, + MFP_PIN_CLK_REQ, + MFP_PIN_MAX, }; diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/plat-pxa/include/plat/ssp.h index 6a2ed35acd5..fe43150690e 100644 --- a/arch/arm/mach-pxa/include/mach/regs-ssp.h +++ b/arch/arm/plat-pxa/include/plat/ssp.h @@ -1,5 +1,26 @@ -#ifndef __ASM_ARCH_REGS_SSP_H -#define __ASM_ARCH_REGS_SSP_H +/* + * ssp.h + * + * Copyright (C) 2003 Russell King, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This driver supports the following PXA CPU/SSP ports:- + * + * PXA250 SSP + * PXA255 SSP, NSSP + * PXA26x SSP, NSSP, ASSP + * PXA27x SSP1, SSP2, SSP3 + * PXA3xx SSP1, SSP2, SSP3, SSP4 + */ + +#ifndef __ASM_ARCH_SSP_H +#define __ASM_ARCH_SSP_H + +#include <linux/list.h> +#include <linux/io.h> /* * SSP Serial Port Registers @@ -19,10 +40,7 @@ #define SSRSA (0x34) /* SSP Rx Timeslot Active */ #define SSTSS (0x38) /* SSP Timeslot Status */ #define SSACD (0x3C) /* SSP Audio Clock Divider */ - -#if defined(CONFIG_PXA3xx) #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ -#endif /* Common PXA2xx bits first */ #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ @@ -33,29 +51,19 @@ #define SSCR0_National (0x2 << 4) /* National Microwire */ #define SSCR0_ECS (1 << 6) /* External clock select */ #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ +#define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ -#if defined(CONFIG_PXA25x) -#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ -#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ -#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) -#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ -#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ -#endif - -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) +/* PXA27x, PXA3xx */ #define SSCR0_EDSS (1 << 20) /* Extended data size select */ #define SSCR0_NCS (1 << 21) /* Network clock select */ #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ +#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ #define SSCR0_ACS (1 << 30) /* Audio clock select */ #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ -#endif -#if defined(CONFIG_PXA3xx) -#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ -#endif #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ @@ -75,10 +83,6 @@ #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ -#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */ -#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */ -#define SSCR0_NCS (1 << 21) /* Network Clock Select */ -#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */ /* extra bits in PXA255, PXA26x and PXA27x SSP ports */ #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ @@ -108,27 +112,75 @@ #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ -#if defined(CONFIG_PXA3xx) -#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ -#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ -#endif -#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ -#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ -#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ -#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ -#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ -#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ -#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ -#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ +#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ +#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ +#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ +#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ +#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ +#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ +#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ +#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ + +/* PXA3xx */ +#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ +#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ +#define SSPSP_TIMING_MASK (0x7f8001f0) #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ -#if defined(CONFIG_PXA3xx) #define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ -#endif - -#endif /* __ASM_ARCH_REGS_SSP_H */ +enum pxa_ssp_type { + SSP_UNDEFINED = 0, + PXA25x_SSP, /* pxa 210, 250, 255, 26x */ + PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ + PXA27x_SSP, + PXA168_SSP, +}; + +struct ssp_device { + struct platform_device *pdev; + struct list_head node; + + struct clk *clk; + void __iomem *mmio_base; + unsigned long phys_base; + + const char *label; + int port_id; + int type; + int use_count; + int irq; + int drcmr_rx; + int drcmr_tx; +}; + +/** + * pxa_ssp_write_reg - Write to a SSP register + * + * @dev: SSP device to access + * @reg: Register to write to + * @val: Value to be written. + */ +static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) +{ + __raw_writel(val, dev->mmio_base + reg); +} + +/** + * pxa_ssp_read_reg - Read from a SSP register + * + * @dev: SSP device to access + * @reg: Register to read from + */ +static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg) +{ + return __raw_readl(dev->mmio_base + reg); +} + +struct ssp_device *pxa_ssp_request(int port, const char *label); +void pxa_ssp_free(struct ssp_device *); +#endif /* __ASM_ARCH_SSP_H */ diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c index be58f9fe65b..b77e018d36c 100644 --- a/arch/arm/plat-pxa/mfp.c +++ b/arch/arm/plat-pxa/mfp.c @@ -110,6 +110,7 @@ static const unsigned long mfpr_lpm[] = { MFPR_LPM_PULL_LOW, MFPR_LPM_PULL_HIGH, MFPR_LPM_FLOAT, + MFPR_LPM_INPUT, }; /* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */ diff --git a/arch/arm/plat-pxa/pmu.c b/arch/arm/plat-pxa/pmu.c new file mode 100644 index 00000000000..267ceb6feb2 --- /dev/null +++ b/arch/arm/plat-pxa/pmu.c @@ -0,0 +1,33 @@ +/* + * PMU IRQ registration for the PXA xscale PMU families. + * Copyright (C) 2010 Will Deacon, ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/platform_device.h> +#include <asm/pmu.h> +#include <mach/irqs.h> + +static struct resource pmu_resource = { + .start = IRQ_PMU, + .end = IRQ_PMU, + .flags = IORESOURCE_IRQ, +}; + +static struct platform_device pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .resource = &pmu_resource, + .num_resources = 1, +}; + +static int __init pxa_pmu_init(void) +{ + platform_device_register(&pmu_device); + return 0; +} +arch_initcall(pxa_pmu_init); diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c new file mode 100644 index 00000000000..c6357e554ab --- /dev/null +++ b/arch/arm/plat-pxa/ssp.c @@ -0,0 +1,224 @@ +/* + * linux/arch/arm/mach-pxa/ssp.c + * + * based on linux/arch/arm/mach-sa1100/ssp.c by Russell King + * + * Copyright (C) 2003 Russell King. + * Copyright (C) 2003 Wolfson Microelectronics PLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * PXA2xx SSP driver. This provides the generic core for simple + * IO-based SSP applications and allows easy port setup for DMA access. + * + * Author: Liam Girdwood <liam.girdwood@wolfsonmicro.com> + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/errno.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/init.h> +#include <linux/mutex.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <asm/irq.h> +#include <mach/hardware.h> +#include <plat/ssp.h> + +static DEFINE_MUTEX(ssp_lock); +static LIST_HEAD(ssp_list); + +struct ssp_device *pxa_ssp_request(int port, const char *label) +{ + struct ssp_device *ssp = NULL; + + mutex_lock(&ssp_lock); + + list_for_each_entry(ssp, &ssp_list, node) { + if (ssp->port_id == port && ssp->use_count == 0) { + ssp->use_count++; + ssp->label = label; + break; + } + } + + mutex_unlock(&ssp_lock); + + if (&ssp->node == &ssp_list) + return NULL; + + return ssp; +} +EXPORT_SYMBOL(pxa_ssp_request); + +void pxa_ssp_free(struct ssp_device *ssp) +{ + mutex_lock(&ssp_lock); + if (ssp->use_count) { + ssp->use_count--; + ssp->label = NULL; + } else + dev_err(&ssp->pdev->dev, "device already free\n"); + mutex_unlock(&ssp_lock); +} +EXPORT_SYMBOL(pxa_ssp_free); + +static int __devinit pxa_ssp_probe(struct platform_device *pdev) +{ + const struct platform_device_id *id = platform_get_device_id(pdev); + struct resource *res; + struct ssp_device *ssp; + int ret = 0; + + ssp = kzalloc(sizeof(struct ssp_device), GFP_KERNEL); + if (ssp == NULL) { + dev_err(&pdev->dev, "failed to allocate memory"); + return -ENOMEM; + } + ssp->pdev = pdev; + + ssp->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(ssp->clk)) { + ret = PTR_ERR(ssp->clk); + goto err_free; + } + + res = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no SSP RX DRCMR defined\n"); + ret = -ENODEV; + goto err_free_clk; + } + ssp->drcmr_rx = res->start; + + res = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (res == NULL) { + dev_err(&pdev->dev, "no SSP TX DRCMR defined\n"); + ret = -ENODEV; + goto err_free_clk; + } + ssp->drcmr_tx = res->start; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + ret = -ENODEV; + goto err_free_clk; + } + + res = request_mem_region(res->start, resource_size(res), + pdev->name); + if (res == NULL) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + ret = -EBUSY; + goto err_free_clk; + } + + ssp->phys_base = res->start; + + ssp->mmio_base = ioremap(res->start, resource_size(res)); + if (ssp->mmio_base == NULL) { + dev_err(&pdev->dev, "failed to ioremap() registers\n"); + ret = -ENODEV; + goto err_free_mem; + } + + ssp->irq = platform_get_irq(pdev, 0); + if (ssp->irq < 0) { + dev_err(&pdev->dev, "no IRQ resource defined\n"); + ret = -ENODEV; + goto err_free_io; + } + + /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id + * starts from 0, do a translation here + */ + ssp->port_id = pdev->id + 1; + ssp->use_count = 0; + ssp->type = (int)id->driver_data; + + mutex_lock(&ssp_lock); + list_add(&ssp->node, &ssp_list); + mutex_unlock(&ssp_lock); + + platform_set_drvdata(pdev, ssp); + return 0; + +err_free_io: + iounmap(ssp->mmio_base); +err_free_mem: + release_mem_region(res->start, resource_size(res)); +err_free_clk: + clk_put(ssp->clk); +err_free: + kfree(ssp); + return ret; +} + +static int __devexit pxa_ssp_remove(struct platform_device *pdev) +{ + struct resource *res; + struct ssp_device *ssp; + + ssp = platform_get_drvdata(pdev); + if (ssp == NULL) + return -ENODEV; + + iounmap(ssp->mmio_base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); + + clk_put(ssp->clk); + + mutex_lock(&ssp_lock); + list_del(&ssp->node); + mutex_unlock(&ssp_lock); + + kfree(ssp); + return 0; +} + +static const struct platform_device_id ssp_id_table[] = { + { "pxa25x-ssp", PXA25x_SSP }, + { "pxa25x-nssp", PXA25x_NSSP }, + { "pxa27x-ssp", PXA27x_SSP }, + { "pxa168-ssp", PXA168_SSP }, + { }, +}; + +static struct platform_driver pxa_ssp_driver = { + .probe = pxa_ssp_probe, + .remove = __devexit_p(pxa_ssp_remove), + .driver = { + .owner = THIS_MODULE, + .name = "pxa2xx-ssp", + }, + .id_table = ssp_id_table, +}; + +static int __init pxa_ssp_init(void) +{ + return platform_driver_register(&pxa_ssp_driver); +} + +static void __exit pxa_ssp_exit(void) +{ + platform_driver_unregister(&pxa_ssp_driver); +} + +arch_initcall(pxa_ssp_init); +module_exit(pxa_ssp_exit); + +MODULE_DESCRIPTION("PXA SSP driver"); +MODULE_AUTHOR("Liam Girdwood"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 6e93ef8f3d4..984bf66826d 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -9,6 +9,7 @@ config PLAT_S3C24XX select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select S3C_DEVICE_NAND + select S3C_GPIO_CFG_S3C24XX help Base platform code for any Samsung S3C24XX device @@ -44,6 +45,12 @@ config S3C2410_CLOCK Clock code for the S3C2410, and similar processors which is currently includes the S3C2410, S3C2440, S3C2442. +config S3C2443_CLOCK + bool + help + Clock code for the S3C2443 and similar processors, which includes + the S3C2416 and S3C2450. + config S3C24XX_DCLK bool help @@ -157,4 +164,9 @@ config S3C24XX_SIMTEC_AUDIO help Add audio devices for common Simtec S3C24XX boards +config S3C2410_SETUP_TS + bool + help + Compile in platform device definition for Samsung TouchScreen. + endif diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index c2237c41141..c2064c30871 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += irq-pm.o obj-$(CONFIG_PM) += sleep.o obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o +obj-$(CONFIG_S3C2443_CLOCK) += s3c2443-clock.o obj-$(CONFIG_S3C2410_DMA) += dma.o obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o @@ -37,6 +38,7 @@ obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o # device specific setup and/or initialisation obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o +obj-$(CONFIG_S3C2410_SETUP_TS) += setup-ts.o # SPI gpio central GPIO functions diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index 9e0e20ad2e4..7b44d0c592b 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c @@ -42,6 +42,7 @@ #include <plat/nand.h> #include <plat/common-smdk.h> +#include <plat/gpio-cfg.h> #include <plat/devs.h> #include <plat/pm.h> @@ -185,10 +186,10 @@ void __init smdk_machine_init(void) { /* Configure the LEDs (even if we have no LED support)*/ - s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT); + s3c_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT); s3c2410_gpio_setpin(S3C2410_GPF(4), 1); s3c2410_gpio_setpin(S3C2410_GPF(5), 1); diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 9ca64df35bf..76d0858c3cb 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -49,6 +49,7 @@ #include <plat/s3c2400.h> #include <plat/s3c2410.h> #include <plat/s3c2412.h> +#include <plat/s3c2416.h> #include <plat/s3c244x.h> #include <plat/s3c2443.h> @@ -57,6 +58,7 @@ static const char name_s3c2400[] = "S3C2400"; static const char name_s3c2410[] = "S3C2410"; static const char name_s3c2412[] = "S3C2412"; +static const char name_s3c2416[] = "S3C2416/S3C2450"; static const char name_s3c2440[] = "S3C2440"; static const char name_s3c2442[] = "S3C2442"; static const char name_s3c2442b[] = "S3C2442B"; @@ -137,6 +139,15 @@ static struct cpu_table cpu_ids[] __initdata = { .init = s3c2412_init, .name = name_s3c2412, }, + { /* a strange version of the s3c2416 */ + .idcode = 0x32450003, + .idmask = 0xffffffff, + .map_io = s3c2416_map_io, + .init_clocks = s3c2416_init_clocks, + .init_uarts = s3c2416_init_uarts, + .init = s3c2416_init, + .name = name_s3c2416, + }, { .idcode = 0x32443001, .idmask = 0xffffffff, @@ -170,6 +181,16 @@ static struct map_desc s3c_iodesc[] __initdata = { static unsigned long s3c24xx_read_idcode_v5(void) { +#if defined(CONFIG_CPU_S3C2416) + /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */ + + u32 gs = __raw_readl(S3C24XX_GSTATUS1); + + /* test for s3c2416 or similar device */ + if ((gs >> 16) == 0x3245) + return gs; +#endif + #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) return __raw_readl(S3C2412_GSTATUS1); #else diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 9265f09bfa5..58583732b29 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -21,6 +21,7 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/slab.h> +#include <linux/string.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -38,8 +39,7 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/regs-spi.h> - -#include <mach/ts.h> +#include <plat/ts.h> /* Serial port registrations */ @@ -149,10 +149,14 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) { struct s3c2410fb_mach_info *npd; - npd = kmalloc(sizeof(*npd), GFP_KERNEL); + npd = kmemdup(pd, sizeof(*npd), GFP_KERNEL); if (npd) { - memcpy(npd, pd, sizeof(*npd)); s3c_device_lcd.dev.platform_data = npd; + npd->displays = kmemdup(pd->displays, + sizeof(struct s3c2410fb_display) * npd->num_displays, + GFP_KERNEL); + if (!npd->displays) + printk(KERN_ERR "no memory for LCD display data\n"); } else { printk(KERN_ERR "no memory for LCD platform data\n"); } @@ -338,14 +342,6 @@ struct platform_device s3c_device_adc = { .resource = s3c_adc_resource, }; -/* HWMON */ - -struct platform_device s3c_device_hwmon = { - .name = "s3c-hwmon", - .id = -1, - .dev.parent = &s3c_device_adc.dev, -}; - /* SDI */ static struct resource s3c_sdi_resource[] = { @@ -371,7 +367,7 @@ struct platform_device s3c_device_sdi = { EXPORT_SYMBOL(s3c_device_sdi); -void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) +void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) { struct s3c24xx_mci_pdata *npd; diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 93827b3d4e8..6ad274e7593 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -1104,7 +1104,7 @@ EXPORT_SYMBOL(s3c2410_dma_config); * devaddr: physical address of the source */ -int s3c2410_dma_devconfig(int channel, +int s3c2410_dma_devconfig(unsigned int channel, enum s3c2410_dmasrc source, unsigned long devaddr) { diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c index 5467470badf..2f3d7c089df 100644 --- a/arch/arm/plat-s3c24xx/gpio.c +++ b/arch/arm/plat-s3c24xx/gpio.c @@ -1,6 +1,6 @@ /* linux/arch/arm/plat-s3c24xx/gpio.c * - * Copyright (c) 2004-2005 Simtec Electronics + * Copyright (c) 2004-2010 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * * S3C24XX GPIO support @@ -20,12 +20,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ - #include <linux/kernel.h> #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> +#include <linux/gpio.h> #include <linux/io.h> #include <mach/hardware.h> @@ -34,133 +34,46 @@ #include <mach/regs-gpio.h> -void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function) -{ - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long mask; - unsigned long con; - unsigned long flags; +#include <plat/gpio-core.h> - if (pin < S3C2410_GPIO_BANKB) { - mask = 1 << S3C2410_GPIO_OFFSET(pin); - } else { - mask = 3 << S3C2410_GPIO_OFFSET(pin)*2; - } - - switch (function) { - case S3C2410_GPIO_LEAVE: - mask = 0; - function = 0; - break; - - case S3C2410_GPIO_INPUT: - case S3C2410_GPIO_OUTPUT: - case S3C2410_GPIO_SFN2: - case S3C2410_GPIO_SFN3: - if (pin < S3C2410_GPIO_BANKB) { - function -= 1; - function &= 1; - function <<= S3C2410_GPIO_OFFSET(pin); - } else { - function &= 3; - function <<= S3C2410_GPIO_OFFSET(pin)*2; - } - } - - /* modify the specified register wwith IRQs off */ - - local_irq_save(flags); - - con = __raw_readl(base + 0x00); - con &= ~mask; - con |= function; - - __raw_writel(con, base + 0x00); - - local_irq_restore(flags); -} - -EXPORT_SYMBOL(s3c2410_gpio_cfgpin); - -unsigned int s3c2410_gpio_getcfg(unsigned int pin) -{ - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long val = __raw_readl(base); - - if (pin < S3C2410_GPIO_BANKB) { - val >>= S3C2410_GPIO_OFFSET(pin); - val &= 1; - val += 1; - } else { - val >>= S3C2410_GPIO_OFFSET(pin)*2; - val &= 3; - } - - return val | S3C2410_GPIO_INPUT; -} - -EXPORT_SYMBOL(s3c2410_gpio_getcfg); +/* gpiolib wrappers until these are totally eliminated */ void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) { - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long offs = S3C2410_GPIO_OFFSET(pin); - unsigned long flags; - unsigned long up; + int ret; - if (pin < S3C2410_GPIO_BANKB) - return; + WARN_ON(to); /* should be none of these left */ - local_irq_save(flags); - - up = __raw_readl(base + 0x08); - up &= ~(1L << offs); - up |= to << offs; - __raw_writel(up, base + 0x08); + if (!to) { + /* if pull is enabled, try first with up, and if that + * fails, try using down */ - local_irq_restore(flags); + ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP); + if (ret) + s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN); + } else { + s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE); + } } - EXPORT_SYMBOL(s3c2410_gpio_pullup); -int s3c2410_gpio_getpull(unsigned int pin) -{ - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long offs = S3C2410_GPIO_OFFSET(pin); - - if (pin < S3C2410_GPIO_BANKB) - return -EINVAL; - - return (__raw_readl(base + 0x08) & (1L << offs)) ? 1 : 0; -} - -EXPORT_SYMBOL(s3c2410_gpio_getpull); - void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) { - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long offs = S3C2410_GPIO_OFFSET(pin); - unsigned long flags; - unsigned long dat; + /* do this via gpiolib until all users removed */ - local_irq_save(flags); - - dat = __raw_readl(base + 0x04); - dat &= ~(1 << offs); - dat |= to << offs; - __raw_writel(dat, base + 0x04); - - local_irq_restore(flags); + gpio_request(pin, "temporary"); + gpio_set_value(pin, to); + gpio_free(pin); } EXPORT_SYMBOL(s3c2410_gpio_setpin); unsigned int s3c2410_gpio_getpin(unsigned int pin) { - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long offs = S3C2410_GPIO_OFFSET(pin); + struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); + unsigned long offs = pin - chip->chip.base; - return __raw_readl(base + 0x04) & (1<< offs); + return __raw_readl(chip->base + 0x04) & (1<< offs); } EXPORT_SYMBOL(s3c2410_gpio_getpin); @@ -181,22 +94,3 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) } EXPORT_SYMBOL(s3c2410_modify_misccr); - -int s3c2410_gpio_getirq(unsigned int pin) -{ - if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15)) - return -EINVAL; /* not valid interrupts */ - - if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7)) - return -EINVAL; /* not valid pin */ - - if (pin < S3C2410_GPF(4)) - return (pin - S3C2410_GPF(0)) + IRQ_EINT0; - - if (pin < S3C2410_GPG(0)) - return (pin - S3C2410_GPF(4)) + IRQ_EINT4; - - return (pin - S3C2410_GPG(0)) + IRQ_EINT8; -} - -EXPORT_SYMBOL(s3c2410_gpio_getirq); diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c index 4f0f11a6a67..4c0896f2572 100644 --- a/arch/arm/plat-s3c24xx/gpiolib.c +++ b/arch/arm/plat-s3c24xx/gpiolib.c @@ -1,6 +1,6 @@ /* linux/arch/arm/plat-s3c24xx/gpiolib.c * - * Copyright (c) 2008 Simtec Electronics + * Copyright (c) 2008-2010 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> * @@ -21,6 +21,8 @@ #include <linux/gpio.h> #include <plat/gpio-core.h> +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> #include <mach/hardware.h> #include <asm/irq.h> #include <plat/pm.h> @@ -77,10 +79,21 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset) return IRQ_EINT8 + offset; } +static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = { + .set_config = s3c_gpio_setcfg_s3c24xx_a, + .get_config = s3c_gpio_getcfg_s3c24xx_a, +}; + +struct s3c_gpio_cfg s3c24xx_gpiocfg_default = { + .set_config = s3c_gpio_setcfg_s3c24xx, + .get_config = s3c_gpio_getcfg_s3c24xx, +}; + struct s3c_gpio_chip s3c24xx_gpios[] = { [0] = { .base = S3C2410_GPACON, .pm = __gpio_pm(&s3c_gpio_pm_1bit), + .config = &s3c24xx_gpiocfg_banka, .chip = { .base = S3C2410_GPA(0), .owner = THIS_MODULE, @@ -161,15 +174,58 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { .ngpio = 11, }, }, + /* GPIOS for the S3C2443 and later devices. */ + { + .base = S3C2440_GPJCON, + .pm = __gpio_pm(&s3c_gpio_pm_2bit), + .chip = { + .base = S3C2410_GPJ(0), + .owner = THIS_MODULE, + .label = "GPIOJ", + .ngpio = 16, + }, + }, { + .base = S3C2443_GPKCON, + .pm = __gpio_pm(&s3c_gpio_pm_2bit), + .chip = { + .base = S3C2410_GPK(0), + .owner = THIS_MODULE, + .label = "GPIOK", + .ngpio = 16, + }, + }, { + .base = S3C2443_GPLCON, + .pm = __gpio_pm(&s3c_gpio_pm_2bit), + .chip = { + .base = S3C2410_GPL(0), + .owner = THIS_MODULE, + .label = "GPIOL", + .ngpio = 15, + }, + }, { + .base = S3C2443_GPMCON, + .pm = __gpio_pm(&s3c_gpio_pm_2bit), + .chip = { + .base = S3C2410_GPM(0), + .owner = THIS_MODULE, + .label = "GPIOM", + .ngpio = 2, + }, + }, }; + static __init int s3c24xx_gpiolib_init(void) { struct s3c_gpio_chip *chip = s3c24xx_gpios; int gpn; - for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) + for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) { + if (!chip->config) + chip->config = &s3c24xx_gpiocfg_default; + s3c_gpiolib_add(chip); + } return 0; } diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h index 7ea8bffa7a9..005729a1077 100644 --- a/arch/arm/plat-s3c24xx/include/plat/pll.h +++ b/arch/arm/plat-s3c24xx/include/plat/pll.h @@ -35,3 +35,28 @@ s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk) return (unsigned int)fvco; } + +#define S3C2416_PLL_M_SHIFT (14) +#define S3C2416_PLL_P_SHIFT (5) +#define S3C2416_PLL_S_MASK (7) +#define S3C2416_PLL_M_MASK ((1 << 10) - 1) +#define S3C2416_PLL_P_MASK (63) + +static inline unsigned int +s3c2416_get_pll(unsigned int pllval, unsigned int baseclk) +{ + unsigned int m, p, s; + uint64_t fvco; + + m = pllval >> S3C2416_PLL_M_SHIFT; + p = pllval >> S3C2416_PLL_P_SHIFT; + + s = pllval & S3C2416_PLL_S_MASK; + m &= S3C2416_PLL_M_MASK; + p &= S3C2416_PLL_P_MASK; + + fvco = (uint64_t)baseclk * m; + do_div(fvco, (p << s)); + + return (unsigned int)fvco; +} diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2416.h b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h new file mode 100644 index 00000000000..dc3c0907d22 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h @@ -0,0 +1,31 @@ +/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h + * + * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com> + * + * Header file for s3c2416 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifdef CONFIG_CPU_S3C2416 + +struct s3c2410_uartcfg; + +extern int s3c2416_init(void); + +extern void s3c2416_map_io(void); + +extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +extern void s3c2416_init_clocks(int xtal); + +extern int s3c2416_baseclk_add(void); + +#else +#define s3c2416_init_clocks NULL +#define s3c2416_init_uarts NULL +#define s3c2416_map_io NULL +#define s3c2416_init NULL +#endif diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h index 815b107ed89..a19715feb79 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h @@ -30,3 +30,22 @@ extern int s3c2443_baseclk_add(void); #define s3c2443_map_io NULL #define s3c2443_init NULL #endif + +/* common code used by s3c2443 and others. + * note, not to be used outside of arch/arm/mach-s3c* */ + +struct clk; /* some files don't need clk.h otherwise */ + +typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base); +typedef unsigned int (*fdiv_fn)(unsigned long clkcon0); + +extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv); +extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv); + +extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable); +extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable); +extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable); + +extern struct clksrc_clk clk_epllref; +extern struct clksrc_clk clk_esysclk; +extern struct clksrc_clk clk_msysclk; diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index 3620dd29909..60627e63a25 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c @@ -43,6 +43,7 @@ #include <asm/mach/time.h> +#include <plat/gpio-cfg.h> #include <plat/pm.h> #define PFX "s3c24xx-pm: " @@ -90,22 +91,22 @@ static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) { unsigned long irqstate; unsigned long pinstate; - int irq = s3c2410_gpio_getirq(pin); + int irq = gpio_to_irq(pin); if (irqoffs < 4) irqstate = s3c_irqwake_intmask & (1L<<irqoffs); else irqstate = s3c_irqwake_eintmask & (1L<<irqoffs); - pinstate = s3c2410_gpio_getcfg(pin); + pinstate = s3c_gpio_getcfg(pin); if (!irqstate) { if (pinstate == S3C2410_GPIO_IRQ) - S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); + S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin); } else { if (pinstate == S3C2410_GPIO_IRQ) { S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); - s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); + s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); } } } diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c index b61bdb79373..9ecc5d91367 100644 --- a/arch/arm/plat-s3c24xx/s3c2410-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c @@ -87,7 +87,7 @@ static int s3c2410_upll_enable(struct clk *clk, int enable) /* standard clock definitions */ -static struct clk init_clocks_disable[] = { +static struct clk init_clocks_off[] = { { .name = "nand", .id = -1, @@ -249,17 +249,8 @@ int __init s3c2410_baseclk_add(void) /* install (and disable) the clocks we do not need immediately */ - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - - s3c2410_clkcon_enable(clkp, 0); - } + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); /* show the clock-slow value */ diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c new file mode 100644 index 00000000000..461f070eb62 --- /dev/null +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -0,0 +1,472 @@ +/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c + * + * Copyright (c) 2007, 2010 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C2443 Clock control suport - common code + */ + +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <mach/regs-s3c2443-clock.h> + +#include <plat/s3c2443.h> +#include <plat/clock.h> +#include <plat/clock-clksrc.h> +#include <plat/cpu.h> + +#include <plat/cpu-freq.h> + + +static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable) +{ + u32 ctrlbit = clk->ctrlbit; + u32 con = __raw_readl(reg); + + if (enable) + con |= ctrlbit; + else + con &= ~ctrlbit; + + __raw_writel(con, reg); + return 0; +} + +int s3c2443_clkcon_enable_h(struct clk *clk, int enable) +{ + return s3c2443_gate(S3C2443_HCLKCON, clk, enable); +} + +int s3c2443_clkcon_enable_p(struct clk *clk, int enable) +{ + return s3c2443_gate(S3C2443_PCLKCON, clk, enable); +} + +int s3c2443_clkcon_enable_s(struct clk *clk, int enable) +{ + return s3c2443_gate(S3C2443_SCLKCON, clk, enable); +} + +/* mpllref is a direct descendant of clk_xtal by default, but it is not + * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as + * such directly equating the two source clocks is impossible. + */ +struct clk clk_mpllref = { + .name = "mpllref", + .parent = &clk_xtal, + .id = -1, +}; + +static struct clk *clk_epllref_sources[] = { + [0] = &clk_mpllref, + [1] = &clk_mpllref, + [2] = &clk_xtal, + [3] = &clk_ext, +}; + +struct clksrc_clk clk_epllref = { + .clk = { + .name = "epllref", + .id = -1, + }, + .sources = &(struct clksrc_sources) { + .sources = clk_epllref_sources, + .nr_sources = ARRAY_SIZE(clk_epllref_sources), + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 }, +}; + +/* esysclk + * + * this is sourced from either the EPLL or the EPLLref clock +*/ + +static struct clk *clk_sysclk_sources[] = { + [0] = &clk_epllref.clk, + [1] = &clk_epll, +}; + +struct clksrc_clk clk_esysclk = { + .clk = { + .name = "esysclk", + .parent = &clk_epll, + .id = -1, + }, + .sources = &(struct clksrc_sources) { + .sources = clk_sysclk_sources, + .nr_sources = ARRAY_SIZE(clk_sysclk_sources), + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 }, +}; + +static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2443_CLKDIV0); + + div &= S3C2443_CLKDIV0_EXTDIV_MASK; + div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */ + + return parent_rate / (div + 1); +} + +static struct clk clk_mdivclk = { + .name = "mdivclk", + .parent = &clk_mpllref, + .id = -1, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_mdivclk, + }, +}; + +static struct clk *clk_msysclk_sources[] = { + [0] = &clk_mpllref, + [1] = &clk_mpll, + [2] = &clk_mdivclk, + [3] = &clk_mpllref, +}; + +struct clksrc_clk clk_msysclk = { + .clk = { + .name = "msysclk", + .parent = &clk_xtal, + .id = -1, + }, + .sources = &(struct clksrc_sources) { + .sources = clk_msysclk_sources, + .nr_sources = ARRAY_SIZE(clk_msysclk_sources), + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 }, +}; + +/* prediv + * + * this divides the msysclk down to pass to h/p/etc. + */ + +static unsigned long s3c2443_prediv_getrate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); + + clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK; + clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT; + + return rate / (clkdiv0 + 1); +} + +static struct clk clk_prediv = { + .name = "prediv", + .id = -1, + .parent = &clk_msysclk.clk, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_prediv_getrate, + }, +}; + +/* usbhost + * + * usb host bus-clock, usually 48MHz to provide USB bus clock timing +*/ + +static struct clksrc_clk clk_usb_bus_host = { + .clk = { + .name = "usb-bus-host-parent", + .id = -1, + .parent = &clk_esysclk.clk, + .ctrlbit = S3C2443_SCLKCON_USBHOST, + .enable = s3c2443_clkcon_enable_s, + }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, +}; + +/* common clksrc clocks */ + +static struct clksrc_clk clksrc_clks[] = { + { + /* ART baud-rate clock sourced from esysclk via a divisor */ + .clk = { + .name = "uartclk", + .id = -1, + .parent = &clk_esysclk.clk, + }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, + }, { + /* camera interface bus-clock, divided down from esysclk */ + .clk = { + .name = "camif-upll", /* same as 2440 name */ + .id = -1, + .parent = &clk_esysclk.clk, + .ctrlbit = S3C2443_SCLKCON_CAMCLK, + .enable = s3c2443_clkcon_enable_s, + }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 }, + }, { + .clk = { + .name = "display-if", + .id = -1, + .parent = &clk_esysclk.clk, + .ctrlbit = S3C2443_SCLKCON_DISPCLK, + .enable = s3c2443_clkcon_enable_s, + }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 }, + }, +}; + + +static struct clk init_clocks_off[] = { + { + .name = "adc", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_ADC, + }, { + .name = "i2c", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_IIC, + } +}; + +static struct clk init_clocks[] = { + { + .name = "dma", + .id = 0, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA0, + }, { + .name = "dma", + .id = 1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA1, + }, { + .name = "dma", + .id = 2, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA2, + }, { + .name = "dma", + .id = 3, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA3, + }, { + .name = "dma", + .id = 4, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA4, + }, { + .name = "dma", + .id = 5, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA5, + }, { + .name = "hsmmc", + .id = 0, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_HSMMC, + }, { + .name = "gpio", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_GPIO, + }, { + .name = "usb-host", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_USBH, + }, { + .name = "usb-device", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_USBD, + }, { + .name = "lcd", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_LCDC, + + }, { + .name = "timers", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_PWMT, + }, { + .name = "cfc", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_CFC, + }, { + .name = "ssmc", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_SSMC, + }, { + .name = "uart", + .id = 0, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_UART0, + }, { + .name = "uart", + .id = 1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_UART1, + }, { + .name = "uart", + .id = 2, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_UART2, + }, { + .name = "uart", + .id = 3, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_UART3, + }, { + .name = "rtc", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_RTC, + }, { + .name = "watchdog", + .id = -1, + .parent = &clk_p, + .ctrlbit = S3C2443_PCLKCON_WDT, + }, { + .name = "ac97", + .id = -1, + .parent = &clk_p, + .ctrlbit = S3C2443_PCLKCON_AC97, + }, { + .name = "nand", + .id = -1, + .parent = &clk_h, + }, { + .name = "usb-bus-host", + .id = -1, + .parent = &clk_usb_bus_host.clk, + } +}; + +static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) +{ + clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; + + return clkcon0 + 1; +} + +/* EPLLCON compatible enough to get on/off information */ + +void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll, + fdiv_fn get_fdiv) +{ + unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); + unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); + unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); + struct clk *xtal_clk; + unsigned long xtal; + unsigned long pll; + unsigned long fclk; + unsigned long hclk; + unsigned long pclk; + int ptr; + + xtal_clk = clk_get(NULL, "xtal"); + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); + + pll = get_mpll(mpllcon, xtal); + clk_msysclk.clk.rate = pll; + + fclk = pll / get_fdiv(clkdiv0); + hclk = s3c2443_prediv_getrate(&clk_prediv); + hclk /= s3c2443_get_hdiv(clkdiv0); + pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); + + s3c24xx_setup_clocks(fclk, hclk, pclk); + + printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", + (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", + print_mhz(pll), print_mhz(fclk), + print_mhz(hclk), print_mhz(pclk)); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++) + s3c_set_clksrc(&clksrc_clks[ptr], true); + + /* ensure usb bus clock is within correct rate of 48MHz */ + + if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) { + printk(KERN_INFO "Warning: USB host bus not at 48MHz\n"); + clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000); + } + + printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", + (epllcon & S3C2443_PLLCON_OFF) ? "off":"on", + print_mhz(clk_get_rate(&clk_epll)), + print_mhz(clk_get_rate(&clk_usb_bus))); +} + +static struct clk *clks[] __initdata = { + &clk_prediv, + &clk_mpllref, + &clk_mdivclk, + &clk_ext, + &clk_epll, + &clk_usb_bus, +}; + +static struct clksrc_clk *clksrcs[] __initdata = { + &clk_usb_bus_host, + &clk_epllref, + &clk_esysclk, + &clk_msysclk, +}; + +void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, + fdiv_fn get_fdiv) +{ + int ptr; + + /* s3c2443 parents h and p clocks from prediv */ + clk_h.parent = &clk_prediv; + clk_p.parent = &clk_prediv; + + clk_usb_bus.parent = &clk_usb_bus_host.clk; + clk_epll.parent = &clk_epllref.clk; + + s3c24xx_register_baseclocks(xtal); + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_register_clksrc(clksrcs[ptr], 1); + + s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks)); + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + + /* See s3c2443/etc notes on disabling clocks at init time */ + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + + s3c2443_common_setup_clocks(get_mpll, get_fdiv); +} diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c index 71a6accf114..9e90a7cbd1d 100644 --- a/arch/arm/plat-s3c24xx/setup-i2c.c +++ b/arch/arm/plat-s3c24xx/setup-i2c.c @@ -15,12 +15,13 @@ struct platform_device; +#include <plat/gpio-cfg.h> #include <plat/iic.h> #include <mach/hardware.h> #include <mach/regs-gpio.h> void s3c_i2c0_cfg_gpio(struct platform_device *dev) { - s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA); - s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL); + s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA); + s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL); } diff --git a/arch/arm/plat-s3c24xx/setup-ts.c b/arch/arm/plat-s3c24xx/setup-ts.c new file mode 100644 index 00000000000..ed263866367 --- /dev/null +++ b/arch/arm/plat-s3c24xx/setup-ts.c @@ -0,0 +1,34 @@ +/* linux/arch/arm/plat-s3c24xx/setup-ts.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Based on S3C24XX setup for i2c device + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/gpio.h> + +struct platform_device; /* don't need the contents */ + +#include <mach/hardware.h> +#include <mach/regs-gpio.h> + +/** + * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems + * + * Configure the GPIO for the S3C2410 system, where we have external FETs + * connected to the device (later systems such as the S3C2440 integrate + * these into the device). + */ +void s3c24xx_ts_cfg_gpio(struct platform_device *dev) +{ + s3c2410_gpio_cfgpin(S3C2410_GPG(12), S3C2410_GPG12_XMON); + s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPG13_nXPON); + s3c2410_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPG14_YMON); + s3c2410_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPG15_nYPON); +} diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c index da7a61728c1..9793544a6ac 100644 --- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c +++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c @@ -21,16 +21,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, int enable) { if (enable) { - s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0); - s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0); - s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0); + s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0); + s3c_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0); + s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0); s3c2410_gpio_pullup(S3C2410_GPE(11), 0); s3c2410_gpio_pullup(S3C2410_GPE(13), 0); } else { - s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT); - s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT); - s3c2410_gpio_pullup(S3C2410_GPE(11), 1); - s3c2410_gpio_pullup(S3C2410_GPE(12), 1); - s3c2410_gpio_pullup(S3C2410_GPE(13), 1); + s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT); + s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT); + s3c_gpio_cfgpull(S3C2410_GPE(11), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpull(S3C2410_GPE(12), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpull(S3C2410_GPE(13), S3C_GPIO_PULL_NONE); } } diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c index 89fcf5308cf..db9e9e477ec 100644 --- a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c @@ -23,16 +23,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi, printk(KERN_INFO "%s(%d)\n", __func__, enable); if (enable) { - s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1); - s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1); - s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1); + s3c_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1); + s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1); + s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1); s3c2410_gpio_pullup(S3C2410_GPD(10), 0); s3c2410_gpio_pullup(S3C2410_GPD(9), 0); } else { - s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT); - s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT); - s3c2410_gpio_pullup(S3C2410_GPD(10), 1); - s3c2410_gpio_pullup(S3C2410_GPD(9), 1); - s3c2410_gpio_pullup(S3C2410_GPD(8), 1); + s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT); + s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT); + s3c_gpio_cfgpull(S3C2410_GPD(10), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE); } } diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c index 86b9edc6741..8ea663a438b 100644 --- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c @@ -21,16 +21,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, int enable) { if (enable) { - s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1); - s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1); - s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1); + s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1); + s3c_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1); + s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1); s3c2410_gpio_pullup(S3C2410_GPG(5), 0); s3c2410_gpio_pullup(S3C2410_GPG(6), 0); } else { - s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT); - s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT); - s3c2410_gpio_pullup(S3C2410_GPG(5), 1); - s3c2410_gpio_pullup(S3C2410_GPG(6), 1); - s3c2410_gpio_pullup(S3C2410_GPG(7), 1); + s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT); + s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT); + s3c_gpio_cfgpull(S3C2410_GPG(5), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpull(S3C2410_GPG(7), S3C_GPIO_PULL_NONE); } } diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index d400a6a20fe..92bd75607b4 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -13,6 +13,7 @@ config PLAT_S5P select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select S3C_GPIO_TRACK + select S5P_GPIO_DRVSTR select SAMSUNG_GPIOLIB_4BIT select S3C_GPIO_CFG_S3C64XX select S3C_GPIO_PULL_UPDOWN diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index a7c54b332d2..0ec09a9c36b 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -16,4 +16,3 @@ obj-y += dev-uart.o obj-y += cpu.o obj-y += clock.o obj-y += irq.o -obj-y += setup-i2c0.o diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c index aa96e335073..24a931fd8d3 100644 --- a/arch/arm/plat-s5p/clock.c +++ b/arch/arm/plat-s5p/clock.c @@ -33,7 +33,12 @@ struct clk clk_ext_xtal_mux = { .id = -1, }; -static struct clk s5p_clk_27m = { +struct clk clk_xusbxti = { + .name = "xusbxti", + .id = -1, +}; + +struct clk s5p_clk_27m = { .name = "clk_27m", .id = -1, .rate = 27000000, @@ -69,6 +74,13 @@ struct clk clk_fout_epll = { .ctrlbit = (1 << 31), }; +/* VPLL clock output */ +struct clk clk_fout_vpll = { + .name = "fout_vpll", + .id = -1, + .ctrlbit = (1 << 31), +}; + /* ARM clock */ struct clk clk_arm = { .name = "armclk", @@ -133,6 +145,7 @@ static struct clk *s5p_clks[] __initdata = { &clk_fout_apll, &clk_fout_mpll, &clk_fout_epll, + &clk_fout_vpll, &clk_arm, &clk_vpll, }; diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h index 42e757f2e40..9ff3d718be3 100644 --- a/arch/arm/plat-s5p/include/plat/irqs.h +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -79,7 +79,7 @@ #define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) #define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) -#define S5P_TIMER_IRQ(x) S5P_IRQ(11 + (x)) +#define S5P_TIMER_IRQ(x) (11 + (x)) #define IRQ_TIMER0 S5P_TIMER_IRQ(0) #define IRQ_TIMER1 S5P_TIMER_IRQ(1) diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index d48325bb29e..7db322726bc 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -81,3 +81,25 @@ static inline unsigned long s5p_get_pll90xx(unsigned long baseclk, return result; } + +#define PLL65XX_MDIV_MASK (0x3FF) +#define PLL65XX_PDIV_MASK (0x3F) +#define PLL65XX_SDIV_MASK (0x7) +#define PLL65XX_MDIV_SHIFT (16) +#define PLL65XX_PDIV_SHIFT (8) +#define PLL65XX_SDIV_SHIFT (0) + +static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con) +{ + u32 mdiv, pdiv, sdiv; + u64 fvco = baseclk; + + mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK; + pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK; + sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h index 56fb8b414d4..09418b1101f 100644 --- a/arch/arm/plat-s5p/include/plat/s5p-clock.h +++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h @@ -21,12 +21,16 @@ #define clk_fin_mpll clk_ext_xtal_mux #define clk_fin_epll clk_ext_xtal_mux #define clk_fin_vpll clk_ext_xtal_mux +#define clk_fin_hpll clk_ext_xtal_mux extern struct clk clk_ext_xtal_mux; +extern struct clk clk_xusbxti; extern struct clk clk_48m; +extern struct clk s5p_clk_27m; extern struct clk clk_fout_apll; extern struct clk clk_fout_mpll; extern struct clk clk_fout_epll; +extern struct clk clk_fout_vpll; extern struct clk clk_arm; extern struct clk clk_vpll; diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig index c7ccdf22eef..c7bd2bbda23 100644 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ b/arch/arm/plat-s5pc1xx/Kconfig @@ -16,9 +16,10 @@ config PLAT_S5PC1XX select SAMSUNG_IRQ_VIC_TIMER select S3C_GPIO_TRACK select S3C_GPIO_PULL_UPDOWN + select S5P_GPIO_DRVSTR select S3C_GPIO_CFG_S3C24XX select S3C_GPIO_CFG_S3C64XX - select S5P_GPIO_CFG_S5PC1XX + select SAMSUNG_GPIOLIB_4BIT help Base platform code for any Samsung S5PC1XX device @@ -38,25 +39,6 @@ config CPU_S5PC100_CLOCK # platform specific device setup -config S5PC1XX_SETUP_FB_24BPP - bool - help - Common setup code for S5PC1XX with an 24bpp RGB display helper. - -config S5PC1XX_SETUP_I2C0 - bool - default y - help - Common setup code for i2c bus 0. - - Note, currently since i2c0 is always compiled, this setup helper - is always compiled with it. - -config S5PC1XX_SETUP_I2C1 - bool - help - Common setup code for i2c bus 1. - config S5PC1XX_SETUP_SDHCI_GPIO bool help diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile index 278f2680608..9ce6409a9e0 100644 --- a/arch/arm/plat-s5pc1xx/Makefile +++ b/arch/arm/plat-s5pc1xx/Makefile @@ -13,9 +13,8 @@ obj- := obj-y += dev-uart.o obj-y += cpu.o -obj-y += irq.o irq-gpio.o irq-eint.o +obj-y += irq.o obj-y += clock.o -obj-y += gpiolib.o # CPU support @@ -24,8 +23,4 @@ obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o # Device setup -obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o -obj-$(CONFIG_S5PC1XX_SETUP_FB_24BPP) += setup-fb-24bpp.o -obj-$(CONFIG_S5PC1XX_SETUP_I2C0) += setup-i2c0.o -obj-$(CONFIG_S5PC1XX_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/plat-s5pc1xx/gpio-config.c b/arch/arm/plat-s5pc1xx/gpio-config.c deleted file mode 100644 index a4f67e80a15..00000000000 --- a/arch/arm/plat-s5pc1xx/gpio-config.c +++ /dev/null @@ -1,62 +0,0 @@ -/* linux/arch/arm/plat-s5pc1xx/gpio-config.c - * - * Copyright 2009 Samsung Electronics - * - * S5PC1XX GPIO Configuration. - * - * Based on plat-s3c64xx/gpio-config.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/gpio.h> -#include <linux/io.h> - -#include <plat/gpio-core.h> -#include <plat/gpio-cfg-s5pc1xx.h> - -s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - void __iomem *reg; - int shift = off * 2; - u32 drvstr; - - if (!chip) - return -EINVAL; - - reg = chip->base + 0x0C; - - drvstr = __raw_readl(reg); - drvstr = 0xffff & (0x3 << shift); - drvstr = drvstr >> shift; - - return (__force s5p_gpio_drvstr_t)drvstr; -} -EXPORT_SYMBOL(s5p_gpio_get_drvstr); - -int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off, - s5p_gpio_drvstr_t drvstr) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - void __iomem *reg; - int shift = off * 2; - u32 tmp; - - if (!chip) - return -EINVAL; - - reg = chip->base + 0x0C; - - tmp = __raw_readl(reg); - tmp |= drvstr << shift; - - __raw_writel(tmp, reg); - - return 0; -} -EXPORT_SYMBOL(s5p_gpio_set_drvstr); diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h deleted file mode 100644 index 72ad59f61ef..00000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h +++ /dev/null @@ -1,32 +0,0 @@ -/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg.h - * - * Copyright 2009 Samsung Electronic - * - * S5PC1XX Platform - GPIO pin configuration - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* This file contains the necessary definitions to get the basic gpio - * pin configuration done such as setting a pin to input or output or - * changing the pull-{up,down} configurations. - */ - -#ifndef __GPIO_CFG_S5PC1XX_H -#define __GPIO_CFG_S5PC1XX_H __FILE__ - -typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; - -#define S5P_GPIO_DRVSTR_LV1 0x00 -#define S5P_GPIO_DRVSTR_LV2 0x01 -#define S5P_GPIO_DRVSTR_LV3 0x10 -#define S5P_GPIO_DRVSTR_LV4 0x11 - -extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off); - -extern int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off, - s5p_gpio_drvstr_t drvstr); - -#endif /* __GPIO_CFG_S5PC1XX_H */ diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index d552c65fa1b..229919e9744 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -90,12 +90,6 @@ config S3C_GPIO_CFG_S3C64XX Internal configuration to enable S3C64XX style GPIO configuration functions. -config S5P_GPIO_CFG_S5PC1XX - bool - help - Internal configuration to enable S5PC1XX style GPIO configuration - functions. - config S3C_GPIO_PULL_UPDOWN bool help @@ -111,6 +105,12 @@ config S3C_GPIO_PULL_UP help Internal configuration to enable the correct GPIO pull helper +config S5P_GPIO_DRVSTR + bool + help + Internal configuration to get and set correct GPIO driver strength + helper + config SAMSUNG_GPIO_EXTRA int "Number of additional GPIO pins" default 0 @@ -160,6 +160,11 @@ config S3C_DEV_HSMMC2 help Compile in platform device definitions for HSMMC channel 2 +config S3C_DEV_HWMON + bool + help + Compile in platform device definitions for HWMON + config S3C_DEV_I2C1 bool help @@ -185,12 +190,27 @@ config S3C_DEV_NAND help Compile in platform device definition for NAND controller +config S3C_DEV_RTC + bool + help + Complie in platform device definition for RTC + +config SAMSUNG_DEV_ADC + bool + help + Compile in platform device definition for ADC controller + config S3C64XX_DEV_SPI bool help Compile in platform device definitions for S3C64XX's type SPI controllers. +config SAMSUNG_DEV_TS + bool + help + Common in platform device definitions for touchscreen device + # DMA config S3C_DMA @@ -198,6 +218,12 @@ config S3C_DMA help Internal configuration for S3C DMA core +config S3C_PL330_DMA + bool + select PL330 + help + S3C DMA API Driver for PL330 DMAC. + comment "Power management" config SAMSUNG_PM_DEBUG diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 22c89d08f6e..48288499a3b 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_S3C_ADC) += adc.o obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o +obj-$(CONFIG_S3C_DEV_HWMON) += dev-hwmon.o obj-y += dev-i2c0.o obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o @@ -40,11 +41,17 @@ obj-y += dev-uart.o obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o +obj-$(CONFIG_S3C_DEV_RTC) += dev-rtc.o + +obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o +obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o # DMA support obj-$(CONFIG_S3C_DMA) += dma.o +obj-$(CONFIG_S3C_PL330_DMA) += s3c-pl330.o + # PM support obj-$(CONFIG_PM) += pm.o diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index 1b25c9d8c40..8bf79f3efdf 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -376,6 +376,21 @@ void __init s3c_register_clocks(struct clk *clkp, int nr_clks) } } +/** + * s3c_disable_clocks() - disable an array of clocks + * @clkp: Pointer to the first clock in the array. + * @nr_clks: Number of clocks to register. + * + * for internal use only at initialisation time. disable the clocks in the + * @clkp array. + */ + +void __init s3c_disable_clocks(struct clk *clkp, int nr_clks) +{ + for (; nr_clks > 0; nr_clks--, clkp++) + (clkp->enable)(clkp, 0); +} + /* initalise all the clocks */ int __init s3c24xx_register_baseclocks(unsigned long xtal) diff --git a/arch/arm/mach-s3c64xx/dev-adc.c b/arch/arm/plat-samsung/dev-adc.c index fafef9b6bcf..9d903d4095e 100644 --- a/arch/arm/mach-s3c64xx/dev-adc.c +++ b/arch/arm/plat-samsung/dev-adc.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/dev-adc.c +/* linux/arch/arm/plat-samsung/dev-adc.c * * Copyright 2010 Maurus Cuelenaere * @@ -22,8 +22,8 @@ static struct resource s3c_adc_resource[] = { [0] = { - .start = S3C64XX_PA_ADC, - .end = S3C64XX_PA_ADC + SZ_256 - 1, + .start = SAMSUNG_PA_ADC, + .end = SAMSUNG_PA_ADC + SZ_256 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -39,7 +39,7 @@ static struct resource s3c_adc_resource[] = { }; struct platform_device s3c_device_adc = { - .name = "s3c64xx-adc", + .name = "samsung-adc", .id = -1, .num_resources = ARRAY_SIZE(s3c_adc_resource), .resource = s3c_adc_resource, diff --git a/arch/arm/plat-samsung/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c index 002a15f313f..bf60204c629 100644 --- a/arch/arm/plat-samsung/dev-fb.c +++ b/arch/arm/plat-samsung/dev-fb.c @@ -19,7 +19,6 @@ #include <mach/irqs.h> #include <mach/map.h> -#include <mach/regs-fb.h> #include <plat/fb.h> #include <plat/devs.h> diff --git a/arch/arm/plat-samsung/dev-hwmon.c b/arch/arm/plat-samsung/dev-hwmon.c new file mode 100644 index 00000000000..b3ffb958725 --- /dev/null +++ b/arch/arm/plat-samsung/dev-hwmon.c @@ -0,0 +1,42 @@ +/* linux/arch/arm/plat-samsung/dev-hwmon.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Adapted for HWMON by Maurus Cuelenaere + * + * Samsung series device definition for HWMON + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <plat/devs.h> +#include <plat/hwmon.h> + +struct platform_device s3c_device_hwmon = { + .name = "s3c-hwmon", + .id = -1, + .dev.parent = &s3c_device_adc.dev, +}; + +void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd) +{ + struct s3c_hwmon_pdata *npd; + + if (!pd) { + printk(KERN_ERR "%s: no platform data\n", __func__); + return; + } + + npd = kmemdup(pd, sizeof(struct s3c_hwmon_pdata), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + + s3c_device_hwmon.dev.platform_data = npd; +} diff --git a/arch/arm/mach-s3c64xx/dev-rtc.c b/arch/arm/plat-samsung/dev-rtc.c index b9e7a05f012..bf4e2267333 100644 --- a/arch/arm/mach-s3c64xx/dev-rtc.c +++ b/arch/arm/plat-samsung/dev-rtc.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/dev-rtc.c +/* linux/arch/arm/plat-samsung/dev-rtc.c * * Copyright 2009 by Maurus Cuelenaere <mcuelenaere@gmail.com> * @@ -18,26 +18,26 @@ static struct resource s3c_rtc_resource[] = { [0] = { - .start = S3C64XX_PA_RTC, - .end = S3C64XX_PA_RTC + 0xff, - .flags = IORESOURCE_MEM, + .start = S3C_PA_RTC, + .end = S3C_PA_RTC + 0xff, + .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_RTC_ALARM, - .end = IRQ_RTC_ALARM, - .flags = IORESOURCE_IRQ, + .start = IRQ_RTC_ALARM, + .end = IRQ_RTC_ALARM, + .flags = IORESOURCE_IRQ, }, [2] = { - .start = IRQ_RTC_TIC, - .end = IRQ_RTC_TIC, - .flags = IORESOURCE_IRQ + .start = IRQ_RTC_TIC, + .end = IRQ_RTC_TIC, + .flags = IORESOURCE_IRQ } }; struct platform_device s3c_device_rtc = { - .name = "s3c64xx-rtc", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_rtc_resource), - .resource = s3c_rtc_resource, + .name = "s3c64xx-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_rtc_resource), + .resource = s3c_rtc_resource, }; EXPORT_SYMBOL(s3c_device_rtc); diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c new file mode 100644 index 00000000000..236ef8427d7 --- /dev/null +++ b/arch/arm/plat-samsung/dev-ts.c @@ -0,0 +1,61 @@ +/* linux/arch/arm/mach-s3c64xx/dev-ts.c + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> + * + * Adapted by Maurus Cuelenaere for s3c64xx + * + * S3C64XX series device definition for touchscreen device + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/map.h> + +#include <plat/devs.h> +#include <plat/ts.h> + +static struct resource s3c_ts_resource[] = { + [0] = { + .start = SAMSUNG_PA_ADC, + .end = SAMSUNG_PA_ADC + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TC, + .end = IRQ_TC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_ts = { + .name = "s3c64xx-ts", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_ts_resource), + .resource = s3c_ts_resource, +}; + +void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd) +{ + struct s3c2410_ts_mach_info *npd; + + if (!pd) { + printk(KERN_ERR "%s: no platform data\n", __func__); + return; + } + + npd = kmemdup(pd, sizeof(struct s3c2410_ts_mach_info), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + + s3c_device_ts.dev.platform_data = npd; +} +EXPORT_SYMBOL(s3c24xx_ts_set_platdata); diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c index 44a84e89654..57b68a50f45 100644 --- a/arch/arm/plat-samsung/gpio-config.c +++ b/arch/arm/plat-samsung/gpio-config.c @@ -1,7 +1,7 @@ /* linux/arch/arm/plat-s3c/gpio-config.c * * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics + * Copyright 2008-2010 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * http://armlinux.simtec.co.uk/ * @@ -33,14 +33,34 @@ int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) offset = pin - chip->chip.base; - local_irq_save(flags); + s3c_gpio_lock(chip, flags); ret = s3c_gpio_do_setcfg(chip, offset, config); - local_irq_restore(flags); + s3c_gpio_unlock(chip, flags); return ret; } EXPORT_SYMBOL(s3c_gpio_cfgpin); +unsigned s3c_gpio_getcfg(unsigned int pin) +{ + struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); + unsigned long flags; + unsigned ret = 0; + int offset; + + if (chip) { + offset = pin - chip->chip.base; + + s3c_gpio_lock(chip, flags); + ret = s3c_gpio_do_getcfg(chip, offset); + s3c_gpio_unlock(chip, flags); + } + + return ret; +} +EXPORT_SYMBOL(s3c_gpio_getcfg); + + int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); @@ -52,17 +72,17 @@ int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) offset = pin - chip->chip.base; - local_irq_save(flags); + s3c_gpio_lock(chip, flags); ret = s3c_gpio_do_setpull(chip, offset, pull); - local_irq_restore(flags); + s3c_gpio_unlock(chip, flags); return ret; } EXPORT_SYMBOL(s3c_gpio_setpull); #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX -int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg) +int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg) { void __iomem *reg = chip->base; unsigned int shift = off; @@ -87,6 +107,19 @@ int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip, return 0; } +unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip, + unsigned int off) +{ + u32 con; + + con = __raw_readl(chip->base); + con >>= off; + con &= 1; + con++; + + return S3C_GPIO_SFN(con); +} + int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg) { @@ -109,6 +142,19 @@ int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, return 0; } + +unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip, + unsigned int off) +{ + u32 con; + + con = __raw_readl(chip->base); + con >>= off * 2; + con &= 3; + + /* this conversion works for IN and OUT as well as special mode */ + return S3C_GPIO_SPECIAL(con); +} #endif #ifdef CONFIG_S3C_GPIO_CFG_S3C64XX @@ -134,6 +180,25 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, return 0; } + +unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, + unsigned int off) +{ + void __iomem *reg = chip->base; + unsigned int shift = (off & 7) * 4; + u32 con; + + if (off < 8 && chip->chip.ngpio > 8) + reg -= 4; + + con = __raw_readl(reg); + con >>= shift; + con &= 0xf; + + /* this conversion works for IN and OUT as well as special mode */ + return S3C_GPIO_SPECIAL(con); +} + #endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */ #ifdef CONFIG_S3C_GPIO_PULL_UPDOWN @@ -164,3 +229,83 @@ s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, return (__force s3c_gpio_pull_t)pup; } #endif + +#ifdef CONFIG_S3C_GPIO_PULL_UP +int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull) +{ + void __iomem *reg = chip->base + 0x08; + u32 pup = __raw_readl(reg); + + pup = __raw_readl(reg); + + if (pup == S3C_GPIO_PULL_UP) + pup &= ~(1 << off); + else if (pup == S3C_GPIO_PULL_NONE) + pup |= (1 << off); + else + return -EINVAL; + + __raw_writel(pup, reg); + return 0; +} + +s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip, + unsigned int off) +{ + void __iomem *reg = chip->base + 0x08; + u32 pup = __raw_readl(reg); + + pup &= (1 << off); + return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP; +} +#endif /* CONFIG_S3C_GPIO_PULL_UP */ + +#ifdef CONFIG_S5P_GPIO_DRVSTR +s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin) +{ + struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); + unsigned int off; + void __iomem *reg; + int shift; + u32 drvstr; + + if (!chip) + return -EINVAL; + + off = chip->chip.base - pin; + shift = off * 2; + reg = chip->base + 0x0C; + + drvstr = __raw_readl(reg); + drvstr = 0xffff & (0x3 << shift); + drvstr = drvstr >> shift; + + return (__force s5p_gpio_drvstr_t)drvstr; +} +EXPORT_SYMBOL(s5p_gpio_get_drvstr); + +int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr) +{ + struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); + unsigned int off; + void __iomem *reg; + int shift; + u32 tmp; + + if (!chip) + return -EINVAL; + + off = chip->chip.base - pin; + shift = off * 2; + reg = chip->base + 0x0C; + + tmp = __raw_readl(reg); + tmp |= drvstr << shift; + + __raw_writel(tmp, reg); + + return 0; +} +EXPORT_SYMBOL(s5p_gpio_set_drvstr); +#endif /* CONFIG_S5P_GPIO_DRVSTR */ diff --git a/arch/arm/plat-samsung/gpio.c b/arch/arm/plat-samsung/gpio.c index 28d2ab8a08d..b83a83351ce 100644 --- a/arch/arm/plat-samsung/gpio.c +++ b/arch/arm/plat-samsung/gpio.c @@ -15,6 +15,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/gpio.h> +#include <linux/spinlock.h> #include <plat/gpio-core.h> @@ -52,14 +53,14 @@ static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset) unsigned long flags; unsigned long con; - local_irq_save(flags); + s3c_gpio_lock(ourchip, flags); con = __raw_readl(base + 0x00); con &= ~(3 << (offset * 2)); __raw_writel(con, base + 0x00); - local_irq_restore(flags); + s3c_gpio_unlock(ourchip, flags); return 0; } @@ -72,7 +73,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip, unsigned long dat; unsigned long con; - local_irq_save(flags); + s3c_gpio_lock(ourchip, flags); dat = __raw_readl(base + 0x04); dat &= ~(1 << offset); @@ -87,7 +88,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip, __raw_writel(con, base + 0x00); __raw_writel(dat, base + 0x04); - local_irq_restore(flags); + s3c_gpio_unlock(ourchip, flags); return 0; } @@ -99,7 +100,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip, unsigned long flags; unsigned long dat; - local_irq_save(flags); + s3c_gpio_lock(ourchip, flags); dat = __raw_readl(base + 0x04); dat &= ~(1 << offset); @@ -107,7 +108,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip, dat |= 1 << offset; __raw_writel(dat, base + 0x04); - local_irq_restore(flags); + s3c_gpio_unlock(ourchip, flags); } static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset) @@ -131,6 +132,8 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip) BUG_ON(!gc->label); BUG_ON(!gc->ngpio); + spin_lock_init(&chip->lock); + if (!gc->direction_input) gc->direction_input = s3c_gpiolib_input; if (!gc->direction_output) diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 60b62692ac7..0fbcd0effd8 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -74,6 +74,7 @@ extern struct clk clk_ext; extern struct clk clk_h2; extern struct clk clk_27m; extern struct clk clk_48m; +extern struct clk clk_xusbxti; extern int clk_default_setrate(struct clk *clk, unsigned long rate); extern struct clk_ops clk_ops_def_setrate; @@ -91,6 +92,7 @@ extern int s3c24xx_register_clock(struct clk *clk); extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); extern void s3c_register_clocks(struct clk *clk, int nr_clks); +extern void s3c_disable_clocks(struct clk *clkp, int nr_clks); extern int s3c24xx_register_baseclocks(unsigned long xtal); diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index d316b4a579f..6412933d6fb 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -73,11 +73,15 @@ extern struct sys_timer s3c24xx_timer; extern struct sysdev_class s3c2410_sysclass; extern struct sysdev_class s3c2410a_sysclass; extern struct sysdev_class s3c2412_sysclass; +extern struct sysdev_class s3c2416_sysclass; extern struct sysdev_class s3c2440_sysclass; extern struct sysdev_class s3c2442_sysclass; extern struct sysdev_class s3c2443_sysclass; extern struct sysdev_class s3c6410_sysclass; extern struct sysdev_class s3c64xx_sysclass; +extern struct sysdev_class s5p6440_sysclass; +extern struct sysdev_class s5p6442_sysclass; +extern struct sysdev_class s5pv210_sysclass; extern void (*s5pc1xx_idle)(void); diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 796d2425831..ef69e56b288 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -64,6 +64,22 @@ extern struct platform_device s3c_device_nand; extern struct platform_device s3c_device_usbgadget; extern struct platform_device s3c_device_usb_hsotg; +extern struct platform_device s5pv210_device_ac97; +extern struct platform_device s5pv210_device_pcm0; +extern struct platform_device s5pv210_device_pcm1; +extern struct platform_device s5pv210_device_pcm2; +extern struct platform_device s5pv210_device_iis0; +extern struct platform_device s5pv210_device_iis1; +extern struct platform_device s5pv210_device_iis2; + +extern struct platform_device s5p6442_device_pcm0; +extern struct platform_device s5p6442_device_pcm1; +extern struct platform_device s5p6442_device_iis0; +extern struct platform_device s5p6442_device_iis1; + +extern struct platform_device s5p6440_device_pcm; +extern struct platform_device s5p6440_device_iis; + /* s3c2440 specific devices */ #ifdef CONFIG_CPU_S3C2440 diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h index 7584d751ed5..2e8f8c6560d 100644 --- a/arch/arm/plat-samsung/include/plat/dma.h +++ b/arch/arm/plat-samsung/include/plat/dma.h @@ -110,8 +110,8 @@ extern int s3c2410_dma_config(unsigned int channel, int xferunit); * configure the device we're talking to */ -extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, - unsigned long devaddr); +extern int s3c2410_dma_devconfig(unsigned int channel, + enum s3c2410_dmasrc source, unsigned long devaddr); /* s3c2410_dma_getposition * diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index ffc01a76b7c..1f85649d8c1 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h @@ -15,6 +15,13 @@ #ifndef __PLAT_S3C_FB_H #define __PLAT_S3C_FB_H __FILE__ +/* S3C_FB_MAX_WIN + * Set to the maximum number of windows that any of the supported hardware + * can use. Since the platform data uses this for an array size, having it + * set to the maximum of any version of the hardware can do is safe. + */ +#define S3C_FB_MAX_WIN (5) + /** * struct s3c_fb_pd_win - per window setup data * @win_mode: The display parameters to initialise (not for window 0) diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h index dda19da037a..3e21c75feef 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h @@ -30,6 +30,12 @@ static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip, return (chip->config->set_config)(chip, off, config); } +static inline unsigned s3c_gpio_do_getcfg(struct s3c_gpio_chip *chip, + unsigned int off) +{ + return (chip->config->get_config)(chip, off); +} + static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip, unsigned int off, s3c_gpio_pull_t pull) { @@ -53,6 +59,18 @@ extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg); /** + * s3c_gpio_getcfg_s3c24xx - S3C24XX style GPIO configuration read. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * + * The reverse of s3c_gpio_setcfg_s3c24xx(). Will return a value whicg + * could be directly passed back to s3c_gpio_setcfg_s3c24xx(), from the + * S3C_GPIO_SPECIAL() macro. + */ +unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip, + unsigned int off); + +/** * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A) * @chip: The gpio chip that is being configured. * @off: The offset for the GPIO being configured. @@ -65,6 +83,21 @@ extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg); + +/** + * s3c_gpio_getcfg_s3c24xx_a - S3C24XX style GPIO configuration read (Bank A) + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * + * The reverse of s3c_gpio_setcfg_s3c24xx_a() turning an GPIO into a usable + * GPIO configuration value. + * + * @sa s3c_gpio_getcfg_s3c24xx + * @sa s3c_gpio_getcfg_s3c64xx_4bit + */ +extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip, + unsigned int off); + /** * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config. * @chip: The gpio chip that is being configured. @@ -85,6 +118,20 @@ extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg); +/** + * s3c_gpio_getcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config read. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * + * The reverse of s3c_gpio_setcfg_s3c64xx_4bit(), turning a gpio configuration + * register setting into a value the software can use, such as could be passed + * to s3c_gpio_setcfg_s3c64xx_4bit(). + * + * @sa s3c_gpio_getcfg_s3c24xx + */ +extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, + unsigned int off); + /* Pull-{up,down} resistor controls. * * S3C2410,S3C2440,S3C24A0 = Pull-UP, @@ -146,6 +193,17 @@ extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, unsigned int off); /** + * s3c_gpio_getpull_1up() - Get configuration for choice of up or none + * @chip: The gpio chip that the GPIO pin belongs to + * @off: The offset to the pin to get the configuration of. + * + * This helper function reads the state of the pull-up resistor for the + * given GPIO in the same case as s3c_gpio_setpull_1up. +*/ +extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip, + unsigned int off); + +/** * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443. * @chip: The gpio chip that is being configured. * @off: The offset for the GPIO being configured. diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index 29cd6a86cad..34efdd2b032 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h @@ -25,6 +25,7 @@ #define __PLAT_GPIO_CFG_H __FILE__ typedef unsigned int __bitwise__ s3c_gpio_pull_t; +typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; /* forward declaration if gpio-core.h hasn't been included */ struct s3c_gpio_chip; @@ -77,6 +78,17 @@ struct s3c_gpio_cfg { */ extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to); +/** + * s3c_gpio_getcfg - Read the current function for a GPIO pin + * @pin: The pin to read the configuration value for. + * + * Read the configuration state of the given @pin, returning a value that + * could be passed back to s3c_gpio_cfgpin(). + * + * @sa s3c_gpio_cfgpin + */ +extern unsigned s3c_gpio_getcfg(unsigned int pin); + /* Define values for the pull-{up,down} available for each gpio pin. * * These values control the state of the weak pull-{up,down} resistors @@ -107,4 +119,33 @@ extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); */ extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); +/* Define values for the drvstr available for each gpio pin. + * + * These values control the value of the output signal driver strength, + * configurable on most pins on the S5C series. + */ +#define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x00) +#define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x01) +#define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x10) +#define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x11) + +/** + * s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin + * @pin: The pin number to get the settings for + * + * Read the driver streght value for the specified pin. +*/ +extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin); + +/** + * s3c_gpio_set_drvstr() - set the driver streght value of a gpio pin + * @pin: The pin number to configure the driver streght value + * @drvstr: The new value of the driver strength + * + * This function sets the driver strength value for the specified pin. + * It will return 0 if successfull, or a negative error code if the pin + * cannot support the requested setting. +*/ +extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr); + #endif /* __PLAT_GPIO_CFG_H */ diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 49ff406a706..e358c7da848 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -44,16 +44,26 @@ struct s3c_gpio_cfg; * @chip: The chip structure to be exported via gpiolib. * @base: The base pointer to the gpio configuration registers. * @config: special function and pull-resistor control information. + * @lock: Lock for exclusive access to this gpio bank. * @pm_save: Save information for suspend/resume support. * * This wrapper provides the necessary information for the Samsung * specific gpios being registered with gpiolib. + * + * The lock protects each gpio bank from multiple access of the shared + * configuration registers, or from reading of data whilst another thread + * is writing to the register set. + * + * Each chip has its own lock to avoid any contention between different + * CPU cores trying to get one lock for different GPIO banks, where each + * bank of GPIO has its own register space and configuration registers. */ struct s3c_gpio_chip { struct gpio_chip chip; struct s3c_gpio_cfg *config; struct s3c_gpio_pm *pm; void __iomem *base; + spinlock_t lock; #ifdef CONFIG_PM u32 pm_save[4]; #endif @@ -97,7 +107,7 @@ extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); * others = Special functions (dependant on bank) * * Note, since the code to deal with the case where there are two control - * registers instead of one, we do not have a seperate set of function + * registers instead of one, we do not have a separate set of function * (samsung_gpiolib_add_4bit2_chips)for each case. */ extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, @@ -108,6 +118,9 @@ extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); +/* exported for core SoC support to change */ +extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default; + #ifdef CONFIG_S3C_GPIO_TRACK extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; @@ -135,3 +148,7 @@ extern struct s3c_gpio_pm s3c_gpio_pm_4bit; #define __gpio_pm(x) NULL #endif /* CONFIG_PM */ + +/* locking wrappers to deal with multiple access to the same gpio bank */ +#define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) +#define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) diff --git a/arch/arm/plat-samsung/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h index 1ba88ea0aa3..c167e4429bc 100644 --- a/arch/arm/plat-samsung/include/plat/hwmon.h +++ b/arch/arm/plat-samsung/include/plat/hwmon.h @@ -37,5 +37,15 @@ struct s3c_hwmon_pdata { struct s3c_hwmon_chcfg *in[8]; }; +/** + * s3c_hwmon_set_platdata - Set platform data for S3C HWMON device + * @pd: Platform data to register to device. + * + * Register the given platform data for use with the S3C HWMON device. + * The call will copy the platform data, so the board definitions can + * make the structure itself __initdata. + */ +extern void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd); + #endif /* __ASM_ARCH_ADC_HWMON_H */ diff --git a/arch/arm/plat-samsung/include/plat/pll6553x.h b/arch/arm/plat-samsung/include/plat/pll6553x.h new file mode 100644 index 00000000000..b8b7e1d884f --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/pll6553x.h @@ -0,0 +1,51 @@ +/* arch/arm/plat-samsung/include/plat/pll6553x.h + * partially from arch/arm/mach-s3c64xx/include/mach/pll.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Samsung PLL6553x PLL code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* S3C6400 and compatible (S3C2416, etc.) EPLL code */ + +#define PLL6553X_MDIV_MASK ((1 << (23-16)) - 1) +#define PLL6553X_PDIV_MASK ((1 << (13-8)) - 1) +#define PLL6553X_SDIV_MASK ((1 << (2-0)) - 1) +#define PLL6553X_MDIV_SHIFT (16) +#define PLL6553X_PDIV_SHIFT (8) +#define PLL6553X_SDIV_SHIFT (0) +#define PLL6553X_KDIV_MASK (0xffff) + +static inline unsigned long s3c_get_pll6553x(unsigned long baseclk, + u32 pll0, u32 pll1) +{ + unsigned long result; + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK; + pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK; + sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK; + kdiv = pll1 & PLL6553X_KDIV_MASK; + + /* We need to multiple baseclk by mdiv (the integer part) and kdiv + * which is in 2^16ths, so shift mdiv up (does not overflow) and + * add kdiv before multiplying. The use of tmp is to avoid any + * overflows before shifting bac down into result when multipling + * by the mdiv and kdiv pair. + */ + + tmp = baseclk; + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + + return result; +} diff --git a/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h deleted file mode 100644 index abf2fbc2eb2..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h +++ /dev/null @@ -1,82 +0,0 @@ -/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h - * - * Copyright 2007 Simtec Electronics <linux@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2412 IIS register definition -*/ - -#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H -#define __ASM_ARCH_REGS_S3C2412_IIS_H - -#define S3C2412_IISCON (0x00) -#define S3C2412_IISMOD (0x04) -#define S3C2412_IISFIC (0x08) -#define S3C2412_IISPSR (0x0C) -#define S3C2412_IISTXD (0x10) -#define S3C2412_IISRXD (0x14) - -#define S3C2412_IISCON_LRINDEX (1 << 11) -#define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10) -#define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9) -#define S3C2412_IISCON_TXFIFO_FULL (1 << 8) -#define S3C2412_IISCON_RXFIFO_FULL (1 << 7) -#define S3C2412_IISCON_TXDMA_PAUSE (1 << 6) -#define S3C2412_IISCON_RXDMA_PAUSE (1 << 5) -#define S3C2412_IISCON_TXCH_PAUSE (1 << 4) -#define S3C2412_IISCON_RXCH_PAUSE (1 << 3) -#define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2) -#define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1) -#define S3C2412_IISCON_IIS_ACTIVE (1 << 0) - -#define S3C64XX_IISMOD_BLC_16BIT (0 << 13) -#define S3C64XX_IISMOD_BLC_8BIT (1 << 13) -#define S3C64XX_IISMOD_BLC_24BIT (2 << 13) -#define S3C64XX_IISMOD_BLC_MASK (3 << 13) - -#define S3C64XX_IISMOD_IMS_PCLK (0 << 10) -#define S3C64XX_IISMOD_IMS_SYSMUX (1 << 10) - -#define S3C2412_IISMOD_MASTER_INTERNAL (0 << 10) -#define S3C2412_IISMOD_MASTER_EXTERNAL (1 << 10) -#define S3C2412_IISMOD_SLAVE (2 << 10) -#define S3C2412_IISMOD_MASTER_MASK (3 << 10) -#define S3C2412_IISMOD_MODE_TXONLY (0 << 8) -#define S3C2412_IISMOD_MODE_RXONLY (1 << 8) -#define S3C2412_IISMOD_MODE_TXRX (2 << 8) -#define S3C2412_IISMOD_MODE_MASK (3 << 8) -#define S3C2412_IISMOD_LR_LLOW (0 << 7) -#define S3C2412_IISMOD_LR_RLOW (1 << 7) -#define S3C2412_IISMOD_SDF_IIS (0 << 5) -#define S3C2412_IISMOD_SDF_MSB (1 << 5) -#define S3C2412_IISMOD_SDF_LSB (2 << 5) -#define S3C2412_IISMOD_SDF_MASK (3 << 5) -#define S3C2412_IISMOD_RCLK_256FS (0 << 3) -#define S3C2412_IISMOD_RCLK_512FS (1 << 3) -#define S3C2412_IISMOD_RCLK_384FS (2 << 3) -#define S3C2412_IISMOD_RCLK_768FS (3 << 3) -#define S3C2412_IISMOD_RCLK_MASK (3 << 3) -#define S3C2412_IISMOD_BCLK_32FS (0 << 1) -#define S3C2412_IISMOD_BCLK_48FS (1 << 1) -#define S3C2412_IISMOD_BCLK_16FS (2 << 1) -#define S3C2412_IISMOD_BCLK_24FS (3 << 1) -#define S3C2412_IISMOD_BCLK_MASK (3 << 1) -#define S3C2412_IISMOD_8BIT (1 << 0) - -#define S3C64XX_IISMOD_CDCLKCON (1 << 12) - -#define S3C2412_IISPSR_PSREN (1 << 15) - -#define S3C2412_IISFIC_TXFLUSH (1 << 15) -#define S3C2412_IISFIC_RXFLUSH (1 << 7) -#define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf) -#define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf) - - - -#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */ - diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h new file mode 100644 index 00000000000..5fe6721b57f --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __S3C_DMA_PL330_H_ +#define __S3C_DMA_PL330_H_ + +#define S3C2410_DMAF_AUTOSTART (1 << 0) +#define S3C2410_DMAF_CIRCULAR (1 << 1) + +/* + * PL330 can assign any channel to communicate with + * any of the peripherals attched to the DMAC. + * For the sake of consistency across client drivers, + * We keep the channel names unchanged and only add + * missing peripherals are added. + * Order is not important since S3C PL330 API driver + * use these just as IDs. + */ +enum dma_ch { + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_IRDA, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S0S_TX, + DMACH_I2S1_RX, + DMACH_I2S1_TX, + DMACH_I2S2_RX, + DMACH_I2S2_TX, + DMACH_SPI0_RX, + DMACH_SPI0_TX, + DMACH_SPI1_RX, + DMACH_SPI1_TX, + DMACH_SPI2_RX, + DMACH_SPI2_TX, + DMACH_AC97_MICIN, + DMACH_AC97_PCMIN, + DMACH_AC97_PCMOUT, + DMACH_EXTERNAL, + DMACH_PWM, + DMACH_SPDIF, + DMACH_HSI_RX, + DMACH_HSI_TX, + DMACH_PCM0_TX, + DMACH_PCM0_RX, + DMACH_PCM1_TX, + DMACH_PCM1_RX, + DMACH_PCM2_TX, + DMACH_PCM2_RX, + DMACH_MSM_REQ3, + DMACH_MSM_REQ2, + DMACH_MSM_REQ1, + DMACH_MSM_REQ0, + /* END Marker, also used to denote a reserved channel */ + DMACH_MAX, +}; + +static inline bool s3c_dma_has_circular(void) +{ + return true; +} + +#include <plat/dma.h> + +#endif /* __S3C_DMA_PL330_H_ */ diff --git a/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h new file mode 100644 index 00000000000..bf5e2a9d408 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h @@ -0,0 +1,32 @@ +/* linux/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __S3C_PL330_PDATA_H +#define __S3C_PL330_PDATA_H + +#include <plat/s3c-dma-pl330.h> + +/* + * Every PL330 DMAC has max 32 peripheral interfaces, + * of which some may be not be really used in your + * DMAC's configuration. + * Populate this array of 32 peri i/fs with relevant + * channel IDs for used peri i/f and DMACH_MAX for + * those unused. + * + * The platforms just need to provide this info + * to the S3C DMA API driver for PL330. + */ +struct s3c_pl330_platdata { + enum dma_ch peri[32]; +}; + +#endif /* __S3C_PL330_PDATA_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/ts.h b/arch/arm/plat-samsung/include/plat/ts.h index dc361700d69..26fdb22e0fc 100644 --- a/arch/arm/mach-s3c2410/include/mach/ts.h +++ b/arch/arm/plat-samsung/include/plat/ts.h @@ -1,4 +1,4 @@ -/* linux/include/asm/arch-s3c2410/ts.h +/* arch/arm/plat-samsung/include/plat/ts.h * * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org> * @@ -14,8 +14,12 @@ struct s3c2410_ts_mach_info { int delay; int presc; int oversampling_shift; + void (*cfg_gpio)(struct platform_device *dev); }; extern void s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *); +/* defined by architecture to configure gpio */ +extern void s3c24xx_ts_cfg_gpio(struct platform_device *dev); + #endif /* __ASM_ARM_TS_H */ diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index 69a4c7f02e2..d50ab9d2af5 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -329,7 +329,7 @@ void s3c_pm_save_gpios(void) struct s3c_gpio_chip *ourchip; unsigned int gpio_nr; - for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) { + for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { ourchip = s3c_gpiolib_getchip(gpio_nr); if (!ourchip) continue; @@ -367,7 +367,7 @@ void s3c_pm_restore_gpios(void) struct s3c_gpio_chip *ourchip; unsigned int gpio_nr; - for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) { + for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { ourchip = s3c_gpiolib_getchip(gpio_nr); if (!ourchip) continue; diff --git a/arch/arm/plat-samsung/s3c-pl330.c b/arch/arm/plat-samsung/s3c-pl330.c new file mode 100644 index 00000000000..a91305a60ae --- /dev/null +++ b/arch/arm/plat-samsung/s3c-pl330.c @@ -0,0 +1,1224 @@ +/* linux/arch/arm/plat-samsung/s3c-pl330.c + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/platform_device.h> + +#include <asm/hardware/pl330.h> + +#include <plat/s3c-pl330-pdata.h> + +/** + * struct s3c_pl330_dmac - Logical representation of a PL330 DMAC. + * @busy_chan: Number of channels currently busy. + * @peri: List of IDs of peripherals this DMAC can work with. + * @node: To attach to the global list of DMACs. + * @pi: PL330 configuration info for the DMAC. + * @kmcache: Pool to quickly allocate xfers for all channels in the dmac. + */ +struct s3c_pl330_dmac { + unsigned busy_chan; + enum dma_ch *peri; + struct list_head node; + struct pl330_info *pi; + struct kmem_cache *kmcache; +}; + +/** + * struct s3c_pl330_xfer - A request submitted by S3C DMA clients. + * @token: Xfer ID provided by the client. + * @node: To attach to the list of xfers on a channel. + * @px: Xfer for PL330 core. + * @chan: Owner channel of this xfer. + */ +struct s3c_pl330_xfer { + void *token; + struct list_head node; + struct pl330_xfer px; + struct s3c_pl330_chan *chan; +}; + +/** + * struct s3c_pl330_chan - Logical channel to communicate with + * a Physical peripheral. + * @pl330_chan_id: Token of a hardware channel thread of PL330 DMAC. + * NULL if the channel is available to be acquired. + * @id: ID of the peripheral that this channel can communicate with. + * @options: Options specified by the client. + * @sdaddr: Address provided via s3c2410_dma_devconfig. + * @node: To attach to the global list of channels. + * @lrq: Pointer to the last submitted pl330_req to PL330 core. + * @xfer_list: To manage list of xfers enqueued. + * @req: Two requests to communicate with the PL330 engine. + * @callback_fn: Callback function to the client. + * @rqcfg: Channel configuration for the xfers. + * @xfer_head: Pointer to the xfer to be next excecuted. + * @dmac: Pointer to the DMAC that manages this channel, NULL if the + * channel is available to be acquired. + * @client: Client of this channel. NULL if the + * channel is available to be acquired. + */ +struct s3c_pl330_chan { + void *pl330_chan_id; + enum dma_ch id; + unsigned int options; + unsigned long sdaddr; + struct list_head node; + struct pl330_req *lrq; + struct list_head xfer_list; + struct pl330_req req[2]; + s3c2410_dma_cbfn_t callback_fn; + struct pl330_reqcfg rqcfg; + struct s3c_pl330_xfer *xfer_head; + struct s3c_pl330_dmac *dmac; + struct s3c2410_dma_client *client; +}; + +/* All DMACs in the platform */ +static LIST_HEAD(dmac_list); + +/* All channels to peripherals in the platform */ +static LIST_HEAD(chan_list); + +/* + * Since we add resources(DMACs and Channels) to the global pool, + * we need to guard access to the resources using a global lock + */ +static DEFINE_SPINLOCK(res_lock); + +/* Returns the channel with ID 'id' in the chan_list */ +static struct s3c_pl330_chan *id_to_chan(const enum dma_ch id) +{ + struct s3c_pl330_chan *ch; + + list_for_each_entry(ch, &chan_list, node) + if (ch->id == id) + return ch; + + return NULL; +} + +/* Allocate a new channel with ID 'id' and add to chan_list */ +static void chan_add(const enum dma_ch id) +{ + struct s3c_pl330_chan *ch = id_to_chan(id); + + /* Return if the channel already exists */ + if (ch) + return; + + ch = kmalloc(sizeof(*ch), GFP_KERNEL); + /* Return silently to work with other channels */ + if (!ch) + return; + + ch->id = id; + ch->dmac = NULL; + + list_add_tail(&ch->node, &chan_list); +} + +/* If the channel is not yet acquired by any client */ +static bool chan_free(struct s3c_pl330_chan *ch) +{ + if (!ch) + return false; + + /* Channel points to some DMAC only when it's acquired */ + return ch->dmac ? false : true; +} + +/* + * Returns 0 is peripheral i/f is invalid or not present on the dmac. + * Index + 1, otherwise. + */ +static unsigned iface_of_dmac(struct s3c_pl330_dmac *dmac, enum dma_ch ch_id) +{ + enum dma_ch *id = dmac->peri; + int i; + + /* Discount invalid markers */ + if (ch_id == DMACH_MAX) + return 0; + + for (i = 0; i < PL330_MAX_PERI; i++) + if (id[i] == ch_id) + return i + 1; + + return 0; +} + +/* If all channel threads of the DMAC are busy */ +static inline bool dmac_busy(struct s3c_pl330_dmac *dmac) +{ + struct pl330_info *pi = dmac->pi; + + return (dmac->busy_chan < pi->pcfg.num_chan) ? false : true; +} + +/* + * Returns the number of free channels that + * can be handled by this dmac only. + */ +static unsigned ch_onlyby_dmac(struct s3c_pl330_dmac *dmac) +{ + enum dma_ch *id = dmac->peri; + struct s3c_pl330_dmac *d; + struct s3c_pl330_chan *ch; + unsigned found, count = 0; + enum dma_ch p; + int i; + + for (i = 0; i < PL330_MAX_PERI; i++) { + p = id[i]; + ch = id_to_chan(p); + + if (p == DMACH_MAX || !chan_free(ch)) + continue; + + found = 0; + list_for_each_entry(d, &dmac_list, node) { + if (d != dmac && iface_of_dmac(d, ch->id)) { + found = 1; + break; + } + } + if (!found) + count++; + } + + return count; +} + +/* + * Measure of suitability of 'dmac' handling 'ch' + * + * 0 indicates 'dmac' can not handle 'ch' either + * because it is not supported by the hardware or + * because all dmac channels are currently busy. + * + * >0 vlaue indicates 'dmac' has the capability. + * The bigger the value the more suitable the dmac. + */ +#define MAX_SUIT UINT_MAX +#define MIN_SUIT 0 + +static unsigned suitablility(struct s3c_pl330_dmac *dmac, + struct s3c_pl330_chan *ch) +{ + struct pl330_info *pi = dmac->pi; + enum dma_ch *id = dmac->peri; + struct s3c_pl330_dmac *d; + unsigned s; + int i; + + s = MIN_SUIT; + /* If all the DMAC channel threads are busy */ + if (dmac_busy(dmac)) + return s; + + for (i = 0; i < PL330_MAX_PERI; i++) + if (id[i] == ch->id) + break; + + /* If the 'dmac' can't talk to 'ch' */ + if (i == PL330_MAX_PERI) + return s; + + s = MAX_SUIT; + list_for_each_entry(d, &dmac_list, node) { + /* + * If some other dmac can talk to this + * peri and has some channel free. + */ + if (d != dmac && iface_of_dmac(d, ch->id) && !dmac_busy(d)) { + s = 0; + break; + } + } + if (s) + return s; + + s = 100; + + /* Good if free chans are more, bad otherwise */ + s += (pi->pcfg.num_chan - dmac->busy_chan) - ch_onlyby_dmac(dmac); + + return s; +} + +/* More than one DMAC may have capability to transfer data with the + * peripheral. This function assigns most suitable DMAC to manage the + * channel and hence communicate with the peripheral. + */ +static struct s3c_pl330_dmac *map_chan_to_dmac(struct s3c_pl330_chan *ch) +{ + struct s3c_pl330_dmac *d, *dmac = NULL; + unsigned sn, sl = MIN_SUIT; + + list_for_each_entry(d, &dmac_list, node) { + sn = suitablility(d, ch); + + if (sn == MAX_SUIT) + return d; + + if (sn > sl) + dmac = d; + } + + return dmac; +} + +/* Acquire the channel for peripheral 'id' */ +static struct s3c_pl330_chan *chan_acquire(const enum dma_ch id) +{ + struct s3c_pl330_chan *ch = id_to_chan(id); + struct s3c_pl330_dmac *dmac; + + /* If the channel doesn't exist or is already acquired */ + if (!ch || !chan_free(ch)) { + ch = NULL; + goto acq_exit; + } + + dmac = map_chan_to_dmac(ch); + /* If couldn't map */ + if (!dmac) { + ch = NULL; + goto acq_exit; + } + + dmac->busy_chan++; + ch->dmac = dmac; + +acq_exit: + return ch; +} + +/* Delete xfer from the queue */ +static inline void del_from_queue(struct s3c_pl330_xfer *xfer) +{ + struct s3c_pl330_xfer *t; + struct s3c_pl330_chan *ch; + int found; + + if (!xfer) + return; + + ch = xfer->chan; + + /* Make sure xfer is in the queue */ + found = 0; + list_for_each_entry(t, &ch->xfer_list, node) + if (t == xfer) { + found = 1; + break; + } + + if (!found) + return; + + /* If xfer is last entry in the queue */ + if (xfer->node.next == &ch->xfer_list) + t = list_entry(ch->xfer_list.next, + struct s3c_pl330_xfer, node); + else + t = list_entry(xfer->node.next, + struct s3c_pl330_xfer, node); + + /* If there was only one node left */ + if (t == xfer) + ch->xfer_head = NULL; + else if (ch->xfer_head == xfer) + ch->xfer_head = t; + + list_del(&xfer->node); +} + +/* Provides pointer to the next xfer in the queue. + * If CIRCULAR option is set, the list is left intact, + * otherwise the xfer is removed from the list. + * Forced delete 'pluck' can be set to override the CIRCULAR option. + */ +static struct s3c_pl330_xfer *get_from_queue(struct s3c_pl330_chan *ch, + int pluck) +{ + struct s3c_pl330_xfer *xfer = ch->xfer_head; + + if (!xfer) + return NULL; + + /* If xfer is last entry in the queue */ + if (xfer->node.next == &ch->xfer_list) + ch->xfer_head = list_entry(ch->xfer_list.next, + struct s3c_pl330_xfer, node); + else + ch->xfer_head = list_entry(xfer->node.next, + struct s3c_pl330_xfer, node); + + if (pluck || !(ch->options & S3C2410_DMAF_CIRCULAR)) + del_from_queue(xfer); + + return xfer; +} + +static inline void add_to_queue(struct s3c_pl330_chan *ch, + struct s3c_pl330_xfer *xfer, int front) +{ + struct pl330_xfer *xt; + + /* If queue empty */ + if (ch->xfer_head == NULL) + ch->xfer_head = xfer; + + xt = &ch->xfer_head->px; + /* If the head already submitted (CIRCULAR head) */ + if (ch->options & S3C2410_DMAF_CIRCULAR && + (xt == ch->req[0].x || xt == ch->req[1].x)) + ch->xfer_head = xfer; + + /* If this is a resubmission, it should go at the head */ + if (front) { + ch->xfer_head = xfer; + list_add(&xfer->node, &ch->xfer_list); + } else { + list_add_tail(&xfer->node, &ch->xfer_list); + } +} + +static inline void _finish_off(struct s3c_pl330_xfer *xfer, + enum s3c2410_dma_buffresult res, int ffree) +{ + struct s3c_pl330_chan *ch; + + if (!xfer) + return; + + ch = xfer->chan; + + /* Do callback */ + if (ch->callback_fn) + ch->callback_fn(NULL, xfer->token, xfer->px.bytes, res); + + /* Force Free or if buffer is not needed anymore */ + if (ffree || !(ch->options & S3C2410_DMAF_CIRCULAR)) + kmem_cache_free(ch->dmac->kmcache, xfer); +} + +static inline int s3c_pl330_submit(struct s3c_pl330_chan *ch, + struct pl330_req *r) +{ + struct s3c_pl330_xfer *xfer; + int ret = 0; + + /* If already submitted */ + if (r->x) + return 0; + + xfer = get_from_queue(ch, 0); + if (xfer) { + r->x = &xfer->px; + + /* Use max bandwidth for M<->M xfers */ + if (r->rqtype == MEMTOMEM) { + struct pl330_info *pi = xfer->chan->dmac->pi; + int burst = 1 << ch->rqcfg.brst_size; + u32 bytes = r->x->bytes; + int bl; + + bl = pi->pcfg.data_bus_width / 8; + bl *= pi->pcfg.data_buf_dep; + bl /= burst; + + /* src/dst_burst_len can't be more than 16 */ + if (bl > 16) + bl = 16; + + while (bl > 1) { + if (!(bytes % (bl * burst))) + break; + bl--; + } + + ch->rqcfg.brst_len = bl; + } else { + ch->rqcfg.brst_len = 1; + } + + ret = pl330_submit_req(ch->pl330_chan_id, r); + + /* If submission was successful */ + if (!ret) { + ch->lrq = r; /* latest submitted req */ + return 0; + } + + r->x = NULL; + + /* If both of the PL330 ping-pong buffers filled */ + if (ret == -EAGAIN) { + dev_err(ch->dmac->pi->dev, "%s:%d!\n", + __func__, __LINE__); + /* Queue back again */ + add_to_queue(ch, xfer, 1); + ret = 0; + } else { + dev_err(ch->dmac->pi->dev, "%s:%d!\n", + __func__, __LINE__); + _finish_off(xfer, S3C2410_RES_ERR, 0); + } + } + + return ret; +} + +static void s3c_pl330_rq(struct s3c_pl330_chan *ch, + struct pl330_req *r, enum pl330_op_err err) +{ + unsigned long flags; + struct s3c_pl330_xfer *xfer; + struct pl330_xfer *xl = r->x; + enum s3c2410_dma_buffresult res; + + spin_lock_irqsave(&res_lock, flags); + + r->x = NULL; + + s3c_pl330_submit(ch, r); + + spin_unlock_irqrestore(&res_lock, flags); + + /* Map result to S3C DMA API */ + if (err == PL330_ERR_NONE) + res = S3C2410_RES_OK; + else if (err == PL330_ERR_ABORT) + res = S3C2410_RES_ABORT; + else + res = S3C2410_RES_ERR; + + /* If last request had some xfer */ + if (xl) { + xfer = container_of(xl, struct s3c_pl330_xfer, px); + _finish_off(xfer, res, 0); + } else { + dev_info(ch->dmac->pi->dev, "%s:%d No Xfer?!\n", + __func__, __LINE__); + } +} + +static void s3c_pl330_rq0(void *token, enum pl330_op_err err) +{ + struct pl330_req *r = token; + struct s3c_pl330_chan *ch = container_of(r, + struct s3c_pl330_chan, req[0]); + s3c_pl330_rq(ch, r, err); +} + +static void s3c_pl330_rq1(void *token, enum pl330_op_err err) +{ + struct pl330_req *r = token; + struct s3c_pl330_chan *ch = container_of(r, + struct s3c_pl330_chan, req[1]); + s3c_pl330_rq(ch, r, err); +} + +/* Release an acquired channel */ +static void chan_release(struct s3c_pl330_chan *ch) +{ + struct s3c_pl330_dmac *dmac; + + if (chan_free(ch)) + return; + + dmac = ch->dmac; + ch->dmac = NULL; + dmac->busy_chan--; +} + +int s3c2410_dma_ctrl(enum dma_ch id, enum s3c2410_chan_op op) +{ + struct s3c_pl330_xfer *xfer; + enum pl330_chan_op pl330op; + struct s3c_pl330_chan *ch; + unsigned long flags; + int idx, ret; + + spin_lock_irqsave(&res_lock, flags); + + ch = id_to_chan(id); + + if (!ch || chan_free(ch)) { + ret = -EINVAL; + goto ctrl_exit; + } + + switch (op) { + case S3C2410_DMAOP_START: + /* Make sure both reqs are enqueued */ + idx = (ch->lrq == &ch->req[0]) ? 1 : 0; + s3c_pl330_submit(ch, &ch->req[idx]); + s3c_pl330_submit(ch, &ch->req[1 - idx]); + pl330op = PL330_OP_START; + break; + + case S3C2410_DMAOP_STOP: + pl330op = PL330_OP_ABORT; + break; + + case S3C2410_DMAOP_FLUSH: + pl330op = PL330_OP_FLUSH; + break; + + case S3C2410_DMAOP_PAUSE: + case S3C2410_DMAOP_RESUME: + case S3C2410_DMAOP_TIMEOUT: + case S3C2410_DMAOP_STARTED: + spin_unlock_irqrestore(&res_lock, flags); + return 0; + + default: + spin_unlock_irqrestore(&res_lock, flags); + return -EINVAL; + } + + ret = pl330_chan_ctrl(ch->pl330_chan_id, pl330op); + + if (pl330op == PL330_OP_START) { + spin_unlock_irqrestore(&res_lock, flags); + return ret; + } + + idx = (ch->lrq == &ch->req[0]) ? 1 : 0; + + /* Abort the current xfer */ + if (ch->req[idx].x) { + xfer = container_of(ch->req[idx].x, + struct s3c_pl330_xfer, px); + + /* Drop xfer during FLUSH */ + if (pl330op == PL330_OP_FLUSH) + del_from_queue(xfer); + + ch->req[idx].x = NULL; + + spin_unlock_irqrestore(&res_lock, flags); + _finish_off(xfer, S3C2410_RES_ABORT, + pl330op == PL330_OP_FLUSH ? 1 : 0); + spin_lock_irqsave(&res_lock, flags); + } + + /* Flush the whole queue */ + if (pl330op == PL330_OP_FLUSH) { + + if (ch->req[1 - idx].x) { + xfer = container_of(ch->req[1 - idx].x, + struct s3c_pl330_xfer, px); + + del_from_queue(xfer); + + ch->req[1 - idx].x = NULL; + + spin_unlock_irqrestore(&res_lock, flags); + _finish_off(xfer, S3C2410_RES_ABORT, 1); + spin_lock_irqsave(&res_lock, flags); + } + + /* Finish off the remaining in the queue */ + xfer = ch->xfer_head; + while (xfer) { + + del_from_queue(xfer); + + spin_unlock_irqrestore(&res_lock, flags); + _finish_off(xfer, S3C2410_RES_ABORT, 1); + spin_lock_irqsave(&res_lock, flags); + + xfer = ch->xfer_head; + } + } + +ctrl_exit: + spin_unlock_irqrestore(&res_lock, flags); + + return ret; +} +EXPORT_SYMBOL(s3c2410_dma_ctrl); + +int s3c2410_dma_enqueue(enum dma_ch id, void *token, + dma_addr_t addr, int size) +{ + struct s3c_pl330_chan *ch; + struct s3c_pl330_xfer *xfer; + unsigned long flags; + int idx, ret = 0; + + spin_lock_irqsave(&res_lock, flags); + + ch = id_to_chan(id); + + /* Error if invalid or free channel */ + if (!ch || chan_free(ch)) { + ret = -EINVAL; + goto enq_exit; + } + + /* Error if size is unaligned */ + if (ch->rqcfg.brst_size && size % (1 << ch->rqcfg.brst_size)) { + ret = -EINVAL; + goto enq_exit; + } + + xfer = kmem_cache_alloc(ch->dmac->kmcache, GFP_ATOMIC); + if (!xfer) { + ret = -ENOMEM; + goto enq_exit; + } + + xfer->token = token; + xfer->chan = ch; + xfer->px.bytes = size; + xfer->px.next = NULL; /* Single request */ + + /* For S3C DMA API, direction is always fixed for all xfers */ + if (ch->req[0].rqtype == MEMTODEV) { + xfer->px.src_addr = addr; + xfer->px.dst_addr = ch->sdaddr; + } else { + xfer->px.src_addr = ch->sdaddr; + xfer->px.dst_addr = addr; + } + + add_to_queue(ch, xfer, 0); + + /* Try submitting on either request */ + idx = (ch->lrq == &ch->req[0]) ? 1 : 0; + + if (!ch->req[idx].x) + s3c_pl330_submit(ch, &ch->req[idx]); + else + s3c_pl330_submit(ch, &ch->req[1 - idx]); + + spin_unlock_irqrestore(&res_lock, flags); + + if (ch->options & S3C2410_DMAF_AUTOSTART) + s3c2410_dma_ctrl(id, S3C2410_DMAOP_START); + + return 0; + +enq_exit: + spin_unlock_irqrestore(&res_lock, flags); + + return ret; +} +EXPORT_SYMBOL(s3c2410_dma_enqueue); + +int s3c2410_dma_request(enum dma_ch id, + struct s3c2410_dma_client *client, + void *dev) +{ + struct s3c_pl330_dmac *dmac; + struct s3c_pl330_chan *ch; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&res_lock, flags); + + ch = chan_acquire(id); + if (!ch) { + ret = -EBUSY; + goto req_exit; + } + + dmac = ch->dmac; + + ch->pl330_chan_id = pl330_request_channel(dmac->pi); + if (!ch->pl330_chan_id) { + chan_release(ch); + ret = -EBUSY; + goto req_exit; + } + + ch->client = client; + ch->options = 0; /* Clear any option */ + ch->callback_fn = NULL; /* Clear any callback */ + ch->lrq = NULL; + + ch->rqcfg.brst_size = 2; /* Default word size */ + ch->rqcfg.swap = SWAP_NO; + ch->rqcfg.scctl = SCCTRL0; /* Noncacheable and nonbufferable */ + ch->rqcfg.dcctl = DCCTRL0; /* Noncacheable and nonbufferable */ + ch->rqcfg.privileged = 0; + ch->rqcfg.insnaccess = 0; + + /* Set invalid direction */ + ch->req[0].rqtype = DEVTODEV; + ch->req[1].rqtype = ch->req[0].rqtype; + + ch->req[0].cfg = &ch->rqcfg; + ch->req[1].cfg = ch->req[0].cfg; + + ch->req[0].peri = iface_of_dmac(dmac, id) - 1; /* Original index */ + ch->req[1].peri = ch->req[0].peri; + + ch->req[0].token = &ch->req[0]; + ch->req[0].xfer_cb = s3c_pl330_rq0; + ch->req[1].token = &ch->req[1]; + ch->req[1].xfer_cb = s3c_pl330_rq1; + + ch->req[0].x = NULL; + ch->req[1].x = NULL; + + /* Reset xfer list */ + INIT_LIST_HEAD(&ch->xfer_list); + ch->xfer_head = NULL; + +req_exit: + spin_unlock_irqrestore(&res_lock, flags); + + return ret; +} +EXPORT_SYMBOL(s3c2410_dma_request); + +int s3c2410_dma_free(enum dma_ch id, struct s3c2410_dma_client *client) +{ + struct s3c_pl330_chan *ch; + struct s3c_pl330_xfer *xfer; + unsigned long flags; + int ret = 0; + unsigned idx; + + spin_lock_irqsave(&res_lock, flags); + + ch = id_to_chan(id); + + if (!ch || chan_free(ch)) + goto free_exit; + + /* Refuse if someone else wanted to free the channel */ + if (ch->client != client) { + ret = -EBUSY; + goto free_exit; + } + + /* Stop any active xfer, Flushe the queue and do callbacks */ + pl330_chan_ctrl(ch->pl330_chan_id, PL330_OP_FLUSH); + + /* Abort the submitted requests */ + idx = (ch->lrq == &ch->req[0]) ? 1 : 0; + + if (ch->req[idx].x) { + xfer = container_of(ch->req[idx].x, + struct s3c_pl330_xfer, px); + + ch->req[idx].x = NULL; + del_from_queue(xfer); + + spin_unlock_irqrestore(&res_lock, flags); + _finish_off(xfer, S3C2410_RES_ABORT, 1); + spin_lock_irqsave(&res_lock, flags); + } + + if (ch->req[1 - idx].x) { + xfer = container_of(ch->req[1 - idx].x, + struct s3c_pl330_xfer, px); + + ch->req[1 - idx].x = NULL; + del_from_queue(xfer); + + spin_unlock_irqrestore(&res_lock, flags); + _finish_off(xfer, S3C2410_RES_ABORT, 1); + spin_lock_irqsave(&res_lock, flags); + } + + /* Pluck and Abort the queued requests in order */ + do { + xfer = get_from_queue(ch, 1); + + spin_unlock_irqrestore(&res_lock, flags); + _finish_off(xfer, S3C2410_RES_ABORT, 1); + spin_lock_irqsave(&res_lock, flags); + } while (xfer); + + ch->client = NULL; + + pl330_release_channel(ch->pl330_chan_id); + + ch->pl330_chan_id = NULL; + + chan_release(ch); + +free_exit: + spin_unlock_irqrestore(&res_lock, flags); + + return ret; +} +EXPORT_SYMBOL(s3c2410_dma_free); + +int s3c2410_dma_config(enum dma_ch id, int xferunit) +{ + struct s3c_pl330_chan *ch; + struct pl330_info *pi; + unsigned long flags; + int i, dbwidth, ret = 0; + + spin_lock_irqsave(&res_lock, flags); + + ch = id_to_chan(id); + + if (!ch || chan_free(ch)) { + ret = -EINVAL; + goto cfg_exit; + } + + pi = ch->dmac->pi; + dbwidth = pi->pcfg.data_bus_width / 8; + + /* Max size of xfer can be pcfg.data_bus_width */ + if (xferunit > dbwidth) { + ret = -EINVAL; + goto cfg_exit; + } + + i = 0; + while (xferunit != (1 << i)) + i++; + + /* If valid value */ + if (xferunit == (1 << i)) + ch->rqcfg.brst_size = i; + else + ret = -EINVAL; + +cfg_exit: + spin_unlock_irqrestore(&res_lock, flags); + + return ret; +} +EXPORT_SYMBOL(s3c2410_dma_config); + +/* Options that are supported by this driver */ +#define S3C_PL330_FLAGS (S3C2410_DMAF_CIRCULAR | S3C2410_DMAF_AUTOSTART) + +int s3c2410_dma_setflags(enum dma_ch id, unsigned int options) +{ + struct s3c_pl330_chan *ch; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&res_lock, flags); + + ch = id_to_chan(id); + + if (!ch || chan_free(ch) || options & ~(S3C_PL330_FLAGS)) + ret = -EINVAL; + else + ch->options = options; + + spin_unlock_irqrestore(&res_lock, flags); + + return 0; +} +EXPORT_SYMBOL(s3c2410_dma_setflags); + +int s3c2410_dma_set_buffdone_fn(enum dma_ch id, s3c2410_dma_cbfn_t rtn) +{ + struct s3c_pl330_chan *ch; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&res_lock, flags); + + ch = id_to_chan(id); + + if (!ch || chan_free(ch)) + ret = -EINVAL; + else + ch->callback_fn = rtn; + + spin_unlock_irqrestore(&res_lock, flags); + + return ret; +} +EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn); + +int s3c2410_dma_devconfig(enum dma_ch id, enum s3c2410_dmasrc source, + unsigned long address) +{ + struct s3c_pl330_chan *ch; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&res_lock, flags); + + ch = id_to_chan(id); + + if (!ch || chan_free(ch)) { + ret = -EINVAL; + goto devcfg_exit; + } + + switch (source) { + case S3C2410_DMASRC_HW: /* P->M */ + ch->req[0].rqtype = DEVTOMEM; + ch->req[1].rqtype = DEVTOMEM; + ch->rqcfg.src_inc = 0; + ch->rqcfg.dst_inc = 1; + break; + case S3C2410_DMASRC_MEM: /* M->P */ + ch->req[0].rqtype = MEMTODEV; + ch->req[1].rqtype = MEMTODEV; + ch->rqcfg.src_inc = 1; + ch->rqcfg.dst_inc = 0; + break; + default: + ret = -EINVAL; + goto devcfg_exit; + } + + ch->sdaddr = address; + +devcfg_exit: + spin_unlock_irqrestore(&res_lock, flags); + + return ret; +} +EXPORT_SYMBOL(s3c2410_dma_devconfig); + +int s3c2410_dma_getposition(enum dma_ch id, dma_addr_t *src, dma_addr_t *dst) +{ + struct s3c_pl330_chan *ch = id_to_chan(id); + struct pl330_chanstatus status; + int ret; + + if (!ch || chan_free(ch)) + return -EINVAL; + + ret = pl330_chan_status(ch->pl330_chan_id, &status); + if (ret < 0) + return ret; + + *src = status.src_addr; + *dst = status.dst_addr; + + return 0; +} +EXPORT_SYMBOL(s3c2410_dma_getposition); + +static irqreturn_t pl330_irq_handler(int irq, void *data) +{ + if (pl330_update(data)) + return IRQ_HANDLED; + else + return IRQ_NONE; +} + +static int pl330_probe(struct platform_device *pdev) +{ + struct s3c_pl330_dmac *s3c_pl330_dmac; + struct s3c_pl330_platdata *pl330pd; + struct pl330_info *pl330_info; + struct resource *res; + int i, ret, irq; + + pl330pd = pdev->dev.platform_data; + + /* Can't do without the list of _32_ peripherals */ + if (!pl330pd || !pl330pd->peri) { + dev_err(&pdev->dev, "platform data missing!\n"); + return -ENODEV; + } + + pl330_info = kzalloc(sizeof(*pl330_info), GFP_KERNEL); + if (!pl330_info) + return -ENOMEM; + + pl330_info->pl330_data = NULL; + pl330_info->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENODEV; + goto probe_err1; + } + + request_mem_region(res->start, resource_size(res), pdev->name); + + pl330_info->base = ioremap(res->start, resource_size(res)); + if (!pl330_info->base) { + ret = -ENXIO; + goto probe_err2; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + ret = irq; + goto probe_err3; + } + + ret = request_irq(irq, pl330_irq_handler, 0, + dev_name(&pdev->dev), pl330_info); + if (ret) + goto probe_err4; + + ret = pl330_add(pl330_info); + if (ret) + goto probe_err5; + + /* Allocate a new DMAC */ + s3c_pl330_dmac = kmalloc(sizeof(*s3c_pl330_dmac), GFP_KERNEL); + if (!s3c_pl330_dmac) { + ret = -ENOMEM; + goto probe_err6; + } + + /* Hook the info */ + s3c_pl330_dmac->pi = pl330_info; + + /* No busy channels */ + s3c_pl330_dmac->busy_chan = 0; + + s3c_pl330_dmac->kmcache = kmem_cache_create(dev_name(&pdev->dev), + sizeof(struct s3c_pl330_xfer), 0, 0, NULL); + + if (!s3c_pl330_dmac->kmcache) { + ret = -ENOMEM; + goto probe_err7; + } + + /* Get the list of peripherals */ + s3c_pl330_dmac->peri = pl330pd->peri; + + /* Attach to the list of DMACs */ + list_add_tail(&s3c_pl330_dmac->node, &dmac_list); + + /* Create a channel for each peripheral in the DMAC + * that is, if it doesn't already exist + */ + for (i = 0; i < PL330_MAX_PERI; i++) + if (s3c_pl330_dmac->peri[i] != DMACH_MAX) + chan_add(s3c_pl330_dmac->peri[i]); + + printk(KERN_INFO + "Loaded driver for PL330 DMAC-%d %s\n", pdev->id, pdev->name); + printk(KERN_INFO + "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", + pl330_info->pcfg.data_buf_dep, + pl330_info->pcfg.data_bus_width / 8, pl330_info->pcfg.num_chan, + pl330_info->pcfg.num_peri, pl330_info->pcfg.num_events); + + return 0; + +probe_err7: + kfree(s3c_pl330_dmac); +probe_err6: + pl330_del(pl330_info); +probe_err5: + free_irq(irq, pl330_info); +probe_err4: +probe_err3: + iounmap(pl330_info->base); +probe_err2: + release_mem_region(res->start, resource_size(res)); +probe_err1: + kfree(pl330_info); + + return ret; +} + +static int pl330_remove(struct platform_device *pdev) +{ + struct s3c_pl330_dmac *dmac, *d; + struct s3c_pl330_chan *ch; + unsigned long flags; + int del, found; + + if (!pdev->dev.platform_data) + return -EINVAL; + + spin_lock_irqsave(&res_lock, flags); + + found = 0; + list_for_each_entry(d, &dmac_list, node) + if (d->pi->dev == &pdev->dev) { + found = 1; + break; + } + + if (!found) { + spin_unlock_irqrestore(&res_lock, flags); + return 0; + } + + dmac = d; + + /* Remove all Channels that are managed only by this DMAC */ + list_for_each_entry(ch, &chan_list, node) { + + /* Only channels that are handled by this DMAC */ + if (iface_of_dmac(dmac, ch->id)) + del = 1; + else + continue; + + /* Don't remove if some other DMAC has it too */ + list_for_each_entry(d, &dmac_list, node) + if (d != dmac && iface_of_dmac(d, ch->id)) { + del = 0; + break; + } + + if (del) { + spin_unlock_irqrestore(&res_lock, flags); + s3c2410_dma_free(ch->id, ch->client); + spin_lock_irqsave(&res_lock, flags); + list_del(&ch->node); + kfree(ch); + } + } + + /* Remove the DMAC */ + list_del(&dmac->node); + kfree(dmac); + + spin_unlock_irqrestore(&res_lock, flags); + + return 0; +} + +static struct platform_driver pl330_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "s3c-pl330", + }, + .probe = pl330_probe, + .remove = pl330_remove, +}; + +static int __init pl330_init(void) +{ + return platform_driver_register(&pl330_driver); +} +module_init(pl330_init); + +static void __exit pl330_exit(void) +{ + platform_driver_unregister(&pl330_driver); + return; +} +module_exit(pl330_exit); + +MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); +MODULE_DESCRIPTION("Driver for PL330 DMA Controller"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig new file mode 100644 index 00000000000..1bb3dbce881 --- /dev/null +++ b/arch/arm/plat-spear/Kconfig @@ -0,0 +1,31 @@ +# +# SPEAr Platform configuration file +# + +if PLAT_SPEAR + +choice + prompt "ST SPEAr Family" + default ARCH_SPEAR3XX + +config ARCH_SPEAR3XX + bool "SPEAr3XX" + select ARM_VIC + select CPU_ARM926T + help + Supports for ARM's SPEAR3XX family + +config ARCH_SPEAR6XX + bool "SPEAr6XX" + select ARM_VIC + select CPU_ARM926T + help + Supports for ARM's SPEAR6XX family + +endchoice + +# Adding SPEAr machine specific configuration files +source "arch/arm/mach-spear3xx/Kconfig" +source "arch/arm/mach-spear6xx/Kconfig" + +endif diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile new file mode 100644 index 00000000000..eb89540aeda --- /dev/null +++ b/arch/arm/plat-spear/Makefile @@ -0,0 +1,8 @@ +# +# SPEAr Platform specific Makefile +# + +# Common support +obj-y := clock.o padmux.o time.o + +obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c new file mode 100644 index 00000000000..ee4f90e534d --- /dev/null +++ b/arch/arm/plat-spear/clock.c @@ -0,0 +1,435 @@ +/* + * arch/arm/plat-spear/clock.c + * + * Clock framework for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/bug.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/spinlock.h> +#include <mach/misc_regs.h> +#include <plat/clock.h> + +static DEFINE_SPINLOCK(clocks_lock); +static LIST_HEAD(root_clks); + +static void propagate_rate(struct list_head *); + +static int generic_clk_enable(struct clk *clk) +{ + unsigned int val; + + if (!clk->en_reg) + return -EFAULT; + + val = readl(clk->en_reg); + if (unlikely(clk->flags & RESET_TO_ENABLE)) + val &= ~(1 << clk->en_reg_bit); + else + val |= 1 << clk->en_reg_bit; + + writel(val, clk->en_reg); + + return 0; +} + +static void generic_clk_disable(struct clk *clk) +{ + unsigned int val; + + if (!clk->en_reg) + return; + + val = readl(clk->en_reg); + if (unlikely(clk->flags & RESET_TO_ENABLE)) + val |= 1 << clk->en_reg_bit; + else + val &= ~(1 << clk->en_reg_bit); + + writel(val, clk->en_reg); +} + +/* generic clk ops */ +static struct clkops generic_clkops = { + .enable = generic_clk_enable, + .disable = generic_clk_disable, +}; + +/* + * clk_enable - inform the system when the clock source should be running. + * @clk: clock source + * + * If the clock can not be enabled/disabled, this should return success. + * + * Returns success (0) or negative errno. + */ +int clk_enable(struct clk *clk) +{ + unsigned long flags; + int ret = 0; + + if (!clk || IS_ERR(clk)) + return -EFAULT; + + spin_lock_irqsave(&clocks_lock, flags); + if (clk->usage_count == 0) { + if (clk->ops && clk->ops->enable) + ret = clk->ops->enable(clk); + } + clk->usage_count++; + spin_unlock_irqrestore(&clocks_lock, flags); + + return ret; +} +EXPORT_SYMBOL(clk_enable); + +/* + * clk_disable - inform the system when the clock source is no longer required. + * @clk: clock source + * + * Inform the system that a clock source is no longer required by + * a driver and may be shut down. + * + * Implementation detail: if the clock source is shared between + * multiple drivers, clk_enable() calls must be balanced by the + * same number of clk_disable() calls for the clock source to be + * disabled. + */ +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + if (!clk || IS_ERR(clk)) + return; + + WARN_ON(clk->usage_count == 0); + + spin_lock_irqsave(&clocks_lock, flags); + clk->usage_count--; + if (clk->usage_count == 0) { + if (clk->ops && clk->ops->disable) + clk->ops->disable(clk); + } + spin_unlock_irqrestore(&clocks_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +/** + * clk_get_rate - obtain the current clock rate (in Hz) for a clock source. + * This is only valid once the clock source has been enabled. + * @clk: clock source + */ +unsigned long clk_get_rate(struct clk *clk) +{ + unsigned long flags, rate; + + spin_lock_irqsave(&clocks_lock, flags); + rate = clk->rate; + spin_unlock_irqrestore(&clocks_lock, flags); + + return rate; +} +EXPORT_SYMBOL(clk_get_rate); + +/** + * clk_set_parent - set the parent clock source for this clock + * @clk: clock source + * @parent: parent clock source + * + * Returns success (0) or negative errno. + */ +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int i, found = 0, val = 0; + unsigned long flags; + + if (!clk || IS_ERR(clk) || !parent || IS_ERR(parent)) + return -EFAULT; + if (clk->usage_count) + return -EBUSY; + if (!clk->pclk_sel) + return -EPERM; + if (clk->pclk == parent) + return 0; + + for (i = 0; i < clk->pclk_sel->pclk_count; i++) { + if (clk->pclk_sel->pclk_info[i].pclk == parent) { + found = 1; + break; + } + } + + if (!found) + return -EINVAL; + + spin_lock_irqsave(&clocks_lock, flags); + /* reflect parent change in hardware */ + val = readl(clk->pclk_sel->pclk_sel_reg); + val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift); + val |= clk->pclk_sel->pclk_info[i].pclk_mask << clk->pclk_sel_shift; + writel(val, clk->pclk_sel->pclk_sel_reg); + spin_unlock_irqrestore(&clocks_lock, flags); + + /* reflect parent change in software */ + clk->recalc(clk); + propagate_rate(&clk->children); + return 0; +} +EXPORT_SYMBOL(clk_set_parent); + +/* registers clock in platform clock framework */ +void clk_register(struct clk_lookup *cl) +{ + struct clk *clk = cl->clk; + unsigned long flags; + + if (!clk || IS_ERR(clk)) + return; + + spin_lock_irqsave(&clocks_lock, flags); + + INIT_LIST_HEAD(&clk->children); + if (clk->flags & ALWAYS_ENABLED) + clk->ops = NULL; + else if (!clk->ops) + clk->ops = &generic_clkops; + + /* root clock don't have any parents */ + if (!clk->pclk && !clk->pclk_sel) { + list_add(&clk->sibling, &root_clks); + /* add clocks with only one parent to parent's children list */ + } else if (clk->pclk && !clk->pclk_sel) { + list_add(&clk->sibling, &clk->pclk->children); + } else { + /* add clocks with > 1 parent to 1st parent's children list */ + list_add(&clk->sibling, + &clk->pclk_sel->pclk_info[0].pclk->children); + } + spin_unlock_irqrestore(&clocks_lock, flags); + + /* add clock to arm clockdev framework */ + clkdev_add(cl); +} + +/** + * propagate_rate - recalculate and propagate all clocks in list head + * + * Recalculates all root clocks in list head, which if the clock's .recalc is + * set correctly, should also propagate their rates. + */ +static void propagate_rate(struct list_head *lhead) +{ + struct clk *clkp, *_temp; + + list_for_each_entry_safe(clkp, _temp, lhead, sibling) { + if (clkp->recalc) + clkp->recalc(clkp); + propagate_rate(&clkp->children); + } +} + +/* returns current programmed clocks clock info structure */ +static struct pclk_info *pclk_info_get(struct clk *clk) +{ + unsigned int mask, i; + unsigned long flags; + struct pclk_info *info = NULL; + + spin_lock_irqsave(&clocks_lock, flags); + mask = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift) + & clk->pclk_sel->pclk_sel_mask; + + for (i = 0; i < clk->pclk_sel->pclk_count; i++) { + if (clk->pclk_sel->pclk_info[i].pclk_mask == mask) + info = &clk->pclk_sel->pclk_info[i]; + } + spin_unlock_irqrestore(&clocks_lock, flags); + + return info; +} + +/* + * Set pclk as cclk's parent and add clock sibling node to current parents + * children list + */ +static void change_parent(struct clk *cclk, struct clk *pclk) +{ + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + list_del(&cclk->sibling); + list_add(&cclk->sibling, &pclk->children); + + cclk->pclk = pclk; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/* + * calculates current programmed rate of pll1 + * + * In normal mode + * rate = (2 * M[15:8] * Fin)/(N * 2^P) + * + * In Dithered mode + * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P) + */ +void pll1_clk_recalc(struct clk *clk) +{ + struct pll_clk_config *config = clk->private_data; + unsigned int num = 2, den = 0, val, mode = 0; + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) & + PLL_MODE_MASK; + + val = readl(config->cfg_reg); + /* calculate denominator */ + den = (val >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK; + den = 1 << den; + den *= (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK; + + /* calculate numerator & denominator */ + if (!mode) { + /* Normal mode */ + num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK; + } else { + /* Dithered mode */ + num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK; + den *= 256; + } + + clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/* calculates current programmed rate of ahb or apb bus */ +void bus_clk_recalc(struct clk *clk) +{ + struct bus_clk_config *config = clk->private_data; + unsigned int div; + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + div = ((readl(config->reg) >> config->shift) & config->mask) + 1; + clk->rate = (unsigned long)clk->pclk->rate / div; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/* + * calculates current programmed rate of auxiliary synthesizers + * used by: UART, FIRDA + * + * Fout from synthesizer can be given from two equations: + * Fout1 = (Fin * X/Y)/2 + * Fout2 = Fin * X/Y + * + * Selection of eqn 1 or 2 is programmed in register + */ +void aux_clk_recalc(struct clk *clk) +{ + struct aux_clk_config *config = clk->private_data; + struct pclk_info *pclk_info = NULL; + unsigned int num = 1, den = 1, val, eqn; + unsigned long flags; + + /* get current programmed parent */ + pclk_info = pclk_info_get(clk); + if (!pclk_info) { + spin_lock_irqsave(&clocks_lock, flags); + clk->pclk = NULL; + clk->rate = 0; + spin_unlock_irqrestore(&clocks_lock, flags); + return; + } + + change_parent(clk, pclk_info->pclk); + + spin_lock_irqsave(&clocks_lock, flags); + if (pclk_info->scalable) { + val = readl(config->synth_reg); + + eqn = (val >> AUX_EQ_SEL_SHIFT) & AUX_EQ_SEL_MASK; + if (eqn == AUX_EQ1_SEL) + den *= 2; + + /* calculate numerator */ + num = (val >> AUX_XSCALE_SHIFT) & AUX_XSCALE_MASK; + + /* calculate denominator */ + den *= (val >> AUX_YSCALE_SHIFT) & AUX_YSCALE_MASK; + val = (((clk->pclk->rate/10000) * num) / den) * 10000; + } else + val = clk->pclk->rate; + + clk->rate = val; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/* + * calculates current programmed rate of gpt synthesizers + * Fout from synthesizer can be given from below equations: + * Fout= Fin/((2 ^ (N+1)) * (M+1)) + */ +void gpt_clk_recalc(struct clk *clk) +{ + struct aux_clk_config *config = clk->private_data; + struct pclk_info *pclk_info = NULL; + unsigned int div = 1, val; + unsigned long flags; + + pclk_info = pclk_info_get(clk); + if (!pclk_info) { + spin_lock_irqsave(&clocks_lock, flags); + clk->pclk = NULL; + clk->rate = 0; + spin_unlock_irqrestore(&clocks_lock, flags); + return; + } + + change_parent(clk, pclk_info->pclk); + + spin_lock_irqsave(&clocks_lock, flags); + if (pclk_info->scalable) { + val = readl(config->synth_reg); + div += (val >> GPT_MSCALE_SHIFT) & GPT_MSCALE_MASK; + div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1); + } + + clk->rate = (unsigned long)clk->pclk->rate / div; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/* + * Used for clocks that always have same value as the parent clock divided by a + * fixed divisor + */ +void follow_parent(struct clk *clk) +{ + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + clk->rate = clk->pclk->rate; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/** + * recalc_root_clocks - recalculate and propagate all root clocks + * + * Recalculates all root clocks (clocks with no parent), which if the + * clock's .recalc is set correctly, should also propagate their rates. + */ +void recalc_root_clocks(void) +{ + propagate_rate(&root_clks); +} diff --git a/arch/arm/plat-spear/include/plat/clkdev.h b/arch/arm/plat-spear/include/plat/clkdev.h new file mode 100644 index 00000000000..a2d0112fcaf --- /dev/null +++ b/arch/arm/plat-spear/include/plat/clkdev.h @@ -0,0 +1,20 @@ +/* + * arch/arm/plat-spear/include/plat/clkdev.h + * + * Clock Dev framework definitions for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_CLKDEV_H +#define __PLAT_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif /* __PLAT_CLKDEV_H */ diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h new file mode 100644 index 00000000000..298bafc0a52 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/clock.h @@ -0,0 +1,126 @@ +/* + * arch/arm/plat-spear/include/plat/clock.h + * + * Clock framework definitions for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_CLOCK_H +#define __PLAT_CLOCK_H + +#include <linux/list.h> +#include <asm/clkdev.h> +#include <linux/types.h> + +/* clk structure flags */ +#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */ +#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */ + +/** + * struct clkops - clock operations + * @enable: pointer to clock enable function + * @disable: pointer to clock disable function + */ +struct clkops { + int (*enable) (struct clk *); + void (*disable) (struct clk *); +}; + +/** + * struct pclk_info - parents info + * @pclk: pointer to parent clk + * @pclk_mask: value to be written for selecting this parent + * @scalable: Is parent scalable (1 - YES, 0 - NO) + */ +struct pclk_info { + struct clk *pclk; + u8 pclk_mask; + u8 scalable; +}; + +/** + * struct pclk_sel - parents selection configuration + * @pclk_info: pointer to array of parent clock info + * @pclk_count: number of parents + * @pclk_sel_reg: register for selecting a parent + * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also) + */ +struct pclk_sel { + struct pclk_info *pclk_info; + u8 pclk_count; + unsigned int *pclk_sel_reg; + unsigned int pclk_sel_mask; +}; + +/** + * struct clk - clock structure + * @usage_count: num of users who enabled this clock + * @flags: flags for clock properties + * @rate: programmed clock rate in Hz + * @en_reg: clk enable/disable reg + * @en_reg_bit: clk enable/disable bit + * @ops: clk enable/disable ops - generic_clkops selected if NULL + * @recalc: pointer to clock rate recalculate function + * @pclk: current parent clk + * @pclk_sel: pointer to parent selection structure + * @pclk_sel_shift: register shift for selecting parent of this clock + * @children: list for childrens or this clock + * @sibling: node for list of clocks having same parents + * @private_data: clock specific private data + */ +struct clk { + unsigned int usage_count; + unsigned int flags; + unsigned long rate; + unsigned int *en_reg; + u8 en_reg_bit; + const struct clkops *ops; + void (*recalc) (struct clk *); + + struct clk *pclk; + struct pclk_sel *pclk_sel; + unsigned int pclk_sel_shift; + + struct list_head children; + struct list_head sibling; + void *private_data; +}; + +/* pll configuration structure */ +struct pll_clk_config { + unsigned int *mode_reg; + unsigned int *cfg_reg; +}; + +/* ahb and apb bus configuration structure */ +struct bus_clk_config { + unsigned int *reg; + unsigned int mask; + unsigned int shift; +}; + +/* + * Aux clk configuration structure: applicable to GPT, UART and FIRDA + */ +struct aux_clk_config { + unsigned int *synth_reg; +}; + +/* platform specific clock functions */ +void clk_register(struct clk_lookup *cl); +void recalc_root_clocks(void); + +/* clock recalc functions */ +void follow_parent(struct clk *clk); +void pll1_clk_recalc(struct clk *clk); +void bus_clk_recalc(struct clk *clk); +void gpt_clk_recalc(struct clk *clk); +void aux_clk_recalc(struct clk *clk); + +#endif /* __PLAT_CLOCK_H */ diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S new file mode 100644 index 00000000000..1670734b7e5 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/debug-macro.S @@ -0,0 +1,38 @@ +/* + * arch/arm/plat-spear/include/plat/debug-macro.S + * + * Debugging macro include header for spear platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/amba/serial.h> +#include <mach/spear.h> + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, =SPEAR_DBG_UART_BASE @ Physical base + movne \rx, =VA_SPEAR_DBG_UART_BASE @ Virtual base + .endm + + .macro senduart, rd, rx + strb \rd, [\rx, #UART01x_DR] @ ASC_TX_BUFFER + .endm + + .macro waituart, rd, rx +1001: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER + tst \rd, #UART01x_FR_TXFF @ TX_FULL + bne 1001b + .endm + + .macro busyuart, rd, rx +1002: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER + tst \rd, #UART011_FR_TXFE @ TX_EMPTY + beq 1002b + .endm diff --git a/arch/arm/plat-spear/include/plat/gpio.h b/arch/arm/plat-spear/include/plat/gpio.h new file mode 100644 index 00000000000..b857c91257d --- /dev/null +++ b/arch/arm/plat-spear/include/plat/gpio.h @@ -0,0 +1,24 @@ +/* + * arch/arm/plat-spear/include/plat/gpio.h + * + * GPIO macros for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_GPIO_H +#define __PLAT_GPIO_H + +#include <asm-generic/gpio.h> + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +#endif /* __PLAT_GPIO_H */ diff --git a/arch/arm/plat-spear/include/plat/io.h b/arch/arm/plat-spear/include/plat/io.h new file mode 100644 index 00000000000..4d4ba822b3e --- /dev/null +++ b/arch/arm/plat-spear/include/plat/io.h @@ -0,0 +1,22 @@ +/* + * arch/arm/plat-spear/include/plat/io.h + * + * IO definitions for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_IO_H +#define __PLAT_IO_H + +#define IO_SPACE_LIMIT 0xFFFFFFFF + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif /* __PLAT_IO_H */ diff --git a/arch/arm/plat-spear/include/plat/memory.h b/arch/arm/plat-spear/include/plat/memory.h new file mode 100644 index 00000000000..27a4aba7734 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/memory.h @@ -0,0 +1,20 @@ +/* + * arch/arm/plat-spear/include/plat/memory.h + * + * Memory map for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_MEMORY_H +#define __PLAT_MEMORY_H + +/* Physical DRAM offset */ +#define PHYS_OFFSET UL(0x00000000) + +#endif /* __PLAT_MEMORY_H */ diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h new file mode 100644 index 00000000000..877f3adcf61 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/padmux.h @@ -0,0 +1,92 @@ +/* + * arch/arm/plat-spear/include/plat/padmux.h + * + * SPEAr platform specific gpio pads muxing file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_PADMUX_H +#define __PLAT_PADMUX_H + +#include <linux/types.h> + +/* + * struct pmx_reg: configuration structure for mode reg and mux reg + * + * offset: offset of mode reg + * mask: mask of mode reg + */ +struct pmx_reg { + u32 offset; + u32 mask; +}; + +/* + * struct pmx_dev_mode: configuration structure every group of modes of a device + * + * ids: all modes for this configuration + * mask: mask for supported mode + */ +struct pmx_dev_mode { + u32 ids; + u32 mask; +}; + +/* + * struct pmx_mode: mode definition structure + * + * name: mode name + * mask: mode mask + */ +struct pmx_mode { + char *name; + u32 id; + u32 mask; +}; + +/* + * struct pmx_dev: device definition structure + * + * name: device name + * modes: device configuration array for different modes supported + * mode_count: size of modes array + * is_active: is peripheral active/enabled + * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg + */ +struct pmx_dev { + char *name; + struct pmx_dev_mode *modes; + u8 mode_count; + bool is_active; + bool enb_on_reset; +}; + +/* + * struct pmx_driver: driver definition structure + * + * mode: mode to be set + * devs: array of pointer to pmx devices + * devs_count: ARRAY_SIZE of devs + * base: base address of soc config registers + * mode_reg: structure of mode config register + * mux_reg: structure of device mux config register + */ +struct pmx_driver { + struct pmx_mode *mode; + struct pmx_dev **devs; + u8 devs_count; + u32 *base; + struct pmx_reg mode_reg; + struct pmx_reg mux_reg; +}; + +/* pmx functions */ +int pmx_register(struct pmx_driver *driver); + +#endif /* __PLAT_PADMUX_H */ diff --git a/arch/arm/plat-spear/include/plat/shirq.h b/arch/arm/plat-spear/include/plat/shirq.h new file mode 100644 index 00000000000..03ed8b585dc --- /dev/null +++ b/arch/arm/plat-spear/include/plat/shirq.h @@ -0,0 +1,73 @@ +/* + * arch/arm/plat-spear/include/plat/shirq.h + * + * SPEAr platform shared irq layer header file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_SHIRQ_H +#define __PLAT_SHIRQ_H + +#include <linux/irq.h> +#include <linux/types.h> + +/* + * struct shirq_dev_config: shared irq device configuration + * + * virq: virtual irq number of device + * enb_mask: enable mask of device + * status_mask: status mask of device + * clear_mask: clear mask of device + */ +struct shirq_dev_config { + u32 virq; + u32 enb_mask; + u32 status_mask; + u32 clear_mask; +}; + +/* + * struct shirq_regs: shared irq register configuration + * + * base: base address of shared irq register + * enb_reg: enable register offset + * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt + * status_reg: status register offset + * status_reg_mask: status register valid mask + * clear_reg: clear register offset + * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt + */ +struct shirq_regs { + void __iomem *base; + u32 enb_reg; + u32 reset_to_enb; + u32 status_reg; + u32 status_reg_mask; + u32 clear_reg; + u32 reset_to_clear; +}; + +/* + * struct spear_shirq: shared irq structure + * + * irq: hardware irq number + * dev_config: array of device config structures which are using "irq" line + * dev_count: size of dev_config array + * regs: register configuration for shared irq block + */ +struct spear_shirq { + u32 irq; + struct shirq_dev_config *dev_config; + u32 dev_count; + struct shirq_regs regs; +}; + +int spear_shirq_register(struct spear_shirq *shirq); + +#endif /* __PLAT_SHIRQ_H */ diff --git a/arch/arm/plat-spear/include/plat/system.h b/arch/arm/plat-spear/include/plat/system.h new file mode 100644 index 00000000000..55a4e405d57 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/system.h @@ -0,0 +1,41 @@ +/* + * arch/arm/plat-spear/include/plat/system.h + * + * SPEAr platform specific architecture functions + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_SYSTEM_H +#define __PLAT_SYSTEM_H + +#include <asm/hardware/sp810.h> +#include <linux/io.h> +#include <mach/spear.h> + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + if (mode == 's') { + /* software reset, Jump into ROM at address 0 */ + cpu_reset(0); + } else { + /* hardware reset, Use on-chip reset capability */ + sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE); + } +} + +#endif /* __PLAT_SYSTEM_H */ diff --git a/arch/arm/plat-spear/include/plat/timex.h b/arch/arm/plat-spear/include/plat/timex.h new file mode 100644 index 00000000000..914d09dd50f --- /dev/null +++ b/arch/arm/plat-spear/include/plat/timex.h @@ -0,0 +1,19 @@ +/* + * arch/arm/plat-spear/include/plat/timex.h + * + * SPEAr platform specific timex definitions + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_TIMEX_H +#define __PLAT_TIMEX_H + +#define CLOCK_TICK_RATE 48000000 + +#endif /* __PLAT_TIMEX_H */ diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h new file mode 100644 index 00000000000..99ba6789cc9 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/uncompress.h @@ -0,0 +1,43 @@ +/* + * arch/arm/plat-spear/include/plat/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/io.h> +#include <linux/amba/serial.h> +#include <mach/spear.h> + +#ifndef __PLAT_UNCOMPRESS_H +#define __PLAT_UNCOMPRESS_H +/* + * This does not append a newline + */ +static inline void putc(int c) +{ + void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE; + + while (readl(base + UART01x_FR) & UART01x_FR_TXFF) + barrier(); + + writel(c, base + UART01x_DR); +} + +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() + +#endif /* __PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-spear/include/plat/vmalloc.h b/arch/arm/plat-spear/include/plat/vmalloc.h new file mode 100644 index 00000000000..09e9372aea2 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/vmalloc.h @@ -0,0 +1,19 @@ +/* + * arch/arm/plat-spear/include/plat/vmalloc.h + * + * Defining Vmalloc area for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_VMALLOC_H +#define __PLAT_VMALLOC_H + +#define VMALLOC_END 0xF0000000 + +#endif /* __PLAT_VMALLOC_H */ diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c new file mode 100644 index 00000000000..d2aab3adcde --- /dev/null +++ b/arch/arm/plat-spear/padmux.c @@ -0,0 +1,164 @@ +/* + * arch/arm/plat-spear/include/plat/padmux.c + * + * SPEAr platform specific gpio pads muxing source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <plat/padmux.h> + +/* + * struct pmx: pmx definition structure + * + * base: base address of configuration registers + * mode_reg: mode configurations + * mux_reg: muxing configurations + * active_mode: pointer to current active mode + */ +struct pmx { + u32 base; + struct pmx_reg mode_reg; + struct pmx_reg mux_reg; + struct pmx_mode *active_mode; +}; + +static struct pmx *pmx; + +/** + * pmx_mode_set - Enables an multiplexing mode + * @mode - pointer to pmx mode + * + * It will set mode of operation in hardware. + * Returns -ve on Err otherwise 0 + */ +static int pmx_mode_set(struct pmx_mode *mode) +{ + u32 val; + + if (!mode->name) + return -EFAULT; + + pmx->active_mode = mode; + + val = readl(pmx->base + pmx->mode_reg.offset); + val &= ~pmx->mode_reg.mask; + val |= mode->mask & pmx->mode_reg.mask; + writel(val, pmx->base + pmx->mode_reg.offset); + + return 0; +} + +/** + * pmx_devs_enable - Enables list of devices + * @devs - pointer to pmx device array + * @count - number of devices to enable + * + * It will enable pads for all required peripherals once and only once. + * If peripheral is not supported by current mode then request is rejected. + * Conflicts between peripherals are not handled and peripherals will be + * enabled in the order they are present in pmx_dev array. + * In case of conflicts last peripheral enalbed will be present. + * Returns -ve on Err otherwise 0 + */ +static int pmx_devs_enable(struct pmx_dev **devs, u8 count) +{ + u32 val, i, mask; + + if (!count) + return -EINVAL; + + val = readl(pmx->base + pmx->mux_reg.offset); + for (i = 0; i < count; i++) { + u8 j = 0; + + if (!devs[i]->name || !devs[i]->modes) { + printk(KERN_ERR "padmux: dev name or modes is null\n"); + continue; + } + /* check if peripheral exists in active mode */ + if (pmx->active_mode) { + bool found = false; + for (j = 0; j < devs[i]->mode_count; j++) { + if (devs[i]->modes[j].ids & + pmx->active_mode->id) { + found = true; + break; + } + } + if (found == false) { + printk(KERN_ERR "%s device not available in %s"\ + "mode\n", devs[i]->name, + pmx->active_mode->name); + continue; + } + } + + /* enable peripheral */ + mask = devs[i]->modes[j].mask & pmx->mux_reg.mask; + if (devs[i]->enb_on_reset) + val &= ~mask; + else + val |= mask; + + devs[i]->is_active = true; + } + writel(val, pmx->base + pmx->mux_reg.offset); + kfree(pmx); + + /* this will ensure that multiplexing can't be changed now */ + pmx = (struct pmx *)-1; + + return 0; +} + +/** + * pmx_register - registers a platform requesting pad mux feature + * @driver - pointer to driver structure containing driver specific parameters + * + * Also this must be called only once. This will allocate memory for pmx + * structure, will call pmx_mode_set, will call pmx_devs_enable. + * Returns -ve on Err otherwise 0 + */ +int pmx_register(struct pmx_driver *driver) +{ + int ret = 0; + + if (pmx) + return -EPERM; + if (!driver->base || !driver->devs) + return -EFAULT; + + pmx = kzalloc(sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->base = (u32)driver->base; + pmx->mode_reg.offset = driver->mode_reg.offset; + pmx->mode_reg.mask = driver->mode_reg.mask; + pmx->mux_reg.offset = driver->mux_reg.offset; + pmx->mux_reg.mask = driver->mux_reg.mask; + + /* choose mode to enable */ + if (driver->mode) { + ret = pmx_mode_set(driver->mode); + if (ret) + goto pmx_fail; + } + ret = pmx_devs_enable(driver->devs, driver->devs_count); + if (ret) + goto pmx_fail; + + return 0; + +pmx_fail: + return ret; +} diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c new file mode 100644 index 00000000000..2172d6946ae --- /dev/null +++ b/arch/arm/plat-spear/shirq.c @@ -0,0 +1,118 @@ +/* + * arch/arm/plat-spear/shirq.c + * + * SPEAr platform shared irq layer source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/spinlock.h> +#include <plat/shirq.h> + +struct spear_shirq *shirq; +static DEFINE_SPINLOCK(lock); + +static void shirq_irq_mask(unsigned irq) +{ + struct spear_shirq *shirq = get_irq_chip_data(irq); + u32 val, id = irq - shirq->dev_config[0].virq; + unsigned long flags; + + if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1) + return; + + spin_lock_irqsave(&lock, flags); + val = readl(shirq->regs.base + shirq->regs.enb_reg); + if (shirq->regs.reset_to_enb) + val |= shirq->dev_config[id].enb_mask; + else + val &= ~(shirq->dev_config[id].enb_mask); + writel(val, shirq->regs.base + shirq->regs.enb_reg); + spin_unlock_irqrestore(&lock, flags); +} + +static void shirq_irq_unmask(unsigned irq) +{ + struct spear_shirq *shirq = get_irq_chip_data(irq); + u32 val, id = irq - shirq->dev_config[0].virq; + unsigned long flags; + + if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1) + return; + + spin_lock_irqsave(&lock, flags); + val = readl(shirq->regs.base + shirq->regs.enb_reg); + if (shirq->regs.reset_to_enb) + val &= ~(shirq->dev_config[id].enb_mask); + else + val |= shirq->dev_config[id].enb_mask; + writel(val, shirq->regs.base + shirq->regs.enb_reg); + spin_unlock_irqrestore(&lock, flags); +} + +static struct irq_chip shirq_chip = { + .name = "spear_shirq", + .ack = shirq_irq_mask, + .mask = shirq_irq_mask, + .unmask = shirq_irq_unmask, +}; + +static void shirq_handler(unsigned irq, struct irq_desc *desc) +{ + u32 i, val, mask; + struct spear_shirq *shirq = get_irq_data(irq); + + desc->chip->ack(irq); + while ((val = readl(shirq->regs.base + shirq->regs.status_reg) & + shirq->regs.status_reg_mask)) { + for (i = 0; (i < shirq->dev_count) && val; i++) { + if (!(shirq->dev_config[i].status_mask & val)) + continue; + + generic_handle_irq(shirq->dev_config[i].virq); + + /* clear interrupt */ + val &= ~shirq->dev_config[i].status_mask; + if ((shirq->regs.clear_reg == -1) || + shirq->dev_config[i].clear_mask == -1) + continue; + mask = readl(shirq->regs.base + shirq->regs.clear_reg); + if (shirq->regs.reset_to_clear) + mask &= ~shirq->dev_config[i].clear_mask; + else + mask |= shirq->dev_config[i].clear_mask; + writel(mask, shirq->regs.base + shirq->regs.clear_reg); + } + } + desc->chip->unmask(irq); +} + +int spear_shirq_register(struct spear_shirq *shirq) +{ + int i; + + if (!shirq || !shirq->dev_config || !shirq->regs.base) + return -EFAULT; + + if (!shirq->dev_count) + return -EINVAL; + + set_irq_chained_handler(shirq->irq, shirq_handler); + for (i = 0; i < shirq->dev_count; i++) { + set_irq_chip(shirq->dev_config[i].virq, &shirq_chip); + set_irq_handler(shirq->dev_config[i].virq, handle_simple_irq); + set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID); + set_irq_chip_data(shirq->dev_config[i].virq, shirq); + } + + set_irq_data(shirq->irq, shirq); + return 0; +} diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c new file mode 100644 index 00000000000..a1025d38f38 --- /dev/null +++ b/arch/arm/plat-spear/time.c @@ -0,0 +1,292 @@ +/* + * arch/arm/plat-spear/time.c + * + * Copyright (C) 2009 ST Microelectronics + * Shiraz Hashim<shiraz.hashim@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/clk.h> +#include <linux/clockchips.h> +#include <linux/clocksource.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/time.h> +#include <linux/irq.h> +#include <asm/mach/time.h> +#include <mach/irqs.h> +#include <mach/hardware.h> +#include <mach/spear.h> +#include <mach/generic.h> + +/* + * We would use TIMER0 and TIMER1 as clockevent and clocksource. + * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further + * they share same functional clock. Any change in one's functional clock will + * also affect other timer. + */ + +#define CLKEVT 0 /* gpt0, channel0 as clockevent */ +#define CLKSRC 1 /* gpt0, channel1 as clocksource */ + +/* Register offsets, x is channel number */ +#define CR(x) ((x) * 0x80 + 0x80) +#define IR(x) ((x) * 0x80 + 0x84) +#define LOAD(x) ((x) * 0x80 + 0x88) +#define COUNT(x) ((x) * 0x80 + 0x8C) + +/* Reg bit definitions */ +#define CTRL_INT_ENABLE 0x0100 +#define CTRL_ENABLE 0x0020 +#define CTRL_ONE_SHOT 0x0010 + +#define CTRL_PRESCALER1 0x0 +#define CTRL_PRESCALER2 0x1 +#define CTRL_PRESCALER4 0x2 +#define CTRL_PRESCALER8 0x3 +#define CTRL_PRESCALER16 0x4 +#define CTRL_PRESCALER32 0x5 +#define CTRL_PRESCALER64 0x6 +#define CTRL_PRESCALER128 0x7 +#define CTRL_PRESCALER256 0x8 + +#define INT_STATUS 0x1 + +static __iomem void *gpt_base; +static struct clk *gpt_clk; + +static void clockevent_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk_event_dev); +static int clockevent_next_event(unsigned long evt, + struct clock_event_device *clk_event_dev); + +/* + * Following clocksource_set_clock and clockevent_set_clock picked + * from arch/mips/kernel/time.c + */ + +void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock) +{ + u64 temp; + u32 shift; + + /* Find a shift value */ + for (shift = 32; shift > 0; shift--) { + temp = (u64) NSEC_PER_SEC << shift; + do_div(temp, clock); + if ((temp >> 32) == 0) + break; + } + cs->shift = shift; + cs->mult = (u32) temp; +} + +void __init clockevent_set_clock(struct clock_event_device *cd, + unsigned int clock) +{ + u64 temp; + u32 shift; + + /* Find a shift value */ + for (shift = 32; shift > 0; shift--) { + temp = (u64) clock << shift; + do_div(temp, NSEC_PER_SEC); + if ((temp >> 32) == 0) + break; + } + cd->shift = shift; + cd->mult = (u32) temp; +} + +static cycle_t clocksource_read_cycles(struct clocksource *cs) +{ + return (cycle_t) readw(gpt_base + COUNT(CLKSRC)); +} + +static struct clocksource clksrc = { + .name = "tmr1", + .rating = 200, /* its a pretty decent clock */ + .read = clocksource_read_cycles, + .mask = 0xFFFF, /* 16 bits */ + .mult = 0, /* to be computed */ + .shift = 0, /* to be computed */ + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void spear_clocksource_init(void) +{ + u32 tick_rate; + u16 val; + + /* program the prescaler (/256)*/ + writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC)); + + /* find out actual clock driving Timer */ + tick_rate = clk_get_rate(gpt_clk); + tick_rate >>= CTRL_PRESCALER256; + + writew(0xFFFF, gpt_base + LOAD(CLKSRC)); + + val = readw(gpt_base + CR(CLKSRC)); + val &= ~CTRL_ONE_SHOT; /* autoreload mode */ + val |= CTRL_ENABLE ; + writew(val, gpt_base + CR(CLKSRC)); + + clocksource_set_clock(&clksrc, tick_rate); + + /* register the clocksource */ + clocksource_register(&clksrc); +} + +static struct clock_event_device clkevt = { + .name = "tmr0", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = clockevent_set_mode, + .set_next_event = clockevent_next_event, + .shift = 0, /* to be computed */ +}; + +static void clockevent_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk_event_dev) +{ + u32 period; + u16 val; + + /* stop the timer */ + val = readw(gpt_base + CR(CLKEVT)); + val &= ~CTRL_ENABLE; + writew(val, gpt_base + CR(CLKEVT)); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + period = clk_get_rate(gpt_clk) / HZ; + period >>= CTRL_PRESCALER16; + writew(period, gpt_base + LOAD(CLKEVT)); + + val = readw(gpt_base + CR(CLKEVT)); + val &= ~CTRL_ONE_SHOT; + val |= CTRL_ENABLE | CTRL_INT_ENABLE; + writew(val, gpt_base + CR(CLKEVT)); + + break; + case CLOCK_EVT_MODE_ONESHOT: + val = readw(gpt_base + CR(CLKEVT)); + val |= CTRL_ONE_SHOT; + writew(val, gpt_base + CR(CLKEVT)); + + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + + break; + default: + pr_err("Invalid mode requested\n"); + break; + } +} + +static int clockevent_next_event(unsigned long cycles, + struct clock_event_device *clk_event_dev) +{ + u16 val; + + writew(cycles, gpt_base + LOAD(CLKEVT)); + + val = readw(gpt_base + CR(CLKEVT)); + val |= CTRL_ENABLE | CTRL_INT_ENABLE; + writew(val, gpt_base + CR(CLKEVT)); + + return 0; +} + +static irqreturn_t spear_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clkevt; + + writew(INT_STATUS, gpt_base + IR(CLKEVT)); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction spear_timer_irq = { + .name = "timer", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = spear_timer_interrupt +}; + +static void __init spear_clockevent_init(void) +{ + u32 tick_rate; + + /* program the prescaler */ + writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT)); + + tick_rate = clk_get_rate(gpt_clk); + tick_rate >>= CTRL_PRESCALER16; + + clockevent_set_clock(&clkevt, tick_rate); + + clkevt.max_delta_ns = clockevent_delta2ns(0xfff0, + &clkevt); + clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt); + + clkevt.cpumask = cpumask_of(0); + + clockevents_register_device(&clkevt); + + setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq); +} + +void __init spear_setup_timer(void) +{ + struct clk *pll3_clk; + + if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) { + pr_err("%s:cannot get IO addr\n", __func__); + return; + } + + gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K); + if (!gpt_base) { + pr_err("%s:ioremap failed for gpt\n", __func__); + goto err_mem; + } + + gpt_clk = clk_get_sys("gpt0", NULL); + if (!gpt_clk) { + pr_err("%s:couldn't get clk for gpt\n", __func__); + goto err_iomap; + } + + pll3_clk = clk_get(NULL, "pll3_48m_clk"); + if (!pll3_clk) { + pr_err("%s:couldn't get PLL3 as parent for gpt\n", __func__); + goto err_iomap; + } + + clk_set_parent(gpt_clk, pll3_clk); + + spear_clockevent_init(); + spear_clocksource_init(); + + return; + +err_iomap: + iounmap(gpt_base); + +err_mem: + release_mem_region(SPEAR_GPT0_BASE, SZ_1K); +} + +struct sys_timer spear_sys_timer = { + .init = spear_setup_timer, +}; diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile new file mode 100644 index 00000000000..9b1a66816aa --- /dev/null +++ b/arch/arm/plat-versatile/Makefile @@ -0,0 +1,4 @@ +obj-y := clock.o +obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o +obj-$(CONFIG_ARCH_REALVIEW) += sched-clock.o +obj-$(CONFIG_ARCH_VERSATILE) += sched-clock.o diff --git a/arch/arm/mach-integrator/clock.c b/arch/arm/plat-versatile/clock.c index 989ecf5f5c4..5c8b6564fdc 100644 --- a/arch/arm/mach-integrator/clock.c +++ b/arch/arm/plat-versatile/clock.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-integrator/clock.c + * linux/arch/arm/plat-versatile/clock.c * * Copyright (C) 2004 ARM Limited. * Written by Deep Blue Solutions Limited. @@ -14,7 +14,8 @@ #include <linux/clk.h> #include <linux/mutex.h> -#include <asm/clkdev.h> +#include <asm/hardware/icst.h> + #include <mach/clkdev.h> int clk_enable(struct clk *clk) @@ -36,24 +37,38 @@ EXPORT_SYMBOL(clk_get_rate); long clk_round_rate(struct clk *clk, unsigned long rate) { - struct icst525_vco vco; - vco = icst525_khz_to_vco(clk->params, rate / 1000); - return icst525_khz(clk->params, vco) * 1000; + long ret = -EIO; + if (clk->ops && clk->ops->round) + ret = clk->ops->round(clk, rate); + return ret; } EXPORT_SYMBOL(clk_round_rate); int clk_set_rate(struct clk *clk, unsigned long rate) { int ret = -EIO; - - if (clk->setvco) { - struct icst525_vco vco; - - vco = icst525_khz_to_vco(clk->params, rate / 1000); - clk->rate = icst525_khz(clk->params, vco) * 1000; - clk->setvco(clk, vco); - ret = 0; - } + if (clk->ops && clk->ops->set) + ret = clk->ops->set(clk, rate); return ret; } EXPORT_SYMBOL(clk_set_rate); + +long icst_clk_round(struct clk *clk, unsigned long rate) +{ + struct icst_vco vco; + vco = icst_hz_to_vco(clk->params, rate); + return icst_hz(clk->params, vco); +} +EXPORT_SYMBOL(icst_clk_round); + +int icst_clk_set(struct clk *clk, unsigned long rate) +{ + struct icst_vco vco; + + vco = icst_hz_to_vco(clk->params, rate); + clk->rate = icst_hz(clk->params, vco); + clk->ops->setvco(clk, vco); + + return 0; +} +EXPORT_SYMBOL(icst_clk_set); diff --git a/arch/arm/plat-versatile/include/plat/clock.h b/arch/arm/plat-versatile/include/plat/clock.h new file mode 100644 index 00000000000..3cfb024ccd7 --- /dev/null +++ b/arch/arm/plat-versatile/include/plat/clock.h @@ -0,0 +1,15 @@ +#ifndef PLAT_CLOCK_H +#define PLAT_CLOCK_H + +#include <asm/hardware/icst.h> + +struct clk_ops { + long (*round)(struct clk *, unsigned long); + int (*set)(struct clk *, unsigned long); + void (*setvco)(struct clk *, struct icst_vco); +}; + +int icst_clk_set(struct clk *, unsigned long); +long icst_clk_round(struct clk *, unsigned long); + +#endif diff --git a/arch/arm/plat-versatile/include/plat/timer-sp.h b/arch/arm/plat-versatile/include/plat/timer-sp.h new file mode 100644 index 00000000000..21e75e30d49 --- /dev/null +++ b/arch/arm/plat-versatile/include/plat/timer-sp.h @@ -0,0 +1,2 @@ +void sp804_clocksource_init(void __iomem *); +void sp804_clockevents_init(void __iomem *, unsigned int); diff --git a/arch/arm/plat-versatile/sched-clock.c b/arch/arm/plat-versatile/sched-clock.c new file mode 100644 index 00000000000..9768cf7e83d --- /dev/null +++ b/arch/arm/plat-versatile/sched-clock.c @@ -0,0 +1,53 @@ +/* + * linux/arch/arm/plat-versatile/sched-clock.c + * + * Copyright (C) 1999 - 2003 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/cnt32_to_63.h> +#include <linux/io.h> +#include <asm/div64.h> + +#include <mach/hardware.h> +#include <mach/platform.h> + +#ifdef VERSATILE_SYS_BASE +#define REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET) +#endif + +#ifdef REALVIEW_SYS_BASE +#define REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) +#endif + +/* + * This is the Realview and Versatile sched_clock implementation. This + * has a resolution of 41.7ns, and a maximum value of about 35583 days. + * + * The return value is guaranteed to be monotonic in that range as + * long as there is always less than 89 seconds between successive + * calls to this function. + */ +unsigned long long sched_clock(void) +{ + unsigned long long v = cnt32_to_63(readl(REFCOUNTER)); + + /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */ + v *= 125<<1; + do_div(v, 3<<1); + + return v; +} diff --git a/arch/arm/plat-versatile/timer-sp.c b/arch/arm/plat-versatile/timer-sp.c new file mode 100644 index 00000000000..fb0d1c29971 --- /dev/null +++ b/arch/arm/plat-versatile/timer-sp.c @@ -0,0 +1,156 @@ +/* + * linux/arch/arm/plat-versatile/timer-sp.c + * + * Copyright (C) 1999 - 2003 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <asm/hardware/arm_timer.h> + +#include <plat/timer-sp.h> + +/* + * These timers are currently always setup to be clocked at 1MHz. + */ +#define TIMER_FREQ_KHZ (1000) +#define TIMER_RELOAD (TIMER_FREQ_KHZ * 1000 / HZ) + +static void __iomem *clksrc_base; + +static cycle_t sp804_read(struct clocksource *cs) +{ + return ~readl(clksrc_base + TIMER_VALUE); +} + +static struct clocksource clocksource_sp804 = { + .name = "timer3", + .rating = 200, + .read = sp804_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +void __init sp804_clocksource_init(void __iomem *base) +{ + struct clocksource *cs = &clocksource_sp804; + + clksrc_base = base; + + /* setup timer 0 as free-running clocksource */ + writel(0, clksrc_base + TIMER_CTRL); + writel(0xffffffff, clksrc_base + TIMER_LOAD); + writel(0xffffffff, clksrc_base + TIMER_VALUE); + writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, + clksrc_base + TIMER_CTRL); + + cs->mult = clocksource_khz2mult(TIMER_FREQ_KHZ, cs->shift); + clocksource_register(cs); +} + + +static void __iomem *clkevt_base; + +/* + * IRQ handler for the timer + */ +static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + /* clear the interrupt */ + writel(1, clkevt_base + TIMER_INTCLR); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static void sp804_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE; + + writel(ctrl, clkevt_base + TIMER_CTRL); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD); + ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; + break; + + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ + ctrl |= TIMER_CTRL_ONESHOT; + break; + + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + break; + } + + writel(ctrl, clkevt_base + TIMER_CTRL); +} + +static int sp804_set_next_event(unsigned long next, + struct clock_event_device *evt) +{ + unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); + + writel(next, clkevt_base + TIMER_LOAD); + writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); + + return 0; +} + +static struct clock_event_device sp804_clockevent = { + .name = "timer0", + .shift = 32, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = sp804_set_mode, + .set_next_event = sp804_set_next_event, + .rating = 300, + .cpumask = cpu_all_mask, +}; + +static struct irqaction sp804_timer_irq = { + .name = "timer", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = sp804_timer_interrupt, + .dev_id = &sp804_clockevent, +}; + +void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq) +{ + struct clock_event_device *evt = &sp804_clockevent; + + clkevt_base = base; + + evt->irq = timer_irq; + evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift); + evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt); + evt->min_delta_ns = clockevent_delta2ns(0xf, evt); + + setup_irq(timer_irq, &sp804_timer_irq); + clockevents_register_device(evt); +} |