diff options
Diffstat (limited to 'arch/arm/plat-orion')
| -rw-r--r-- | arch/arm/plat-orion/addr-map.c | 7 | ||||
| -rw-r--r-- | arch/arm/plat-orion/include/plat/pcie.h | 3 | ||||
| -rw-r--r-- | arch/arm/plat-orion/pcie.c | 6 |
3 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c index c27ad88bc40..367ca89ac40 100644 --- a/arch/arm/plat-orion/addr-map.c +++ b/arch/arm/plat-orion/addr-map.c @@ -9,6 +9,7 @@ */ #include <linux/kernel.h> +#include <linux/module.h> #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> @@ -16,6 +17,12 @@ struct mbus_dram_target_info orion_mbus_dram_info; +const struct mbus_dram_target_info *mv_mbus_dram_info(void) +{ + return &orion_mbus_dram_info; +} +EXPORT_SYMBOL_GPL(mv_mbus_dram_info); + /* * DDR target is the same on all Orion platforms. */ diff --git a/arch/arm/plat-orion/include/plat/pcie.h b/arch/arm/plat-orion/include/plat/pcie.h index cc99163e73f..fe5b9e86274 100644 --- a/arch/arm/plat-orion/include/plat/pcie.h +++ b/arch/arm/plat-orion/include/plat/pcie.h @@ -20,8 +20,7 @@ int orion_pcie_x4_mode(void __iomem *base); int orion_pcie_get_local_bus_nr(void __iomem *base); void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); void orion_pcie_reset(void __iomem *base); -void orion_pcie_setup(void __iomem *base, - struct mbus_dram_target_info *dram); +void orion_pcie_setup(void __iomem *base); int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val); int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index af2d733c50b..86dbb5bdb17 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -13,6 +13,7 @@ #include <linux/mbus.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <plat/addr-map.h> #include <linux/delay.h> /* @@ -175,8 +176,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base, writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); } -void __init orion_pcie_setup(void __iomem *base, - struct mbus_dram_target_info *dram) +void __init orion_pcie_setup(void __iomem *base) { u16 cmd; u32 mask; @@ -184,7 +184,7 @@ void __init orion_pcie_setup(void __iomem *base, /* * Point PCIe unit MBUS decode windows to DRAM space. */ - orion_pcie_setup_wins(base, dram); + orion_pcie_setup_wins(base, &orion_mbus_dram_info); /* * Master + slave enable. |