diff options
Diffstat (limited to 'arch/arm/plat-omap/include/plat')
| -rw-r--r-- | arch/arm/plat-omap/include/plat/clock.h | 130 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/common.h | 4 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/omap-pm.h | 130 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/omap_device.h | 2 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/omap_hwmod.h | 14 |
5 files changed, 222 insertions, 58 deletions
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index dfc472ca0cc..fef4696dcf6 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -19,6 +19,22 @@ struct module; struct clk; struct clockdomain; +/** + * struct clkops - some clock function pointers + * @enable: fn ptr that enables the current clock in hardware + * @disable: fn ptr that enables the current clock in hardware + * @find_idlest: function returning the IDLEST register for the clock's IP blk + * @find_companion: function returning the "companion" clk reg for the clock + * + * A "companion" clk is an accompanying clock to the one being queried + * that must be enabled for the IP module connected to the clock to + * become accessible by the hardware. Neither @find_idlest nor + * @find_companion should be needed; that information is IP + * block-specific; the hwmod code has been created to handle this, but + * until hwmod data is ready and drivers have been converted to use PM + * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and + * @find_companion must, unfortunately, remain. + */ struct clkops { int (*enable)(struct clk *); void (*disable)(struct clk *); @@ -30,12 +46,45 @@ struct clkops { #ifdef CONFIG_ARCH_OMAP2PLUS +/* struct clksel_rate.flags possibilities */ +#define RATE_IN_242X (1 << 0) +#define RATE_IN_243X (1 << 1) +#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */ +#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */ +#define RATE_IN_36XX (1 << 4) +#define RATE_IN_4430 (1 << 5) + +#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) +#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX) + +/** + * struct clksel_rate - register bitfield values corresponding to clk divisors + * @val: register bitfield value (shifted to bit 0) + * @div: clock divisor corresponding to @val + * @flags: (see "struct clksel_rate.flags possibilities" above) + * + * @val should match the value of a read from struct clk.clksel_reg + * AND'ed with struct clk.clksel_mask, shifted right to bit 0. + * + * @div is the divisor that should be applied to the parent clock's rate + * to produce the current clock's rate. + * + * XXX @flags probably should be replaced with an struct omap_chip. + */ struct clksel_rate { u32 val; u8 div; u8 flags; }; +/** + * struct clksel - available parent clocks, and a pointer to their divisors + * @parent: struct clk * to a possible parent clock + * @rates: available divisors for this parent clock + * + * A struct clksel is always associated with one or more struct clks + * and one or more struct clksel_rates. + */ struct clksel { struct clk *parent; const struct clksel_rate *rates; @@ -116,6 +165,60 @@ struct dpll_data { #endif +/* struct clk.flags possibilities */ +#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ +#define CLOCK_IDLE_CONTROL (1 << 1) +#define CLOCK_NO_IDLE_PARENT (1 << 2) +#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ +#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ + +/** + * struct clk - OMAP struct clk + * @node: list_head connecting this clock into the full clock list + * @ops: struct clkops * for this clock + * @name: the name of the clock in the hardware (used in hwmod data and debug) + * @parent: pointer to this clock's parent struct clk + * @children: list_head connecting to the child clks' @sibling list_heads + * @sibling: list_head connecting this clk to its parent clk's @children + * @rate: current clock rate + * @enable_reg: register to write to enable the clock (see @enable_bit) + * @recalc: fn ptr that returns the clock's current rate + * @set_rate: fn ptr that can change the clock's current rate + * @round_rate: fn ptr that can round the clock's current rate + * @init: fn ptr to do clock-specific initialization + * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) + * @usecount: number of users that have requested this clock to be enabled + * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div + * @flags: see "struct clk.flags possibilities" above + * @clksel_reg: for clksel clks, register va containing src/divisor select + * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector + * @clksel: for clksel clks, pointer to struct clksel for this clock + * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock + * @clkdm_name: clockdomain name that this clock is contained in + * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime + * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) + * @src_offset: bitshift for source selection bitfield (OMAP1 only) + * + * XXX @rate_offset, @src_offset should probably be removed and OMAP1 + * clock code converted to use clksel. + * + * XXX @usecount is poorly named. It should be "enable_count" or + * something similar. "users" in the description refers to kernel + * code (core code or drivers) that have called clk_enable() and not + * yet called clk_disable(); the usecount of parent clocks is also + * incremented by the clock code when clk_enable() is called on child + * clocks and decremented by the clock code when clk_disable() is + * called on child clocks. + * + * XXX @clkdm, @usecount, @children, @sibling should be marked for + * internal use only. + * + * @children and @sibling are used to optimize parent-to-child clock + * tree traversals. (child-to-parent traversals use @parent.) + * + * XXX The notion of the clock's current rate probably needs to be + * separated from the clock's target rate. + */ struct clk { struct list_head node; const struct clkops *ops; @@ -129,8 +232,8 @@ struct clk { int (*set_rate)(struct clk *, unsigned long); long (*round_rate)(struct clk *, unsigned long); void (*init)(struct clk *); - __u8 enable_bit; - __s8 usecount; + u8 enable_bit; + s8 usecount; u8 fixed_div; u8 flags; #ifdef CONFIG_ARCH_OMAP2PLUS @@ -141,8 +244,8 @@ struct clk { const char *clkdm_name; struct clockdomain *clkdm; #else - __u8 rate_offset; - __u8 src_offset; + u8 rate_offset; + u8 src_offset; #endif #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) struct dentry *dent; /* For visible tree hierarchy */ @@ -188,23 +291,4 @@ extern const struct clkops clkops_null; extern struct clk dummy_ck; -/* Clock flags */ -#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ -#define CLOCK_IDLE_CONTROL (1 << 1) -#define CLOCK_NO_IDLE_PARENT (1 << 2) -#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ - -/* Clksel_rate flags */ -#define RATE_IN_242X (1 << 0) -#define RATE_IN_243X (1 << 1) -#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */ -#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */ -#define RATE_IN_36XX (1 << 4) -#define RATE_IN_4430 (1 << 5) - -#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) - -#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX) - #endif diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index d265018f5e6..fe83e901ba6 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -87,4 +87,8 @@ void omap2_set_globals_uart(struct omap_globals *); } \ }) +extern struct device *omap2_get_mpuss_device(void); +extern struct device *omap2_get_dsp_device(void); +extern struct device *omap2_get_l3_device(void); + #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h index 3ee41d71149..728fbb9dd54 100644 --- a/arch/arm/plat-omap/include/plat/omap-pm.h +++ b/arch/arm/plat-omap/include/plat/omap-pm.h @@ -1,8 +1,8 @@ /* * omap-pm.h - OMAP power management interface * - * Copyright (C) 2008-2009 Texas Instruments, Inc. - * Copyright (C) 2008-2009 Nokia Corporation + * Copyright (C) 2008-2010 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation * Paul Walmsley * * Interface developed by (in alphabetical order): Karthik Dasu, Jouni @@ -16,6 +16,7 @@ #include <linux/device.h> #include <linux/cpufreq.h> +#include <linux/clk.h> #include "powerdomain.h" @@ -89,7 +90,7 @@ void omap_pm_if_exit(void); * @t: maximum MPU wakeup latency in microseconds * * Request that the maximum interrupt latency for the MPU to be no - * greater than 't' microseconds. "Interrupt latency" in this case is + * greater than @t microseconds. "Interrupt latency" in this case is * defined as the elapsed time from the occurrence of a hardware or * timer interrupt to the time when the device driver's interrupt * service routine has been entered by the MPU. @@ -105,15 +106,19 @@ void omap_pm_if_exit(void); * elapsed from when a device driver enables a hardware device with * clk_enable(), to when the device is ready for register access or * other use. To control this device wakeup latency, use - * set_max_dev_wakeup_lat() + * omap_pm_set_max_dev_wakeup_lat() * - * Multiple calls to set_max_mpu_wakeup_lat() will replace the + * Multiple calls to omap_pm_set_max_mpu_wakeup_lat() will replace the * previous t value. To remove the latency target for the MPU, call * with t = -1. * - * No return value. + * XXX This constraint will be deprecated soon in favor of the more + * general omap_pm_set_max_dev_wakeup_lat() + * + * Returns -EINVAL for an invalid argument, -ERANGE if the constraint + * is not satisfiable, or 0 upon success. */ -void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); +int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); /** @@ -123,8 +128,8 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); * @r: minimum throughput (in KiB/s) * * Request that the minimum data throughput on the OCP interconnect - * attached to device 'dev' interconnect agent 'tbus_id' be no less - * than 'r' KiB/s. + * attached to device @dev interconnect agent @tbus_id be no less + * than @r KiB/s. * * It is expected that the OMAP PM or bus code will use this * information to set the interconnect clock to run at the lowest @@ -138,40 +143,44 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); * code will also need to add an minimum L3 interconnect speed * constraint, * - * Multiple calls to set_min_bus_tput() will replace the previous rate - * value for this device. To remove the interconnect throughput - * restriction for this device, call with r = 0. + * Multiple calls to omap_pm_set_min_bus_tput() will replace the + * previous rate value for this device. To remove the interconnect + * throughput restriction for this device, call with r = 0. * - * No return value. + * Returns -EINVAL for an invalid argument, -ERANGE if the constraint + * is not satisfiable, or 0 upon success. */ -void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); +int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); /** * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency - * @dev: struct device * + * @req_dev: struct device * requesting the constraint, or NULL if none + * @dev: struct device * to set the constraint one * @t: maximum device wakeup latency in microseconds * - * Request that the maximum amount of time necessary for a device to - * become accessible after its clocks are enabled should be no greater - * than 't' microseconds. Specifically, this represents the time from - * when a device driver enables device clocks with clk_enable(), to - * when the register reads and writes on the device will succeed. - * This function should be called before clk_disable() is called, - * since the power state transition decision may be made during - * clk_disable(). + * Request that the maximum amount of time necessary for a device @dev + * to become accessible after its clocks are enabled should be no + * greater than @t microseconds. Specifically, this represents the + * time from when a device driver enables device clocks with + * clk_enable(), to when the register reads and writes on the device + * will succeed. This function should be called before clk_disable() + * is called, since the power state transition decision may be made + * during clk_disable(). * * It is intended that underlying PM code will use this information to * determine what power state to put the powerdomain enclosing this * device into. * - * Multiple calls to set_max_dev_wakeup_lat() will replace the - * previous wakeup latency values for this device. To remove the wakeup - * latency restriction for this device, call with t = -1. + * Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the + * previous wakeup latency values for this device. To remove the + * wakeup latency restriction for this device, call with t = -1. * - * No return value. + * Returns -EINVAL for an invalid argument, -ERANGE if the constraint + * is not satisfiable, or 0 upon success. */ -void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t); +int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev, + long t); /** @@ -198,10 +207,71 @@ void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t); * value for this device. To remove the maximum DMA latency for this * device, call with t = -1. * - * No return value. + * Returns -EINVAL for an invalid argument, -ERANGE if the constraint + * is not satisfiable, or 0 upon success. */ -void omap_pm_set_max_sdma_lat(struct device *dev, long t); +int omap_pm_set_max_sdma_lat(struct device *dev, long t); + +/** + * omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev + * @dev: struct device * requesting the constraint + * @clk: struct clk * to set the minimum rate constraint on + * @r: minimum rate in Hz + * + * Request that the minimum clock rate on the device @dev's clk @clk + * be no less than @r Hz. + * + * It is expected that the OMAP PM code will use this information to + * find an OPP or clock setting that will satisfy this clock rate + * constraint, along with any other applicable system constraints on + * the clock rate or corresponding voltage, etc. + * + * omap_pm_set_min_clk_rate() differs from the clock code's + * clk_set_rate() in that it considers other constraints before taking + * any hardware action, and may change a system OPP rather than just a + * clock rate. clk_set_rate() is intended to be a low-level + * interface. + * + * omap_pm_set_min_clk_rate() is easily open to abuse. A better API + * would be something like "omap_pm_set_min_dev_performance()"; + * however, there is no easily-generalizable concept of performance + * that applies to all devices. Only a device (and possibly the + * device subsystem) has both the subsystem-specific knowledge, and + * the hardware IP block-specific knowledge, to translate a constraint + * on "touchscreen sampling accuracy" or "number of pixels or polygons + * rendered per second" to a clock rate. This translation can be + * dependent on the hardware IP block's revision, or firmware version, + * and the driver is the only code on the system that has this + * information and can know how to translate that into a clock rate. + * + * The intended use-case for this function is for userspace or other + * kernel code to communicate a particular performance requirement to + * a subsystem; then for the subsystem to communicate that requirement + * to something that is meaningful to the device driver; then for the + * device driver to convert that requirement to a clock rate, and to + * then call omap_pm_set_min_clk_rate(). + * + * Users of this function (such as device drivers) should not simply + * call this function with some high clock rate to ensure "high + * performance." Rather, the device driver should take a performance + * constraint from its subsystem, such as "render at least X polygons + * per second," and use some formula or table to convert that into a + * clock rate constraint given the hardware type and hardware + * revision. Device drivers or subsystems should not assume that they + * know how to make a power/performance tradeoff - some device use + * cases may tolerate a lower-fidelity device function for lower power + * consumption; others may demand a higher-fidelity device function, + * no matter what the power consumption. + * + * Multiple calls to omap_pm_set_min_clk_rate() will replace the + * previous rate value for the device @dev. To remove the minimum clock + * rate constraint for the device, call with r = 0. + * + * Returns -EINVAL for an invalid argument, -ERANGE if the constraint + * is not satisfiable, or 0 upon success. + */ +int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r); /* * DSP Bridge-specific constraints diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index 3694b622c4a..25cd9ac3b09 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h @@ -101,6 +101,8 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, int omap_device_register(struct omap_device *od); int omap_early_device_register(struct omap_device *od); +void __iomem *omap_device_get_rt_va(struct omap_device *od); + /* OMAP PM interface */ int omap_device_align_pm_lat(struct platform_device *pdev, u32 new_wakeup_lat_limit); diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 0eccc09ac4a..a4e508dfaba 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -1,7 +1,7 @@ /* * omap_hwmod macros, structures * - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Nokia Corporation * Paul Walmsley * * Created in collaboration with (alphabetical order): Benoît Cousson, @@ -419,7 +419,7 @@ struct omap_hwmod_class { * @slaves: ptr to array of OCP ifs that this hwmod can respond on * @dev_attr: arbitrary device attributes that can be passed to the driver * @_sysc_cache: internal-use hwmod flags - * @_rt_va: cached register target start address (internal use) + * @_mpu_rt_va: cached register target start address (internal use) * @_mpu_port_index: cached MPU register target slave ID (internal use) * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift @@ -460,7 +460,7 @@ struct omap_hwmod { struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ void *dev_attr; u32 _sysc_cache; - void __iomem *_rt_va; + void __iomem *_mpu_rt_va; struct list_head node; u16 flags; u8 _mpu_port_index; @@ -482,11 +482,14 @@ int omap_hwmod_init(struct omap_hwmod **ohs); int omap_hwmod_register(struct omap_hwmod *oh); int omap_hwmod_unregister(struct omap_hwmod *oh); struct omap_hwmod *omap_hwmod_lookup(const char *name); -int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)); -int omap_hwmod_late_init(void); +int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), + void *data); +int omap_hwmod_late_init(u8 skip_setup_idle); int omap_hwmod_enable(struct omap_hwmod *oh); +int _omap_hwmod_enable(struct omap_hwmod *oh); int omap_hwmod_idle(struct omap_hwmod *oh); +int _omap_hwmod_idle(struct omap_hwmod *oh); int omap_hwmod_shutdown(struct omap_hwmod *oh); int omap_hwmod_enable_clocks(struct omap_hwmod *oh); @@ -504,6 +507,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh); int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); +void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh); |