diff options
Diffstat (limited to 'arch/arm/mach-stmp378x')
42 files changed, 3438 insertions, 0 deletions
diff --git a/arch/arm/mach-stmp378x/Makefile b/arch/arm/mach-stmp378x/Makefile new file mode 100644 index 00000000000..d156f76b379 --- /dev/null +++ b/arch/arm/mach-stmp378x/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o +obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o diff --git a/arch/arm/mach-stmp378x/Makefile.boot b/arch/arm/mach-stmp378x/Makefile.boot new file mode 100644 index 00000000000..1568ad404d5 --- /dev/null +++ b/arch/arm/mach-stmp378x/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S new file mode 100644 index 00000000000..731a92286da --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/entry-macro.S @@ -0,0 +1,35 @@ +/* + * Low-level IRQ helper macros for Freescale STMP378X + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + mov \base, #0xf0000000 @ vm address of IRQ controller + ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT + cmp \irqnr, #0x7f + moveqs \irqnr, #0 @ Zero flag set for no IRQ + + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h new file mode 100644 index 00000000000..cc59673becd --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/irqs.h @@ -0,0 +1,95 @@ +/* + * Freescale STMP378X interrupts + * + * Copyright (C) 2005 Sigmatel Inc + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#define IRQ_DEBUG_UART 0 +#define IRQ_COMMS_RX 1 +#define IRQ_COMMS_TX 1 +#define IRQ_SSP2_ERROR 2 +#define IRQ_VDD5V 3 +#define IRQ_HEADPHONE_SHORT 4 +#define IRQ_DAC_DMA 5 +#define IRQ_DAC_ERROR 6 +#define IRQ_ADC_DMA 7 +#define IRQ_ADC_ERROR 8 +#define IRQ_SPDIF_DMA 9 +#define IRQ_SAIF2_DMA 9 +#define IRQ_SPDIF_ERROR 10 +#define IRQ_SAIF1_IRQ 10 +#define IRQ_SAIF2_IRQ 10 +#define IRQ_USB_CTRL 11 +#define IRQ_USB_WAKEUP 12 +#define IRQ_GPMI_DMA 13 +#define IRQ_SSP1_DMA 14 +#define IRQ_SSP_ERROR 15 +#define IRQ_GPIO0 16 +#define IRQ_GPIO1 17 +#define IRQ_GPIO2 18 +#define IRQ_SAIF1_DMA 19 +#define IRQ_SSP2_DMA 20 +#define IRQ_ECC8_IRQ 21 +#define IRQ_RTC_ALARM 22 +#define IRQ_UARTAPP_TX_DMA 23 +#define IRQ_UARTAPP_INTERNAL 24 +#define IRQ_UARTAPP_RX_DMA 25 +#define IRQ_I2C_DMA 26 +#define IRQ_I2C_ERROR 27 +#define IRQ_TIMER0 28 +#define IRQ_TIMER1 29 +#define IRQ_TIMER2 30 +#define IRQ_TIMER3 31 +#define IRQ_BATT_BRNOUT 32 +#define IRQ_VDDD_BRNOUT 33 +#define IRQ_VDDIO_BRNOUT 34 +#define IRQ_VDD18_BRNOUT 35 +#define IRQ_TOUCH_DETECT 36 +#define IRQ_LRADC_CH0 37 +#define IRQ_LRADC_CH1 38 +#define IRQ_LRADC_CH2 39 +#define IRQ_LRADC_CH3 40 +#define IRQ_LRADC_CH4 41 +#define IRQ_LRADC_CH5 42 +#define IRQ_LRADC_CH6 43 +#define IRQ_LRADC_CH7 44 +#define IRQ_LCDIF_DMA 45 +#define IRQ_LCDIF_ERROR 46 +#define IRQ_DIGCTL_DEBUG_TRAP 47 +#define IRQ_RTC_1MSEC 48 +#define IRQ_DRI_DMA 49 +#define IRQ_DRI_ATTENTION 50 +#define IRQ_GPMI_ATTENTION 51 +#define IRQ_IR 52 +#define IRQ_DCP_VMI 53 +#define IRQ_DCP 54 +#define IRQ_BCH 56 +#define IRQ_PXP 57 +#define IRQ_UARTAPP2_TX_DMA 58 +#define IRQ_UARTAPP2_INTERNAL 59 +#define IRQ_UARTAPP2_RX_DMA 60 +#define IRQ_VDAC_DETECT 61 +#define IRQ_VDD5V_DROOP 64 +#define IRQ_DCDC4P2_BO 65 + + +#define NR_REAL_IRQS 128 +#define NR_IRQS (NR_REAL_IRQS + 32 * 3) + +/* All interrupts are FIQ capable */ +#define FIQ_START IRQ_DEBUG_UART + +/* Hard disk IRQ is a GPMI attention IRQ */ +#define IRQ_HARDDISK IRQ_GPMI_ATTENTION diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h new file mode 100644 index 00000000000..93f952d3596 --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/pins.h @@ -0,0 +1,151 @@ +/* + * Freescale STMP378X SoC pin multiplexing + * + * Author: Vladislav Buzov <vbuzov@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_PINS_H +#define __ASM_ARCH_PINS_H + +/* + * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware + * interface this pin belongs to. + */ + +/* Bank 0 */ +#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0) +#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1) +#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2) +#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3) +#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4) +#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5) +#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6) +#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7) +#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8) +#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9) +#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10) +#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11) +#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12) +#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13) +#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14) +#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15) +#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16) +#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17) +#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18) +#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19) +#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20) +#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21) +#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22) +#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23) +#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24) +#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25) +#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26) +#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27) +#define PINID_AUART1_RX STMP3XXX_PINID(0, 28) +#define PINID_AUART1_TX STMP3XXX_PINID(0, 29) +#define PINID_I2C_SCL STMP3XXX_PINID(0, 30) +#define PINID_I2C_SDA STMP3XXX_PINID(0, 31) + +/* Bank 1 */ +#define PINID_LCD_D00 STMP3XXX_PINID(1, 0) +#define PINID_LCD_D01 STMP3XXX_PINID(1, 1) +#define PINID_LCD_D02 STMP3XXX_PINID(1, 2) +#define PINID_LCD_D03 STMP3XXX_PINID(1, 3) +#define PINID_LCD_D04 STMP3XXX_PINID(1, 4) +#define PINID_LCD_D05 STMP3XXX_PINID(1, 5) +#define PINID_LCD_D06 STMP3XXX_PINID(1, 6) +#define PINID_LCD_D07 STMP3XXX_PINID(1, 7) +#define PINID_LCD_D08 STMP3XXX_PINID(1, 8) +#define PINID_LCD_D09 STMP3XXX_PINID(1, 9) +#define PINID_LCD_D10 STMP3XXX_PINID(1, 10) +#define PINID_LCD_D11 STMP3XXX_PINID(1, 11) +#define PINID_LCD_D12 STMP3XXX_PINID(1, 12) +#define PINID_LCD_D13 STMP3XXX_PINID(1, 13) +#define PINID_LCD_D14 STMP3XXX_PINID(1, 14) +#define PINID_LCD_D15 STMP3XXX_PINID(1, 15) +#define PINID_LCD_D16 STMP3XXX_PINID(1, 16) +#define PINID_LCD_D17 STMP3XXX_PINID(1, 17) +#define PINID_LCD_RESET STMP3XXX_PINID(1, 18) +#define PINID_LCD_RS STMP3XXX_PINID(1, 19) +#define PINID_LCD_WR STMP3XXX_PINID(1, 20) +#define PINID_LCD_CS STMP3XXX_PINID(1, 21) +#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22) +#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23) +#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24) +#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25) +#define PINID_PWM0 STMP3XXX_PINID(1, 26) +#define PINID_PWM1 STMP3XXX_PINID(1, 27) +#define PINID_PWM2 STMP3XXX_PINID(1, 28) +#define PINID_PWM3 STMP3XXX_PINID(1, 29) +#define PINID_PWM4 STMP3XXX_PINID(1, 30) + +/* Bank 2 */ +#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0) +#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1) +#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2) +#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3) +#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4) +#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5) +#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6) +#define PINID_ROTARYA STMP3XXX_PINID(2, 7) +#define PINID_ROTARYB STMP3XXX_PINID(2, 8) +#define PINID_EMI_A00 STMP3XXX_PINID(2, 9) +#define PINID_EMI_A01 STMP3XXX_PINID(2, 10) +#define PINID_EMI_A02 STMP3XXX_PINID(2, 11) +#define PINID_EMI_A03 STMP3XXX_PINID(2, 12) +#define PINID_EMI_A04 STMP3XXX_PINID(2, 13) +#define PINID_EMI_A05 STMP3XXX_PINID(2, 14) +#define PINID_EMI_A06 STMP3XXX_PINID(2, 15) +#define PINID_EMI_A07 STMP3XXX_PINID(2, 16) +#define PINID_EMI_A08 STMP3XXX_PINID(2, 17) +#define PINID_EMI_A09 STMP3XXX_PINID(2, 18) +#define PINID_EMI_A10 STMP3XXX_PINID(2, 19) +#define PINID_EMI_A11 STMP3XXX_PINID(2, 20) +#define PINID_EMI_A12 STMP3XXX_PINID(2, 21) +#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22) +#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23) +#define PINID_EMI_CASN STMP3XXX_PINID(2, 24) +#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25) +#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26) +#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27) +#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28) +#define PINID_EMI_CKE STMP3XXX_PINID(2, 29) +#define PINID_EMI_RASN STMP3XXX_PINID(2, 30) +#define PINID_EMI_WEN STMP3XXX_PINID(2, 31) + +/* Bank 3 */ +#define PINID_EMI_D00 STMP3XXX_PINID(3, 0) +#define PINID_EMI_D01 STMP3XXX_PINID(3, 1) +#define PINID_EMI_D02 STMP3XXX_PINID(3, 2) +#define PINID_EMI_D03 STMP3XXX_PINID(3, 3) +#define PINID_EMI_D04 STMP3XXX_PINID(3, 4) +#define PINID_EMI_D05 STMP3XXX_PINID(3, 5) +#define PINID_EMI_D06 STMP3XXX_PINID(3, 6) +#define PINID_EMI_D07 STMP3XXX_PINID(3, 7) +#define PINID_EMI_D08 STMP3XXX_PINID(3, 8) +#define PINID_EMI_D09 STMP3XXX_PINID(3, 9) +#define PINID_EMI_D10 STMP3XXX_PINID(3, 10) +#define PINID_EMI_D11 STMP3XXX_PINID(3, 11) +#define PINID_EMI_D12 STMP3XXX_PINID(3, 12) +#define PINID_EMI_D13 STMP3XXX_PINID(3, 13) +#define PINID_EMI_D14 STMP3XXX_PINID(3, 14) +#define PINID_EMI_D15 STMP3XXX_PINID(3, 15) +#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16) +#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17) +#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18) +#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19) +#define PINID_EMI_CLK STMP3XXX_PINID(3, 20) +#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21) + +#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h new file mode 100644 index 00000000000..dbcf85b6ac2 --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h @@ -0,0 +1,101 @@ +/* + * stmp378x: APBH register definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _MACH_REGS_APBH +#define _MACH_REGS_APBH + +#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) +#define REGS_APBH_PHYS 0x80004000 +#define REGS_APBH_SIZE 0x2000 + +#define HW_APBH_CTRL0 0x0 +#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 +#define BP_APBH_CTRL0_RESET_CHANNEL 16 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BM_APBH_CTRL0_SFTRST 0x80000000 + +#define HW_APBH_CTRL1 0x10 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 +#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 + +#define HW_APBH_CTRL2 0x20 + +#define HW_APBH_DEVSEL 0x30 + +#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70) +#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70) +#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70) +#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70) +#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70) +#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70) +#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70) +#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70) +#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70) +#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70) +#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70) +#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70) +#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70) +#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70) +#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70) +#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70) + +#define HW_APBH_CHn_NXTCMDAR 0x50 + +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3 +#define BM_APBH_CHn_CMD_COMMAND 0x00000003 +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BP_APBH_CHn_CMD_XFER_COUNT 16 + +#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70) +#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70) +#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70) +#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70) +#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70) +#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70) +#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70) +#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70) +#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70) +#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70) +#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70) +#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70) +#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70) +#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70) +#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70) +#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70) + +#define HW_APBH_CHn_SEMA 0x80 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +#define BP_APBH_CHn_SEMA_PHORE 16 + +#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h new file mode 100644 index 00000000000..3b934a4d27f --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h @@ -0,0 +1,119 @@ +/* + * stmp378x: APBX register definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _MACH_REGS_APBX +#define _MACH_REGS_APBX + +#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) +#define REGS_APBX_PHYS 0x80024000 +#define REGS_APBX_SIZE 0x2000 + +#define HW_APBX_CTRL0 0x0 +#define BM_APBX_CTRL0_CLKGATE 0x40000000 +#define BM_APBX_CTRL0_SFTRST 0x80000000 + +#define HW_APBX_CTRL1 0x10 + +#define HW_APBX_CTRL2 0x20 + +#define HW_APBX_CHANNEL_CTRL 0x30 +#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 +#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 + +#define HW_APBX_DEVSEL 0x40 + +#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70) +#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70) +#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70) +#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70) +#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70) +#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70) +#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70) +#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70) +#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70) +#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70) +#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70) +#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70) +#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70) +#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70) +#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70) +#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70) + +#define HW_APBX_CHn_NXTCMDAR 0x110 +#define BM_APBX_CHn_CMD_COMMAND 0x00000003 +#define BP_APBX_CHn_CMD_COMMAND 0 +#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0 +#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1 +#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2 +#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3 +#define BM_APBX_CHn_CMD_CHAIN 0x00000004 +#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 +#define BP_APBX_CHn_CMD_CMDWORDS 12 +#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BP_APBX_CHn_CMD_XFER_COUNT 16 + +#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70) +#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70) +#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70) +#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70) +#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70) +#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70) +#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70) +#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70) +#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70) +#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70) +#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70) +#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70) +#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70) +#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70) +#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70) +#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70) + +#define HW_APBX_CHn_BAR 0x130 + +#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70) +#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70) +#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70) +#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70) +#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70) +#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70) +#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70) +#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70) +#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70) +#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70) +#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70) +#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70) +#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70) +#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70) +#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70) +#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70) + +#define HW_APBX_CHn_SEMA 0x140 +#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 +#define BP_APBX_CHn_SEMA_PHORE 16 + +#endif + diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h new file mode 100644 index 00000000000..641ac6126f8 --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h @@ -0,0 +1,63 @@ +/* + * stmp378x: AUDIOIN register definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000) +#define REGS_AUDIOIN_PHYS 0x8004C000 +#define REGS_AUDIOIN_SIZE 0x2000 + +#define HW_AUDIOIN_CTRL 0x0 +#define BM_AUDIOIN_CTRL_RUN 0x00000001 +#define BP_AUDIOIN_CTRL_RUN 0 +#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 +#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 +#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 +#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 +#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 +#define BM_AUDIOIN_CTRL_SFTRST 0x80000000 + +#define HW_AUDIOIN_STAT 0x10 + +#define HW_AUDIOIN_ADCSRR 0x20 + +#define HW_AUDIOIN_ADCVOLUME 0x30 +#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF +#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 +#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 +#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 + +#define HW_AUDIOIN_ADCDEBUG 0x40 + +#define HW_AUDIOIN_ADCVOL 0x50 +#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F +#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 +#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 +#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 +#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 +#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 +#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 +#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 +#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000 + +#define HW_AUDIOIN_MICLINE 0x60 + +#define HW_AUDIOIN_ANACLKCTRL 0x70 +#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 + +#define HW_AUDIOIN_DATA 0x80 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h new file mode 100644 index 00000000000..f533e23694a --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h @@ -0,0 +1,104 @@ +/* + * stmp378x: AUDIOOUT register definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000) +#define REGS_AUDIOOUT_PHYS 0x80048000 +#define REGS_AUDIOOUT_SIZE 0x2000 + +#define HW_AUDIOOUT_CTRL 0x0 +#define BM_AUDIOOUT_CTRL_RUN 0x00000001 +#define BP_AUDIOOUT_CTRL_RUN 0 +#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 +#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 +#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 +#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 +#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 +#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 + +#define HW_AUDIOOUT_STAT 0x10 + +#define HW_AUDIOOUT_DACSRR 0x20 +#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF +#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 +#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 +#define BP_AUDIOOUT_DACSRR_SRC_INT 16 +#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 +#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 +#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 +#define BP_AUDIOOUT_DACSRR_BASEMULT 28 + +#define HW_AUDIOOUT_DACVOLUME 0x30 +#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 +#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 +#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000 + +#define HW_AUDIOOUT_DACDEBUG 0x40 + +#define HW_AUDIOOUT_HPVOL 0x50 +#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 +#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000 + +#define HW_AUDIOOUT_PWRDN 0x70 +#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 +#define BP_AUDIOOUT_PWRDN_HEADPHONE 0 +#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 +#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 +#define BM_AUDI |