diff options
Diffstat (limited to 'arch/arm/mach-sa1100/pci-nanoengine.c')
| -rw-r--r-- | arch/arm/mach-sa1100/pci-nanoengine.c | 27 |
1 files changed, 10 insertions, 17 deletions
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c index dd39fee5954..ff02e2da99f 100644 --- a/arch/arm/mach-sa1100/pci-nanoengine.c +++ b/arch/arm/mach-sa1100/pci-nanoengine.c @@ -129,17 +129,8 @@ static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot, return NANOENGINE_IRQ_GPIO_PCI; } -struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_bus(sys->busnr, &pci_nano_ops, sys); -} - -static struct resource pci_io_ports = { - .name = "PCI IO", - .start = 0x400, - .end = 0x7FF, - .flags = IORESOURCE_IO, -}; +static struct resource pci_io_ports = + DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO"); static struct resource pci_non_prefetchable_memory = { .name = "PCI non-prefetchable", @@ -226,7 +217,7 @@ static struct resource pci_prefetchable_memory = { .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, }; -static int __init pci_nanoengine_setup_resources(struct resource **resource) +static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys) { if (request_resource(&ioport_resource, &pci_io_ports)) { printk(KERN_ERR "PCI: unable to allocate io port region\n"); @@ -243,9 +234,11 @@ static int __init pci_nanoengine_setup_resources(struct resource **resource) printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); return -EBUSY; } - resource[0] = &pci_io_ports; - resource[1] = &pci_non_prefetchable_memory; - resource[2] = &pci_prefetchable_memory; + pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset); + pci_add_resource_offset(&sys->resources, + &pci_non_prefetchable_memory, sys->mem_offset); + pci_add_resource_offset(&sys->resources, + &pci_prefetchable_memory, sys->mem_offset); return 1; } @@ -260,7 +253,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys) if (nr == 0) { sys->mem_offset = NANO_PCI_MEM_RW_PHYS; sys->io_offset = 0x400; - ret = pci_nanoengine_setup_resources(sys->resource); + ret = pci_nanoengine_setup_resources(sys); /* Enable alternate memory bus master mode, see * "Intel StrongARM SA1110 Developer's Manual", * section 10.8, "Alternate Memory Bus Master Mode". */ @@ -275,7 +268,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys) static struct hw_pci nanoengine_pci __initdata = { .map_irq = pci_nanoengine_map_irq, .nr_controllers = 1, - .scan = pci_nanoengine_scan_bus, + .ops = &pci_nano_ops, .setup = pci_nanoengine_setup, }; |