23 files changed, 2656 insertions, 201 deletions

diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 5ebec6d88b5..656d49661a2 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -1,6 +1,24 @@
 if ARCH_PXA
 
-menu "Intel PXA2xx Implementations"
+menu "Intel PXA2xx/PXA3xx Implementations"
+
+if PXA3xx
+
+menu "Supported PXA3xx Processor Variants"
+
+config CPU_PXA300
+	bool "PXA300 (codename Monahans-L)"
+
+config CPU_PXA310
+	bool "PXA310 (codename Monahans-LV)"
+	select CPU_PXA300
+
+config CPU_PXA320
+	bool "PXA320 (codename Monahans-P)"
+
+endmenu
+
+endif
 
 choice
 	prompt "Select target board"
@@ -41,6 +59,15 @@ config MACH_EM_X270
 	bool "CompuLab EM-x270 platform"
 	select PXA27x
 
+config MACH_ZYLONITE
+	bool "PXA3xx Development Platform"
+	select PXA3xx
+
+config MACH_ARMCORE
+	bool "CompuLab CM-X270 modules"
+	select PXA27x
+	select IWMMXT
+
 endchoice
 
 if PXA_SHARPSL
@@ -130,6 +157,11 @@ config PXA27x
 	help
 	  Select code specific to PXA27x variants
 
+config PXA3xx
+	bool
+	help
+	  Select code specific to PXA3xx variants
+
 config PXA_SHARP_C7xx
 	bool
 	select PXA_SSP
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 7d6ab5c59ab..4263527e512 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -3,36 +3,51 @@
 #
 
 # Common support (must be linked before board specific support)
-obj-y += clock.o generic.o irq.o dma.o time.o
-obj-$(CONFIG_PXA25x) += pxa25x.o
-obj-$(CONFIG_PXA27x) += pxa27x.o
+obj-y				+= clock.o generic.o irq.o dma.o time.o
+obj-$(CONFIG_PXA25x)		+= pxa25x.o
+obj-$(CONFIG_PXA27x)		+= pxa27x.o
+obj-$(CONFIG_PXA3xx)		+= pxa3xx.o mfp.o
+obj-$(CONFIG_CPU_PXA300)	+= pxa300.o
+obj-$(CONFIG_CPU_PXA320)	+= pxa320.o
 
 # Specific board support
-obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
+obj-$(CONFIG_ARCH_LUBBOCK)	+= lubbock.o
 obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
-obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
-obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
+obj-$(CONFIG_MACH_MAINSTONE)	+= mainstone.o
+obj-$(CONFIG_ARCH_PXA_IDP)	+= idp.o
 obj-$(CONFIG_MACH_TRIZEPS4)	+= trizeps4.o
 obj-$(CONFIG_PXA_SHARP_C7xx)	+= corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
 obj-$(CONFIG_PXA_SHARP_Cxx00)	+= spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o
 obj-$(CONFIG_MACH_AKITA)	+= akita-ioexp.o
 obj-$(CONFIG_MACH_POODLE)	+= poodle.o corgi_ssp.o
-obj-$(CONFIG_MACH_TOSA)         += tosa.o
-obj-$(CONFIG_MACH_EM_X270) += em-x270.o
+obj-$(CONFIG_MACH_TOSA)		+= tosa.o
+obj-$(CONFIG_MACH_EM_X270)	+= em-x270.o
+
+ifeq ($(CONFIG_MACH_ZYLONITE),y)
+  obj-y				+= zylonite.o
+  obj-$(CONFIG_CPU_PXA300)	+= zylonite_pxa300.o
+  obj-$(CONFIG_CPU_PXA320)	+= zylonite_pxa320.o
+endif
+
+obj-$(CONFIG_MACH_ARMCORE)      += cm-x270.o
 
 # Support for blinky lights
 led-y := leds.o
-led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
-led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o
-led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
-led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
+led-$(CONFIG_ARCH_LUBBOCK)	+= leds-lubbock.o
+led-$(CONFIG_MACH_MAINSTONE)	+= leds-mainstone.o
+led-$(CONFIG_ARCH_PXA_IDP)	+= leds-idp.o
+led-$(CONFIG_MACH_TRIZEPS4)	+= leds-trizeps4.o
 
-obj-$(CONFIG_LEDS) += $(led-y)
+obj-$(CONFIG_LEDS)		+= $(led-y)
 
 # Misc features
-obj-$(CONFIG_PM) += pm.o sleep.o
-obj-$(CONFIG_PXA_SSP) += ssp.o
+obj-$(CONFIG_PM)		+= pm.o sleep.o
+obj-$(CONFIG_PXA_SSP)		+= ssp.o
 
 ifeq ($(CONFIG_PXA27x),y)
-obj-$(CONFIG_PM) += standby.o
+obj-$(CONFIG_PM)		+= standby.o
+endif
+
+ifeq ($(CONFIG_PCI),y)
+obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
 endif
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index 34a31caa6f9..83ef5ecaf43 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -9,19 +9,15 @@
 #include <linux/string.h>
 #include <linux/clk.h>
 #include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/hardware.h>
 
-struct clk {
-	struct list_head	node;
-	unsigned long		rate;
-	struct module		*owner;
-	const char		*name;
-	unsigned int		enabled;
-	void			(*enable)(void);
-	void			(*disable)(void);
-};
+#include "devices.h"
+#include "generic.h"
+#include "clock.h"
 
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
@@ -33,7 +29,8 @@ struct clk *clk_get(struct device *dev, const char *id)
 
 	mutex_lock(&clocks_mutex);
 	list_for_each_entry(p, &clocks, node) {
-		if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
+		if (strcmp(id, p->name) == 0 &&
+		    (p->dev == NULL || p->dev == dev)) {
 			clk = p;
 			break;
 		}
@@ -46,7 +43,6 @@ EXPORT_SYMBOL(clk_get);
 
 void clk_put(struct clk *clk)
 {
-	module_put(clk->owner);
 }
 EXPORT_SYMBOL(clk_put);
 
@@ -56,8 +52,12 @@ int clk_enable(struct clk *clk)
 
 	spin_lock_irqsave(&clocks_lock, flags);
 	if (clk->enabled++ == 0)
-		clk->enable();
+		clk->ops->enable(clk);
 	spin_unlock_irqrestore(&clocks_lock, flags);
+
+	if (clk->delay)
+		udelay(clk->delay);
+
 	return 0;
 }
 EXPORT_SYMBOL(clk_enable);
@@ -70,54 +70,75 @@ void clk_disable(struct clk *clk)
 
 	spin_lock_irqsave(&clocks_lock, flags);
 	if (--clk->enabled == 0)
-		clk->disable();
+		clk->ops->disable(clk);
 	spin_unlock_irqrestore(&clocks_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 
 unsigned long clk_get_rate(struct clk *clk)
 {
-	return clk->rate;
+	unsigned long rate;
+
+	rate = clk->rate;
+	if (clk->ops->getrate)
+		rate = clk->ops->getrate(clk);
+
+	return rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
 
 
-static void clk_gpio27_enable(void)
+static void clk_gpio27_enable(struct clk *clk)
 {
 	pxa_gpio_mode(GPIO11_3_6MHz_MD);
 }
 
-static void clk_gpio27_disable(void)
+static void clk_gpio27_disable(struct clk *clk)
 {
 }
 
-static struct clk clk_gpio27 = {
-	.name		= "GPIO27_CLK",
-	.rate		= 3686400,
+static const struct clkops clk_gpio27_ops = {
 	.enable		= clk_gpio27_enable,
 	.disable	= clk_gpio27_disable,
 };
 
-int clk_register(struct clk *clk)
+
+void clk_cken_enable(struct clk *clk)
 {
-	mutex_lock(&clocks_mutex);
-	list_add(&clk->node, &clocks);
-	mutex_unlock(&clocks_mutex);
-	return 0;
+	CKEN |= 1 << clk->cken;
 }
-EXPORT_SYMBOL(clk_register);
 
-void clk_unregister(struct clk *clk)
+void clk_cken_disable(struct clk *clk)
 {
+	CKEN &= ~(1 << clk->cken);
+}
+
+const struct clkops clk_cken_ops = {
+	.enable		= clk_cken_enable,
+	.disable	= clk_cken_disable,
+};
+
+static struct clk common_clks[] = {
+	{
+		.name		= "GPIO27_CLK",
+		.ops		= &clk_gpio27_ops,
+		.rate		= 3686400,
+	},
+};
+
+void clks_register(struct clk *clks, size_t num)
+{
+	int i;
+
 	mutex_lock(&clocks_mutex);
-	list_del(&clk->node);
+	for (i = 0; i < num; i++)
+		list_add(&clks[i].node, &clocks);
 	mutex_unlock(&clocks_mutex);
 }
-EXPORT_SYMBOL(clk_unregister);
 
 static int __init clk_init(void)
 {
-	clk_register(&clk_gpio27);
+	clks_register(common_clks, ARRAY_SIZE(common_clks));
 	return 0;
 }
 arch_initcall(clk_init);
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
new file mode 100644
index 00000000000..bc6b77e1592
--- /dev/null
+++ b/arch/arm/mach-pxa/clock.h
@@ -0,0 +1,43 @@
+struct clk;
+
+struct clkops {
+	void			(*enable)(struct clk *);
+	void			(*disable)(struct clk *);
+	unsigned long		(*getrate)(struct clk *);
+};
+
+struct clk {
+	struct list_head	node;
+	const char		*name;
+	struct device		*dev;
+	const struct clkops	*ops;
+	unsigned long		rate;
+	unsigned int		cken;
+	unsigned int		delay;
+	unsigned int		enabled;
+};
+
+#define INIT_CKEN(_name, _cken, _rate, _delay, _dev)	\
+	{						\
+		.name	= _name,			\
+		.dev	= _dev,				\
+		.ops	= &clk_cken_ops,		\
+		.rate	= _rate,			\
+		.cken	= CKEN_##_cken,			\
+		.delay	= _delay,			\
+	}
+
+#define INIT_CK(_name, _cken, _ops, _dev)		\
+	{						\
+		.name	= _name,			\
+		.dev	= _dev,				\
+		.ops	= _ops,				\
+		.cken	= CKEN_##_cken,			\
+	}
+
+extern const struct clkops clk_cken_ops;
+
+void clk_cken_enable(struct clk *clk);
+void clk_cken_disable(struct clk *clk);
+
+void clks_register(struct clk *clks, size_t num);
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c
new file mode 100644
index 00000000000..878d3b9b863
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x270-pci.c
@@ -0,0 +1,218 @@
+/*
+ * linux/arch/arm/mach-pxa/cm-x270-pci.c
+ *
+ * PCI bios-type initialisation for PCI machines
+ *
+ * Bits taken from various places.
+ *
+ * Copyright (C) 2007 Compulab, Ltd.
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+
+#include <asm/mach/pci.h>
+#include <asm/arch/cm-x270.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/mach-types.h>
+
+#include <asm/hardware/it8152.h>
+
+unsigned long it8152_base_address = CMX270_IT8152_VIRT;
+
+/*
+ * Only first 64MB of memory can be accessed via PCI.
+ * We use GFP_DMA to allocate safe buffers to do map/unmap.
+ * This is really ugly and we need a better way of specifying
+ * DMA-capable regions of memory.
+ */
+void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
+	unsigned long *zhole_size)
+{
+	unsigned int sz = SZ_64M >> PAGE_SHIFT;
+
+	printk(KERN_INFO "Adjusting zones for CM-x270\n");
+
+	/*
+	 * Only adjust if > 64M on current system
+	 */
+	if (node || (zone_size[0] <= sz))
+		return;
+
+	zone_size[1] = zone_size[0] - sz;
+	zone_size[0] = sz;
+	zhole_size[1] = zhole_size[0];
+	zhole_size[0] = 0;
+}
+
+static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+	/* clear our parent irq */
+	GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ);
+
+	it8152_irq_demux(irq, desc);
+}
+
+void __cmx270_pci_init_irq(void)
+{
+	it8152_init_irq();
+	pxa_gpio_mode(IRQ_TO_GPIO(GPIO_IT8152_IRQ));
+	set_irq_type(IRQ_GPIO(GPIO_IT8152_IRQ), IRQT_RISING);
+
+	set_irq_chained_handler(IRQ_GPIO(GPIO_IT8152_IRQ),
+				cmx270_it8152_irq_demux);
+}
+
+#ifdef CONFIG_PM
+static unsigned long sleep_save_ite[10];
+
+void __cmx270_pci_suspend(void)
+{
+	/* save ITE state */
+	sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
+	sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR);
+	sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR);
+
+	/* Clear ITE IRQ's */
+	__raw_writel((0), IT8152_INTC_PDCNIRR);
+	__raw_writel((0), IT8152_INTC_LPCNIRR);
+}
+
+void __cmx270_pci_resume(void)
+{
+	/* restore IT8152 state */
+	__raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
+	__raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR);
+	__raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
+}
+#else
+void cmx270_pci_suspend(void) {}
+void cmx270_pci_resume(void) {}
+#endif
+
+/* PCI IRQ mapping*/
+static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	int irq;
+
+	printk(KERN_DEBUG "===> %s: %s slot=%x, pin=%x\n", __FUNCTION__,
+	       pci_name(dev), slot, pin);
+
+	irq = it8152_pci_map_irq(dev, slot, pin);
+	if (irq)
+		return irq;
+
+	/*
+	  Here comes the ugly part. The routing is baseboard specific,
+	  but defining a platform for each possible base of CM-x270 is
+	  unrealistic. Here we keep mapping for ATXBase and SB-x270.
+	*/
+	/* ATXBASE PCI slot */
+	if (slot == 7)
+		return IT8152_PCI_INTA;
+
+	/* ATXBase/SB-x270 CardBus */
+	if (slot == 8 || slot == 0)
+		return IT8152_PCI_INTB;
+
+	/* ATXBase Ethernet */
+	if (slot == 9)
+		return IT8152_PCI_INTA;
+
+	/* SB-x270 Ethernet */
+	if (slot == 16)
+		return IT8152_PCI_INTA;
+
+	/* PC104+ interrupt routing */
+	if ((slot == 17) || (slot == 19))
+		return IT8152_PCI_INTA;
+	if ((slot == 18) || (slot == 20))
+		return IT8152_PCI_INTB;
+
+	return(0);
+}
+
+static struct pci_bus * __init
+cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys)
+{
+	printk(KERN_INFO "Initializing CM-X270 PCI subsystem\n");
+
+	__raw_writel(0x800, IT8152_PCI_CFG_ADDR);
+	if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
+		printk(KERN_INFO "PCI Bridge found.\n");
+
+		/* set PCI I/O base at 0 */
+		writel(0x848, IT8152_PCI_CFG_ADDR);
+		writel(0, IT8152_PCI_CFG_DATA);
+
+		/* set PCI memory base at 0 */
+		writel(0x840, IT8152_PCI_CFG_ADDR);
+		writel(0, IT8152_PCI_CFG_DATA);
+
+		writel(0x20, IT8152_GPIO_GPDR);
+
+		/* CardBus Controller on ATXbase baseboard */
+		writel(0x4000, IT8152_PCI_CFG_ADDR);
+		if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) {
+			printk(KERN_INFO "CardBus Bridge found.\n");
+
+			/* Configure socket 0 */
+			writel(0x408C, IT8152_PCI_CFG_ADDR);
+			writel(0x1022, IT8152_PCI_CFG_DATA);
+
+			writel(0x4080, IT8152_PCI_CFG_ADDR);
+			writel(0x3844d060, IT8152_PCI_CFG_DATA);
+
+			writel(0x4090, IT8152_PCI_CFG_ADDR);
+			writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
+				0x60440000),
+			       IT8152_PCI_CFG_DATA);
+
+			writel(0x4018, IT8152_PCI_CFG_ADDR);
+			writel(0xb0000000, IT8152_PCI_CFG_DATA);
+
+			/* Configure socket 1 */
+			writel(0x418C, IT8152_PCI_CFG_ADDR);
+			writel(0x1022, IT8152_PCI_CFG_DATA);
+
+			writel(0x4180, IT8152_PCI_CFG_ADDR);
+			writel(0x3844d060, IT8152_PCI_CFG_DATA);
+
+			writel(0x4190, IT8152_PCI_CFG_ADDR);
+			writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
+				0x60440000),
+			       IT8152_PCI_CFG_DATA);
+
+			writel(0x4118, IT8152_PCI_CFG_ADDR);
+			writel(0xb0000000, IT8152_PCI_CFG_DATA);
+		}
+	}
+	return it8152_pci_scan_bus(nr, sys);
+}
+
+static struct hw_pci cmx270_pci __initdata = {
+	.swizzle	= pci_std_swizzle,
+	.map_irq	= cmx270_pci_map_irq,
+	.nr_controllers	= 1,
+	.setup		= it8152_pci_setup,
+	.scan		= cmx270_pci_scan_bus,
+};
+
+static int __init cmx270_init_pci(void)
+{
+	if (machine_is_armcore())
+		pci_common_init(&cmx270_pci);
+
+	return 0;
+}
+
+subsys_initcall(cmx270_init_pci);
diff --git a/arch/arm/mach-pxa/cm-x270-pci.h b/arch/arm/mach-pxa/cm-x270-pci.h
new file mode 100644
index 00000000000..ffe37b66f9a
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x270-pci.h
@@ -0,0 +1,13 @@
+extern void __cmx270_pci_init_irq(void);
+extern void __cmx270_pci_suspend(void);
+extern void __cmx270_pci_resume(void);
+
+#ifdef CONFIG_PCI
+#define cmx270_pci_init_irq __cmx270_pci_init_irq
+#define cmx270_pci_suspend __cmx270_pci_suspend
+#define cmx270_pci_resume __cmx270_pci_resume
+#else
+#define cmx270_pci_init_irq() do {} while (0)
+#define cmx270_pci_suspend() do {} while (0)
+#define cmx270_pci_resume() do {} while (0)
+#endif
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
new file mode 100644
index 00000000000..177664ccb2e
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -0,0 +1,645 @@
+/*
+ * linux/arch/arm/mach-pxa/cm-x270.c
+ *
+ * Copyright (C) 2007 CompuLab, Ltd.
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include <linux/pm.h>
+#include <linux/fb.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <linux/dm9000.h>
+#include <linux/rtc-v3020.h>
+#include <linux/serial_8250.h>
+
+#include <video/mbxfb.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxafb.h>
+#include <asm/arch/ohci.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/bitfield.h>
+#include <asm/arch/cm-x270.h>
+
+#include <asm/hardware/it8152.h>
+
+#include "generic.h"
+#include "cm-x270-pci.h"
+
+#define RTC_PHYS_BASE		(PXA_CS1_PHYS + (5 << 22))
+#define DM9000_PHYS_BASE	(PXA_CS1_PHYS + (6 << 22))
+
+static struct resource cmx270_dm9k_resource[] = {
+	[0] = {
+		.start = DM9000_PHYS_BASE,
+		.end   = DM9000_PHYS_BASE + 4,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = DM9000_PHYS_BASE + 8,
+		.end   = DM9000_PHYS_BASE + 8 + 500,
+		.flags = IORESOURCE_MEM,
+	},
+	[2] = {
+		.start = CMX270_ETHIRQ,
+		.end   = CMX270_ETHIRQ,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+
+/* for the moment we limit ourselves to 32bit IO until some
+ * better IO routines can be written and tested
+ */
+static struct dm9000_plat_data cmx270_dm9k_platdata = {
+	.flags		= DM9000_PLATF_32BITONLY,
+};
+
+/* Ethernet device */
+static struct platform_device cmx270_device_dm9k = {
+	.name		= "dm9000",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(cmx270_dm9k_resource),
+	.resource	= cmx270_dm9k_resource,
+	.dev		= {
+		.platform_data = &cmx270_dm9k_platdata,
+	}
+};
+
+/* audio device */
+static struct platform_device cmx270_audio_device = {
+	.name		= "pxa2xx-ac97",
+	.id		= -1,
+};
+
+/* touchscreen controller */
+static struct platform_device cmx270_ts_device = {
+	.name		= "ucb1400_ts",
+	.id		= -1,
+};
+
+/* RTC */
+static struct resource cmx270_v3020_resource[] = {
+	[0] = {
+		.start = RTC_PHYS_BASE,
+		.end   = RTC_PHYS_BASE + 4,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct v3020_platform_data cmx270_v3020_pdata = {
+	.leftshift = 16,
+};
+
+static struct platform_device cmx270_rtc_device = {
+	.name		= "v3020",
+	.num_resources	= ARRAY_SIZE(cmx270_v3020_resource),
+	.resource	= cmx270_v3020_resource,
+	.id		= -1,
+	.dev		= {
+		.platform_data = &cmx270_v3020_pdata,
+	}
+};
+
+/*
+ * CM-X270 LEDs
+ */
+static struct platform_device cmx270_led_device = {
+	.name		= "cm-x270-led",
+	.id		= -1,
+};
+
+/* 2700G graphics */
+static u64 fb_dma_mask = ~(u64)0;
+
+static struct resource cmx270_2700G_resource[] = {
+	/* frame buffer memory including ODFB and External SDRAM */
+	[0] = {
+		.start = MARATHON_PHYS,
+		.end   = MARATHON_PHYS + 0x02000000,
+		.flags = IORESOURCE_MEM,
+	},
+	/* Marathon registers */
+	[1] = {
+		.start = MARATHON_PHYS + 0x03fe0000,
+		.end   = MARATHON_PHYS + 0x03ffffff,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static unsigned long save_lcd_regs[10];
+
+static int cmx270_marathon_probe(struct fb_info *fb)
+{
+	/* save PXA-270 pin settings before enabling 2700G */
+	save_lcd_regs[0] = GPDR1;
+	save_lcd_regs[1] = GPDR2;
+	save_lcd_regs[2] = GAFR1_U;
+	save_lcd_regs[3] = GAFR2_L;
+	save_lcd_regs[4] = GAFR2_U;
+
+	/* Disable PXA-270 on-chip controller driving pins */
+	GPDR1 &= ~(0xfc000000);
+	GPDR2 &= ~(0x00c03fff);
+	GAFR1_U &= ~(0xfff00000);
+	GAFR2_L &= ~(0x0fffffff);
+	GAFR2_U &= ~(0x0000f000);
+	return 0;
+}
+
+static int cmx270_marathon_remove(struct fb_info *fb)
+{
+	GPDR1 =   save_lcd_regs[0];
+	GPDR2 =   save_lcd_regs[1];
+	GAFR1_U = save_lcd_regs[2];
+	GAFR2_L = save_lcd_regs[3];
+	GAFR2_U = save_lcd_regs[4];
+	return 0;
+}
+
+static struct mbxfb_platform_data cmx270_2700G_data = {
+	.xres = {
+		.min = 240,
+		.max = 1200,
+		.defval = 640,
+	},
+	.yres = {
+		.min = 240,
+		.max = 1200,
+		.defval = 480,
+	},
+	.bpp = {
+		.min = 16,
+		.max = 32,
+		.defval = 16,
+	},
+	.memsize = 8*1024*1024,
+	.probe = cmx270_marathon_probe,
+	.remove = cmx270_marathon_remove,
+};
+
+static struct platform_device cmx270_2700G = {
+	.name		= "mbx-fb",
+	.dev		= {
+		.platform_data	= &cmx270_2700G_data,
+		.dma_mask	= &fb_dma_mask,
+		.coherent_dma_mask = 0xffffffff,
+	},
+	.num_resources	= ARRAY_SIZE(cmx270_2700G_resource),
+	.resource	= cmx270_2700G_resource,
+	.id		= -1,
+};
+
+static u64 ata_dma_mask = ~(u64)0;
+
+static struct platform_device cmx270_ata = {
+	.name = "pata_cm_x270",
+	.id = -1,
+	.dev		= {
+		.dma_mask	= &ata_dma_mask,
+		.coherent_dma_mask = 0xffffffff,
+	},
+};
+
+/* platform devices */
+static struct platform_device *platform_devices[] __initdata = {
+	&cmx270_device_dm9k,
+	&cmx270_audio_device,
+	&cmx270_rtc_device,
+	&cmx270_2700G,
+	&cmx270_led_device,
+	&cmx270_ts_device,
+	&cmx270_ata,
+};
+
+/* Map PCI companion and IDE/General Purpose CS statically */
+static struct map_desc cmx270_io_desc[] __initdata = {
+	[0] = { /* IDE/general purpose space */
+		.virtual	= CMX270_IDE104_VIRT,
+		.pfn		= __phys_to_pfn(CMX270_IDE104_PHYS),
+		.length		= SZ_64M - SZ_8M,
+		.type		= MT_DEVICE
+	},
+	[1] = { /* PCI bridge */
+		.virtual	= CMX270_IT8152_VIRT,
+		.pfn		= __phys_to_pfn(CMX270_IT8152_PHYS),
+		.length		= SZ_64M,
+		.type		= MT_DEVICE
+	},
+};
+
+/*
+  Display definitions
+  keep these for backwards compatibility, although symbolic names (as
+  e.g. in lpd270.c) looks better
+*/
+#define MTYPE_STN320x240	0
+#define MTYPE_TFT640x480	1
+#define MTYPE_CRT640x480	2
+#define MTYPE_CRT800x600	3
+#define MTYPE_TFT320x240	6
+#define MTYPE_STN640x480	7
+
+static struct pxafb_mode_info generic_stn_320x240_mode = {
+	.pixclock	= 76923,
+	.bpp		= 8,
+	.xres		= 320,
+	.yres		= 240,
+	.hsync_len	= 3,
+	.vsync_len	= 2,
+	.left_margin	= 3,
+	.upper_margin	= 0,
+	.right_margin	= 3,
+	.lower_margin	= 0,
+	.sync		= (FB_SYNC_HOR_HIGH_ACT |
+			   FB_SYNC_VERT_HIGH_ACT),
+	.cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_stn_320x240 = {
+	.modes		= &generic_stn_320x240_mode,
+	.num_modes	= 1,
+	.lccr0		= 0,
+	.lccr3		= (LCCR3_PixClkDiv(0x03) |
+			   LCCR3_Acb(0xff) |
+			   LCCR3_PCP),
+	.cmap_inverse	= 0,
+	.cmap_static	= 0,
+};
+
+static struct pxafb_mode_info generic_tft_640x480_mode = {
+	.pixclock	= 38461,
+	.bpp		= 8,
+	.xres		= 640,
+	.yres		= 480,
+	.hsync_len	= 60,
+	.vsync_len	= 2,
+	.left_margin	= 70,
+	.upper_margin	= 10,
+	.right_margin	= 70,
+	.lower_margin	= 5,
+	.sync		= 0,
+	.cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_tft_640x480 = {
+	.modes		= &generic_tft_640x480_mode,
+	.num_modes	= 1,
+	.lccr0		= (LCCR0_PAS),
+	.lccr3		= (LCCR3_PixClkDiv(0x01) |
+			   LCCR3_Acb(0xff) |
+			   LCCR3_PCP),
+	.cmap_inverse	= 0,
+	.cmap_static	= 0,
+};
+
+static struct pxafb_mode_info generic_crt_640x480_mode = {
+	.pixclock	= 38461,
+	.bpp		= 8,
+	.xres		= 640,
+	.yres		= 480,
+	.hsync_len	= 63,
+	.vsync_len	= 2,
+	.left_margin	= 81,
+	.upper_margin	= 33,
+	.right_margin	= 16,
+	.lower_margin	= 10,
+	.sync		= (FB_SYNC_HOR_HIGH_ACT |
+			   FB_SYNC_VERT_HIGH_ACT),
+	.cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_crt_640x480 = {
+	.modes		= &generic_crt_640x480_mode,
+	.num_modes	= 1,
+	.lccr0		= (LCCR0_PAS),
+	.lccr3		= (LCCR3_PixClkDiv(0x01) |
+			   LCCR3_Acb(0xff)),
+	.cmap_inverse	= 0,
+	.cmap_static	= 0,
+};
+
+static struct pxafb_mode_info generic_crt_800x600_mode = {
+	.pixclock	= 28846,
+	.bpp		= 8,
+	.xres		= 800,
+	.yres	  	= 600,
+	.hsync_len	= 63,
+	.vsync_len	= 2,
+	.left_margin	= 26,
+	.upper_margin	= 21,
+	.right_margin	= 26,
+	.lower_margin	= 11,
+	.sync		= (FB_SYNC_HOR_HIGH_ACT |
+			   FB_SYNC_VERT_HIGH_ACT),
+	.cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_crt_800x600 = {
+	.modes		= &generic_crt_800x600_mode,
+	.num_modes	= 1,
+	.lccr0		= (LCCR0_PAS),
+	.lccr3		= (LCCR3_PixClkDiv(0x02) |
+			   LCCR3_Acb(0xff)),
+	.cmap_inverse	= 0,
+	.cmap_static	= 0,
+};
+
+static struct pxafb_mode_info generic_tft_320x240_mode = {
+	.pixclock	= 134615,
+	.bpp		= 16,
+	.xres		= 320,
+	.yres		= 240,
+	.hsync_len	= 63,
+	.vsync_len	= 7,
+	.left_margin	= 75,
+	.upper_margin	= 0,
+	.right_margin	= 15,
+	.lower_margin	= 15,
+	.sync		= 0,
+	.cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_tft_320x240 = {
+	.modes		= &generic_tft_320x240_mode,
+	.num_modes	= 1,
+	.lccr0		= (LCCR0_PAS),
+	.lccr3		= (LCCR3_PixClkDiv(0x06) |
+			   LCCR3_Acb(0xff) |
+			   LCCR3_PCP),
+	.cmap_inverse	= 0,
+	.cmap_static	= 0,
+};
+
+static struct pxafb_mode_info generic_stn_640x480_mode = {
+	.pixclock	= 57692,
+	.bpp		= 8,
+	.xres		= 640,
+	.yres		= 480,
+	.hsync_len	= 4,
+	.vsync_len	= 2,
+	.left_margin	= 10,
+	.upper_margin	= 5,
+	.right_margin	= 10,
+	.lower_margin	= 5,
+	.sync		= (FB_SYNC_HOR_HIGH_ACT |
+			   FB_SYNC_VERT_HIGH_ACT),
+	.cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_stn_640x480 = {
+	.modes		= &generic_stn_640x480_mode,
+	.num_modes	= 1,
+	.lccr0		= 0,
+	.lccr3		= (LCCR3_PixClkDiv(0x02) |
+			   LCCR3_Acb(0xff)),
+	.cmap_inverse	= 0,
+	.cmap_static	= 0,
+};
+
+static struct pxafb_mach_info *cmx270_display = &generic_crt_640x480;
+
+static int __init cmx270_set_display(char *str)
+{
+	int disp_type = simple_strtol(str, NULL, 0);
+	switch (disp_type) {
+	case MTYPE_STN320x240:
+		cmx270_display = &generic_stn_320x240;
+		break;
+	case MTYPE_TFT640x480:
+		cmx270_display = &generic_tft_640x480;
+		break;
+	case MTYPE_CRT640x480:
+		cmx270_display = &generic_crt_640x480;
+		break;
+	case MTYPE_CRT800x600:
+		cmx270_display = &generic_crt_800x600;
+		break;
+	case MTYPE_TFT320x240:
+		cmx270_display = &generic_tft_320x240;
+		break;
+	case MTYPE_STN640x480:
+		cmx270_display = &generic_stn_640x480;
+		break;
+	default: /* fallback to CRT 640x480 */
+		cmx270_display = &generic_crt_640x480;
+		break;
+	}
+	return 1;
+}
+
+/*
+   This should be done really early to get proper configuration for
+   frame buffer.
+   Indeed, pxafb parameters can be used istead, but CM-X270 bootloader
+   has limitied line length for kernel command line, and also it will
+   break compatibitlty with proprietary releases already in field.
+*/
+__setup("monitor=", cmx270_set_display);
+
+/* PXA27x OHCI controller setup */
+static int cmx270_ohci_init(struct device *dev)
+{
+	/* Set the Power Control Polarity Low */
+	UHCHR = (UHCHR | UHCHR_PCPL) &
+		~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+
+	return 0;
+}
+
+static struct pxaohci_platform_data cmx270_ohci_platform_data = {
+	.port_mode	= PMM_PERPORT_MODE,
+	.init		= cmx270_ohci_init,
+};
+
+
+static int cmx270_mci_init(struct device *dev,
+			   irq_handler_t cmx270_detect_int,
+			   void *data)
+{
+	int err;
+
+	/*
+	 * setup GPIO for PXA27x MMC controller
+	 */
+	pxa_gpio_mode(GPIO32_MMCCLK_MD);
+	pxa_gpio_mode(GPIO112_MMCCMD_MD);
+	pxa_gpio_mode(GPIO92_MMCDAT0_MD);
+	pxa_gpio_mode(GPIO109_MMCDAT1_MD);
+	pxa_gpio_mode(GPIO110_MMCDAT2_MD);
+	pxa_gpio_mode(GPIO111_MMCDAT3_MD);
+
+	/* SB-X270 uses GPIO105 as SD power enable */
+	pxa_gpio_mode(105 | GPIO_OUT);
+
+	/* card detect IRQ on GPIO 83 */
+	pxa_gpio_mode(IRQ_TO_GPIO(CMX270_MMC_IRQ));
+	set_irq_type(CMX270_MMC_IRQ, IRQT_FALLING);