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-rw-r--r--arch/arm/mach-mxc91231/Kconfig11
-rw-r--r--arch/arm/mach-mxc91231/Makefile2
-rw-r--r--arch/arm/mach-mxc91231/Makefile.boot3
-rw-r--r--arch/arm/mach-mxc91231/clock.c642
-rw-r--r--arch/arm/mach-mxc91231/crm_regs.h399
-rw-r--r--arch/arm/mach-mxc91231/devices.c251
-rw-r--r--arch/arm/mach-mxc91231/devices.h13
-rw-r--r--arch/arm/mach-mxc91231/iomux.c177
-rw-r--r--arch/arm/mach-mxc91231/magx-zn5.c63
-rw-r--r--arch/arm/mach-mxc91231/mm.c94
-rw-r--r--arch/arm/mach-mxc91231/system.c51
11 files changed, 1706 insertions, 0 deletions
diff --git a/arch/arm/mach-mxc91231/Kconfig b/arch/arm/mach-mxc91231/Kconfig
new file mode 100644
index 00000000000..8e5fa38ebb6
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MXC91231
+
+comment "MXC91231 platforms:"
+
+config MACH_MAGX_ZN5
+ bool "Support Motorola Zn5 GSM phone"
+ default n
+ help
+ Include support for Motorola Zn5 GSM phone.
+
+endif
diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile
new file mode 100644
index 00000000000..011d5e19712
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile
@@ -0,0 +1,2 @@
+obj-y := mm.o clock.o devices.o system.o iomux.o
+obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
diff --git a/arch/arm/mach-mxc91231/Makefile.boot b/arch/arm/mach-mxc91231/Makefile.boot
new file mode 100644
index 00000000000..9939a19d99a
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile.boot
@@ -0,0 +1,3 @@
+ zreladdr-y := 0x90008000
+params_phys-y := 0x90000100
+initrd_phys-y := 0x90800000
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
new file mode 100644
index 00000000000..ecfa37fef8a
--- /dev/null
+++ b/arch/arm/mach-mxc91231/clock.c
@@ -0,0 +1,642 @@
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#include <asm/clkdev.h>
+#include <asm/bug.h>
+#include <asm/div64.h>
+
+#include "crm_regs.h"
+
+#define CRM_SMALL_DIVIDER(base, name) \
+ crm_small_divider(base, \
+ base ## _ ## name ## _OFFSET, \
+ base ## _ ## name ## _MASK)
+#define CRM_1DIVIDER(base, name) \
+ crm_divider(base, \
+ base ## _ ## name ## _OFFSET, \
+ base ## _ ## name ## _MASK, 1)
+#define CRM_16DIVIDER(base, name) \
+ crm_divider(base, \
+ base ## _ ## name ## _OFFSET, \
+ base ## _ ## name ## _MASK, 16)
+
+static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
+{
+ static const u32 crm_small_dividers[] = {
+ 2, 3, 4, 5, 6, 8, 10, 12
+ };
+ u8 idx;
+
+ idx = (__raw_readl(reg) & mask) >> offset;
+ if (idx > 7)
+ return 1;
+
+ return crm_small_dividers[idx];
+}
+
+static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
+{
+ u32 div;
+ div = (__raw_readl(reg) & mask) >> offset;
+ return div ? div : z;
+}
+
+static int _clk_1bit_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg |= 1 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
+ return 0;
+}
+
+static void _clk_1bit_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(1 << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_3bit_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg |= 0x7 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
+ return 0;
+}
+
+static void _clk_3bit_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(0x7 << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+}
+
+static unsigned long ckih_rate;
+
+static unsigned long clk_ckih_get_rate(struct clk *clk)
+{
+ return ckih_rate;
+}
+
+static struct clk ckih_clk = {
+ .get_rate = clk_ckih_get_rate,
+};
+
+static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
+{
+ return 2 * clk_get_rate(clk->parent);
+}
+
+static struct clk ckih_x2_clk = {
+ .parent = &ckih_clk,
+ .get_rate = clk_ckih_x2_get_rate,
+};
+
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+ return CKIL_CLK_FREQ;
+}
+
+static struct clk ckil_clk = {
+ .get_rate = clk_ckil_get_rate,
+};
+
+/* plls stuff */
+static struct clk mcu_pll_clk;
+static struct clk dsp_pll_clk;
+static struct clk usb_pll_clk;
+
+static struct clk *pll_clk(u8 sel)
+{
+ switch (sel) {
+ case 0:
+ return &mcu_pll_clk;
+ case 1:
+ return &dsp_pll_clk;
+ case 2:
+ return &usb_pll_clk;
+ }
+ BUG();
+}
+
+static void __iomem *pll_base(struct clk *clk)
+{
+ if (clk == &mcu_pll_clk)
+ return MXC_PLL0_BASE;
+ else if (clk == &dsp_pll_clk)
+ return MXC_PLL1_BASE;
+ else if (clk == &usb_pll_clk)
+ return MXC_PLL2_BASE;
+ BUG();
+}
+
+static unsigned long clk_pll_get_rate(struct clk *clk)
+{
+ const void __iomem *pllbase;
+ unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
+ long mfn, mfn_abs, mfd, pdf;
+ s64 temp;
+ pllbase = pll_base(clk);
+
+ pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
+ if (pll_hfsm == 0) {
+ dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+ dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+ dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+ } else {
+ dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+ dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+ dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+ }
+
+ pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+ mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
+ mfi = (mfi <= 5) ? 5 : mfi;
+ mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+ mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
+ mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
+
+ if (mfn < 0)
+ mfn_abs = -mfn;
+ else
+ mfn_abs = mfn;
+
+/* XXX: actually this asumes that ckih is fed to pll, but spec says
+ * that ckih_x2 is also possible. need to check this out.
+ */
+ ref_clk = clk_get_rate(&ckih_clk);
+
+ ref_clk *= 2;
+ ref_clk /= pdf + 1;
+
+ temp = (u64) ref_clk * mfn_abs;
+ do_div(temp, mfd);
+ if (mfn < 0)
+ temp = -temp;
+ temp += ref_clk * mfi;
+
+ return temp;
+}
+
+static int clk_pll_enable(struct clk *clk)
+{
+ void __iomem *ctl;
+ u32 reg;
+
+ ctl = pll_base(clk);
+ reg = __raw_readl(ctl);
+ reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
+ __raw_writel(reg, ctl);
+ do {
+ reg = __raw_readl(ctl);
+ } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
+ return 0;
+}
+
+static void clk_pll_disable(struct clk *clk)
+{
+ void __iomem *ctl;
+ u32 reg;
+
+ ctl = pll_base(clk);
+ reg = __raw_readl(ctl);
+ reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
+ __raw_writel(reg, ctl);
+}
+
+static struct clk mcu_pll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = clk_pll_get_rate,
+ .enable = clk_pll_enable,
+ .disable = clk_pll_disable,
+};
+
+static struct clk dsp_pll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = clk_pll_get_rate,
+ .enable = clk_pll_enable,
+ .disable = clk_pll_disable,
+};
+
+static struct clk usb_pll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = clk_pll_get_rate,
+ .enable = clk_pll_enable,
+ .disable = clk_pll_disable,
+};
+/* plls stuff end */
+
+/* ap_ref_clk stuff */
+static struct clk ap_ref_clk;
+
+static unsigned long clk_ap_ref_get_rate(struct clk *clk)
+{
+ u32 ascsr, acsr;
+ u8 ap_pat_ref_div_2, ap_isel, acs, ads;
+
+ ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+ acsr = __raw_readl(MXC_CRMAP_ACSR);
+
+ /* 0 for ckih, 1 for ckih*2 */
+ ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
+ /* reg divider */
+ ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
+ /* undocumented, 1 for disabling divider */
+ ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
+ /* 0 for pat_ref, 1 for divider out */
+ acs = acsr & MXC_CRMAP_ACSR_ACS;
+
+ if (acs & !ads)
+ /* use divided clock */
+ return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
+
+ return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
+}
+
+static struct clk ap_ref_clk = {
+ .parent = &ckih_clk,
+ .get_rate = clk_ap_ref_get_rate,
+};
+/* ap_ref_clk stuff end */
+
+/* ap_pre_dfs_clk stuff */
+static struct clk ap_pre_dfs_clk;
+
+static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
+{
+ u32 acsr, ascsr;
+
+ acsr = __raw_readl(MXC_CRMAP_ACSR);
+ ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+
+ if (acsr & MXC_CRMAP_ACSR_ACS) {
+ u8 sel;
+ sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
+ MXC_CRMAP_ASCSR_APSEL_OFFSET;
+ return clk_get_rate(pll_clk(sel)) /
+ CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
+ }
+ return clk_get_rate(&ap_ref_clk);
+}
+
+static struct clk ap_pre_dfs_clk = {
+ .get_rate = clk_ap_pre_dfs_get_rate,
+};
+/* ap_pre_dfs_clk stuff end */
+
+/* usb_clk stuff */
+static struct clk usb_clk;
+
+static struct clk *clk_usb_parent(struct clk *clk)
+{
+ u32 acsr, ascsr;
+
+ acsr = __raw_readl(MXC_CRMAP_ACSR);
+ ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+
+ if (acsr & MXC_CRMAP_ACSR_ACS) {
+ u8 sel;
+ sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
+ MXC_CRMAP_ASCSR_USBSEL_OFFSET;
+ return pll_clk(sel);
+ }
+ return &ap_ref_clk;
+}
+
+static unsigned long clk_usb_get_rate(struct clk *clk)
+{
+ return clk_get_rate(clk->parent) /
+ CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
+}
+
+static struct clk usb_clk = {
+ .enable_reg = MXC_CRMAP_ACDER2,
+ .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
+ .get_rate = clk_usb_get_rate,
+ .enable = _clk_1bit_enable,
+ .disable = _clk_1bit_disable,
+};
+/* usb_clk stuff end */
+
+static unsigned long clk_ipg_get_rate(struct clk *clk)
+{
+ return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
+}
+
+static unsigned long clk_ahb_get_rate(struct clk *clk)
+{
+ return clk_get_rate(clk->parent) /
+ CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
+}
+
+static struct clk ipg_clk = {
+ .parent = &ap_pre_dfs_clk,
+ .get_rate = clk_ipg_get_rate,
+};
+
+static struct clk ahb_clk = {
+ .parent = &ap_pre_dfs_clk,
+ .get_rate = clk_ahb_get_rate,
+};
+
+/* perclk_clk stuff */
+static struct clk perclk_clk;
+
+static unsigned long clk_perclk_get_rate(struct clk *clk)
+{
+ u32 acder2;
+
+ acder2 = __raw_readl(MXC_CRMAP_ACDER2);
+ if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
+ return 2 * clk_get_rate(clk->parent);
+
+ return clk_get_rate(clk->parent);
+}
+
+static struct clk perclk_clk = {
+ .parent = &ckih_clk,
+ .get_rate = clk_perclk_get_rate,
+};
+/* perclk_clk stuff end */
+
+/* uart_clk stuff */
+static struct clk uart_clk[];
+
+static unsigned long clk_uart_get_rate(struct clk *clk)
+{
+ u32 div;
+
+ switch (clk->id) {
+ case 0:
+ case 1:
+ div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
+ break;
+ case 2:
+ div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
+ break;
+ default:
+ BUG();
+ }
+ return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk uart_clk[] = {
+ {
+ .id = 0,
+ .parent = &perclk_clk,
+ .enable_reg = MXC_CRMAP_APRA,
+ .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
+ .get_rate = clk_uart_get_rate,
+ .enable = _clk_1bit_enable,
+ .disable = _clk_1bit_disable,
+ }, {
+ .id = 1,
+ .parent = &perclk_clk,
+ .enable_reg = MXC_CRMAP_APRA,
+ .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
+ .get_rate = clk_uart_get_rate,
+ .enable = _clk_1bit_enable,
+ .disable = _clk_1bit_disable,
+ }, {
+ .id = 2,
+ .parent = &perclk_clk,
+ .enable_reg = MXC_CRMAP_APRA,
+ .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
+ .get_rate = clk_uart_get_rate,
+ .enable = _clk_1bit_enable,
+ .disable = _clk_1bit_disable,
+ },
+};
+/* uart_clk stuff end */
+
+/* sdhc_clk stuff */
+static struct clk nfc_clk;
+
+static unsigned long clk_nfc_get_rate(struct clk *clk)
+{
+ return clk_get_rate(clk->parent) /
+ CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
+}
+
+static struct clk nfc_clk = {
+ .parent = &ahb_clk,
+ .enable_reg = MXC_CRMAP_ACDER2,
+ .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
+ .get_rate = clk_nfc_get_rate,
+ .enable = _clk_1bit_enable,
+ .disable = _clk_1bit_disable,
+};
+/* sdhc_clk stuff end */
+
+/* sdhc_clk stuff */
+static struct clk sdhc_clk[];
+
+static struct clk *clk_sdhc_parent(struct clk *clk)
+{
+ u32 aprb;
+ u8 sel;
+ u32 mask;
+ int offset;
+
+ aprb = __raw_readl(MXC_CRMAP_APRB);
+
+ switch (clk->id) {
+ case 0:
+ mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
+ offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
+ break;
+ case 1:
+ mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
+ offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
+ break;
+ default:
+ BUG();
+ }
+ sel = (aprb & mask) >> offset;
+
+ switch (sel) {
+ case 0:
+ return &ckih_clk;
+ case 1:
+ return &ckih_x2_clk;
+ }
+ return &usb_clk;
+}
+
+static unsigned long clk_sdhc_get_rate(struct clk *clk)
+{
+ u32 div;
+
+ switch (clk->id) {
+ case 0:
+ div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
+ break;
+ case 1:
+ div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
+ break;
+ default:
+ BUG();
+ }
+
+ return clk_get_rate(clk->parent) / div;
+}
+
+static int clk_sdhc_enable(struct clk *clk)
+{
+ u32 amlpmre1, aprb;
+
+ amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
+ aprb = __raw_readl(MXC_CRMAP_APRB);
+ switch (clk->id) {
+ case 0:
+ amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
+ aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
+ break;
+ case 1:
+ amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
+ aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
+ break;
+ }
+ __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
+ __raw_writel(aprb, MXC_CRMAP_APRB);
+ return 0;
+}
+
+static void clk_sdhc_disable(struct clk *clk)
+{
+ u32 amlpmre1, aprb;
+
+ amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
+ aprb = __raw_readl(MXC_CRMAP_APRB);
+ switch (clk->id) {
+ case 0:
+ amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
+ aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
+ break;
+ case 1:
+ amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
+ aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
+ break;
+ }
+ __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
+ __raw_writel(aprb, MXC_CRMAP_APRB);
+}
+
+static struct clk sdhc_clk[] = {
+ {
+ .id = 0,
+ .get_rate = clk_sdhc_get_rate,
+ .enable = clk_sdhc_enable,
+ .disable = clk_sdhc_disable,
+ }, {
+ .id = 1,
+ .get_rate = clk_sdhc_get_rate,
+ .enable = clk_sdhc_enable,
+ .disable = clk_sdhc_disable,
+ },
+};
+/* sdhc_clk stuff end */
+
+/* wdog_clk stuff */
+static struct clk wdog_clk[] = {
+ {
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CRMAP_AMLPMRD,
+ .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
+ .enable = _clk_3bit_enable,
+ .disable = _clk_3bit_disable,
+ }, {
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CRMAP_AMLPMRD,
+ .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
+ .enable = _clk_3bit_enable,
+ .disable = _clk_3bit_disable,
+ },
+};
+/* wdog_clk stuff end */
+
+/* gpt_clk stuff */
+static struct clk gpt_clk = {
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CRMAP_AMLPMRC,
+ .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
+ .enable = _clk_3bit_enable,
+ .disable = _clk_3bit_disable,
+};
+/* gpt_clk stuff end */
+
+/* cspi_clk stuff */
+static struct clk cspi_clk[] = {
+ {
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CRMAP_AMLPMRE2,
+ .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
+ .enable = _clk_3bit_enable,
+ .disable = _clk_3bit_disable,
+ }, {
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CRMAP_AMLPMRE1,
+ .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
+ .enable = _clk_3bit_enable,
+ .disable = _clk_3bit_disable,
+ },
+};
+/* cspi_clk stuff end */
+
+#define _REGISTER_CLOCK(d, n, c) \
+ { \
+ .dev_id = d, \
+ .con_id = n, \
+ .clk = &c, \
+ },
+
+static struct clk_lookup lookups[] = {
+ _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
+ _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
+ _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
+ _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
+ _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
+ _REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
+ _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
+ _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
+};
+
+int __init mxc91231_clocks_init(unsigned long fref)
+{
+ void __iomem *gpt_base;
+ int i;
+
+ ckih_rate = fref;
+
+ usb_clk.parent = clk_usb_parent(&usb_clk);
+ sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
+ sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
+
+ for (i = 0; i < ARRAY_SIZE(lookups); i++)
+ clkdev_add(&lookups[i]);
+
+ gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
+ mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
+
+ return 0;
+}
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
new file mode 100644
index 00000000000..ce4f5905818
--- /dev/null
+++ b/arch/arm/mach-mxc91231/crm_regs.h
@@ -0,0 +1,399 @@
+/*
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ * Copyright 2006-2007 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
+#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
+
+#define CKIL_CLK_FREQ 32768
+
+#define MXC_CRM_AP_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
+#define MXC_CRM_COM_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
+#define MXC_DSM_BASE MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
+#define MXC_PLL0_BASE MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
+#define MXC_PLL1_BASE MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
+#define MXC_PLL2_BASE MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
+#define MXC_CLKCTL_BASE MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL 0x00
+#define MXC_PLL_DP_CONFIG 0x04
+#define MXC_PLL_DP_OP 0x08
+#define MXC_PLL_DP_MFD 0x0C
+#define MXC_PLL_DP_MFN 0x10
+#define MXC_PLL_DP_HFS_OP 0x1C
+#define MXC_PLL_DP_HFS_MFD 0x20
+#define MXC_PLL_DP_HFS_MFN 0x24
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
+#define MXC_PLL_DP_CTL_ADE 0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
+#define MXC_PLL_DP_CTL_HFSM 0x80
+#define MXC_PLL_DP_CTL_PRE 0x40
+#define MXC_PLL_DP_CTL_UPEN 0x20
+#define MXC_PLL_DP_CTL_RST 0x10
+#define MXC_PLL_DP_CTL_RCP 0x8
+#define MXC_PLL_DP_CTL_PLM 0x4
+#define MXC_PLL_DP_CTL_BRM0 0x2
+#define MXC_PLL_DP_CTL_LRF 0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET 4
+#define MXC_PLL_DP_OP_MFI_MASK 0xF
+#define MXC_PLL_DP_OP_PDF_OFFSET 0
+#define MXC_PLL_DP_OP_PDF_MASK 0xF
+
+#define MXC_PLL_DP_MFD_OFFSET 0
+#define MXC_PLL_DP_MFD_MASK 0x7FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET 0
+#define MXC_PLL_DP_MFN_MASK 0x7FFFFFF
+
+/* CRM AP Register Offsets */
+#define MXC_CRMAP_ASCSR (MXC_CRM_AP_BASE + 0x00)
+#define MXC_CRMAP_ACDR (MXC_CRM_AP_BASE + 0x04)
+#define MXC_CRMAP_ACDER1 (MXC_CRM_AP_BASE + 0x08)
+#define MXC_CRMAP_ACDER2 (MXC_CRM_AP_BASE + 0x0C)
+#define MXC_CRMAP_ACGCR (MXC_CRM_AP_BASE + 0x10)
+#define MXC_CRMAP_ACCGCR (MXC_CRM_AP_BASE + 0x14)
+#define MXC_CRMAP_AMLPMRA (MXC_CRM_AP_BASE + 0x18)
+#define MXC_CRMAP_AMLPMRB (MXC_CRM_AP_BASE + 0x1C)
+#define MXC_CRMAP_AMLPMRC (MXC_CRM_AP_BASE + 0x20)
+#define MXC_CRMAP_AMLPMRD (MXC_CRM_AP_BASE + 0x24)
+#define MXC_CRMAP_AMLPMRE1 (MXC_CRM_AP_BASE + 0x28)
+#define MXC_CRMAP_AMLPMRE2 (MXC_CRM_AP_BASE + 0x2C)
+#define MXC_CRMAP_AMLPMRF (MXC_CRM_AP_BASE + 0x30)
+#define MXC_CRMAP_AMLPMRG (MXC_CRM_AP_BASE + 0x34)
+#define MXC_CRMAP_APGCR (MXC_CRM_AP_BASE + 0x38)
+#define MXC_CRMAP_ACSR (MXC_CRM_AP_BASE + 0x3C)
+#define MXC_CRMAP_ADCR (MXC_CRM_AP_BASE + 0x40)
+#define MXC_CRMAP_ACR (MXC_CRM_AP_BASE + 0x44)
+#define MXC_CRMAP_AMCR (MXC_CRM_AP_BASE + 0x48)
+#define MXC_CRMAP_APCR (MXC_CRM_AP_BASE + 0x4C)
+#define MXC_CRMAP_AMORA (MXC_CRM_AP_BASE + 0x50)
+#define MXC_CRMAP_AMORB (MXC_CRM_AP_BASE + 0x54)
+#define MXC_CRMAP_AGPR (MXC_CRM_AP_BASE + 0x58)
+#define MXC_CRMAP_APRA (MXC_CRM_AP_BASE + 0x5C)
+#define MXC_CRMAP_APRB (MXC_CRM_AP_BASE + 0x60)
+#define MXC_CRMAP_APOR (MXC_CRM_AP_BASE + 0x64)
+#define MXC_CRMAP_ADFMR (MXC_CRM_AP_BASE + 0x68)
+
+/* CRM AP Register Bit definitions */
+#define MXC_CRMAP_ASCSR_CRS 0x10000
+#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET 15
+#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2 0x8000
+#define MXC_CRMAP_ASCSR_USBSEL_OFFSET 13
+#define MXC_CRMAP_ASCSR_USBSEL_MASK (0x3 << 13)
+#define MXC_CRMAP_ASCSR_CSISEL_OFFSET 11
+#define MXC_CRMAP_ASCSR_CSISEL_MASK (0x3 << 11)
+#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET 7
+#define MXC_CRMAP_ASCSR_SSI2SEL_MASK (0x3 << 7)
+#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET 5
+#define MXC_CRMAP_ASCSR_SSI1SEL_MASK (0x3 << 5)
+#define MXC_CRMAP_ASCSR_APSEL_OFFSET 3
+#define MXC_CRMAP_ASCSR_APSEL_MASK (0x3 << 3)
+#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET 2
+#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1 0x4
+#define MXC_CRMAP_ASCSR_APISEL 0x1
+
+#define MXC_CRMAP_ACDR_ARMDIV_OFFSET 8
+#define MXC_CRMAP_ACDR_ARMDIV_MASK (0xF << 8)
+#define MXC_CRMAP_ACDR_AHBDIV_OFFSET 4
+#define MXC_CRMAP_ACDR_AHBDIV_MASK (0xF << 4)
+#define MXC_CRMAP_ACDR_IPDIV_OFFSET 0
+#define MXC_CRMAP_ACDR_IPDIV_MASK 0xF
+
+#define MXC_CRMAP_ACDER1_CSIEN_OFFSET 30
+#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET 24
+#define MXC_CRMAP_ACDER1_CSIDIV_MASK (0x3F << 24)
+#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET 14
+#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET 8
+#define MXC_CRMAP_ACDER1_SSI2DIV_MASK (0x3F << 8)
+#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET 6
+#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET 0
+#define MXC_CRMAP_ACDER1_SSI1DIV_MASK 0x3F
+
+#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET 24
+#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK (0x7 << 24)
+#define MXC_CRMAP_ACDER2_NFCEN_OFFSET 20
+#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET 16
+#define MXC_CRMAP_ACDER2_NFCDIV_MASK (0xF << 16)
+#define MXC_CRMAP_ACDER2_USBEN_OFFSET 12
+#define MXC_CRMAP_ACDER2_USBDIV_OFFSET 8
+#define MXC_CRMAP_ACDER2_USBDIV_MASK (0xF << 8)
+#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET 5
+#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK (0x3 << 5)
+#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET 0
+#define MXC_CRMAP_ACDER2_BAUDDIV_MASK 0xF
+
+#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET 22
+#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK (0x7 << 22)
+#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET 19
+#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK (0x7 << 19)
+#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET 12
+#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK (0x7 << 12)
+#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET 9
+#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK (0x7 << 9)
+#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET 6
+#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK (0x7 << 6)
+#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET 3
+#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK (0x7 << 3)
+
+#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET 0
+#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK 0x7
+
+#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET 28
+#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK (0x7 << 28)
+#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET 22
+#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK (0x7 << 22)
+#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET 16
+#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK (0x7 << 16)
+#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET 12
+#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK (0x7 << 12)
+#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET 9
+#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK (0x7 << 9)
+#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET 6
+#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK (0x7 << 6)
+#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET 3
+#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK (0x7 << 3)
+#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET 0
+#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK 0x7
+
+#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET 22
+#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK (0x7 << 22)
+#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET 12
+#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK (0x7 << 12)
+#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET 9
+#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK (0x7 << 9)
+#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET 6
+#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK (0x7 << 6)
+#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET 0
+#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK 0x7
+
+#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET 28
+#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK (0x7 << 28)
+#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET 25
+#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK (0x7 << 25)
+#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET 22
+#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK (0x7 << 22)
+#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET 19
+#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK (0x7 << 19)
+#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET 16
+#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK (0x7 << 16)
+#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET 12
+#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK (0x7 << 12)
+#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET 9
+#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK (0x7 << 9)
+#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET 6
+#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK (0x7 << 6)
+#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET 3
+#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK (0x7 << 3)
+#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET 0
+#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK 0x7
+
+#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET 0
+#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK 0x7
+
+#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET 19
+#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK (0x7 << 19)
+#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET 16
+#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK (0x7 << 16)
+#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET 9
+#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK (0x7 << 9)
+#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET 6
+#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK (0x7 << 6)
+#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET 3
+#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK (0x7 << 3)
+#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET 0
+#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK (0x7 << 0)
+
+#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET 28
+#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK (0x7 << 28)
+#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET 22
+#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK (0x7 << 22)
+#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET 19
+#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK (0x7 << 19)
+#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET 16
+#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK (0x7 << 16)
+#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET 12
+#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK (0x7 << 12)
+#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET 9
+#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK (0x7 << 9)
+#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET 6
+#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK (0x7 << 6)
+#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET 3
+#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK (0x7 << 3)
+#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET 0
+#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK 0x7
+
+#define MXC_CRMAP_AGPR_IPUPAD_OFFSET 20
+#define MXC_CRMAP_AGPR_IPUPAD_MASK (0x7 << 20)
+
+#define MXC_CRMAP_APRA_EL1TEN_OFFSET 29
+#define MXC_CRMAP_APRA_SIMEN_OFFSET 24
+#define MXC_CRMAP_APRA_UART3DIV_OFFSET 17
+#define MXC_CRMAP_APRA_UART3DIV_MASK (0xF << 17)
+#define MXC_CRMAP_APRA_UART3EN_OFFSET 16
+#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
+#define MXC_CRMAP_APRA_MQSPIEN_OFFSET 13
+#define MXC_CRMAP_APRA_UART2EN_OFFSET 8
+#define MXC_CRMAP_APRA_UART1EN_OFFSET 0
+
+#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET 13
+#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK (0x7 << 13)
+#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET 9
+#define MXC_CRMAP_APRB_SDHC2_DIV_MASK (0xF << 9)
+#define MXC_CRMAP_APRB_SDHC2EN_OFFSET 8
+#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET 5
+#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK (0x7 << 5)
+#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET 1
+#define MXC_CRMAP_APRB_SDHC1_DIV_MASK (0xF << 1)
+#define MXC_CRMAP_APRB_SDHC1EN_OFFSET 0
+
+#define MXC_CRMAP_ACSR_ADS_OFFSET 8
+#define MXC_CRMAP_ACSR_ADS (0x1 << 8)
+#define MXC_CRMAP_ACSR_ACS 0x1
+
+#define MXC_CRMAP_ADCR_LFDF_0 (0x0 << 8)
+#define MXC_CRMAP_ADCR_LFDF_2 (0x1 << 8)
+#define MXC_CRMAP_ADCR_LFDF_4 (0x2 << 8)
+#define MXC_CRMAP_ADCR_LFDF_8 (0x3 << 8)
+#define MXC_CRMAP_ADCR_LFDF_OFFSET 8
+#define MXC_CRMAP_ADCR_LFDF_MASK (0x3 << 8)
+#define MXC_CRMAP_ADCR_ALT_PLL 0x80
+#define MXC_CRMAP_ADCR_DFS_DIVEN 0x20
+#define MXC_CRMAP_ADCR_DIV_BYP 0x2
+#define MXC_CRMAP_ADCR_VSTAT 0x8
+#define MXC_CRMAP_ADCR_TSTAT 0x10
+#define MXC_CRMAP_ADCR_DVFS_VCTRL 0x10
+#define MXC_CRMAP_ADCR_CLK_ON 0x40
+
+#define MXC_CRMAP_ADFMR_FC_OFFSET 16
+#define MXC_CRMAP_ADFMR_FC_MASK (0x1F << 16)
+#define MXC_CRMAP_ADFMR_MF_OFFSET 1
+#define MXC_CRMAP_ADFMR_MF_MASK (0x3FF << 1)
+#define MXC_CRMAP_ADFMR_DFM_CLK_READY 0x1
+#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN 0x8000
+
+#define MXC_CRMAP_ACR_CKOHS_HIGH (1 << 18)
+#define MXC_CRMAP_ACR_CKOS_HIGH (1 << 16)
+#define MXC_CRMAP_ACR_CKOHS_MASK (0x7 << 12)
+#define MXC_CRMAP_ACR_CKOHD (1 << 11)
+#define MXC_CRMAP_ACR_CKOHDIV_MASK (0xF << 8)
+#define MXC_CRMAP_ACR_CKOHDIV_OFFSET 8
+#define MXC_CRMAP_ACR_CKOD (1 << 7)
+#define MXC_CRMAP_ACR_CKOS_MASK (0x7 << 4)
+
+/* AP Warm reset */
+#define MXC_CRMAP_AMCR_SW_AP (1 << 14)
+
+/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
+#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT 0x00000001
+#define MXC_CRMAP_ACGCR_ACG0_STOP 0x00000003
+#define MXC_CRMAP_ACGCR_ACG0_RUN 0x00000007
+#define MXC_CRMAP_ACGCR_ACG0_DISABLED 0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT 0x00000008
+#define MXC_CRMAP_ACGCR_ACG1_STOP 0x00000018
+#define MXC_CRMAP_ACGCR_ACG1_RUN 0x00000038
+#define MXC_CRMAP_ACGCR_ACG1_DISABLED 0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT 0x00000040
+#define MXC_CRMAP_ACGCR_ACG2_STOP 0x000000C0
+#define MXC_CRMAP_ACGCR_ACG2_RUN 0x000001C0
+#define MXC_CRMAP_ACGCR_ACG2_DISABLED 0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT 0x00000200
+#define MXC_CRMAP_ACGCR_ACG3_STOP 0x00000600
+#define MXC_CRMAP_ACGCR_ACG3_RUN 0x00000E00
+#define MXC_CRMAP_ACGCR_ACG3_DISABLED 0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT 0x00001000
+#define MXC_CRMAP_ACGCR_ACG4_STOP 0x00003000
+#define MXC_CRMAP_ACGCR_ACG4_RUN 0x00007000
+#define MXC_CRMAP_ACGCR_ACG4_DISABLED 0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT 0x00010000
+#define MXC_CRMAP_ACGCR_ACG5_STOP 0x00030000
+#define MXC_CRMAP_ACGCR_ACG5_RUN 0x00070000
+#define MXC_CRMAP_ACGCR_ACG5_DISABLED 0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT 0x00080000
+#define MXC_CRMAP_ACGCR_ACG6_STOP 0x00180000
+#define MXC_CRMAP_ACGCR_ACG6_RUN 0x00380000
+#define MXC_CRMAP_ACGCR_ACG6_DISABLED 0x00000000
+
+#define NUM_GATE_CTRL 6
+
+/* CRM COM Register Offsets */
+#define MXC_CRMCOM_CSCR (MXC_CRM_COM_BASE + 0x0C)
+#define MXC_CRMCOM_CCCR (MXC_CRM_COM_BASE + 0x10)
+
+/* CRM COM Bit Definitions */
+#define MXC_CRMCOM_CSCR_PPD1 0x08000000
+#define MXC_CRMCOM_CSCR_CKOHSEL (1 << 18)
+#define MXC_CRMCOM_CSCR_CKOSEL (1 << 17)
+#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET 8
+#define MXC_CRMCOM_CCCR_CC_DIV_MASK (0x1F << 8)
+#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET 0
+#define MXC_CRMCOM_CCCR_CC_SEL_MASK 0x3
+
+/* DSM Register Offsets */
+#define MXC_DSM_SLEEP_TIME (MXC_DSM_BASE + 0x0c)
+#define MXC_DSM_CONTROL0 (MXC_DSM_BASE + 0x20)
+#define MXC_DSM_CONTROL1 (MXC_DSM_BASE + 0x24)
+#define MXC_DSM_CTREN (MXC_DSM_BASE + 0x28)
+#define MXC_DSM_WARM_PER (MXC_DSM_BASE + 0x40)
+#define MXC_DSM_LOCK_PER (MXC_DSM_BASE + 0x44)
+#define MXC_DSM_MGPER (MXC_DSM_BASE + 0x4c)
+#define MXC_DSM_CRM_CONTROL (MXC_DSM_BASE + 0x50)
+
+/* Bit definitions of various registers in DSM */
+#define MXC_DSM_CRM_CTRL_DVFS_BYP 0x00000008
+#define MXC_DSM_CRM_CTRL_DVFS_VCTRL 0x00000004
+#define MXC_DSM_CRM_CTRL_LPMD1 0x00000002
+#define MXC_DSM_CRM_CTRL_LPMD0 0x00000001
+#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE 0x00000000
+#define MXC_DSM_CRM_CTRL_LPMD_