diff options
Diffstat (limited to 'arch/arm/mach-clps711x/include')
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/autcpu12.h | 78 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/clps711x.h | 204 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/debug-macro.S | 15 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/entry-macro.S | 58 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/hardware.h | 192 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/io.h | 36 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/irqs.h | 53 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/memory.h | 78 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/syspld.h | 121 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/system.h | 40 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/time.h | 49 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/timex.h | 23 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/uncompress.h | 24 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/vmalloc.h | 20 |
14 files changed, 238 insertions, 753 deletions
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h deleted file mode 100644 index 1588a365f61..00000000000 --- a/arch/arm/mach-clps711x/include/mach/autcpu12.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * AUTCPU12 specific defines - * - * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_AUTCPU12_H -#define __ASM_ARCH_AUTCPU12_H - -/* - * The CS8900A ethernet chip has its I/O registers wired to chip select 2 - * (nCS2). This is the mapping for it. - */ -#define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE /* physical */ -#define AUTCPU12_VIRT_CS8900A (0xfe000000) /* virtual */ - -/* - * The flash bank is wired to chip select 0 - */ -#define AUTCPU12_PHYS_FLASH CS0_PHYS_BASE /* physical */ - -/* offset for device specific information structure */ -#define AUTCPU12_LCDINFO_OFFS (0x00010000) -/* -* Videomemory is the internal SRAM (CS 6) -*/ -#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE -#define AUTCPU12_VIRT_VIDEO (0xfd000000) - -/* -* All special IO's are tied to CS1 -*/ -#define AUTCPU12_PHYS_CHAR_LCD CS1_PHYS_BASE +0x00000000 /* physical */ - -#define AUTCPU12_PHYS_NVRAM CS1_PHYS_BASE +0x02000000 /* physical */ - -#define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */ - -#define AUTCPU12_PHYS_SMC CS1_PHYS_BASE +0x06000000 /* physical */ - -#define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */ - -#define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */ - -#define AUTCPU12_PHYS_IO CS1_PHYS_BASE +0x0C000000 /* physical */ - -#define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */ - -/* -* defines for smartmedia card access -*/ -#define AUTCPU12_SMC_RDY (1<<2) -#define AUTCPU12_SMC_ALE (1<<3) -#define AUTCPU12_SMC_CLE (1<<4) -#define AUTCPU12_SMC_PORT_OFFSET PBDR -#define AUTCPU12_SMC_SELECT_OFFSET 0x10 -/* -* defines for lcd contrast -*/ -#define AUTCPU12_DPOT_PORT_OFFSET PEDR -#define AUTCPU12_DPOT_CS (1<<0) -#define AUTCPU12_DPOT_CLK (1<<1) -#define AUTCPU12_DPOT_UD (1<<2) - -#endif diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h new file mode 100644 index 00000000000..eb052a11aa9 --- /dev/null +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -0,0 +1,204 @@ +/* + * This file contains the hardware definitions of the Cirrus Logic + * ARM7 CLPS711X internal registers. + * + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __MACH_CLPS711X_H +#define __MACH_CLPS711X_H + +#include <linux/mfd/syscon/clps711x.h> + +#define CLPS711X_PHYS_BASE (0x80000000) + +#define PADR (0x0000) +#define PBDR (0x0001) +#define PCDR (0x0002) +#define PDDR (0x0003) +#define PADDR (0x0040) +#define PBDDR (0x0041) +#define PCDDR (0x0042) +#define PDDDR (0x0043) +#define PEDR (0x0083) +#define PEDDR (0x00c3) +#define SYSCON1 (0x0100) +#define SYSFLG1 (0x0140) +#define MEMCFG1 (0x0180) +#define MEMCFG2 (0x01c0) +#define DRFPR (0x0200) +#define LCDCON (0x02c0) +#define TC1D (0x0300) +#define TC2D (0x0340) +#define RTCDR (0x0380) +#define RTCMR (0x03c0) +#define PMPCON (0x0400) +#define CODR (0x0440) +#define UARTDR1 (0x0480) +#define UBRLCR1 (0x04c0) +#define SYNCIO (0x0500) +#define PALLSW (0x0540) +#define PALMSW (0x0580) +#define STFCLR (0x05c0) +#define HALT (0x0800) +#define STDBY (0x0840) + +#define FBADDR (0x1000) +#define SYSCON2 (0x1100) +#define SYSFLG2 (0x1140) +#define UARTDR2 (0x1480) +#define UBRLCR2 (0x14c0) +#define SS2DR (0x1500) +#define SS2POP (0x16c0) + +#define DAIR (0x2000) +#define DAIDR0 (0x2040) +#define DAIDR1 (0x2080) +#define DAIDR2 (0x20c0) +#define DAISR (0x2100) +#define SYSCON3 (0x2200) +#define LEDFLSH (0x22c0) +#define SDCONF (0x2300) +#define SDRFPR (0x2340) +#define UNIQID (0x2440) +#define DAI64FS (0x2600) +#define PLLW (0x2610) +#define PLLR (0xa5a8) +#define RANDID0 (0x2700) +#define RANDID1 (0x2704) +#define RANDID2 (0x2708) +#define RANDID3 (0x270c) + +#define LCDCON_GSEN (1 << 30) +#define LCDCON_GSMD (1 << 31) + +/* common bits: UARTDR1 / UARTDR2 */ +#define UARTDR_FRMERR (1 << 8) +#define UARTDR_PARERR (1 << 9) +#define UARTDR_OVERR (1 << 10) + +/* common bits: UBRLCR1 / UBRLCR2 */ +#define UBRLCR_BAUD_MASK ((1 << 12) - 1) +#define UBRLCR_BREAK (1 << 12) +#define UBRLCR_PRTEN (1 << 13) +#define UBRLCR_EVENPRT (1 << 14) +#define UBRLCR_XSTOP (1 << 15) +#define UBRLCR_FIFOEN (1 << 16) +#define UBRLCR_WRDLEN5 (0 << 17) +#define UBRLCR_WRDLEN6 (1 << 17) +#define UBRLCR_WRDLEN7 (2 << 17) +#define UBRLCR_WRDLEN8 (3 << 17) +#define UBRLCR_WRDLEN_MASK (3 << 17) + +#define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8) +#define SYNCIO_SMCKEN (1 << 13) +#define SYNCIO_TXFRMEN (1 << 14) + +#define DAIR_RESERVED (0x0404) +#define DAIR_DAIEN (1 << 16) +#define DAIR_ECS (1 << 17) +#define DAIR_LCTM (1 << 19) +#define DAIR_LCRM (1 << 20) +#define DAIR_RCTM (1 << 21) +#define DAIR_RCRM (1 << 22) +#define DAIR_LBM (1 << 23) + +#define DAIDR2_FIFOEN (1 << 15) +#define DAIDR2_FIFOLEFT (0x0d << 16) +#define DAIDR2_FIFORIGHT (0x11 << 16) + +#define DAISR_RCTS (1 << 0) +#define DAISR_RCRS (1 << 1) +#define DAISR_LCTS (1 << 2) +#define DAISR_LCRS (1 << 3) +#define DAISR_RCTU (1 << 4) +#define DAISR_RCRO (1 << 5) +#define DAISR_LCTU (1 << 6) +#define DAISR_LCRO (1 << 7) +#define DAISR_RCNF (1 << 8) +#define DAISR_RCNE (1 << 9) +#define DAISR_LCNF (1 << 10) +#define DAISR_LCNE (1 << 11) +#define DAISR_FIFO (1 << 12) + +#define DAI64FS_I2SF64 (1 << 0) +#define DAI64FS_AUDIOCLKEN (1 << 1) +#define DAI64FS_AUDIOCLKSRC (1 << 2) +#define DAI64FS_MCLK256EN (1 << 3) +#define DAI64FS_LOOPBACK (1 << 5) + +#define SDCONF_ACTIVE (1 << 10) +#define SDCONF_CLKCTL (1 << 9) +#define SDCONF_WIDTH_4 (0 << 7) +#define SDCONF_WIDTH_8 (1 << 7) +#define SDCONF_WIDTH_16 (2 << 7) +#define SDCONF_WIDTH_32 (3 << 7) +#define SDCONF_SIZE_16 (0 << 5) +#define SDCONF_SIZE_64 (1 << 5) +#define SDCONF_SIZE_128 (2 << 5) +#define SDCONF_SIZE_256 (3 << 5) +#define SDCONF_CASLAT_2 (2) +#define SDCONF_CASLAT_3 (3) + +#define MEMCFG_BUS_WIDTH_32 (1) +#define MEMCFG_BUS_WIDTH_16 (0) +#define MEMCFG_BUS_WIDTH_8 (3) + +#define MEMCFG_SQAEN (1 << 6) +#define MEMCFG_CLKENB (1 << 7) + +#define MEMCFG_WAITSTATE_8_3 (0 << 2) +#define MEMCFG_WAITSTATE_7_3 (1 << 2) +#define MEMCFG_WAITSTATE_6_3 (2 << 2) +#define MEMCFG_WAITSTATE_5_3 (3 << 2) +#define MEMCFG_WAITSTATE_4_2 (4 << 2) +#define MEMCFG_WAITSTATE_3_2 (5 << 2) +#define MEMCFG_WAITSTATE_2_2 (6 << 2) +#define MEMCFG_WAITSTATE_1_2 (7 << 2) +#define MEMCFG_WAITSTATE_8_1 (8 << 2) +#define MEMCFG_WAITSTATE_7_1 (9 << 2) +#define MEMCFG_WAITSTATE_6_1 (10 << 2) +#define MEMCFG_WAITSTATE_5_1 (11 << 2) +#define MEMCFG_WAITSTATE_4_0 (12 << 2) +#define MEMCFG_WAITSTATE_3_0 (13 << 2) +#define MEMCFG_WAITSTATE_2_0 (14 << 2) +#define MEMCFG_WAITSTATE_1_0 (15 << 2) + +/* INTSR1 Interrupts */ +#define IRQ_CSINT (4) +#define IRQ_EINT1 (5) +#define IRQ_EINT2 (6) +#define IRQ_EINT3 (7) +#define IRQ_TC1OI (8) +#define IRQ_TC2OI (9) +#define IRQ_RTCMI (10) +#define IRQ_TINT (11) +#define IRQ_UTXINT1 (12) +#define IRQ_URXINT1 (13) +#define IRQ_UMSINT (14) +#define IRQ_SSEOTI (15) + +/* INTSR2 Interrupts */ +#define IRQ_KBDINT (16 + 0) +#define IRQ_SS2RX (16 + 1) +#define IRQ_SS2TX (16 + 2) +#define IRQ_UTXINT2 (16 + 12) +#define IRQ_URXINT2 (16 + 13) + +/* INTSR3 Interrupts */ +#define IRQ_DAIINT (32 + 0) + +#endif /* __MACH_CLPS711X_H */ diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S index 507c6873b7e..cb3684f8dae 100644 --- a/arch/arm/mach-clps711x/include/mach/debug-macro.S +++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S @@ -12,16 +12,15 @@ */ #include <mach/hardware.h> -#include <asm/hardware/clps7111.h> - .macro addruart, rp, rv + .macro addruart, rp, rv, tmp #ifndef CONFIG_DEBUG_CLPS711X_UART2 mov \rp, #0x0000 @ UART1 #else mov \rp, #0x1000 @ UART2 #endif - orr \rv, \rp, #CLPS7111_VIRT_BASE - orr \rp, \rp, #CLPS7111_PHYS_BASE + orr \rv, \rp, #CLPS711X_VIRT_BASE + orr \rp, \rp, #CLPS711X_PHYS_BASE .endm .macro senduart,rd,rx @@ -29,17 +28,11 @@ .endm .macro waituart,rd,rx -1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx - tst \rd, #1 << 11 @ UBUSYx - bne 1001b .endm .macro busyuart,rd,rx - tst \rx, #0x1000 @ UART2 does not have CTS here - bne 1002f 1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx - tst \rd, #1 << 8 @ CTS + tst \rd, #1 << 11 @ UBUSYx bne 1001b -1002: .endm diff --git a/arch/arm/mach-clps711x/include/mach/entry-macro.S b/arch/arm/mach-clps711x/include/mach/entry-macro.S deleted file mode 100644 index 90fa2f70489..00000000000 --- a/arch/arm/mach-clps711x/include/mach/entry-macro.S +++ /dev/null @@ -1,58 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for CLPS711X-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/hardware.h> -#include <asm/hardware/clps7111.h> - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - -#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1) -#error INTSR stride != INTMR stride -#endif - - .macro get_irqnr_and_base, irqnr, stat, base, mask - mov \base, #CLPS7111_BASE - ldr \stat, [\base, #INTSR1] - ldr \mask, [\base, #INTMR1] - mov \irqnr, #4 - mov \mask, \mask, lsl #16 - and \stat, \stat, \mask, lsr #16 - movs \stat, \stat, lsr #4 - bne 1001f - - add \base, \base, #INTSR2 - INTSR1 - ldr \stat, [\base, #INTSR1] - ldr \mask, [\base, #INTMR1] - mov \irqnr, #16 - mov \mask, \mask, lsl #16 - and \stat, \stat, \mask, lsr #16 - -1001: tst \stat, #255 - addeq \irqnr, \irqnr, #8 - moveq \stat, \stat, lsr #8 - tst \stat, #15 - addeq \irqnr, \irqnr, #4 - moveq \stat, \stat, lsr #4 - tst \stat, #3 - addeq \irqnr, \irqnr, #2 - moveq \stat, \stat, lsr #2 - tst \stat, #1 - addeq \irqnr, \irqnr, #1 - moveq \stat, \stat, lsr #1 - tst \stat, #1 @ bit 0 should be set - .endm - - diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index d0b7d870be9..5d6afda1c0e 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -19,20 +19,25 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H +#include <mach/clps711x.h> -#define CLPS7111_VIRT_BASE 0xff000000 -#define CLPS7111_BASE CLPS7111_VIRT_BASE +#define IO_ADDRESS(x) (0xdc000000 + (((x) & 0x03ffffff) | \ + (((x) >> 2) & 0x3c000000))) + +#define CLPS711X_VIRT_BASE IOMEM(IO_ADDRESS(CLPS711X_PHYS_BASE)) + +#ifndef __ASSEMBLY__ +#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off)) +#define clps_readw(off) readw(CLPS711X_VIRT_BASE + (off)) +#define clps_readl(off) readl(CLPS711X_VIRT_BASE + (off)) +#define clps_writeb(val,off) writeb(val, CLPS711X_VIRT_BASE + (off)) +#define clps_writew(val,off) writew(val, CLPS711X_VIRT_BASE + (off)) +#define clps_writel(val,off) writel(val, CLPS711X_VIRT_BASE + (off)) +#endif -/* - * The physical addresses that the external chip select signals map to is - * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212 - * processors. CONFIG_EP72XX_BOOT_ROM is only available if these - * processors are in use. - */ -#ifndef CONFIG_EP72XX_ROM_BOOT #define CS0_PHYS_BASE (0x00000000) #define CS1_PHYS_BASE (0x10000000) #define CS2_PHYS_BASE (0x20000000) @@ -41,168 +46,11 @@ #define CS5_PHYS_BASE (0x50000000) #define CS6_PHYS_BASE (0x60000000) #define CS7_PHYS_BASE (0x70000000) -#else -#define CS0_PHYS_BASE (0x70000000) -#define CS1_PHYS_BASE (0x60000000) -#define CS2_PHYS_BASE (0x50000000) -#define CS3_PHYS_BASE (0x40000000) -#define CS4_PHYS_BASE (0x30000000) -#define CS5_PHYS_BASE (0x20000000) -#define CS6_PHYS_BASE (0x10000000) -#define CS7_PHYS_BASE (0x00000000) -#endif - -#if defined (CONFIG_ARCH_EP7211) - -#define EP7211_VIRT_BASE CLPS7111_VIRT_BASE -#define EP7211_BASE CLPS7111_VIRT_BASE -#include <asm/hardware/ep7211.h> - -#elif defined (CONFIG_ARCH_EP7212) - -#define EP7212_VIRT_BASE CLPS7111_VIRT_BASE -#define EP7212_BASE CLPS7111_VIRT_BASE -#include <asm/hardware/ep7212.h> - -#endif - -#define SYSPLD_VIRT_BASE 0xfe000000 -#define SYSPLD_BASE SYSPLD_VIRT_BASE - -#if defined (CONFIG_ARCH_AUTCPU12) - -#define CS89712_VIRT_BASE CLPS7111_VIRT_BASE -#define CS89712_BASE CLPS7111_VIRT_BASE - -#include <asm/hardware/clps7111.h> -#include <asm/hardware/ep7212.h> -#include <asm/hardware/cs89712.h> - -#endif +#define CLPS711X_SRAM_BASE CS6_PHYS_BASE +#define CLPS711X_SRAM_SIZE (48 * 1024) -#if defined (CONFIG_ARCH_CDB89712) - -#include <asm/hardware/clps7111.h> -#include <asm/hardware/ep7212.h> -#include <asm/hardware/cs89712.h> - -/* static cdb89712_map_io() areas */ -#define REGISTER_START 0x80000000 -#define REGISTER_SIZE 0x4000 -#define REGISTER_BASE 0xff000000 - -#define ETHER_START 0x20000000 -#define ETHER_SIZE 0x1000 -#define ETHER_BASE 0xfe000000 - -#endif - - -#if defined (CONFIG_ARCH_EDB7211) - -/* - * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) - * and repeat across it. This is the mapping for it. - * - * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This - * was cause for much consternation and headscratching. This should probably - * be made a compile/run time kernel option. - */ -#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */ - -#define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */ - - -/* - * The CS8900A ethernet chip has its I/O registers wired to chip select 2 - * (nCS2). This is the mapping for it. - * - * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This - * was cause for much consternation and headscratching. This should probably - * be made a compile/run time kernel option. - */ -#define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */ - -#define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */ - - -/* - * The two flash banks are wired to chip selects 0 and 1. This is the mapping - * for them. - * - * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running - * in jumpered boot mode. - */ -#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */ -#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */ - -#define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */ -#define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */ - -#endif /* CONFIG_ARCH_EDB7211 */ - - -/* - * Relevant bits in port D, which controls power to the various parts of - * the LCD on the EDB7211. - */ -#define EDB_PD1_LCD_DC_DC_EN (1<<1) -#define EDB_PD2_LCDEN (1<<2) -#define EDB_PD3_LCDBL (1<<3) - - -#if defined (CONFIG_ARCH_CEIVA) - -#define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE -#define CEIVA_BASE CLPS7111_VIRT_BASE - -#include <asm/hardware/clps7111.h> -#include <asm/hardware/ep7212.h> - - -/* - * The two flash banks are wired to chip selects 0 and 1. This is the mapping - * for them. - * - * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running - * in jumpered boot mode. - */ -#define CEIVA_PHYS_FLASH1 CS0_PHYS_BASE /* physical */ -#define CEIVA_PHYS_FLASH2 CS1_PHYS_BASE /* physical */ - -#define CEIVA_VIRT_FLASH1 (0xfa000000) /* virtual */ -#define CEIVA_VIRT_FLASH2 (0xfb000000) /* virtual */ - -#define CEIVA_FLASH_SIZE 0x100000 -#define CEIVA_FLASH_WIDTH 2 - -/* - * SED1355 LCD controller - */ -#define CEIVA_PHYS_SED1355 CS2_PHYS_BASE -#define CEIVA_VIRT_SED1355 (0xfc000000) - -/* - * Relevant bits in port D, which controls power to the various parts of - * the LCD on the Ceiva Photo Max, and reset to the LCD controller. - */ - -// Reset line to SED1355 (must be high to operate) -#define CEIVA_PD1_LCDRST (1<<1) -// LCD panel enable (set to one, to enable LCD) -#define CEIVA_PD4_LCDEN (1<<4) -// Backlight (set to one, to turn on backlight -#define CEIVA_PD5_LCDBL (1<<5) - -/* - * Relevant bits in port B, which report the status of the buttons. - */ - -// White button -#define CEIVA_PB4_WHT_BTN (1<<4) -// Black button -#define CEIVA_PB0_BLK_BTN (1<<0) -#endif // #if defined (CONFIG_ARCH_CEIVA) +#define CLPS711X_SDRAM0_BASE (0xc0000000) +#define CLPS711X_SDRAM1_BASE (0xd0000000) #endif diff --git a/arch/arm/mach-clps711x/include/mach/io.h b/arch/arm/mach-clps711x/include/mach/io.h deleted file mode 100644 index 2e0b3ced8f0..00000000000 --- a/arch/arm/mach-clps711x/include/mach/io.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/io.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -/* - * We don't support ins[lb]/outs[lb]. Make them fault. - */ -#define __raw_readsb(p,d,l) do { *(int *)0 = 0; } while (0) -#define __raw_readsl(p,d,l) do { *(int *)0 = 0; } while (0) -#define __raw_writesb(p,d,l) do { *(int *)0 = 0; } while (0) -#define __raw_writesl(p,d,l) do { *(int *)0 = 0; } while (0) - -#endif diff --git a/arch/arm/mach-clps711x/include/mach/irqs.h b/arch/arm/mach-clps711x/include/mach/irqs.h deleted file mode 100644 index 30b7e97285a..00000000000 --- a/arch/arm/mach-clps711x/include/mach/irqs.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/irqs.h - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* - * Interrupts from INTSR1 - */ -#define IRQ_CSINT 4 -#define IRQ_EINT1 5 -#define IRQ_EINT2 6 -#define IRQ_EINT3 7 -#define IRQ_TC1OI 8 -#define IRQ_TC2OI 9 -#define IRQ_RTCMI 10 -#define IRQ_TINT 11 -#define IRQ_UTXINT1 12 -#define IRQ_URXINT1 13 -#define IRQ_UMSINT 14 -#define IRQ_SSEOTI 15 - -#define INT1_IRQS (0x0000fff0) -#define INT1_ACK_IRQS (0x00004f10) - -/* - * Interrupts from INTSR2 - */ -#define IRQ_KBDINT (16+0) /* bit 0 */ -#define IRQ_SS2RX (16+1) /* bit 1 */ -#define IRQ_SS2TX (16+2) /* bit 2 */ -#define IRQ_UTXINT2 (16+12) /* bit 12 */ -#define IRQ_URXINT2 (16+13) /* bit 13 */ - -#define INT2_IRQS (0x30070000) -#define INT2_ACK_IRQS (0x00010000) - -#define NR_IRQS 30 - diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h deleted file mode 100644 index 3a032a67725..00000000000 --- a/arch/arm/mach-clps711x/include/mach/memory.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/memory.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PLAT_PHYS_OFFSET UL(0xc0000000) - -#if !defined(CONFIG_ARCH_CDB89712) && !defined (CONFIG_ARCH_AUTCPU12) - -#define __virt_to_bus(x) ((x) - PAGE_OFFSET) -#define __bus_to_virt(x) ((x) + PAGE_OFFSET) -#define __pfn_to_bus(x) (__pfn_to_phys(x) - PHYS_OFFSET) -#define __bus_to_pfn(x) __phys_to_pfn((x) + PHYS_OFFSET) - -#endif - - -/* - * Like the SA1100, the EDB7211 has a large gap between physical RAM - * banks. In 2.2, the Psion (CL-PS7110) port added custom support for - * discontiguous physical memory. In 2.4, we can use the standard - * Linux NUMA support. - * - * This is not necessary for EP7211 implementations with only one used - * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM. - */ - -/* - * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 - * uses only one of the two banks (bank #1). However, even within - * bank #1, memory is discontiguous. - * - * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between - * them, so we use 24 for the node max shift to get 16MB node sizes. - */ - -/* - * Because of the wide memory address space between physical RAM banks on the - * SA1100, it's much more convenient to use Linux's NUMA support to implement - * our memory map representation. Assuming all memory nodes have equal access - * characteristics, we then have generic discontiguous memory support. - * - * Of course, all this isn't mandatory for SA1100 implementations with only - * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. - * - * The nodes are matched with the physical memory bank addresses which are - * incidentally the same as virtual addresses. - * - * node 0: 0xc0000000 - 0xc7ffffff - * node 1: 0xc8000000 - 0xcfffffff - * node 2: 0xd0000000 - 0xd7ffffff - * node 3: 0xd8000000 - 0xdfffffff - */ -#define SECTION_SIZE_BITS 24 -#define MAX_PHYSMEM_BITS 32 - -#endif - diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h deleted file mode 100644 index f7f4c120189..00000000000 --- a/arch/arm/mach-clps711x/include/mach/syspld.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/syspld.h - * - * System Control PLD register definitions. - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_SYSPLD_H -#define __ASM_ARCH_SYSPLD_H - -#define SYSPLD_PHYS_BASE (0x10000000) - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -#define SYSPLD_REG(type,off) (*(volatile type *)(SYSPLD_BASE + off)) -#else -#define SYSPLD_REG(type,off) (off) -#endif - -#define PLD_INT SYSPLD_REG(u32, 0x000000) -#define PLD_INT_PENIRQ (1 << 5) -#define PLD_INT_UCB_IRQ (1 << 1) -#define PLD_INT_KBD_ATN (1 << 0) /* EINT1 */ - -#define PLD_PWR SYSPLD_REG(u32, 0x000004) -#define PLD_PWR_EXT (1 << 5) -#define PLD_PWR_MODE (1 << 4) /* 1 = PWM, 0 = PFM */ -#define PLD_S4_ON (1 << 3) /* LCD bias voltage enable */ -#define PLD_S3_ON (1 << 2) /* LCD backlight enable */ -#define PLD_S2_ON (1 << 1) /* LCD 3V3 supply enable */ -#define PLD_S1_ON (1 << 0) /* LCD 3V supply enable */ - -#define PLD_KBD SYSPLD_REG(u32, 0x000008) -#define PLD_KBD_WAKE (1 << 1) -#define PLD_KBD_EN (1 << 0) - -#define PLD_SPI SYSPLD_REG(u32, 0x00000c) -#define PLD_SPI_EN (1 << 0) - -#define PLD_IO SYSPLD_REG(u32, 0x000010) -#define PLD_IO_BOOTSEL (1 << 6) /* boot sel switch */ -#define PLD_IO_USER (1 << 5) /* user defined switch */ -#define PLD_IO_LED3 (1 << 4) -#define PLD_IO_LED2 (1 << 3) -#define PLD_IO_LED1 (1 << 2) -#define PLD_IO_LED0 (1 << 1) -#define PLD_IO_LEDEN (1 << 0) - -#define PLD_IRDA SYSPLD_REG(u32, 0x000014) -#define PLD_IRDA_EN (1 << 0) - -#define PLD_COM2 SYSPLD_REG(u32, 0x000018) -#define PLD_COM2_EN (1 << 0) - -#define PLD_COM1 SYSPLD_REG(u32, 0x00001c) -#define PLD_COM1_EN (1 << 0) - -#define PLD_AUD SYSPLD_REG(u32, 0x000020) -#define PLD_AUD_DIV1 (1 << 6) -#define PLD_AUD_DIV0 (1 << 5) -#define PLD_AUD_CLK_SEL1 (1 << 4) -#define PLD_AUD_CLK_SEL0 (1 << 3) -#define PLD_AUD_MIC_PWR (1 << 2) -#define PLD_AUD_MIC_GAIN (1 << 1) -#define PLD_AUD_CODEC_EN (1 << 0) - -#define PLD_CF SYSPLD_REG(u32, 0x000024) -#define PLD_CF2_SLEEP (1 << 5) -#define PLD_CF1_SLEEP (1 << 4) -#define PLD_CF2_nPDREQ (1 << 3) -#define PLD_CF1_nPDREQ (1 << 2) -#define PLD_CF2_nIRQ (1 << 1) -#define PLD_CF1_nIRQ (1 << 0) - -#define PLD_SDC SYSPLD_REG(u32, 0x000028) -#define PLD_SDC_INT_EN (1 << 2) -#define PLD_SDC_WP (1 << 1) -#define PLD_SDC_CD (1 << 0) - -#define PLD_FPGA SYSPLD_REG(u32, 0x00002c) - -#define PLD_CODEC SYSPLD_REG(u32, 0x400000) -#define PLD_CODEC_IRQ3 (1 << 4) -#define PLD_CODEC_IRQ2 (1 << 3) -#define PLD_CODEC_IRQ1 (1 << 2) -#define PLD_CODEC_EN (1 << 0) - -#define PLD_BRITE SYSPLD_REG(u32, 0x400004) -#define PLD_BRITE_UP (1 << 1) -#define PLD_BRITE_DN (1 << 0) - -#define PLD_LCDEN SYSPLD_REG(u32, 0x400008) -#define PLD_LCDEN_EN (1 << 0) - -#define PLD_ID SYSPLD_REG(u32, 0x40000c) - -#define PLD_TCH SYSPLD_REG(u32, 0x400010) -#define PLD_TCH_PENIRQ (1 << 1) -#define PLD_TCH_EN (1 << 0) - -#define PLD_GPIO SYSPLD_REG(u32, 0x400014) -#define PLD_GPIO2 (1 << 2) -#define PLD_GPIO1 (1 << 1) -#define PLD_GPIO0 (1 << 0) - -#endif diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h deleted file mode 100644 index f916cd7a477..00000000000 --- a/arch/arm/mach-clps711x/include/mach/system.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/system.h - * - * Copyright (C) 2000 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include <linux/io.h> -#include <mach/hardware.h> -#include <asm/hardware/clps7111.h> - -static inline void arch_idle(void) -{ - clps_writel(1, HALT); - __asm__ __volatile__( - "mov r0, r0\n\ - mov r0, r0"); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - cpu_reset(0); -} - -#endif diff --git a/arch/arm/mach-clps711x/include/mach/time.h b/arch/arm/mach-clps711x/include/mach/time.h deleted file mode 100644 index 61fef9129c6..00000000000 --- a/arch/arm/mach-clps711x/include/mach/time.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/time.h - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <asm/leds.h> -#include <asm/hardware/clps7111.h> - -extern void clps711x_setup_timer(void); - -/* - * IRQ handler for the timer - */ -static irqreturn_t -p720t_timer_interrupt(int irq, void *dev_id) -{ - struct pt_regs *regs = get_irq_regs(); - do_leds(); - xtime_update(1); -#ifndef CONFIG_SMP - update_process_times(user_mode(regs)); -#endif - do_profile(regs); - return IRQ_HANDLED; -} - -/* - * Set up timer interrupt, and return the current time in seconds. - */ -void __init time_init(void) -{ - clps711x_setup_timer(); - timer_irq.handler = p720t_timer_interrupt; - setup_irq(IRQ_TC2OI, &timer_irq); -} diff --git a/arch/arm/mach-clps711x/include/mach/timex.h b/arch/arm/mach-clps711x/include/mach/timex.h deleted file mode 100644 index ac8823ccff9..00000000000 --- a/arch/arm/mach-clps711x/include/mach/timex.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/timex.h - * - * Prospector 720T architecture timex specifications - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#define CLOCK_TICK_RATE 512000 diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h index 7164310dea7..5f02d06dc65 100644 --- a/arch/arm/mach-clps711x/include/mach/uncompress.h +++ b/arch/arm/mach-clps711x/include/mach/uncompress.h @@ -17,15 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include <mach/io.h> -#include <mach/hardware.h> -#include <asm/hardware/clps7111.h> - -#undef CLPS7111_BASE -#define CLPS7111_BASE CLPS7111_PHYS_BASE - -#define __raw_readl(p) (*(unsigned long *)(p)) -#define __raw_writel(v,p) (*(unsigned long *)(p) = (v)) +#include <mach/clps711x.h> #ifdef CONFIG_DEBUG_CLPS711X_UART2 #define SYSFLGx SYSFLG2 @@ -35,19 +27,25 @@ #define UARTDRx UARTDR1 #endif +#define phys_reg(x) (*(volatile u32 *)(CLPS711X_PHYS_BASE + (x))) + /* + * The following code assumes the serial port has already been + * initialized by the bootloader. If you didn't setup a port in + * your bootloader then nothing will appear (which might be desired). + * * This does not append a newline */ static inline void putc(int c) { - while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) + while (phys_reg(SYSFLGx) & SYSFLG_UTXFF) barrier(); - clps_writel(c, UARTDRx); + phys_reg(UARTDRx) = c; } static inline void flush(void) { - while (clps_readl(SYSFLGx) & SYSFLG_UBUSY) + while (phys_reg(SYSFLGx) & SYSFLG_UBUSY) barrier(); } @@ -55,5 +53,3 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() - -#define arch_decomp_wdog() diff --git a/arch/arm/mach-clps711x/include/mach/vmalloc.h b/arch/arm/mach-clps711x/include/mach/vmalloc.h deleted file mode 100644 index 467b96137e4..00000000000 --- a/arch/arm/mach-clps711x/include/mach/vmalloc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/vmalloc.h - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define VMALLOC_END 0xd0000000UL |