diff options
Diffstat (limited to 'arch/arm/boot/compressed/head.S')
| -rw-r--r-- | arch/arm/boot/compressed/head.S | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index b9b03eda70e..3c2c8f2a1dc 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -31,7 +31,7 @@ .macro loadsp, rb .endm .macro writeb, ch, rb - mcr p14, 0, \ch, c0, c1, 0 + mcr p14, 0, \ch, c1, c0, 0 .endm #endif @@ -623,6 +623,12 @@ proc_types: b __armv4_mmu_cache_off b __armv4_mmu_cache_flush + .word 0x56055310 @ Feroceon + .word 0xfffffff0 + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv5tej_mmu_cache_flush + @ These match on the architecture ID .word 0x00020000 @ ARMv4T @@ -641,7 +647,7 @@ proc_types: .word 0x000f0000 b __armv4_mmu_cache_on b __armv4_mmu_cache_off - b __armv4_mmu_cache_flush + b __armv5tej_mmu_cache_flush .word 0x0007b000 @ ARMv6 .word 0x000ff000 @@ -821,6 +827,13 @@ iflush: mcr p15, 0, r10, c7, c10, 4 @ drain WB mov pc, lr +__armv5tej_mmu_cache_flush: +1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache + bne 1b + mcr p15, 0, r0, c7, c5, 0 @ flush I cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + __armv4_mmu_cache_flush: mov r2, #64*1024 @ default: 32K dcache size (*2) mov r11, #32 @ default: 32 byte line size |