diff options
Diffstat (limited to 'Documentation/devicetree')
156 files changed, 5381 insertions, 4770 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt new file mode 100644 index 00000000000..2c28f1d12f4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt @@ -0,0 +1,11 @@ +Altera SOCFPGA Clock Manager + +Required properties: +- compatible : "altr,clk-mgr" +- reg : Should contain base address and length for Clock Manager + +Example: + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/atmel-adc.txt b/Documentation/devicetree/bindings/arm/atmel-adc.txt index c63097d6afe..16769d9cedd 100644 --- a/Documentation/devicetree/bindings/arm/atmel-adc.txt +++ b/Documentation/devicetree/bindings/arm/atmel-adc.txt @@ -14,9 +14,19 @@ Required properties: - atmel,adc-status-register: Offset of the Interrupt Status Register - atmel,adc-trigger-register: Offset of the Trigger Register - atmel,adc-vref: Reference voltage in millivolts for the conversions + - atmel,adc-res: List of resolution in bits supported by the ADC. List size + must be two at least. + - atmel,adc-res-names: Contains one identifier string for each resolution + in atmel,adc-res property. "lowres" and "highres" + identifiers are required. Optional properties: - atmel,adc-use-external: Boolean to enable of external triggers + - atmel,adc-use-res: String corresponding to an identifier from + atmel,adc-res-names property. If not specified, the highest + resolution will be used. + - atmel,adc-sleep-mode: Boolean to enable sleep mode when no conversion + - atmel,adc-sample-hold-time: Sample and Hold Time in microseconds Optional trigger Nodes: - Required properties: @@ -40,6 +50,9 @@ adc0: adc@fffb0000 { atmel,adc-trigger-register = <0x08>; atmel,adc-use-external; atmel,adc-vref = <3300>; + atmel,adc-res = <8 10>; + atmel,adc-res-names = "lowres", "highres"; + atmel,adc-use-res = "lowres"; trigger@0 { trigger-name = "external-rising"; diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt b/Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt new file mode 100644 index 00000000000..59fa6e68d4f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt @@ -0,0 +1,19 @@ +Broadcom Kona Family timer +----------------------------------------------------- +This timer is used in the following Broadcom SoCs: + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155 + +Required properties: +- compatible : "bcm,kona-timer" +- reg : Register range for the timer +- interrupts : interrupt for the timer +- clock-frequency: frequency that the clock operates + +Example: + timer@35006000 { + compatible = "bcm,kona-timer"; + reg = <0x35006000 0x1000>; + interrupts = <0x0 7 0x4>; + clock-frequency = <32768>; + }; + diff --git a/Documentation/devicetree/bindings/arm/msm/ssbi.txt b/Documentation/devicetree/bindings/arm/msm/ssbi.txt new file mode 100644 index 00000000000..54fd5ced340 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/ssbi.txt @@ -0,0 +1,18 @@ +* Qualcomm SSBI + +Some Qualcomm MSM devices contain a point-to-point serial bus used to +communicate with a limited range of devices (mostly power management +chips). + +These require the following properties: + +- compatible: "qcom,ssbi" + +- qcom,controller-type + indicates the SSBI bus variant the controller should use to talk + with the slave device. This should be one of "ssbi", "ssbi2", or + "pmic-arbiter". The type chosen is determined by the attached + slave. + +The slave device should be the single child node of the ssbi device +with a compatible field. diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt index 8c5907b9cae..c6ef8f13dc7 100644 --- a/Documentation/devicetree/bindings/arm/msm/timer.txt +++ b/Documentation/devicetree/bindings/arm/msm/timer.txt @@ -3,36 +3,35 @@ Properties: - compatible : Should at least contain "qcom,msm-timer". More specific - properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general - purpose timer and a debug timer respectively. + properties specify which subsystem the timers are paired with. -- interrupts : Interrupt indicating a match event. + "qcom,kpss-timer" - krait subsystem + "qcom,scss-timer" - scorpion subsystem -- reg : Specifies the base address of the timer registers. The second region - specifies an optional register used to configure the clock divider. +- interrupts : Interrupts for the the debug timer, the first general purpose + timer, and optionally a second general purpose timer in that + order. -- clock-frequency : The frequency of the timer in Hz. +- reg : Specifies the base address of the timer registers. + +- clock-frequency : The frequency of the debug timer and the general purpose + timer(s) in Hz in that order. Optional: - cpu-offset : per-cpu offset used when the timer is accessed without the - CPU remapping facilities. The offset is cpu-offset * cpu-nr. + CPU remapping facilities. The offset is + cpu-offset + (0x10000 * cpu-nr). Example: - timer@200a004 { - compatible = "qcom,msm-gpt", "qcom,msm-timer"; - interrupts = <1 2 0x301>; - reg = <0x0200a004 0x10>; - clock-frequency = <32768>; - cpu-offset = <0x40000>; - }; - - timer@200a024 { - compatible = "qcom,msm-dgt", "qcom,msm-timer"; - interrupts = <1 3 0x301>; - reg = <0x0200a024 0x10>, - <0x0200a034 0x4>; - clock-frequency = <6750000>; + timer@200a000 { + compatible = "qcom,scss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <19200000>, + <32768>; cpu-offset = <0x40000>; }; diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt index 6888a5efc86..c0105de55cb 100644 --- a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt +++ b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt @@ -6,6 +6,7 @@ provided by Arteris. Required properties: - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family Should be "ti,omap4-l3-noc" for OMAP4 family +- reg: Contains L3 register address range for each noc domain. - ti,hwmods: "l3_main_1", ... One hwmod for each noc domain. Examples: diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt index 8732d4d41f8..d02e27c764e 100644 --- a/Documentation/devicetree/bindings/arm/omap/timer.txt +++ b/Documentation/devicetree/bindings/arm/omap/timer.txt @@ -1,7 +1,20 @@ OMAP Timer bindings Required properties: -- compatible: Must be "ti,omap2-timer" for OMAP2+ controllers. +- compatible: Should be set to one of the below. Please note that + OMAP44xx devices have timer instances that are 100% + register compatible with OMAP3xxx devices as well as + newer timers that are not 100% register compatible. + So for OMAP44xx devices timer instances may use + different compatible strings. + + ti,omap2420-timer (applicable to OMAP24xx devices) + ti,omap3430-timer (applicable to OMAP3xxx/44xx devices) + ti,omap4430-timer (applicable to OMAP44xx devices) + ti,omap5430-timer (applicable to OMAP543x devices) + ti,am335x-timer (applicable to AM335x devices) + ti,am335x-timer-1ms (applicable to AM335x devices) + - reg: Contains timer register address range (base address and length). - interrupts: Contains the interrupt information for the timer. The @@ -22,7 +35,7 @@ Optional properties: Example: timer12: timer@48304000 { - compatible = "ti,omap2-timer"; + compatible = "ti,omap3430-timer"; reg = <0x48304000 0x400>; interrupts = <95>; ti,hwmods = "timer12" diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt index 64fc82bc892..0df6acacfae 100644 --- a/Documentation/devicetree/bindings/arm/primecell.txt +++ b/Documentation/devicetree/bindings/arm/primecell.txt @@ -16,14 +16,31 @@ Optional properties: - clocks : From common clock binding. First clock is phandle to clock for apb pclk. Additional clocks are optional and specific to those peripherals. - clock-names : From common clock binding. Shall be "apb_pclk" for first clock. +- dmas : From common DMA binding. If present, refers to one or more dma channels. +- dma-names : From common DMA binding, needs to match the 'dmas' property. + Devices with exactly one receive and transmit channel shall name + these "rx" and "tx", respectively. +- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt +- pinctrl-names : Names corresponding to the numbered pinctrl states +- interrupts : one or more interrupt specifiers +- interrupt-names : names corresponding to the interrupts properties Example: serial@fff36000 { compatible = "arm,pl011", "arm,primecell"; arm,primecell-periphid = <0x00341011>; + clocks = <&pclk>; clock-names = "apb_pclk"; - + + dmas = <&dma-controller 4>, <&dma-controller 5>; + dma-names = "rx", "tx"; + + pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>; + pinctrl-1 = <&uart0_sleep_mode>; + pinctrl-names = "default","sleep"; + + interrupts = <0 11 0x4>; }; diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung-boards.txt index 0bf68be56fd..2168ed31e1b 100644 --- a/Documentation/devicetree/bindings/arm/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung-boards.txt @@ -6,3 +6,13 @@ Required root node properties: - compatible = should be one or more of the following. (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board. (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC. + +Optional: + - firmware node, specifying presence and type of secure firmware: + - compatible: only "samsung,secure-firmware" is currently supported + - reg: address of non-secure SYSRAM used for communication with firmware + + firmware@0203F000 { + compatible = "samsung,secure-firmware"; + reg = <0x0203F000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt new file mode 100644 index 00000000000..47ada1dff21 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt @@ -0,0 +1,60 @@ +Samsung Exynos Analog to Digital Converter bindings + +The devicetree bindings are for the new ADC driver written for +Exynos4 and upward SoCs from Samsung. + +New driver handles the following +1. Supports ADC IF found on EXYNOS4412/EXYNOS5250 + and future SoCs from Samsung +2. Add ADC driver under iio/adc framework +3. Also adds the Documentation for device tree bindings + +Required properties: +- compatible: Must be "samsung,exynos-adc-v1" + for exynos4412/5250 controllers. + Must be "samsung,exynos-adc-v2" for + future controllers. +- reg: Contains ADC register address range (base address and + length) and the address of the phy enable register. +- interrupts: Contains the interrupt information for the timer. The + format is being dependent on which interrupt controller + the Samsung device uses. +- #io-channel-cells = <1>; As ADC has multiple outputs +- clocks From common clock binding: handle to adc clock. +- clock-names From common clock binding: Shall be "adc". +- vdd-supply VDD input supply. + +Note: child nodes can be added for auto probing from device tree. + +Example: adding device info in dtsi file + +adc: adc@12D10000 { + compatible = "samsung,exynos-adc-v1"; + reg = <0x12D10000 0x100>, <0x10040718 0x4>; + interrupts = <0 106 0>; + #io-channel-cells = <1>; + io-channel-ranges; + + clocks = <&clock 303>; + clock-names = "adc"; + + vdd-supply = <&buck5_reg>; +}; + + +Example: Adding child nodes in dts file + +adc@12D10000 { + + /* NTC thermistor is a hwmon device */ + ncp15wb473@0 { + compatible = "ntc,ncp15wb473"; + pullup-uV = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 4>; + }; +}; + +Note: Does not apply to ADC driver under arch/arm/plat-samsung/ +Note: The child node can be added under the adc node or separately. diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt new file mode 100644 index 00000000000..5039c0a12f5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt @@ -0,0 +1,7 @@ +SAMSUNG S5P/Exynos SoC series System Registers (SYSREG) + +Properties: + - name : should be 'sysreg'; + - compatible : should contain "samsung,<chip name>-sysreg", "syscon"; + For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon"; + - reg : offset and length of the register set. diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index b5846e21cc2..1608a54e90e 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt @@ -1,19 +1,84 @@ NVIDIA Tegra Power Management Controller (PMC) -Properties: +The PMC block interacts with an external Power Management Unit. The PMC +mostly controls the entry and exit of the system from different sleep +modes. It provides power-gating controllers for SoC and CPU power-islands. + +Required properties: - name : Should be pmc - compatible : Should contain "nvidia,tegra<chip>-pmc". - reg : Offset and length of the register set for the device +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Must include the following entries: + "pclk" (The Tegra clock of that name), + "clk32k_in" (The 32KHz clock input to Tegra). + +Optional properties: - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. The PMU is an external Power Management Unit, whose interrupt output signal is fed into the PMC. This signal is optionally inverted, and then fed into the ARM GIC. The PMC is not involved in the detection or handling of this interrupt signal, merely its inversion. +- nvidia,suspend-mode : The suspend mode that the platform should use. + Valid values are 0, 1 and 2: + 0 (LP0): CPU + Core voltage off and DRAM in self-refresh + 1 (LP1): CPU voltage off and DRAM in self-refresh + 2 (LP2): CPU voltage off +- nvidia,core-power-req-active-high : Boolean, core power request active-high +- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high +- nvidia,combined-power-req : Boolean, combined power request for CPU & Core +- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) + is enabled. + +Required properties when nvidia,suspend-mode is specified: +- nvidia,cpu-pwr-good-time : CPU power good time in uS. +- nvidia,cpu-pwr-off-time : CPU power off time in uS. +- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time> + Core power good time in uS. +- nvidia,core-pwr-off-time : Core power off time in uS. + +Required properties when nvidia,suspend-mode=<0>: +- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector + The LP0 vector contains the warm boot code that is executed by AVP when + resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7 + processor and always being the first boot processor when chip is power on + or resume from deep sleep mode. When the system is resumed from the deep + sleep mode, the warm boot code will restore some PLLs, clocks and then + bring up CPU0 for resuming the system. Example: +/ SoC dts including file pmc@7000f400 { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car 110>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <100>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + nvidia,lp0-vec = <0xbdffd000 0x2000>; +}; + +/ Tegra board dts file +{ + ... + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + ... }; diff --git a/Documentation/devicetree/bindings/ata/imx-pata.txt b/Documentation/devicetree/bindings/ata/imx-pata.txt new file mode 100644 index 00000000000..e38d73414b0 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/imx-pata.txt @@ -0,0 +1,17 @@ +* Freescale i.MX PATA Controller + +Required properties: +- compatible: "fsl,imx27-pata" +- reg: Address range of the PATA Controller +- interrupts: The interrupt of the PATA Controller +- clocks: the clocks for the PATA Controller + +Example: + + pata: pata@83fe0000 { + compatible = "fsl,imx51-pata", "fsl,imx27-pata"; + reg = <0x83fe0000 0x4000>; + interrupts = <70>; + clocks = <&clks 161>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/ata/pata-arasan.txt b/Documentation/devicetree/bindings/ata/pata-arasan.txt index 95ec7f825ed..2aff154be84 100644 --- a/Documentation/devicetree/bindings/ata/pata-arasan.txt +++ b/Documentation/devicetree/bindings/ata/pata-arasan.txt @@ -6,6 +6,26 @@ Required properties: - interrupt-parent: Should be the phandle for the interrupt controller that services interrupts for this device - interrupt: Should contain the CF interrupt number +- clock-frequency: Interface clock rate, in Hz, one of + 25000000 + 33000000 + 40000000 + 50000000 + 66000000 + 75000000 + 100000000 + 125000000 + 150000000 + 166000000 + 200000000 + +Optional properties: +- arasan,broken-udma: if present, UDMA mode is unusable +- arasan,broken-mwdma: if present, MWDMA mode is unusable +- arasan,broken-pio: if present, PIO mode is unusable +- dmas: one DMA channel, as described in bindings/dma/dma.txt + required unless both UDMA and MWDMA mode are broken +- dma-names: the corresponding channel name, must be "data" Example: @@ -14,4 +34,6 @@ Example: reg = <0xfc000000 0x1000>; interrupt-parent = <&vic1>; interrupts = <12>; + dmas = <&dma-controller 23>; + dma-names = "data"; }; diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt index 5ddb2e9efaa..4b87ea1194e 100644 --- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt +++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt @@ -35,36 +35,83 @@ Required properties: Timing properties for child nodes. All are optional and default to 0. - - gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds - - Chip-select signal timings corresponding to GPMC_CONFIG2: - - gpmc,cs-on: Assertion time - - gpmc,cs-rd-off: Read deassertion time - - gpmc,cs-wr-off: Write deassertion time - - ADV signal timings corresponding to GPMC_CONFIG3: - - gpmc,adv-on: Assertion time - - gpmc,adv-rd-off: Read deassertion time - - gpmc,adv-wr-off: Write deassertion time - - WE signals timings corresponding to GPMC_CONFIG4: - - gpmc,we-on: Assertion time - - gpmc,we-off: Deassertion time - - OE signals timings corresponding to GPMC_CONFIG4: - - gpmc,oe-on: Assertion time - - gpmc,oe-off: Deassertion time - - Access time and cycle time timings corresponding to GPMC_CONFIG5: - - gpmc,page-burst-access: Multiple access word delay - - gpmc,access: Start-cycle to first data valid delay - - gpmc,rd-cycle: Total read cycle time - - gpmc,wr-cycle: Total write cycle time + - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds + + Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2: + - gpmc,cs-on-ns: Assertion time + - gpmc,cs-rd-off-ns: Read deassertion time + - gpmc,cs-wr-off-ns: Write deassertion time + + ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: + - gpmc,adv-on-ns: Assertion time + - gpmc,adv-rd-off-ns: Read deassertion time + - gpmc,adv-wr-off-ns: Write deassertion time + + WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: + - gpmc,we-on-ns Assertion time + - gpmc,we-off-ns: Deassertion time + + OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: + - gpmc,oe-on-ns: Assertion time + - gpmc,oe-off-ns: Deassertion time + + Access time and cycle time timings (in nanoseconds) corresponding to + GPMC_CONFIG5: + - gpmc,page-burst-access-ns: Multiple access word delay + - gpmc,access-ns: Start-cycle to first data valid delay + - gpmc,rd-cycle-ns: Total read cycle time + - gpmc,wr-cycle-ns: Total write cycle time + - gpmc,bus-turnaround-ns: Turn-around time between successive accesses + - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses + - gpmc,clk-activation-ns: GPMC clock activation time + - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid + data + +Boolean timing parameters. If property is present parameter enabled and +disabled if omitted: + - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock + - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock + - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive + accesses to a different CS + - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive + accesses to the same CS + - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock + - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock + - gpmc,time-para-granularity: Multiply all access times by 2 The following are only applicable to OMAP3+ and AM335x: - - gpmc,wr-access - - gpmc,wr-data-mux-bus - + - gpmc,wr-access-ns: In synchronous write mode, for single or + burst accesses, defines the number of + GPMC_FCLK cycles from start access time + to the GPMC_CLK rising edge used by the + memory device for the first data capture. + - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies + the time when the first data is driven on + the address-data bus. + +GPMC chip-select settings properties for child nodes. All are optional. + +- gpmc,burst-length Page/burst length. Must be 4, 8 or 16. +- gpmc,burst-wrap Enables wrap bursting +- gpmc,burst-read Enables read page/burst mode +- gpmc,burst-write Enables write page/burst mode +- gpmc,device-nand Device is NAND +- gpmc,device-width Total width of device(s) connected to a GPMC + chip-select in bytes. The GPMC supports 8-bit + and 16-bit devices and so this property must be + 1 or 2. +- gpmc,mux-add-data Address and data multiplexing configuration. + Valid values are 1 for address-address-data + multiplexing mode and 2 for address-data + multiplexing mode. +- gpmc,sync-read Enables synchronous read. Defaults to asynchronous + is this is not set. +- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous + is this is not set. +- gpmc,wait-pin Wait-pin used by client. Must be less than + "gpmc,num-waitpins". +- gpmc,wait-on-read Enables wait monitoring on reads. +- gpmc,wait-on-write Enables wait monitoring on writes. Example for an AM33xx board: diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt new file mode 100644 index 00000000000..bd0c8416a5c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt @@ -0,0 +1,18 @@ +Device Tree Clock bindings for Altera's SoCFPGA platform + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "altr,socfpga-pll-clock" - for a PLL clock + "altr,socfpga-perip-clock" - The peripheral clock divided from the + PLL clock. +- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. +- clocks : shall be the input parent clock phandle for the clock. This is + either an oscillator or a pll output. +- #clock-cells : from common clock binding, shall be set to 0. + +Optional properties: +- fixed-divider : If clocks have a fixed divider value, use this property. diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt new file mode 100644 index 00000000000..028b493e97f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/axi-clkgen.txt @@ -0,0 +1,22 @@ +Binding for the axi-clkgen clock generator + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "adi,axi-clkgen". +- #clock-cells : from common clock binding; Should always be set to 0. +- reg : Address and length of the axi-clkgen register set. +- clocks : Phandle and clock specifier for the parent clock. + +Optional properties: +- clock-output-names : From common clock binding. + +Example: + clock@0xff000000 { + compatible = "adi,axi-clkgen"; + #clock-cells = <0>; + reg = <0xff000000 0x1000>; + clocks = <&osc 1>; + }; diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt new file mode 100644 index 00000000000..ea5e26f16ae --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -0,0 +1,288 @@ +* Samsung Exynos4 Clock Controller + +The Exynos4 clock controller generates and supplies clock to various controllers +within the Exynos4 SoC. The clock binding described here is applicable to all +SoC's in the Exynos4 family. + +Required Properties: + +- comptible: should be one of the following. + - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC. + - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the controller. Each clock is +assigned an identifier and client nodes use this identifier to specify the +clock which they consume. Some of the clocks are available only on a particular +Exynos4 SoC and this is specified where applicable. + + + [Core Clocks] + + Clock ID SoC (if specific) + ----------------------------------------------- + + xxti 1 + xusbxti 2 + fin_pll 3 + fout_apll 4 + fout_mpll 5 + fout_epll 6 + fout_vpll 7 + sclk_apll 8 + sclk_mpll 9 + sclk_epll 10 + sclk_vpll 11 + arm_clk 12 + aclk200 13 + aclk100 14 + aclk160 15 + aclk133 16 + mout_mpll_user_t 17 Exynos4x12 + mout_mpll_user_c 18 Exynos4x12 + mout_core 19 + mout_apll 20 + + + [Clock Gate for Special Clocks] + + Clock ID SoC (if specific) + ----------------------------------------------- + + sclk_fimc0 128 + sclk_fimc1 129 + sclk_fimc2 130 + sclk_fimc3 131 + sclk_cam0 132 + sclk_cam1 133 + sclk_csis0 134 + sclk_csis1 135 + sclk_hdmi 136 + sclk_mixer 137 + sclk_dac 138 + sclk_pixel 139 + sclk_fimd0 140 + sclk_mdnie0 141 Exynos4412 + sclk_mdnie_pwm0 12 142 Exynos4412 + sclk_mipi0 143 + sclk_audio0 144 + sclk_mmc0 145 + sclk_mmc1 146 + sclk_mmc2 147 + sclk_mmc3 148 + sclk_mmc4 149 + sclk_sata 150 Exynos4210 + sclk_uart0 151 + sclk_uart1 152 + sclk_uart2 153 + sclk_uart3 154 + sclk_uart4 155 + sclk_audio1 156 + sclk_audio2 157 + sclk_spdif 158 + sclk_spi0 159 + sclk_spi1 160 + sclk_spi2 161 + sclk_slimbus 162 + sclk_fimd1 163 Exynos4210 + sclk_mipi1 164 Exynos4210 + sclk_pcm1 165 + sclk_pcm2 166 + sclk_i2s1 167 + sclk_i2s2 168 + sclk_mipihsi 169 Exynos4412 + sclk_mfc 170 + sclk_pcm0 171 + sclk_g3d 172 + sclk_pwm_isp 173 Exynos4x12 + sclk_spi0_isp 174 Exynos4x12 + sclk_spi1_isp 175 Exynos4x12 + sclk_uart_isp 176 Exynos4x12 + + [Peripheral Clock Gates] + + Clock ID SoC (if specific) + ----------------------------------------------- + + fimc0 256 + fimc1 257 + fimc2 258 + fimc3 259 + csis0 260 + csis1 261 + jpeg 262 + smmu_fimc0 263 + smmu_fimc1 264 + smmu_fimc2 265 + smmu_fimc3 266 + smmu_jpeg 267 + vp 268 + mixer 269 + tvenc 270 Exynos4210 + hdmi 271 + smmu_tv 272 + mfc 273 + smmu_mfcl 274 + smmu_mfcr 275 + g3d 276 + g2d 277 Exynos4210 + rotator 278 Exynos4210 + mdma 279 Exynos4210 + smmu_g2d 280 Exynos4210 + smmu_rotator 281 Exynos4210 + smmu_mdma 282 Exynos4210 + fimd0 283 + mie0 284 + mdnie0 285 Exynos4412 + dsim0 286 + smmu_fimd0 287 + fimd1 288 Exynos4210 + mie1 289 Exynos4210 + dsim1 290 Exynos4210 + smmu_fimd1 291 Exynos4210 + pdma0 292 + pdma1 293 + pcie_phy 294 + sata_phy 295 Exynos4210 + tsi 296 + sdmmc0 297 + sdmmc1 298 + sdmmc2 299 + sdmmc3 300 + sdmmc4 301 + sata 302 Exynos4210 + sromc 303 + usb_host 304 + usb_device 305 + pcie 306 + onenand 307 + nfcon 308 + smmu_pcie 309 + gps 310 + smmu_gps 311 + uart0 312 + uart1 313 + uart2 314 + uart3 315 + uart4 316 + i2c0 317 + i2c1 318 + i2c2 319 + i2c3 320 + i2c4 321 + i2c5 322 + i2c6 323 + i2c7 324 + i2c_hdmi 325 + tsadc 326 + spi0 327 + spi1 328 + spi2 329 + i2s1 330 + i2s2 331 + pcm0 332 + i2s0 333 + pcm1 334 + pcm2 335 + pwm 336 + slimbus 337 + spdif 338 + ac97 339 + modemif 340 + chipid 341 + sysreg 342 + hdmi_cec 343 + mct 344 + wdt 345 + rtc 346 + keyif 347 + audss 348 + mipi_hsi 349 Exynos4210 + mdma2 350 Exynos4210 + pixelasyncm0 351 + pixelasyncm1 352 + fimc_lite0 353 Exynos4x12 + fimc_lite1 354 Exynos4x12 + ppmuispx 355 Exynos4x12 + ppmuispmx 356 Exynos4x12 + fimc_isp 357 Exynos4x12 + fimc_drc 358 Exynos4x12 + fimc_fd 359 Exynos4x12 + mcuisp 360 Exynos4x12 + gicisp 361 Exynos4x12 + smmu_isp 362 Exynos4x12 + smmu_drc 363 Exynos4x12 + smmu_fd 364 Exynos4x12 + smmu_lite0 365 Exynos4x12 + smmu_lite1 366 Exynos4x12 + mcuctl_isp 367 Exynos4x12 + mpwm_isp 368 Exynos4x12 + i2c0_isp 369 Exynos4x12 + i2c1_isp 370 Exynos4x12 + mtcadc_isp 371 Exynos4x12 + pwm_isp 372 Exynos4x12 + wdt_isp 373 Exynos4x12 + uart_isp 374 Exynos4x12 + asyncaxim 375 Exynos4x12 + smmu_ispcx 376 Exynos4x12 + spi0_isp 377 Exynos4x12 + spi1_isp 378 Exynos4x12 + pwm_isp_sclk 379 Exynos4x12 + spi0_isp_sclk 380 Exynos4x12 + spi1_isp_sclk 381 Exynos4x12 + uart_isp_sclk 382 Exynos4x12 + + [Mux Clocks] + + Clock ID SoC (if specific) + ----------------------------------------------- + + mout_fimc0 384 + mout_fimc1 385 + mout_fimc2 386 + mout_fimc3 387 + mout_cam0 388 + mout_cam1 389 + mout_csis0 390 + mout_csis1 391 + mout_g3d0 392 + mout_g3d1 393 + mout_g3d 394 + aclk400_mcuisp 395 Exynos4x12 + + [Div Clocks] + + Clock ID SoC (if specific) + ----------------------------------------------- + + div_isp0 450 Exynos4x12 + div_isp1 451 Exynos4x12 + div_mcuisp0 452 Exynos4x12 + div_mcuisp1 453 Exynos4x12 + div_aclk200 454 Exynos4x12 + div_aclk400_mcuisp 455 Exynos4x12 + + +Example 1: An example of a clock controller node is listed below. + + clock: clock-controller@0x10030000 { + compatible = "samsung,exynos4210-clock"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; + +Example 2: UART controller node that consumes the clock generated by the clock + controller. Refer to the standard clock bindings for information + about 'clocks' and 'clock-names' property. + + serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 54 0>; + clocks = <&clock 314>, <&clock 153>; + clock-names = "uart", "clk_uart_baud0"; + }; diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt new file mode 100644 index 00000000000..781a6276adf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -0,0 +1,177 @@ +* Samsung Exynos5250 Clock Controller + +The Exynos5250 clock controller generates and supplies clock to various +controllers within the Exynos5250 SoC. + +Required Properties: + +- comptible: should be one of the following. + - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the controller. Each clock is +assigned an identifier and client nodes use this identifier to specify the +clock which they consume. + + + [Core Clocks] + + Clock ID + ---------------------------- + + fin_pll 1 + + [Clock Gate for Special Clocks] + + Clock ID + ---------------------------- + + sclk_cam_bayer 128 + sclk_cam0 129 + sclk_cam1 130 + sclk_gscl_wa 131 + sclk_gscl_wb 132 + sclk_fimd1 133 + sclk_mipi1 134 + sclk_dp 135 + sclk_hdmi 136 + sclk_pixel 137 + sclk_audio0 138 + sclk_mmc0 139 + sclk_mmc1 140 + sclk_mmc2 141 + sclk_mmc3 142 + sclk_sata 143 + sclk_usb3 144 + sclk_jpeg 145 + sclk_uart0 146 + sclk_uart1 147 + sclk_uart2 148 + sclk_uart3 149 + sclk_pwm 150 + sclk_audio1 151 + sclk_audio2 152 + sclk_spdif 153 + sclk_spi0 154 + sclk_spi1 155 + sclk_spi2 156 + + + [Peripheral Clock Gates] + + Clock ID + ---------------------------- + + gscl0 256 + gscl1 257 + gscl2 258 + gscl3 259 + gscl_wa 260 + gscl_wb 261 + smmu_gscl0 262 + smmu_gscl1 263 + smmu_gscl2 264 + smmu_gscl3 265 + mfc 266 + smmu_mfcl 267 + smmu_mfcr 268 + rotator 269 + jpeg 270 + mdma1 271 + smmu_rotator 272 + smmu_jpeg 273 + smmu_mdma1 274 + pdma0 275 + pdma1 276 + sata 277 + usbotg 278 + mipi_hsi 279 + sdmmc0 280 + sdmmc1 281 + sdmmc2 282 + sdmmc3 283 + sromc 284 + usb2 285 + usb3 286 + sata_phyctrl 287 + sata_phyi2c 288 + uart0 289 + uart1 290 + uart2 291 + uart3 292 + uart4 293 + i2c0 294 + i2c1 295 + i2c2 296 + i2c3 297 + i2c4 298 + i2c5 299 + i2c6 300 + i2c7 301 + i2c_hdmi 302 + adc 303 + spi0 304 + spi1 305 + spi2 306 + i2s1 307 + i2s2 308 + pcm1 309 + pcm2 310 + pwm 311 + spdif 312 + ac97 313 + hsi2c0 314 + hsi2c1 315 + hs12c2 316 + hs12c3 317 + chipid 318 + sysreg 319 + pmu 320 + cmu_top 321 + cmu_core 322 + cmu_mem 323 + tzpc0 324 + tzpc1 325 + tzpc2 326 + tzpc3 327 + tzpc4 328 + tzpc5 329 + tzpc6 330 + tzpc7 331 + tzpc8 332 + tzpc9 333 + hdmi_cec 334 + mct 335 + wdt 336 + rtc 337 + tmu 338 + fimd1 339 + mie1 340 + dsim0 341 + dp 342 + mixer 343 + hdmi 345 + +Example 1: An example of a clock controller node is listed below. + + clock: clock-controller@0x10010000 { + compatible = "samsung,exynos5250-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + }; + +Example 2: UART controller node that consumes the clock generated by the clock + controller. Refer to the standard clock bindings for information + about 'clocks' and 'clock-names' property. + + serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 54 0>; + clocks = <&clock 314>, <&clock 153>; + clock-names = "uart", "clk_uart_baud0"; + }; diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt new file mode 100644 index 00000000000..4499e9966bc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt @@ -0,0 +1,61 @@ +* Samsung Exynos5440 Clock Controller + +The Exynos5440 clock controller generates and supplies clock to various +controllers within the Exynos5440 SoC. + +Required Properties: + +- comptible: should be "samsung,exynos5440-clock". + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the controller. Each clock is +assigned an identifier and client nodes use this identifier to specify the +clock which they consume. + + + [Core Clocks] + + Clock ID + ---------------------------- + + xtal 1 + arm_clk 2 + + [Peripheral Clock Gates] + + Clock ID + ---------------------------- + + spi_baud 16 + pb0_250 17 + pr0_250 18 + pr1_250 19 + b_250 20 + b_125 21 + b_200 22 + sata 23 + usb 24 + gmac0 25 + cs250 26 + pb0_250_o 27 + pr0_250_o 28 + pr1_250_o 29 + b_250_o 30 + b_125_o 31 + b_200_o 32 + sata_o 33 + usb_o 34 + gmac0_o 35 + cs250_o 36 + +Example: An example of a clock controller node is listed below. + + clock: clock-controller@0x10010000 { + compatible = "samsung,exynos5440-clock"; + reg = <0x160000 0x10000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt new file mode 100644 index 00000000000..5757f9abfc2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt @@ -0,0 +1,24 @@ +Binding for simple fixed factor rate clock sources. + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "fixed-factor-clock". +- #clock-cells : from common clock binding; shall be set to 0. +- clock-div: fixed divider. +- clock-mult: fixed multiplier. +- clocks: parent clock. + +Optional properties: +- clock-output-names : From common clock binding. + +Example: + clock { + compatible = "fixed-factor-clock"; + clocks = <&parentclk>; + #clock-cells = <0>; + div = <2>; + mult = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx27-clock.txt b/Documentation/devicetree/bindings/clock/imx27-clock.txt new file mode 100644 index 00000000000..ab1a56e9de9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx27-clock.txt @@ -0,0 +1,117 @@ +* Clock bindings for Freescale i.MX27 + +Required properties: +- compatible: Should be "fsl,imx27-ccm" +- reg: Address and length of the register set +- interrupts: Should contain CCM interrupt +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. The following is a full list of i.MX27 +clocks and IDs. + + Clock ID + ----------------------- + dummy 0 + ckih 1 + ckil 2 + mpll 3 + spll 4 + mpll_main2 5 + ahb 6 + ipg 7 + nfc_div 8 + per1_div 9 + per2_div 10 + per3_div 11 + per4_div 12 + vpu_sel 13 + vpu_div 14 + usb_div 15 + cpu_sel 16 + clko_sel 17 + cpu_div 18 + clko_div 19 + ssi1_sel 20 + ssi2_sel 21 + ssi1_div 22 + ssi2_div 23 + clko_en 24 + ssi2_ipg_gate 25 + ssi1_ipg_gate 26 + slcdc_ipg_gate 27 + sdhc3_ipg_gate 28 + sdhc2_ipg_gate 29 + sdhc1_ipg_gate 30 + scc_ipg_gate 31 + sahara_ipg_gate 32 + rtc_ipg_gate 33 + pwm_ipg_gate 34 + owire_ipg_gate 35 + lcdc_ipg_gate 36 + kpp_ipg_gate 37 + iim_ipg_gate 38 + i2c2_ipg_gate 39 + i2c1_ipg_gate 40 + gpt6_ipg_gate 41 + gpt5_ipg_gate 42 + gpt4_ipg_gate 43 + gpt3_ipg_gate 44 + gpt2_ipg_gate 45 + gpt1_ipg_gate 46 + gpio_ipg_gate 47 + fec_ipg_gate 48 + emma_ipg_gate 49 + dma_ipg_gate 50 + cspi3_ipg_gate 51 + cspi2_ipg_gate 52 + cspi1_ipg_gate 53 + nfc_baud_gate 54 + ssi2_baud_gate 55 + ssi1_baud_gate 56 + vpu_baud_gate 57 + per4_gate 58 + per3_gate 59 + per2_gate 60 + per1_gate 61 + usb_ahb_gate 62 + slcdc_ahb_gate 63 + sahara_ahb_gate 64 + lcdc_ahb_gate 65 + vpu_ahb_gate 66 + fec_ahb_gate 67 + emma_ahb_gate 68 + emi_ahb_gate 69 + dma_ahb_gate 70 + csi_ahb_gate 71 + brom_ahb_gate 72 + ata_ahb_gate 73 + wdog_ipg_gate 74 + usb_ipg_gate 75 + uart6_ipg_gate 76 + uart5_ipg_gate 77 + uart4_ipg_gate 78 + uart3_ipg_gate 79 + uart2_ipg_gate 80 + uart1_ipg_gate 81 + ckih_div1p5 82 + fpm 83 + mpll_osc_sel 84 + mpll_sel 85 + +Examples: + +clks: ccm@10027000{ + compatible = "fsl,imx27-ccm"; + reg = <0x10027000 0x1000>; + #clock-cells = <1>; +}; + +uart1: serial@1000a000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000a000 0x1000>; + interrupts = <20>; + clocks = <&clks 81>, <&clks 61>; + clock-names = "ipg", "per"; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt index 2a0c904c46a..d71b4b2c077 100644 --- a/Documentation/devicetree/bindings/clock/imx5-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt @@ -38,7 +38,6 @@ clocks and IDs. usb_phy_podf 23 cpu_podf 24 di_pred 25 - tve_di 26 tve_s 27 uart1_ipg_gate 28 uart1_per_gate 29 @@ -172,6 +171,19 @@ clocks and IDs. can1_serial_gate 157 can1_ipg_gate 158 owire_gate 159 + gpu3d_s 160 + gpu2d_s 161 + gpu3d_gate 162 + gpu2d_gate 163 + garb_gate 164 + cko1_sel 165 + cko1_podf 166 + cko1 167 + cko2_sel 168 + cko2_podf 169 + cko2 170 + srtc_gate 171 + pata_gate 172 Examples (for mx53): diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index 969b38e06ad..6deb6fd1c7c 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -205,6 +205,9 @@ clocks and IDs. enet_ref 190 usbphy1_gate 191 usbphy2_gate 192 + pll4_post_div 193 + pll5_post_div 194 + pll5_video_div 195 Examples: diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt new file mode 100644 index 00000000000..d6cb083b90a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt @@ -0,0 +1,303 @@ +NVIDIA Tegra114 Clock And Reset Controller + +This binding uses the common clock binding: +Documentation/devicetree/bindings/clock/clock-bindings.txt + +The CAR (Clock And Reset) Controller on Tegra is the HW module responsible +for muxing and gating Tegra's clocks, and setting their rates. + +Required properties : +- compatible : Should be "nvidia,tegra114-car" +- reg : Should contain CAR registers location and length +- clocks : Should contain phandle and clock specifiers for two clocks: + the 32 KHz "32k_in", and the board-specific oscillator "osc". +- #clock-cells : Should be 1. + In clock consumers, this cell represents the clock ID exposed by the CAR. + + The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + registers. These IDs often match those in the CAR's RST_DEVICES registers, + but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + this case, those clocks are assigned IDs above 160 in order to highlight + this issue. Implementations that interpret these clock IDs as bit values + within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + explicitly handle these special cases. + + The balance of the clocks controlled by the CAR are assigned IDs of 160 and + above. + + 0 unassigned + 1 unassigned + 2 unassigned + 3 unassigned + 4 rtc + 5 timer + 6 uarta + 7 unassigned (register bit affects uartb and vfir) + 8 unassigned + 9 sdmmc2 + 10 unassigned (register bit affects spdif_in and spdif_out) + 11 i2s1 + 12 i2c1 + 13 ndflash + 14 sdmmc1 + 15 sdmmc4 + 16 unassigned + 17 pwm + 18 i2s2 + 19 epp + 20 unassigned (register bit affects vi and vi_sensor) + 21 2d + 22 usbd + 23 isp + 24 3d + 25 unassigned + 26 disp2 + 27 disp1 + 28 host1x + 29 vcp + 30 i2s0 + 31 unassigned + + 32 unassigned + 33 unassigned + 34 apbdma + 35 unassigned + 36 kbc + 37 unassigned + 38 unassigned + 39 unassigned (register bit affects fuse and fuse_burn) + 40 kfuse + 41 sbc1 + 42 nor + 43 unassigned + 44 sbc2 + 45 unassigned + 46 sbc3 + 47 i2c5 + 48 dsia + 49 unassigned + 50 mipi + 51 hdmi + 52 csi + 53 unassigned + 54 i2c2 + 55 uartc + 56 mipi-cal + 57 emc + 58 usb2 + 59 usb3 + 60 msenc + 61 vde + 62 bsea + 63 bsev + + 64 unassigned + 65 uartd + 66 unassigned + 67 i2c3 + 68 sbc4 + 69 sdmmc3 + 70 unassigned + 71 owr + 72 afi + 73 csite + 74 unassigned + 75 unassigned + 76 la + 77 trace + 78 soc_therm + 79 dtv + 80 ndspeed + 81 i2cslow + 82 dsib + 83 tsec + 84 unassigned + 85 unassigned + 86 unassigned + 87 unassigned + 88 unassigned + 89 xusb_host + 90 unassigned + 91 msenc + 92 csus + 93 unassigned + 94 unassigned + 95 unassigned (bit affects xusb_dev and xusb_dev_src) + + 96 unassigned + 97 unassigned + 98 unassigned + 99 mselect + 100 tsensor + 101 i2s3 + 102 i2s4 + 103 i2c4 + 104 sbc5 + 105 sbc6 + 106 d_audio + 107 apbif + 108 dam0 + 109 dam1 + 110 dam2 + 111 hda2codec_2x + 112 unassigned + 113 audio0_2x + 114 audio1_2x + 115 audio2_2x + 116 audio3_2x + 117 audio4_2x + 118 spdif_2x + 119 actmon + 120 extern1 + 121 extern2 + 122 extern3 + 123 unassigned + 124 unassigned + 125 hda + 126 unassigned + 127 se + + 128 hda2hdmi + 129 unassigned + 130 unassigned + 131 unassigned + 132 unassigned + 133 unassigned + 134 unassigned + 135 unassigned + 136 unassigned + 137 unassigned + 138 unassigned + 139 unassigned + 140 unassigned + 141 unassigned + 142 unassigned + 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src, + xusb_host_src and xusb_ss_src) + 144 cilab + 145 cilcd + 146 cile + 147 dsialp + 148 dsiblp + 149 unassigned + 150 dds + 151 unassigned + 152 dp2 + 153 amx + 154 adx + 155 unassigned (bit affects dfll_ref and dfll_soc) + 156 xusb_ss + + 192 uartb + 193 vfir + 194 spdif_in + 195 spdif_out + 196 vi + 197 vi_sensor + 198 fuse + 199 fuse_burn + 200 clk_32k + 201 clk_m + 202 clk_m_div2 + 203 clk_m_div4 + 204 pll_ref + 205 pll_c + 206 pll_c_out1 + 207 pll_c2 + 208 pll_c3 + 209 pll_m + 210 pll_m_out1 + 211 pll_p + 212 pll_p_out1 + 213 pll_p_out2 + 214 pll_p_out3 + 215 pll_p_out4 + 216 pll_a + 217 pll_a_out0 + 218 pll_d + 219 pll_d_out0 + 220 pll_d2 + 221 pll_d2_out0 + 222 pll_u + 223 pll_u_480M + 224 pll_u_60M + 225 pll_u_48M + 226 pll_u_12M + 227 pll_x + 228 pll_x_out0 + 229 pll_re_vco + 230 pll_re_out + 231 pll_e_out0 + 232 spdif_in_sync + 233 i2s0_sync + 234 i2s1_sync + 235 i2s2_sync + 236 i2s3_sync + 237 i2s4_sync + 238 vimclk_sync + 239 audio0 + 240 audio1 + 241 audio2 + 242 audio3 + 243 audio4 + 244 spdif + 245 clk_out_1 + 246 clk_out_2 + 247 clk_out_3 + 248 blink + 252 xusb_host_src + 253 xusb_falcon_src + 254 xusb_fs_src + 255 xusb_ss_src + 256 xusb_dev_src + 257 xusb_dev + 258 xusb_hs_src + 259 sclk + 260 hclk + 261 pclk + 262 cclk_g + 263 cclk_lp + 264 dfll_ref + 265 dfll_soc + +Example SoC include file: + +/ { + tegra_car: clock { + compatible = "nvidia,tegra114-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + usb@c5004000 { + clocks = <&tegra_car 58>; /* usb2 */ + }; +}; + +Example board file: + +/ { + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + osc: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + clk_32k: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + &tegra_car { + clocks = <&clk_32k> <&osc>; + }; +}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt index 0921fac7352..e885680f6b4 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt @@ -120,8 +120,8 @@ Required properties : 90 clk_d 91 unassigned 92 sus - 93 cdev1 - 94 cdev2 + 93 cdev2 + 94 cdev1 95 unassigned 96 uart2 diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt new file mode 100644 index 00000000000..cc374651662 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.txt @@ -0,0 +1,114 @@ +Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. + +Reference +[1] Si5351A/B/C Data Sheet + http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf + +The Si5351a/b/c are programmable i2c clock generators with upto 8 output +clocks. Si5351a also has a reduced pin-count package (MSOP10) where only +3 output clocks are accessible. The internal structure of the clock +generators can be found in [1]. + +==I2C device node== + +Required properties: +- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}". +- reg: i2c device address, shall be 0x60 or 0x61. +- #clock-cells: from common clock binding; shall be set to 1. +- clocks: from common clock binding; list of parent clock + handles, shall be xtal reference clock or xtal and clkin for + si5351c only. +- #address-cells: shall be set to 1. +- #size-cells: shall be set to 0. + +Optional properties: +- silabs,pll-source: pair of (number, source) for each pll. Allows + to overwrite clock source of pll A (number=0) or B (number=1). + +==Child nodes== + +Each of the clock outputs can be overwritten individually by +using a child node to the I2C device node. If a child node for a clock +output is not set, the eeprom configuration is not overwritten. + +Required child node properties: +- reg: number of clock output. + +Optional child node properties: +- silabs,clock-source: source clock of the output divider stage N, shall be + 0 = multisynth N + 1 = multisynth 0 for output clocks 0-3, else multisynth4 + 2 = xtal + 3 = clkin (si5351c only) +- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. +- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth + divider. +- silabs,pll-master: boolean, multisynth can change pll frequency. + +==Example== + +/* 25MHz reference crystal */ +ref25: ref25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; +}; + +i2c-master-node { + + /* Si5351a msop10 i2c clock generator */ + si5351a: clock-generator@60 { + compatible = "silabs,si5351a-msop"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + /* connect xtal input to 25MHz reference */ + clocks = <&ref25>; + + /* connect xtal input as source of pll0 and pll1 */ + silabs,pll-source = <0 0>, <1 0>; + + /* + * overwrite clkout0 configuration with: + * - 8mA output drive strength + * - pll0 as clock source of multisynth0 + * - multisynth0 as clock source of output divider + * - multisynth0 can change pll0 + * - set initial clock frequency of 74.25MHz + */ + clkout0 { + reg = <0>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <0>; + silabs,clock-source = <0>; + silabs,pll-master; + clock-frequency = <74250000>; + }; + + /* + * overwrite clkout1 configuration with: + * - 4mA output drive strength + * - pll1 as clock source of multisynth1 + * - multisynth1 as clock source of output divider + * - multisynth1 can change pll1 + */ + clkout1 { + reg = <1>; + silabs,drive-strength = <4>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + pll-master; + }; + + /* + * overwrite clkout2 configuration with: + * - xtal as clock source of output divider + */ + clkout2 { + reg = <2>; + silabs,clock-source = <2>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt new file mode 100644 index 00000000000..729f52426fe --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -0,0 +1,151 @@ +Device Tree Clock bindings for arch-sunxi + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "allwinner,sun4i-osc-clk" - for a gatable oscillator + "allwinner,sun4i-pll1-clk" - for the main PLL clock + "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock + "allwinner,sun4i-axi-clk" - for the AXI clock + "allwinner,sun4i-axi-gates-clk" - for the AXI gates + "allwinner,sun4i-ahb-clk" - for the AHB clock + "allwinner,sun4i-ahb-gates-clk" - for the AHB gates + "allwinner,sun4i-apb0-clk" - for the APB0 clock + "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates + "allwinner,sun4i-apb1-clk" - for the APB1 clock + "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing + "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates + +Required properties for all clocks: +- reg : shall be the control register address for the clock. +- clocks : shall be the input parent clock(s) phandle for the clock +- #clock-cells : from common clock binding; shall be set to 0 except for + "allwinner,sun4i-*-gates-clk" where it shall be set to 1 + +Additionally, "allwinner,sun4i-*-gates-clk" clocks require: +- clock-output-names : the corresponding gate names that the clock controls + +For example: + +osc24M: osc24M@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-osc-clk"; + reg = <0x01c20050 0x4>; + clocks = <&osc24M_fixed>; +}; + +pll1: pll1@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; +}; + +cpu: cpu@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>; +}; + + + +Gate clock outputs + +The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs; +their corresponding offsets as present on sun4i are listed below. Note that +some of these gates are not present on sun5i. + + * AXI gates ("allwinner,sun4i-axi-gates-clk") + + DRAM 0 + + * AHB gates ("allwinner,sun4i-ahb-gates-clk") + + USB0 0 + EHCI0 1 + OHCI0 2* + EHCI1 3 + OHCI1 4* + SS 5 + DMA 6 + BIST 7 + MMC0 8 + MMC1 9 + MMC2 10 + MMC3 11 + MS 12** + NAND 13 + SDRAM 14 + + ACE 16 + EMAC 17 + TS 18 + + SPI0 20 + SPI1 21 + SPI2 22 + SPI3 23 + PATA 24 + SATA 25** + GPS 26* + + VE 32 + TVD 33 + TVE0 34 + TVE1 35 + LCD0 36 + LCD1 37 + + CSI0 40 + CSI1 41 + + HDMI 43 + DE_BE0 44 + DE_BE1 45 + DE_FE0 46 + DE_FE1 47 + + MP 50 + + MALI400 52 + + * APB0 gates ("allwinner,sun4i-apb0-gates-clk") + + CODEC 0 + SPDIF 1* + AC97 2 + IIS 3 + + PIO 5 + IR0 6 + IR1 7 + + KEYPAD 10 + + * APB1 gates ("allwinner,sun4i-apb1-gates-clk") + + I2C0 0 + I2C1 1 + I2C2 2 + + CAN 4 + SCR 5 + PS20 6 + PS21 7 + + UART0 16 + UART1 17 + UART2 18 + UART3 19 + UART4 20 + UART5 21 + UART6 22 + UART7 23 + +Notation: + [*]: The datasheet didn't mention these, but they are present on AW code + [**]: The datasheet had this marked as "NC" but they are used on AW code diff --git a/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt b/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt new file mode 100644 index 00000000000..0715695e94a --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt @@ -0,0 +1,65 @@ +Generic ARM big LITTLE cpufreq driver's DT glue +----------------------------------------------- + +This is DT specific glue layer for generic cpufreq driver for big LITTLE +systems. + +Both required and optional properties listed below must be defined +under node /cpus/cpu@x. Where x is the first cpu inside a cluster. + +FIXME: Cpus should boot in the order specified in DT and all cpus for a cluster +must be present contiguously. Generic DT driver will check only node 'x' for +cpu:x. + +Required properties: +- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt + for details + +Optional properties: +- clock-latency: Specify the possible maximum transition latency for clock, + in unit of nanoseconds. + +Examples: + +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a15"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@100 { + compatible = "arm,cortex-a7"; + reg = <100>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 792000 950000 + 396000 750000 + 198000 450000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + }; + + cpu@101 { + compatible = "arm,cortex-a7"; + reg = <101>; + next-level-cache = <&L2>; + }; +}; diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt index 4416ccc3347..051f764bedb 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt @@ -32,7 +32,7 @@ cpus { 396000 950000 198000 850000 >; - transition-latency = <61036>; /* two CLK32 periods */ + clock-latency = <61036>; /* two CLK32 periods */ }; cpu@1 { diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt new file mode 100644 index 00000000000..caff1a57436 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt @@ -0,0 +1,28 @@ + +Exynos5440 cpufreq driver +------------------- + +Exynos5440 SoC cpufreq driver for CPU frequency scaling. + +Required properties: +- interrupts: Interrupt to know the completion of cpu frequency change. +- operating-points: Table of frequencies and voltage CPU could be transitioned into, + in the decreasing order. Frequency should be in KHz units and voltage + should be in microvolts. + +Optional properties: +- clock-latency: Clock monitor latency in microsecond. + +All the required listed above must be defined under node cpufreq. + +Example: +-------- + cpufreq@160000 { + compatible = "samsung,exynos5440-cpufreq"; + reg = <0x160000 0x1000>; + interrupts = <0 57 0>; + operating-points = < + 1000000 975000 + 800000 925000>; + clock-latency = <100000>; + }; diff --git a/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt new file mode 100644 index 00000000000..5c65eccd0e5 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt @@ -0,0 +1,15 @@ +Freescale SAHARA Cryptographic Accelerator included in some i.MX chips. +Currently only i.MX27 is supported. + +Required properties: +- compatible : Should be "fsl,<soc>-sahara" +- reg : Should contain SAHARA registers location and length +- interrupts : Should contain SAHARA interrupt number + +Example: + +sah@10025000 { + compatible = "fsl,imx27-sahara"; + reg = < 0x10025000 0x800>; + interrupts = <75>; +}; diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt index 3c046ee6e8b..c80e8a3402f 100644 --- a/Documentation/devicetree/bindings/dma/atmel-dma.txt +++ b/Documentation/devicetree/bindings/dma/atmel-dma.txt @@ -1,14 +1,39 @@ * Atmel Direct Memory Access Controller (DMA) Required properties: -- compatible: Should be "atmel,<chip>-dma" -- reg: Should contain DMA registers location and length -- interrupts: Should contain DMA interrupt +- compatible: Should be "atmel,<chip>-dma". +- reg: Should contain DMA registers location and length. +- interrupts: Should contain DMA interrupt. +- #dma-cells: Must be <2>, used to represent the number of integer cells in +the dmas property of client devices. -Examples: +Example: -dma@ffffec00 { +dma0: dma@ffffec00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; interrupts = <21>; + #dma-cells = <2>; +}; + +DMA clients connected to the Atmel DMA controller must use the format +described in the dma.txt file, using a three-cell specifier for each channel: +a phandle plus two interger cells. +The three cells in order are: + +1. A phandle pointing to the DMA controller. +2. The memory interface (16 most significant bits), the peripheral interface +(16 less significant bits). +3. The peripheral identifier for the hardware handshaking interface. The +identifier can be different for tx and rx. + +Example: + +i2c0@i2c@f8010000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8010000 0x100>; + interrupts = <9 4 6>; + dmas = <&dma0 1 7>, + <&dma0 1 8>; + dma-names = "tx", "rx"; }; diff --git a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt index ded0398d3bd..a4873e5e3e3 100644 --- a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt @@ -3,17 +3,58 @@ Required properties: - compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx" - reg : Should contain registers location and length +- interrupts : Should contain the interrupt numbers of DMA channels. + If a channel is empty/reserved, 0 should be filled in place. +- #dma-cells : Must be <1>. The number cell specifies the channel ID. +- dma-channels : Number of channels supported by the DMA controller + +Optional properties: +- interrupt-names : Name of DMA channel interrupts Supported chips: imx23, imx28. Examples: -dma-apbh@80004000 { + +dma_apbh: dma-apbh@80004000 { compatible = "fsl,imx28-dma-apbh"; - reg = <0x80004000 2000>; + reg = <0x80004000 0x2000>; + interrupts = <82 83 84 85 + 88 88 88 88 + 88 88 88 88 + 87 86 0 0>; + interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", + "gpmi0", "gmpi1", "gpmi2", "gmpi3", + "gpmi4", "gmpi5", "gpmi6", "gmpi7", + "hsadc", "lcdif", "empty", "empty"; + #dma-cells = <1>; + dma-channels = <16>; }; -dma-apbx@80024000 { +dma_apbx: dma-apbx@80024000 { compatible = "fsl,imx28-dma-apbx"; - reg = <0x80024000 2000>; + reg = <0x80024000 0x2000>; + interrupts = <78 79 66 0 + 80 81 68 69 + 70 71 72 73 + 74 75 76 77>; + interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", + "saif0", "saif1", "i2c0", "i2c1", + "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", + "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; + #dma-cells = <1>; + dma-channels = <16>; +}; + +DMA clients connected to the MXS DMA controller must use the format +described in the dma.txt file. + +Examples: + +auart0: serial@8006a000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006a000 0x2000>; + interrupts = <112>; + dmas = <&dma_apbx 8>, <&dma_apbx 9>; + dma-names = "rx", "tx"; }; diff --git a/Documentation/devicetree/bindings/drm/exynos/g2d.txt b/Documentation/devicetree/bindings/drm/exynos/g2d.txt deleted file mode 100644 index 1eb124d35a9..00000000000 --- a/Documentation/devicetree/bindings/drm/exynos/g2d.txt +++ /dev/null @@ -1,22 +0,0 @@ -Samsung 2D Graphic Accelerator using DRM frame work - -Samsung FIMG2D is a graphics 2D accelerator which supports Bit Block Transfer. -We set the drawing-context registers for configuring rendering parameters and -then start rendering. -This driver is for SOCs which contain G2D IPs with version 4.1. - -Required properties: - -compatible: - should be "samsung,exynos-g2d-41". - -reg: - physical base address of the controller and length - of memory mapped region. - -interrupts: - interrupt combiner values. - -Example: - g2d { - compatible = "samsung,exynos-g2d-41"; - reg = <0x10850000 0x1000>; - interrupts = <0 91 0>; - }; diff --git a/Documentation/devicetree/bindings/fb/mxsfb.txt b/Documentation/devicetree/bindings/fb/mxsfb.txt index b41e5e52a67..96ec5179c8a 100644 --- a/Documentation/devicetree/bindings/fb/mxsfb.txt +++ b/Documentation/devicetree/bindings/fb/mxsfb.txt @@ -5,9 +5,16 @@ Required properties: imx23 and imx28. - reg: Address and length of the register set for lcdif - interrupts: Should contain lcdif interrupts +- display : phandle to display node (see below for details) -Optional properties: -- panel-enable-gpios : Should specify the gpio for panel enable +* display node + +Required properties: +- bits-per-pixel : <16> for RGB565, <32> for RGB888/666. +- bus-width : number of data lines. Could be <8>, <16>, <18> or <24>. + +Required sub-node: +- display-timings : Refer to binding doc display-timing.txt for details. Examples: @@ -15,5 +22,28 @@ lcdif@80030000 { compatible = "fsl,imx28-lcdif"; reg = <0x80030000 2000>; interrupts = <38 86>; - panel-enable-gpios = <&gpio3 30 0>; + + display: display { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <164>; + hback-porch = <89>; + hsync-len = <10>; + vback-porch = <23>; + vfront-porch = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-grgpio.txt b/Documentation/devicetree/bindings/gpio/gpio-grgpio.txt new file mode 100644 index 00000000000..e466598105f --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-grgpio.txt @@ -0,0 +1,26 @@ +Aeroflex Gaisler GRGPIO General Purpose I/O cores. + +The GRGPIO GPIO core is available in the GRLIB VHDL IP core library. + +Note: In the ordinary environment for the GRGPIO core, a Leon SPARC system, +these properties are built from information in the AMBA plug&play. + +Required properties: + +- name : Should be "GAISLER_GPIO" or "01_01a" + +- reg : Address and length of the register set for the device + +- interrupts : Interrupt numbers for this device + +Optional properties: + +- nbits : The number of gpio lines. If not present driver assumes 32 lines. + +- irqmap : An array with an index for each gpio line. An index is either a valid + index into the interrupts property array, or 0xffffffff that indicates + no irq for that line. Driver provides no interrupt support if not + present. + +For further information look in the documentation for the GLIB IP core library: +http://www.gaisler.com/products/grlib/grip.pdf diff --git a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt new file mode 100644 index 00000000000..629d0ef1730 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt @@ -0,0 +1,47 @@ +Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for +8-/16-bit I/O expander with serial interface (I2C/SPI) + +Required properties: +- compatible : Should be + - "mcp,mcp23s08" for 8 GPIO SPI version + - "mcp,mcp23s17" for 16 GPIO SPI version + - "mcp,mcp23008" for 8 GPIO I2C version or + - "mcp,mcp23017" for 16 GPIO I2C version of the chip +- #gpio-cells : Should be two. + - first cell is the pin number + - second cell is used to specify flags. Flags are currently unused. +- gpio-controller : Marks the device node as a GPIO controller. +- reg : For an address on its bus. I2C uses this a the I2C address of the chip. + SPI uses this to specify the chipselect line which the chip is + connected to. The driver and the SPI variant of the chip support + multiple chips on the same chipselect. Have a look at + mcp,spi-present-mask below. + +Required device specific properties (only for SPI chips): +- mcp,spi-present-mask : This is a present flag, that makes only sense for SPI + chips - as the name suggests. Multiple SPI chips can share the same + SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a + chip connected with the corresponding spi address set. For example if + you have a chip with address 3 connected, you have to set bit3 to 1, + which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not + possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at + least one bit to 1 for SPI chips. +- spi-max-frequency = The maximum frequency this chip is able to handle + +Example I2C: +gpiom1: gpio@20 { + compatible = "mcp,mcp23017"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; +}; + +Example SPI: +gpiom1: gpio@0 { + compatible = "mcp,mcp23s17"; + gpio-controller; + #gpio-cells = <2>; + spi-present-mask = <0x01>; + reg = <0>; + spi-max-frequency = <1000000>; +}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-omap.txt b/Documentation/devicetree/bindings/gpio/gpio-omap.txt index bff51a2fee1..8d950522e7f 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-omap.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-omap.txt @@ -5,12 +5,12 @@ Required properties: - "ti,omap2-gpio" for OMAP2 controllers - "ti,omap3-gpio" for OMAP3 controllers - "ti,omap4-gpio" for OMAP4 controllers +- gpio-controller : Marks the device node as a GPIO controller. - #gpio-cells : Should be two. - first cell is the pin number - second cell is used to specify optional parameters (unused) -- gpio-controller : Marks the device node as a GPIO controller. +- interrupt-controller: Mark the device node as an interrupt controller. - #interrupt-cells : Should be 2. -- interrupt-controller: Mark the device node as an interrupt controller The first cell is the GPIO number. The second cell is used to specify flags: bits[3:0] trigger type and level flags: @@ -20,8 +20,11 @@ Required properties: 8 = active low level-sensitive. OMAP specific properties: -- ti,hwmods: Name of the hwmod associated to the GPIO: - "gpio<X>", <X> being the 1-based instance number from the HW spec +- ti,hwmods: Name of the hwmod associated to the GPIO: + "gpio<X>", <X> being the 1-based instance number + from the HW spec. +- ti,gpio-always-on: Indicates if a GPIO bank is always powered and + so will never lose its logic state. Example: @@ -29,8 +32,8 @@ Example: gpio4: gpio4 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio4"; - #gpio-cells = <2>; gpio-controller; - #interrupt-cells = <2>; + #gpio-cells = <2>; interrupt-controller; + #interrupt-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt deleted file mode 100644 index f4dc5233167..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt +++ /dev/null @@ -1,24 +0,0 @@ -VIA/Wondermedia VT8500 GPIO Controller ------------------------------------------------------ - -Required properties: -- compatible : "via,vt8500-gpio", "wm,wm8505-gpio" - or "wm,wm8650-gpio" depending on your SoC -- reg : Should contain 1 register range (address and length) -- #gpio-cells : should be <3>. - 1) bank - 2) pin number - 3) flags - should be 0 - -Example: - - gpio: gpio-controller@d8110000 { - compatible = "via,vt8500-gpio"; - gpio-controller; - reg = <0xd8110000 0x10000>; - #gpio-cells = <3>; - }; - - vibrate { - gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */ - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index a33628759d3..d933af37069 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example, compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; reg = <0x1460 0x18>; gpio-controller; - gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>; + gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; } @@ -107,8 +107,8 @@ where, Next values specify the base pin and number of pins for the range handled by 'qe_pio_e' gpio. In the given example from base pin 20 to - pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled - by this gpio controller. + pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under + pinctrl2 with gpio offset 10 is handled by this gpio controller. The pinctrl node must have "#gpio-range-cells" property to show number of arguments to pass with phandle from gpio controllers node. diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt index e13787498bc..9b3f1d4a88d 100644 --- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt @@ -1,7 +1,10 @@ * Marvell PXA GPIO controller Required properties: -- compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio" +- compatible : Should be "intel,pxa25x-gpio", "intel,pxa26x-gpio", + "intel,pxa27x-gpio", "intel,pxa3xx-gpio", + "marvell,pxa93x-gpio", "marvell,mmp-gpio" or + "marvell,mmp2-gpio". - reg : Address and length of the register set for the device - interrupts : Should be the port interrupt shared by all gpio pins. There're three gpio interrupts in arch-pxa, and they're gpio0, @@ -18,7 +21,7 @@ Required properties: Example: gpio: gpio@d4019000 { - compatible = "mrvl,mmp-gpio"; + compatible = "marvell,mmp-gpio"; reg = <0xd4019000 0x1000>; interrupts = <49>; interrupt-name = "gpio_mux"; diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt new file mode 100644 index 00000000000..2b14a940eb7 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt @@ -0,0 +1,20 @@ +* Samsung 2D Graphics Accelerator + +Required properties: + - compatible : value should be one among the following: + (a) "samsung,s5pv210-g2d" for G2D IP present in S5PV210 & Exynos4210 SoC + (b) "samsung,exynos4212-g2d" for G2D IP present in Exynos4x12 SoCs + (c) "samsung,exynos5250-g2d" for G2D IP present in Exynos5250 SoC + + - reg : Physical base address of the IP registers and length of memory + mapped region. + + - interrupts : G2D interrupt number to the CPU. + +Example: + g2d@12800000 { + compatible = "samsung,s5pv210-g2d"; + reg = <0x12800000 0x1000>; + interrupts = <0 89 0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt new file mode 100644 index 00000000000..c6f66674f19 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt @@ -0,0 +1,29 @@ +NTC Thermistor hwmon sensors +------------------------------- + +Requires node properties: +- "compatible" value : one of + "ntc,ncp15wb473" + "ntc,ncp18wb473" + "ntc,ncp21wb473" + "ntc,ncp03wb473" + "ntc,ncp15wl333" +- "pullup-uv" Pull up voltage in micro volts +- "pullup-ohm" Pull up resistor value in ohms +- "pulldown-ohm" Pull down resistor value in ohms +- "connected-positive" Always ON, If not specified. + Status change is possible. +- "io-channels" Channel node of ADC to be used for + conversion. + +Read more about iio bindings at + Documentation/devicetree/bindings/iio/iio-bindings.txt + +Example: + ncp15wb473@0 { + compatible = "ntc,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 3>; + }; diff --git a/Documentation/devicetree/bindings/hwrng/timeriomem_rng.txt b/Documentation/devicetree/bindings/hwrng/timeriomem_rng.txt new file mode 100644 index 00000000000..6616d15866a --- /dev/null +++ b/Documentation/devicetree/bindings/hwrng/timeriomem_rng.txt @@ -0,0 +1,18 @@ +HWRNG support for the timeriomem_rng driver + +Required properties: +- compatible : "timeriomem_rng" +- reg : base address to sample from +- period : wait time in microseconds to use between samples + +N.B. currently 'reg' must be four bytes wide and aligned + +Example: + +hwrng@44 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "timeriomem_rng"; + reg = <0x44 0x04>; + period = <1000000>; +}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt b/Documentation/devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt new file mode 100644 index 00000000000..1ac8ea8ade1 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt @@ -0,0 +1,80 @@ +GPIO-based I2C Arbitration Using a Challenge & Response Mechanism +================================================================= +This uses GPIO lines and a challenge & response mechanism to arbitrate who is +the master of an I2C bus in a multimaster situation. + +In many cases using GPIOs to arbitrate is not needed and a design can use +the standard I2C multi-master rules. Using GPIOs is generally useful in +the case where there is a device on the bus that has errata and/or bugs +that makes standard multimaster mode not feasible. + + +Algorithm: + +All masters on the bus have a 'bus claim' line which is an output that the +others can see. These are all active low with pull-ups enabled. We'll +describe these lines as: + +- OUR_CLAIM: output from us signaling to other hosts that we want the bus +- THEIR_CLAIMS: output from others signaling that they want the bus + +The basic algorithm is to assert your line when you want the bus, then make +sure that the other side doesn't want it also. A detailed explanation is best +done with an example. + +Let's say we want to claim the bus. We: +1. Assert OUR_CLAIM. +2. Waits a little bit for the other sides to notice (slew time, say 10 + microseconds). +3. Check THEIR_CLAIMS. If none are asserted then the we have the bus and we are + done. +4. Otherwise, wait for a few milliseconds and see if THEIR_CLAIMS are released. +5. If not, back off, release the claim and wait for a few more milliseconds. +6. Go back to 1 (until retry time has expired). + + +Required properties: +- compatible: i2c-arb-gpio-challenge +- our-claim-gpio: The GPIO that we use to claim the bus. +- their-claim-gpios: The GPIOs that the other sides use to claim the bus. + Note that some implementations may only support a single other master. +- Standard I2C mux properties. See mux.txt in this directory. +- Single I2C child bus node at reg 0. See mux.txt in this directory. + +Optional properties: +- slew-delay-us: microseconds to wait for a GPIO to go high. Default is 10 us. +- wait-retry-us: we'll attempt another claim after this many microseconds. + Default is 3000 us. +- wait-free-us: we'll give up after this many microseconds. Default is 50000 us. + + +Example: + i2c@12CA0000 { + compatible = "acme,some-i2c-device"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c-arbitrator { + compatible = "i2c-arb-gpio-challenge"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@12CA0000}>; + + our-claim-gpio = <&gpf0 3 1>; + their-claim-gpios = <&gpe0 4 1>; + slew-delay-us = <10>; + wait-retry-us = <3000>; + wait-free-us = <50000>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@52 { + // Normal I2C device + }; + }; + }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt index 7a3fe9e5f4c..4e1c8ac01eb 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt @@ -3,10 +3,13 @@ Required properties: - compatible: Should be "fsl,<chip>-i2c" - reg: Should contain registers location and length -- interrupts: Should contain ERROR and DMA interrupts +- interrupts: Should contain ERROR interrupt number - clock-frequency: Desired I2C bus clock frequency in Hz. Only 100000Hz and 400000Hz modes are supported. -- fsl,i2c-dma-channel: APBX DMA channel for the I2C +- dmas: DMA specifier, consisting of a phandle to DMA controller node + and I2C DMA channel ID. + Refer to dma.txt and fsl-mxs-dma.txt for details. +- dma-names: Must be "rx-tx". Examples: @@ -15,7 +18,8 @@ i2c0: i2c@80058000 { #size-cells = <0>; compatible = "fsl,imx28-i2c"; reg = <0x80058000 2000>; - interrupts = <111 68>; + interrupts = <111>; clock-frequency = <100000>; - fsl,i2c-dma-channel = <6>; + dmas = <&dma_apbx 6>; + dma-names = "rx-tx"; }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt index f98d4c5b5cc..296eb453612 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt @@ -26,7 +26,7 @@ Required for all cases except "samsung,s3c2440-hdmiphy-i2c": - pinctrl-names: Should contain only one value - "default". Optional properties: - - samsung,i2c-slave-addr: Slave address in multi-master enviroment. If not + - samsung,i2c-slave-addr: Slave address in multi-master environment. If not specified, default value is 0. - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not specified, the default value in Hz is 100000. diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt new file mode 100644 index 00000000000..ef77cc7a0e4 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt @@ -0,0 +1,60 @@ +NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver. + +Required properties: +- compatible : should be: + "nvidia,tegra114-i2c" + "nvidia,tegra30-i2c" + "nvidia,tegra20-i2c" + "nvidia,tegra20-i2c-dvc" + Details of compatible are as follows: + nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C + controller. This only support master mode of I2C communication. Register + interface/offset and interrupts handling are different than generic I2C + controller. Driver of DVC I2C controller is only compatible with + "nvidia,tegra20-i2c-dvc". + nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support + master and slave mode of I2C communication. The i2c-tegra driver only + support master mode of I2C communication. Driver of I2C controller is + only compatible with "nvidia,tegra20-i2c". + nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is + very much similar to Tegra20 I2C controller with additional feature: + Continue Transfer Support. This feature helps to implement M_NO_START + as per I2C core API transfer flags. Driver of I2C controller is + compatible with "nvidia,tegra30-i2c" to enable the continue transfer + support. This is also compatible with "nvidia,tegra20-i2c" without + continue transfer support. + nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is + very much similar to Tegra30 I2C controller with some hardware + modification: + - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and + fast-clk. Tegra114 has only one clock source called as div-clk and + hence clock mechanism is changed in I2C controller. + - Tegra30/Tegra20 I2C controller has enabled per packet transfer by + default and there is no way to disable it. Tegra114 has this + interrupt disable by default and SW need to enable explicitly. + Due to above changes, Tegra114 I2C driver makes incompatible with + previous hardware driver. Hence, tegra114 I2C controller is compatible + with "nvidia,tegra114-i2c". +- reg: Should contain I2C controller registers physical address and length. +- interrupts: Should contain I2C controller interrupts. +- address-cells: Address cells for I2C device address. +- size-cells: Size of the I2C device address. +- clocks: Clock ID as per + Documentation/devicetree/bindings/clock/tegra<chip-id>.txt + for I2C controller. +- clock-names: Name of the clock: + Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk". + Tegra114 I2C controller: "div-clk". + +Example: + + i2c@7000c000 { + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <0 38 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 12>, <&tegra_car 124>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index 446859fcdca..ad6a73852f0 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -35,6 +35,8 @@ fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51 fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec +infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) +infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface diff --git a/Documentation/devicetree/bindings/iio/iio-bindings.txt b/Documentation/devicetree/bindings/iio/iio-bindings.txt new file mode 100644 index 00000000000..0b447d9ad19 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/iio-bindings.txt @@ -0,0 +1,97 @@ +This binding is derived from clock bindings, and based on suggestions +from Lars-Peter Clausen [1]. + +Sources of IIO channels can be represented by any node in the device +tree. Those nodes are designated as IIO providers. IIO consumer +nodes use a phandle and IIO specifier pair to connect IIO provider +outputs to IIO inputs. Similar to the gpio specifiers, an IIO +specifier is an array of one or more cells identifying the IIO +output on a device. The length of an IIO specifier is defined by the +value of a #io-channel-cells property in the IIO provider node. + +[1] http://marc.info/?l=linux-iio&m=135902119507483&w=2 + +==IIO providers== + +Required properties: +#io-channel-cells: Number of cells in an IIO specifier; Typically 0 for nodes + with a single IIO output and 1 for nodes with multiple + IIO outputs. + +Example for a simple configuration with no trigger: + + adc: voltage-sensor@35 { + compatible = "maxim,max1139"; + reg = <0x35>; + #io-channel-cells = <1>; + }; + +Example for a configuration with trigger: + + adc@35 { + compatible = "some-vendor,some-adc"; + reg = <0x35>; + + adc1: iio-device@0 { + #io-channel-cells = <1>; + /* other properties */ + }; + adc2: iio-device@1 { + #io-channel-cells = <1>; + /* other properties */ + }; + }; + +==IIO consumers== + +Required properties: +io-channels: List of phandle and IIO specifier pairs, one pair + for each IIO input to the device. Note: if the + IIO provider specifies '0' for #io-channel-cells, + then only the phandle portion of the pair will appear. + +Optional properties: +io-channel-names: + List of IIO input name strings sorted in the same + order as the io-channels property. Consumers drivers + will use io-channel-names to match IIO input names + with IIO specifiers. +io-channel-ranges: + Empty property indicating that child nodes can inherit named + IIO channels from this node. Useful for bus nodes to provide + and IIO channel to their children. + +For example: + + device { + io-channels = <&adc 1>, <&ref 0>; + io-channel-names = "vcc", "vdd"; + }; + +This represents a device with two IIO inputs, named "vcc" and "vdd". +The vcc channel is connected to output 1 of the &adc device, and the +vdd channel is connected to output 0 of the &ref device. + +==Example== + + adc: max1139@35 { + compatible = "maxim,max1139"; + reg = <0x35>; + #io-channel-cells = <1>; + }; + + ... + + iio_hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, + <&adc 3>, <&adc 4>, <&adc 5>, + <&adc 6>, <&adc 7>, <&adc 8>, + <&adc 9>; + }; + + some_consumer { + compatible = "some-consumer"; + io-channels = <&adc 10>, <&adc 11>; + io-channel-names = "adc1", "adc2"; + }; diff --git a/Documentation/devicetree/bindings/input/cros-ec-keyb.txt b/Documentation/devicetree/bindings/input/cros-ec-keyb.txt new file mode 100644 index 00000000000..0f6355ce39b --- /dev/null +++ b/Documentation/devicetree/bindings/input/cros-ec-keyb.txt @@ -0,0 +1,72 @@ +ChromeOS EC Keyboard + +Google's ChromeOS EC Keyboard is a simple matrix keyboard implemented on +a separate EC (Embedded Controller) device. It provides a message for reading +key scans from the EC. These are then converted into keycodes for processing +by the kernel. + +This binding is based on matrix-keymap.txt and extends/modifies it as follows: + +Required properties: +- compatible: "google,cros-ec-keyb" + +Optional properties: +- google,needs-ghost-filter: True to enable a ghost filter for the matrix +keyboard. This is recommended if the EC does not have its own logic or +hardware for this. + + +Example: + +cros-ec-keyb { + compatible = "google,cros-ec-keyb"; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,needs-ghost-filter; + /* + * Keymap entries take the form of 0xRRCCKKKK where + * RR=Row CC=Column KKKK=Key Code + * The values below are for a US keyboard layout and + * are taken from the Linux driver. Note that the + * 102ND key is not used for US keyboards. + */ + linux,keymap = < + /* CAPSLCK F1 B F10 */ + 0x0001003a 0x0002003b 0x00030030 0x00040044 + /* N = R_ALT ESC */ + 0x00060031 0x0008000d 0x000a0064 0x01010001 + /* F4 G F7 H */ + 0x0102003e 0x01030022 0x01040041 0x01060023 + /* ' F9 BKSPACE L_CTRL */ + 0x01080028 0x01090043 0x010b000e 0x0200001d + /* TAB F3 T F6 */ + 0x0201000f 0x0202003d 0x02030014 0x02040040 + /* ] Y 102ND [ */ + 0x0205001b 0x02060015 0x02070056 0x0208001a + /* F8 GRAVE F2 5 */ + 0x02090042 0x03010029 0x0302003c 0x03030006 + /* F5 6 - \ */ + 0x0304003f 0x03060007 0x0308000c 0x030b002b + /* R_CTRL A D F */ + 0x04000061 0x0401001e 0x04020020 0x04030021 + /* S K J ; */ + 0x0404001f 0x04050025 0x04060024 0x04080027 + /* L ENTER Z C */ + 0x04090026 0x040b001c 0x0501002c 0x0502002e + /* V X , M */ + 0x0503002f 0x0504002d 0x05050033 0x05060032 + /* L_SHIFT / . SPACE */ + 0x0507002a 0x05080035 0x05090034 0x050B0039 + /* 1 3 4 2 */ + 0x06010002 0x06020004 0x06030005 0x06040003 + /* 8 7 0 9 */ + 0x06050009 0x06060008 0x0608000b 0x0609000a + /* L_ALT DOWN RIGHT Q */ + 0x060a0038 0x060b006c 0x060c006a 0x07010010 + /* E R W I */ + 0x07020012 0x07030013 0x07040011 0x07050017 + /* U R_SHIFT P O */ + 0x07060016 0x07070036 0x07080019 0x07090018 + /* UP LEFT */ + 0x070b0067 0x070c0069>; +}; diff --git a/Documentation/devicetree/bindings/input/ps2keyb-mouse-apbps2.txt b/Documentation/devicetree/bindings/input/ps2keyb-mouse-apbps2.txt new file mode 100644 index 00000000000..3029c5694cf --- /dev/null +++ b/Documentation/devicetree/bindings/input/ps2keyb-mouse-apbps2.txt @@ -0,0 +1,16 @@ +Aeroflex Gaisler APBPS2 PS/2 Core, supporting Keyboard or Mouse. + +The APBPS2 PS/2 core is available in the GRLIB VHDL IP core library. + +Note: In the ordinary environment for the APBPS2 core, a LEON SPARC system, +these properties are built from information in the AMBA plug&play and from +bootloader settings. + +Required properties: + +- name : Should be "GAISLER_APBPS2" or "01_060" +- reg : Address and length of the register set for the device +- interrupts : Interrupt numbers for this device + +For further information look in the documentation for the GLIB IP core library: +http://www.gaisler.com/products/grlib/grip.pdf diff --git a/Documentation/devicetree/bindings/input/touchscreen/auo_pixcir_ts.txt b/Documentation/devicetree/bindings/input/touchscreen/auo_pixcir_ts.txt new file mode 100644 index 00000000000..f40f21c642b --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/auo_pixcir_ts.txt @@ -0,0 +1,30 @@ +* AUO in-cell touchscreen controller using Pixcir sensors + +Required properties: +- compatible: must be "auo,auo_pixcir_ts" +- reg: I2C address of the chip +- interrupts: interrupt to which the chip is connected +- gpios: gpios the chip is connected to + first one is the interrupt gpio and second one the reset gpio +- x-size: horizontal resolution of touchscreen +- y-size: vertical resolution of touchscreen + +Example: + + i2c@00000000 { + /* ... */ + + auo_pixcir_ts@5c { + compatible = "auo,auo_pixcir_ts"; + reg = <0x5c>; + interrupts = <2 0>; + + gpios = <&gpf 2 0 2>, /* INT */ + <&gpf 5 1 0>; /* RST */ + + x-size = <800>; + y-size = <600>; + }; + + /* ... */ + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/sitronix-st1232.txt b/Documentation/devicetree/bindings/input/touchscreen/sitronix-st1232.txt new file mode 100644 index 00000000000..64ad48b824a --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/sitronix-st1232.txt @@ -0,0 +1,24 @@ +* Sitronix st1232 touchscreen controller + +Required properties: +- compatible: must be "sitronix,st1232" +- reg: I2C address of the chip +- interrupts: interrupt to which the chip is connected + +Optional properties: +- gpios: a phandle to the reset GPIO + +Example: + + i2c@00000000 { + /* ... */ + + touchscreen@55 { + compatible = "sitronix,st1232"; + reg = <0x55>; + interrupts = <2 0>; + gpios = <&gpio1 166 0>; + }; + + /* ... */ + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt index 7f9fb85f545..e7f4dc14eff 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt @@ -2,7 +2,7 @@ Allwinner Sunxi Interrupt Controller Required properties: -- compatible : should be "allwinner,sunxi-ic" +- compatible : should be "allwinner,sun4i-ic" - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an @@ -97,7 +97,7 @@ The interrupt sources are as follows: Example: intc: interrupt-controller { - compatible = "allwinner,sunxi-ic"; + compatible = "allwinner,sun4i-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <2>; diff --git a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt new file mode 100644 index 00000000000..c54c5a9a2a9 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt @@ -0,0 +1,53 @@ +Samsung S3C24XX Interrupt Controllers + +The S3C24XX SoCs contain a custom set of interrupt controllers providing a +varying number of interrupt sources. The set consists of a main- and sub- +controller and on newer SoCs even a second main controller. + +Required properties: +- compatible: Compatible property value should be "samsung,s3c2410-irq" + for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later. + +- reg: Physical base address of the controller and length of memory mapped + region. + +- interrupt-controller : Identifies the node as an interrupt controller + +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 4 and interrupt descriptor shall + have the following format: + <ctrl_num parent_irq ctrl_irq type> + + ctrl_num contains the controller to use: + - 0 ... main controller + - 1 ... sub controller + - 2 ... second main controller on s3c2416 and s3c2450 + parent_irq contains the parent bit in the main controller and will be + ignored in main controllers + ctrl_irq contains the interrupt bit of the controller + type contains the trigger type to use + +Example: + + interrupt-controller@4a000000 { + compatible = "samsung,s3c2410-irq"; + reg = <0x4a000000 0x100>; + interrupt-controller; + #interrupt-cells=<4>; + }; + + [...] + + serial@50000000 { + compatible = "samsung,s3c2410-uart"; + reg = <0x50000000 0x4000>; + interrupt-parent = <&subintc>; + interrupts = <1 28 0 4>, <1 28 1 4>; + }; + + rtc@57000000 { + compatible = "samsung,s3c2410-rtc"; + reg = <0x57000000 0x100>; + interrupt-parent = <&intc>; + interrupts = <0 30 0 3>, <0 8 0 3>; + }; diff --git a/Documentation/devicetree/bindings/leds/tca6507.txt b/Documentation/devicetree/bindings/leds/tca6507.txt index 2b6693b972f..80ff3dfb1f3 100644 --- a/Documentation/devicetree/bindings/leds/tca6507.txt +++ b/Documentation/devicetree/bindings/leds/tca6507.txt @@ -1,4 +1,4 @@ -LEDs conected to tca6507 +LEDs connected to tca6507 Required properties: - compatible : should be : "ti,tca6507". diff --git a/Documentation/devicetree/bindings/marvell.txt b/Documentation/devicetree/bindings/marvell.txt index f1533d91953..f7a0da6b402 100644 --- a/Documentation/devicetree/bindings/marvell.txt +++ b/Documentation/devicetree/bindings/marvell.txt @@ -115,6 +115,9 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd. - compatible : "marvell,mv64360-eth-block" - reg : Offset and length of the register set for this block + Optional properties: + - clocks : Phandle to the clock control device and gate bit + Example Discovery Ethernet block node: ethernet-block@2000 { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/media/coda.txt b/Documentation/devicetree/bindings/media/coda.txt new file mode 100644 index 00000000000..2865d04e403 --- /dev/null +++ b/Documentation/devicetree/bindings/media/coda.txt @@ -0,0 +1,30 @@ +Chips&Media Coda multi-standard codec IP +======================================== + +Coda codec IPs are present in i.MX SoCs in various versions, +called VPU (Video Processing Unit). + +Required properties: +- compatible : should be "fsl,<chip>-src" for i.MX SoCs: + (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27 + (b) "fsl,imx53-vpu" for CODA7541 present in i.MX53 + (c) "fsl,imx6q-vpu" for CODA960 present in i.MX6q +- reg: should be register base and length as documented in the + SoC reference manual +- interrupts : Should contain the VPU interrupt. For CODA960, + a second interrupt is needed for the MJPEG unit. +- clocks : Should contain the ahb and per clocks, in the order + determined by the clock-names property. +- clock-names : Should be "ahb", "per" +- iram : phandle pointing to the SRAM device node + +Example: + +vpu: vpu@63ff4000 { + compatible = "fsl,imx53-vpu"; + reg = <0x63ff4000 0x1000>; + interrupts = <9>; + clocks = <&clks 63>, <&clks 63>; + clock-names = "ahb", "per"; + iram = <&ocram>; +}; diff --git a/Documentation/devicetree/bindings/media/exynos-fimc-lite.txt b/Documentation/devicetree/bindings/media/exynos-fimc-lite.txt new file mode 100644 index 00000000000..3f62adfb3e0 --- /dev/null +++ b/Documentation/devicetree/bindings/media/exynos-fimc-lite.txt @@ -0,0 +1,14 @@ +Exynos4x12/Exynos5 SoC series camera host interface (FIMC-LITE) + +Required properties: + +- compatible : should be "samsung,exynos4212-fimc" for Exynos4212 and + Exynos4412 SoCs; +- reg : physical base address and size of the device memory mapped + registers; +- interrupts : should contain FIMC-LITE interrupt; +- clocks : FIMC LITE gate clock should be specified in this property. +- clock-names : should contain "flite" entry. + +Each FIMC device should have an alias in the aliases node, in the form of +fimc-lite<n>, where <n> is an integer specifying the IP block instance. diff --git a/Documentation/devicetree/bindings/media/exynos4-fimc-is.txt b/Documentation/devicetree/bindings/media/exynos4-fimc-is.txt new file mode 100644 index 00000000000..55c9ad6f959 --- /dev/null +++ b/Documentation/devicetree/bindings/media/exynos4-fimc-is.txt @@ -0,0 +1,49 @@ +Exynos4x12 SoC series Imaging Subsystem (FIMC-IS) + +The FIMC-IS is a subsystem for processing image signal from an image sensor. +The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5 +processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C +and SPI bus controllers, PWM and ADC. + +fimc-is node +------------ + +Required properties: +- compatible : should be "samsung,exynos4212-fimc-is" for Exynos4212 and + Exynos4412 SoCs; +- reg : physical base address and length of the registers set; +- interrupts : must contain two FIMC-IS interrupts, in order: ISP0, ISP1; +- clocks : list of clock specifiers, corresponding to entries in + clock-names property; +- clock-names : must contain "ppmuispx", "ppmuispx", "lite0", "lite1" + "mpll", "sysreg", "isp", "drc", "fd", "mcuisp", "uart", + "ispdiv0", "ispdiv1", "mcuispdiv0", "mcuispdiv1", "aclk200", + "div_aclk200", "aclk400mcuisp", "div_aclk400mcuisp" entries, + matching entries in the clocks property. +pmu subnode +----------- + +Required properties: + - reg : must contain PMU physical base address and size of the register set. + +The following are the FIMC-IS peripheral device nodes and can be specified +either standalone or as the fimc-is node child nodes. + +i2c-isp (ISP I2C bus controller) nodes +------------------------------------------ + +Required properties: + +- compatible : should be "samsung,exynos4212-i2c-isp" for Exynos4212 and + Exynos4412 SoCs; +- reg : physical base address and length of the registers set; +- clocks : must contain gate clock specifier for this controller; +- clock-names : must contain "i2c_isp" entry. + +For the above nodes it is required to specify a pinctrl state named "default", +according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt. + +Device tree nodes of the image sensors' controlled directly by the FIMC-IS +firmware must be child nodes of their corresponding ISP I2C bus controller node. +The data link of these image sensors must be specified using the common video +interfaces bindings, defined in video-interfaces.txt. diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt index 67ec3d4ccc7..bf0182d8da2 100644 --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt @@ -21,3 +21,24 @@ Required properties: - samsung,mfc-l : Base address of the second memory bank used by MFC for DMA contiguous memory allocation and its size. + +Optional properties: + - samsung,power-domain : power-domain property defined with a phandle + to respective power domain. + +Example: +SoC specific DT entry: + +mfc: codec@13400000 { + compatible = "samsung,mfc-v5"; + reg = <0x13400000 0x10000>; + interrupts = <0 94 0>; + samsung,power-domain = <&pd_mfc>; +}; + +Board specific DT entry: + +codec@13400000 { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; +}; diff --git a/Documentation/devicetree/bindings/media/samsung-fimc.txt b/Documentation/devicetree/bindings/media/samsung-fimc.txt new file mode 100644 index 00000000000..51c776b7f7a --- /dev/null +++ b/Documentation/devicetree/bindings/media/samsung-fimc.txt @@ -0,0 +1,197 @@ +Samsung S5P/EXYNOS SoC Camera Subsystem (FIMC) +---------------------------------------------- + +The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices +represented by separate device tree nodes. Currently this includes: FIMC (in +the S5P SoCs series known as CAMIF), MIPI CSIS, FIMC-LITE and FIMC-IS (ISP). + +The sub-subdevices are defined as child nodes of the common 'camera' node which +also includes common properties of the whole subsystem not really specific to +any single sub-device, like common camera port pins or the CAMCLK clock outputs +for external image sensors attached to an SoC. + +Common 'camera' node +-------------------- + +Required properties: + +- compatible : must be "samsung,fimc", "simple-bus" +- clocks : list of clock specifiers, corresponding to entries in + the clock-names property; +- clock-names : must contain "sclk_cam0", "sclk_cam1", "pxl_async0", + "pxl_async1" entries, matching entries in the clocks property. + +The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used +to define a required pinctrl state named "default" and optional pinctrl states: +"idle", "active-a", active-b". These optional states can be used to switch the +camera port pinmux at runtime. The "idle" state should configure both the camera +ports A and B into high impedance state, especially the CAMCLK clock output +should be inactive. For the "active-a" state the camera port A must be activated +and the port B deactivated and for the state "active-b" it should be the other +way around. + +The 'camera' node must include at least one 'fimc' child node. + +'fimc' device nodes +------------------- + +Required properties: + +- compatible: "samsung,s5pv210-fimc" for S5PV210, "samsung,exynos4210-fimc" + for Exynos4210 and "samsung,exynos4212-fimc" for Exynos4x12 SoCs; +- reg: physical base address and length of the registers set for the device; +- interrupts: should contain FIMC interrupt; +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names; +- clock-names: must contain "fimc", "sclk_fimc" entries. +- samsung,pix-limits: an array of maximum supported image sizes in pixels, for + details refer to Table 2-1 in the S5PV210 SoC User Manual; The meaning of + each cell is as follows: + 0 - scaler input horizontal size, + 1 - input horizontal size for the scaler bypassed, + 2 - REAL_WIDTH without input rotation, + 3 - REAL_HEIGHT with input rotation, +- samsung,sysreg: a phandle to the SYSREG node. + +Each FIMC device should have an alias in the aliases node, in the form of +fimc<n>, where <n> is an integer specifying the IP block instance. + +Optional properties: + +- clock-frequency: maximum FIMC local clock (LCLK) frequency; +- samsung,min-pix-sizes: an array specyfing minimum image size in pixels at + the FIMC input and output DMA, in the first and second cell respectively. + Default value when this property is not present is <16 16>; +- samsung,min-pix-alignment: minimum supported image height alignment (first + cell) and the horizontal image offset (second cell). The values are in pixels + and default to <2 1> when this property is not present; +- samsung,mainscaler-ext: a boolean property indicating whether the FIMC IP + supports extended image size and has CIEXTEN register; +- samsung,rotators: a bitmask specifying whether this IP has the input and + the output rotator. Bits 4 and 0 correspond to input and output rotator + respectively. If a rotator is present its corresponding bit should be set. + Default value when this property is not specified is 0x11. +- samsung,cam-if: a bolean property indicating whether the IP block includes + the camera input interface. +- samsung,isp-wb: this property must be present if the IP block has the ISP + writeback input. +- samsung,lcd-wb: this property must be present if the IP block has the LCD + writeback input. + + +'parallel-ports' node +--------------------- + +This node should contain child 'port' nodes specifying active parallel video +input ports. It includes camera A and camera B inputs. 'reg' property in the +port nodes specifies data input - 0, 1 indicates input A, B respectively. + +Optional properties + +- samsung,camclk-out : specifies clock output for remote sensor, + 0 - CAM_A_CLKOUT, 1 - CAM_B_CLKOUT; + +Image sensor nodes +------------------ + +The sensor device nodes should be added to their control bus controller (e.g. +I2C0) nodes and linked to a port node in the csis or the parallel-ports node, +using the common video interfaces bindings, defined in video-interfaces.txt. +The implementation of this bindings requires clock-frequency property to be +present in the sensor device nodes. + +Example: + + aliases { + fimc0 = &fimc_0; + }; + + /* Parallel bus IF sensor */ + i2c_0: i2c@13860000 { + s5k6aa: sensor@3c { + compatible = "samsung,s5k6aafx"; + reg = <0x3c>; + vddio-supply = <...>; + + clock-frequency = <24000000>; + clocks = <...>; + clock-names = "mclk"; + + port { + s5k6aa_ep: endpoint { + remote-endpoint = <&fimc0_ep>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; + }; + + /* MIPI CSI-2 bus IF sensor */ + s5c73m3: sensor@0x1a { + compatible = "samsung,s5c73m3"; + reg = <0x1a>; + vddio-supply = <...>; + + clock-frequency = <24000000>; + clocks = <...>; + clock-names = "mclk"; + + port { + s5c73m3_1: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&csis0_ep>; + }; + }; + }; + + camera { + compatible = "samsung,fimc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam_port_a_clk_active>; + + /* parallel camera ports */ + parallel-ports { + /* camera A input */ + port@0 { + reg = <0>; + fimc0_ep: endpoint { + remote-endpoint = <&s5k6aa_ep>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; + + fimc_0: fimc@11800000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11800000 0x1000>; + interrupts = <0 85 0>; + status = "okay"; + }; + + csis_0: csis@11880000 { + compatible = "samsung,exynos4210-csis"; + reg = <0x11880000 0x1000>; + interrupts = <0 78 0>; + /* camera C input */ + port@3 { + reg = <3>; + csis0_ep: endpoint { + remote-endpoint = <&s5c73m3_ep>; + data-lanes = <1 2 3 4>; + samsung,csis-hs-settle = <12>; + }; + }; + }; + }; + +The MIPI-CSIS device binding is defined in samsung-mipi-csis.txt. diff --git a/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt b/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt new file mode 100644 index 00000000000..5f8e28e2484 --- /dev/null +++ b/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt @@ -0,0 +1,81 @@ +Samsung S5P/EXYNOS SoC series MIPI CSI-2 receiver (MIPI CSIS) +------------------------------------------------------------- + +Required properties: + +- compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110), + "samsung,exynos4210-csis" for Exynos4210 (S5PC210), + "samsung,exynos4212-csis" for Exynos4212/Exynos4412 + SoC series; +- reg : offset and length of the register set for the device; +- interrupts : should contain MIPI CSIS interrupt; the format of the + interrupt specifier depends on the interrupt controller; +- bus-width : maximum number of data lanes supported (SoC specific); +- vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V); +- vddcore-supply : MIPI CSIS Core voltage supply (e.g. 1.1V); +- clocks : list of clock specifiers, corresponding to entries in + clock-names property; +- clock-names : must contain "csis", "sclk_csis" entries, matching entries + in the clocks property. + +Optional properties: + +- clock-frequency : The IP's main (system bus) clock frequency in Hz, default + value when this property is not specified is 166 MHz; +- samsung,csis-wclk : CSI-2 wrapper clock selection. If this property is present + external clock from CMU will be used, or the bus clock if + if it's not specified. + +The device node should contain one 'port' child node with one child 'endpoint' +node, according to the bindings defined in Documentation/devicetree/bindings/ +media/video-interfaces.txt. The following are properties specific to those nodes. + +port node +--------- + +- reg : (required) must be 3 for camera C input (CSIS0) or 4 for + camera D input (CSIS1); + +endpoint node +------------- + +- data-lanes : (required) an array specifying active physical MIPI-CSI2 + data input lanes and their mapping to logical lanes; the + array's content is unused, only its length is meaningful; + +- samsung,csis-hs-settle : (optional) differential receiver (HS-RX) settle time; + + +Example: + + reg0: regulator@0 { + }; + + reg1: regulator@1 { + }; + +/* SoC properties */ + + csis_0: csis@11880000 { + compatible = "samsung,exynos4210-csis"; + reg = <0x11880000 0x1000>; + interrupts = <0 78 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + +/* Board properties */ + + csis_0: csis@11880000 { + clock-frequency = <166000000>; + vddio-supply = <®0>; + vddcore-supply = <®1>; + port { + reg = <3>; /* 3 - CSIS0, 4 - CSIS1 */ + csis0_ep: endpoint { + remote-endpoint = <...>; + data-lanes = <1>, <2>; + samsung,csis-hs-settle = <12>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt new file mode 100644 index 00000000000..e022d2dc496 --- /dev/null +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt @@ -0,0 +1,228 @@ +Common bindings for video receiver and transmitter interfaces + +General concept +--------------- + +Video data pipelines usually consist of external devices, e.g. camera sensors, +controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including +video DMA engines and video data processors. + +SoC internal blocks are described by DT nodes, placed similarly to other SoC +blocks. External devices are represented as child nodes of their respective +bus controller nodes, e.g. I2C. + +Data interfaces on all video devices are described by their child 'port' nodes. +Configuration of a port depends on other devices participating in the data +transfer and is described by 'endpoint' subnodes. + +device { + ... + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + ... + endpoint@0 { ... }; + endpoint@1 { ... }; + }; + port@1 { ... }; + }; +}; + +If a port can be configured to work with more than one remote device on the same +bus, an 'endpoint' child node must be provided for each of them. If more than +one port is present in a device node or there is more than one endpoint at a +port, or port node needs to be associated with a selected hardware interface, +a common scheme using '#address-cells', '#size-cells' and 'reg' properties is +used. + +All 'port' nodes can be grouped under optional 'ports' node, which allows to +specify #address-cells, #size-cells properties independently for the 'port' +and 'endpoint' nodes and any child device nodes a device might have. + +Two 'endpoint' nodes are linked with each other through their 'remote-endpoint' +phandles. An endpoint subnode of a device contains all properties needed for +configuration of this device for data exchange with other device. In most +cases properties at the peer 'endpoint' nodes will be identical, however they +might need to be different when there is any signal modifications on the bus +between two devices, e.g. there are logic signal inverters on the lines. + +It is allowed for multiple endpoints at a port to be active simultaneously, +where supported by a device. For example, in case where a data interface of +a device is partitioned into multiple data busses, e.g. 16-bit input port +divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width +and data-shift properties can be used to assign physical data lines to each +endpoint node (logical bus). + + +Required properties +------------------- + +If there is more than one 'port' or more than one 'endpoint' node or 'reg' +property is present in port and/or endpoint nodes the following properties +are required in a relevant parent node: + + - #address-cells : number of cells required to define port/endpoint + identifier, should be 1. + - #size-cells : should be zero. + +Optional endpoint properties +---------------------------- + +- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node. +- slave-mode: a boolean property indicating that the link is run in slave mode. + The default when this property is not specified is master mode. In the slave + mode horizontal and vertical synchronization signals are provided to the + slave device (data source) by the master device (data sink). In the master + mode the data source device is also the source of the synchronization signals. +- bus-width: number of data lines actively used, valid for the parallel busses. +- data-shift: on the parallel data busses, if bus-width is used to specify the + number of data lines, data-shift can be used to specify which data lines are + used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used. +- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. +- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. + Note, that if HSYNC and VSYNC polarities are not specified, embedded + synchronization may be required, where supported. +- data-active: similar to HSYNC and VSYNC, specifies data line polarity. +- field-even-active: field signal level during the even field data transmission. +- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock + signal. +- data-lanes: an array of physical data lane indexes. Position of an entry + determines the logical lane number, while the value of an entry indicates + physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have + "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0. + This property is valid for serial busses only (e.g. MIPI CSI-2). +- clock-lanes: an array of physical clock lane indexes. Position of an entry + determines the logical lane number, while the value of an entry indicates + physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;", + which places the clock lane on hardware lane 0. This property is valid for + serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this + array contains only one entry. +- clock-noncontinuous: a boolean property to allow MIPI CSI-2 non-continuous + clock mode. + + +Example +------- + +The example snippet below describes two data pipelines. ov772x and imx074 are +camera sensors with a parallel and serial (MIPI CSI-2) video bus respectively. +Both sensors are on the I2C control bus corresponding to the i2c0 controller +node. ov772x sensor is linked directly to the ceu0 video host interface. +imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a +(single) DMA engine writing captured data to memory. ceu0 node has a single +'port' node which may indicate that at any time only one of the following data +pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0. + + ceu0: ceu@0xfe910000 { + compatible = "renesas,sh-mobile-ceu"; + reg = <0xfe910000 0xa0>; + interrupts = <0x880>; + + mclk: master_clock { + compatible = "renesas,ceu-clock"; + #clock-cells = <1>; + clock-frequency = <50000000>; /* Max clock frequency */ + clock-output-names = "mclk"; + }; + + port { + #address-cells = <1>; + #size-cells = <0>; + + /* Parallel bus endpoint */ + ceu0_1: endpoint@1 { + reg = <1>; /* Local endpoint # */ + remote = <&ov772x_1_1>; /* Remote phandle */ + bus-width = <8>; /* Used data lines */ + data-shift = <2>; /* Lines 9:2 are used */ + + /* If hsync-active/vsync-active are missing, + embedded BT.656 sync is used */ + hsync-active = <0>; /* Active low */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + + /* MIPI CSI-2 bus endpoint */ + ceu0_0: endpoint@0 { + reg = <0>; + remote = <&csi2_2>; + }; + }; + }; + + i2c0: i2c@0xfff20000 { + ... + ov772x_1: camera@0x21 { + compatible = "omnivision,ov772x"; + reg = <0x21>; + vddio-supply = <®ulator1>; + vddcore-supply = <®ulator2>; + + clock-frequency = <20000000>; + clocks = <&mclk 0>; + clock-names = "xclk"; + + port { + /* With 1 endpoint per port no need for addresses. */ + ov772x_1_1: endpoint { + bus-width = <8>; + remote-endpoint = <&ceu0_1>; + hsync-active = <1>; + vsync-active = <0>; /* Who came up with an + inverter here ?... */ + data-active = <1>; + pclk-sample = <1>; + }; + }; + }; + + imx074: camera@0x1a { + compatible = "sony,imx074"; + reg = <0x1a>; + vddio-supply = <®ulator1>; + vddcore-supply = <®ulator2>; + + clock-frequency = <30000000>; /* Shared clock with ov772x_1 */ + clocks = <&mclk 0>; + clock-names = "sysclk"; /* Assuming this is the + name in the datasheet */ + port { + imx074_1: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi2_1>; + }; + }; + }; + }; + + csi2: csi2@0xffc90000 { + compatible = "renesas,sh-mobile-csi2"; + reg = <0xffc90000 0x1000>; + interrupts = <0x17a0>; + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + compatible = "renesas,csi2c"; /* One of CSI2I and CSI2C. */ + reg = <1>; /* CSI-2 PHY #1 of 2: PHY_S, + PHY_M has port address 0, + is unused. */ + csi2_1: endpoint { + clock-lanes = <0>; + data-lanes = <2 1>; + remote-endpoint = <&imx074_1>; + }; + }; + port@2 { + reg = <2>; /* port 2: link to the CEU */ + + csi2_2: endpoint { + remote-endpoint = <&ceu0_0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/metag/meta-intc.txt b/Documentation/devicetree/bindings/metag/meta-intc.txt index 8c47dcbfabc..80994adab39 100644 --- a/Documentation/devicetree/bindings/metag/meta-intc.txt +++ b/Documentation/devicetree/bindings/metag/meta-intc.txt @@ -12,7 +12,7 @@ Required properties: handle 32 interrupt sources). - interrupt-controller: The presence of this property identifies the node - as an interupt controller. No property value shall be defined. + as an interrupt controller. No property value shall be defined. - #interrupt-cells: Specifies the number of cells needed to encode an interrupt source. The type shall be a <u32> and the value shall be 2. diff --git a/Documentation/devicetree/bindings/mfd/as3711.txt b/Documentation/devicetree/bindings/mfd/as3711.txt new file mode 100644 index 00000000000..d98cf18c721 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/as3711.txt @@ -0,0 +1,73 @@ +AS3711 is an I2C PMIC from Austria MicroSystems with multiple DCDC and LDO power +supplies, a battery charger and an RTC. So far only bindings for the two stepup +DCDC converters are defined. Other DCDC and LDO supplies are configured, using +standard regulator properties, they must belong to a sub-node, called +"regulators" and be called "sd1" to "sd4" and "ldo1" to "ldo8." Stepup converter +configuration should be placed in a subnode, called "backlight." + +Compulsory properties: +- compatible : must be "ams,as3711" +- reg : specifies the I2C address + +To use the SU1 converter as a backlight source the following two properties must +be provided: +- su1-dev : framebuffer phandle +- su1-max-uA : maximum current + +To use the SU2 converter as a backlight source the following two properties must +be provided: +- su2-dev : framebuffer phandle +- su1-max-uA : maximum current + +Additionally one of these properties must be provided to select the type of +feedback used: +- su2-feedback-voltage : voltage feedback is used +- su2-feedback-curr1 : CURR1 input used for current feedback +- su2-feedback-curr2 : CURR2 input used for current feedback +- su2-feedback-curr3 : CURR3 input used for current feedback +- su2-feedback-curr-auto: automatic current feedback selection + +and one of these to select the over-voltage protection pin +- su2-fbprot-lx-sd4 : LX_SD4 is used for over-voltage protection +- su2-fbprot-gpio2 : GPIO2 is used for over-voltage protection +- su2-fbprot-gpio3 : GPIO3 is used for over-voltage protection +- su2-fbprot-gpio4 : GPIO4 is used for over-voltage protection + +If "su2-feedback-curr-auto" is selected, one or more of the following properties +have to be specified: +- su2-auto-curr1 : use CURR1 input for current feedback +- su2-auto-curr2 : use CURR2 input for current feedback +- su2-auto-curr3 : use CURR3 input for current feedback + +Example: + +as3711@40 { + compatible = "ams,as3711"; + reg = <0x40>; + + regulators { + sd4 { + regulator-name = "1.215V"; + regulator-min-microvolt = <1215000>; + regulator-max-microvolt = <1235000>; + }; + ldo2 { + regulator-name = "2.8V CPU"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + + backlight { + compatible = "ams,as3711-bl"; + su2-dev = <&lcdc>; + su2-max-uA = <36000>; + su2-feedback-curr-auto; + su2-fbprot-gpio4; + su2-auto-curr1; + su2-auto-curr2; + su2-auto-curr3; + }; +}; diff --git a/Documentation/devicetree/bindings/mfd/cros-ec.txt b/Documentation/devicetree/bindings/mfd/cros-ec.txt new file mode 100644 index 00000000000..e0e59c58a1f --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/cros-ec.txt @@ -0,0 +1,56 @@ +ChromeOS Embedded Controller + +Google's ChromeOS EC is a Cortex-M device which talks to the AP and +implements various function such as keyboard and battery charging. + +The EC can be connect through various means (I2C, SPI, LPC) and the +compatible string used depends on the inteface. Each connection method has +its own driver which connects to the top level interface-agnostic EC driver. +Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to +the top-level driver. + +Required properties (I2C): +- compatible: "google,cros-ec-i2c" +- reg: I2C slave address + +Required properties (SPI): +- compatible: "google,cros-ec-spi" +- reg: SPI chip select + +Required properties (LPC): +- compatible: "google,cros-ec-lpc" +- reg: List of (IO address, size) pairs defining the interface uses + + +Example for I2C: + +i2c@12CA0000 { + cros-ec@1e { + reg = <0x1e>; + compatible = "google,cros-ec-i2c"; + interrupts = <14 0>; + interrupt-parent = <&wakeup_eint>; + wakeup-source; + }; + + +Example for SPI: + +spi@131b0000 { + ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0x0>; + interrupts = <14 0>; + interrupt-parent = <&wakeup_eint>; + wakeup-source; + spi-max-frequency = <5000000>; + controller-data { + cs-gpio = <&gpf0 3 4 3 0>; + samsung,spi-cs; + samsung,spi-feedback-delay = <2>; + }; + }; +}; + + +Example for LPC is not supplied as it is not yet implemented. diff --git a/Documentation/devicetree/bindings/mfd/mc13xxx.txt b/Documentation/devicetree/bindings/mfd/mc13xxx.txt index baf07987ae6..abd9e3cb2db 100644 --- a/Documentation/devicetree/bindings/mfd/mc13xxx.txt +++ b/Documentation/devicetree/bindings/mfd/mc13xxx.txt @@ -10,10 +10,40 @@ Optional properties: - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used Sub-nodes: -- regulators : Contain the regulator nodes. The MC13892 regulators are - bound using their names as listed below with their registers and bits - for enabling. +- regulators : Contain the regulator nodes. The regulators are bound using + their names as listed below with their registers and bits for enabling. +MC13783 regulators: + sw1a : regulator SW1A (register 24, bit 0) + sw1b : regulator SW1B (register 25, bit 0) + sw2a : regulator SW2A (register 26, bit 0) + sw2b : regulator SW2B (register 27, bit 0) + sw3 : regulator SW3 (register 29, bit 20) + vaudio : regulator VAUDIO (register 32, bit 0) + viohi : regulator VIOHI (register 32, bit 3) + violo : regulator VIOLO (register 32, bit 6) + vdig : regulator VDIG (register 32, bit 9) + vgen : regulator VGEN (register 32, bit 12) + vrfdig : regulator VRFDIG (register 32, bit 15) + vrfref : regulator VRFREF (register 32, bit 18) + vrfcp : regulator VRFCP (register 32, bit 21) + vsim : regulator VSIM (register 33, bit 0) + vesim : regulator VESIM (register 33, bit 3) + vcam : regulator VCAM (register 33, bit 6) + vrfbg : regulator VRFBG (register 33, bit 9) + vvib : regulator VVIB (register 33, bit 11) + vrf1 : regulator VRF1 (register 33, bit 12) + vrf2 : regulator VRF2 (register 33, bit 15) + vmmc1 : regulator VMMC1 (register 33, bit 18) + vmmc2 : regulator VMMC2 (register 33, bit 21) + gpo1 : regulator GPO1 (register 34, bit 6) + gpo2 : regulator GPO2 (register 34, bit 8) + gpo3 : regulator GPO3 (register 34, bit 10) + gpo4 : regulator GPO4 (register 34, bit 12) + pwgt1spi : regulator PWGT1SPI (register 34, bit 15) + pwgt2spi : regulator PWGT2SPI (register 34, bit 16) + +MC13892 regulators: vcoincell : regulator VCOINCELL (register 13, bit 23) sw1 : regulator SW1 (register 24, bit 0) sw2 : regulator SW2 (register 25, bit 0) diff --git a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt new file mode 100644 index 00000000000..b381fa696bf --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt @@ -0,0 +1,80 @@ +OMAP HS USB Host + +Required properties: + +- compatible: should be "ti,usbhs-host" +- reg: should contain one register range i.e. start and length +- ti,hwmods: must contain "usb_host_hs" + +Optional properties: + +- num-ports: number of USB ports. Usually this is automatically detected + from the IP's revision register but can be overridden by specifying + this property. A maximum of 3 ports are supported at the moment. + +- portN-mode: String specifying the port mode for port N, where N can be + from 1 to 3. If the port mode is not specified, that port is treated + as unused. When specified, it must be one of the following. + "ehci-phy", + "ehci-tll", + "ehci-hsic", + "ohci-phy-6pin-datse0", + "ohci-phy-6pin-dpdm", + "ohci-phy-3pin-datse0", + "ohci-phy-4pin-dpdm", + "ohci-tll-6pin-datse0", + "ohci-tll-6pin-dpdm", + "ohci-tll-3pin-datse0", + "ohci-tll-4pin-dpdm", + "ohci-tll-2pin-datse0", + "ohci-tll-2pin-dpdm", + +- single-ulpi-bypass: Must be present if the controller contains a single + ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1 + +Required properties if child node exists: + +- #address-cells: Must be 1 +- #size-cells: Must be 1 +- ranges: must be present + +Properties for children: + +The OMAP HS USB Host subsystem contains EHCI and OHCI controllers. +See Documentation/devicetree/bindings/usb/omap-ehci.txt and +omap3-ohci.txt + +Example for OMAP4: + +usbhshost: usbhshost@4a064000 { + compatible = "ti,usbhs-host"; + reg = <0x4a064000 0x800>; + ti,hwmods = "usb_host_hs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbhsohci: ohci@4a064800 { + compatible = "ti,ohci-omap3", "usb-ohci"; + reg = <0x4a064800 0x400>; + interrupt-parent = <&gic>; + interrupts = <0 76 0x4>; + }; + + usbhsehci: ehci@4a064c00 { + compatible = "ti,ehci-omap", "usb-ehci"; + reg = <0x4a064c00 0x400>; + interrupt-parent = <&gic>; + interrupts = <0 77 0x4>; + }; +}; + +&usbhshost { + port1-mode = "ehci-phy"; + port2-mode = "ehci-tll"; + port3-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy 0 &hsusb3_phy>; +}; diff --git a/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt b/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt new file mode 100644 index 00000000000..62fe69724e3 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt @@ -0,0 +1,17 @@ +OMAP HS USB Host TLL (Transceiver-Less Interface) + +Required properties: + +- compatible : should be "ti,usbhs-tll" +- reg : should contain one register range i.e. start and length +- interrupts : should contain the TLL module's interrupt +- ti,hwmod : must contain "usb_tll_hs" + +Example: + + usbhstll: usbhstll@4a062000 { + compatible = "ti,usbhs-tll"; + reg = <0x4a062000 0x1000>; + interrupts = <78>; + ti,hwmods = "usb_tll_hs"; + }; diff --git a/Documentation/devicetree/bindings/misc/smc.txt b/Documentation/devicetree/bindings/misc/smc.txt new file mode 100644 index 00000000000..02b42813617 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/smc.txt @@ -0,0 +1,14 @@ +Broadcom Secure Monitor Bounce buffer +----------------------------------------------------- +This binding defines the location of the bounce buffer +used for non-secure to secure communications. + +Required properties: +- compatible : "bcm,kona-smc" +- reg : Location and size of bounce buffer + +Example: + smc@0x3404c000 { + compatible = "bcm,bcm11351-smc", "bcm,kona-smc"; + reg = <0x3404c000 0x400>; //1 KiB in SRAM + }; diff --git a/Documentation/devicetree/bindings/misc/sram.txt b/Documentation/devicetree/bindings/misc/sram.txt new file mode 100644 index 00000000000..4d0a00e453a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/sram.txt @@ -0,0 +1,16 @@ +Generic on-chip SRAM + +Simple IO memory regions to be managed by the genalloc API. + +Required properties: + +- compatible : mmio-sram + +- reg : SRAM iomem address range + +Example: + +sram: sram@5c000000 { + compatible = "mmio-sram"; + reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ +}; diff --git a/Documentation/devicetree/bindings/mmc/davinci_mmc.txt b/Documentation/devicetree/bindings/mmc/davinci_mmc.txt new file mode 100644 index 00000000000..e5a0140b238 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/davinci_mmc.txt @@ -0,0 +1,33 @@ +* TI Highspeed MMC host controller for DaVinci + +The Highspeed MMC Host Controller on TI DaVinci family +provides an interface for MMC, SD and SDIO types of memory cards. + +This file documents the properties used by the davinci_mmc driver. + +Required properties: +- compatible: + Should be "ti,da830-mmc": for da830, da850, dm365 + Should be "ti,dm355-mmc": for dm355, dm644x + +Optional properties: +- bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1> +- max-frequency: Maximum operating clock frequency, default 25MHz. +- dmas: List of DMA specifiers with the controller specific format + as described in the generic DMA client binding. A tx and rx + specifier is required. +- dma-names: RX and TX DMA request names. These strings correspond + 1:1 with the DMA specifiers listed in dmas. + +Example: +mmc0: mmc@1c40000 { + compatible = "ti,da830-mmc", + reg = <0x40000 0x1000>; + interrupts = <16>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + dmas = <&edma 16 + &edma 17>; + dma-names = "rx", "tx"; +}; diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt new file mode 100644 index 00000000000..db442355cd2 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt @@ -0,0 +1,24 @@ +* Freescale Secure Digital Host Controller for i.MX2/3 series + +This file documents differences to the properties defined in mmc.txt. + +Required properties: +- compatible : Should be "fsl,<chip>-mmc", chip can be imx21 or imx31 + +Optional properties: +- dmas: One DMA phandle with arguments as defined by the devicetree bindings + of the used DMA controller. +- dma-names: Has to be "rx-tx". + +Example: + +sdhci1: sdhci@10014000 { + compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; + reg = <0x10014000 0x1000>; + interrupts = <11>; + dmas = <&dma 7>; + dma-names = "rx-tx"; + bus-width = <4>; + cd-gpios = <&gpio3 29>; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/mmc/mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/mxs-mmc.txt index 54949f6faed..515addc2007 100644 --- a/Documentation/devicetree/bindings/mmc/mxs-mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mxs-mmc.txt @@ -9,15 +9,19 @@ and the properties used by the mxsmmc driver. Required properties: - compatible: Should be "fsl,<chip>-mmc". The supported chips include imx23 and imx28. -- interrupts: Should contain ERROR and DMA interrupts -- fsl,ssp-dma-channel: APBH DMA channel for the SSP +- interrupts: Should contain ERROR interrupt number +- dmas: DMA specifier, consisting of a phandle to DMA controller node + and SSP DMA channel ID. + Refer to dma.txt and fsl-mxs-dma.txt for details. +- dma-names: Must be "rx-tx". Examples: ssp0: ssp@80010000 { compatible = "fsl,imx28-mmc"; reg = <0x80010000 2000>; - interrupts = <96 82>; - fsl,ssp-dma-channel = <0>; + interrupts = <96>; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; bus-width = <8>; }; diff --git a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt b/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt index 3b3a1ee055f..328e990d254 100644 --- a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt @@ -5,13 +5,6 @@ MMC, SD and eMMC storage mediums. This file documents differences between the core mmc properties described by mmc.txt and the properties used by the Samsung implmentation of the SDHCI controller. -Note: The mmc core bindings documentation states that if none of the core -card-detect bindings are used, then the standard sdhci card detect mechanism -is used. The Samsung's SDHCI controller bindings extends this as listed below. - -[A] The property "samsung,cd-pinmux-gpio" can be used as stated in the - "Optional Board Specific Properties" section below. - Required SoC Specific Properties: - compatible: should be one of the following - "samsung,s3c6410-sdhci": For controllers compatible with s3c6410 sdhci @@ -20,18 +13,8 @@ Required SoC Specific Properties: controller. Required Board Specific Properties: -- Samsung GPIO variant (will be completely replaced by pinctrl): - - gpios: Should specify the gpios used for clock, command and data lines. The - gpio specifier format depends on the gpio controller. -- Pinctrl variant (preferred if available): - - pinctrl-0: Should specify pin control groups used for this controller. - - pinctrl-names: Should contain only one value - "default". - -Optional Board Specific Properties: -- samsung,cd-pinmux-gpio: Specifies the card detect line that is routed - through a pinmux to the card-detect pin of the card slot. This property - should be used only if none of the mmc core card-detect properties are - used. Only for Samsung GPIO variant. +- pinctrl-0: Should specify pin control groups used for this controller. +- pinctrl-names: Should contain only one value - "default". Example: sdhci@12530000 { @@ -39,19 +22,9 @@ Example: reg = <0x12530000 0x100>; interrupts = <0 75 0>; bus-width = <4>; - cd-gpios = <&gpk2 2 2 3 3>; - - /* Samsung GPIO variant */ - gpios = <&gpk2 0 2 0 3>, /* clock line */ - <&gpk2 1 2 0 3>, /* command line */ - <&gpk2 3 2 3 3>, /* data line 0 */ - <&gpk2 4 2 3 3>, /* data line 1 */ - <&gpk2 5 2 3 3>, /* data line 2 */ - <&gpk2 6 2 3 3>; /* data line 3 */ - - /* Pinctrl variant */ - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; + cd-gpios = <&gpk2 2 0>; pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; }; Note: This example shows both SoC specific and board specific properties diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt b/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt new file mode 100644 index 00000000000..dd6ed464bcb --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt @@ -0,0 +1,18 @@ +* SiRFprimII/marco/atlas6 SDHCI Controller + +This file documents differences between the core properties in mmc.txt +and the properties used by the sdhci-sirf driver. + +Required properties: +- compatible: sirf,prima2-sdhc + +Optional properties: +- cd-gpios: card detect gpio, with zero flags. + +Example: + + sd0: sdhci@56000000 { + compatible = "sirf,prima2-sdhc"; + reg = <0xcd000000 0x100000>; + cd-gpios = <&gpio 6 0>; + }; diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nor.txt b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt new file mode 100644 index 00000000000..420b3ab1889 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt @@ -0,0 +1,98 @@ +Device tree bindings for NOR flash connect to TI GPMC + +NOR flash connected to the TI GPMC (found on OMAP boards) are represented as +child nodes of the GPMC controller with a name of "nor". + +All timing relevant properties as well as generic GPMC child properties are +explained in a separate documents. Please refer to +Documentation/devicetree/bindings/bus/ti-gpmc.txt + +Required properties: +- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and + 16-bit devices and so must be either 1 or 2 bytes. +- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt +- gpmc,cs-on-ns: Chip-select assertion time +- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads +- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes +- gpmc,oe-on-ns: Output-enable assertion time +- gpmc,oe-off-ns: Output-enable de-assertion time +- gpmc,we-on-ns Write-enable assertion time +- gpmc,we-off-ns: Write-enable de-assertion time +- gpmc,access-ns: Start cycle to first data capture (read access) +- gpmc,rd-cycle-ns: Total read cycle time +- gpmc,wr-cycle-ns: Total write cycle time +- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt +- reg: Chip-select, base address (relative to chip-select) + and size of NOR flash. Note that base address will be + typically 0 as this is the start of the chip-select. + +Optional properties: +- gpmc,XXX Additional GPMC timings and settings parameters. See + Documentation/devicetree/bindings/bus/ti-gpmc.txt + +Optional properties for partiton table parsing: +- #address-cells: should be set to 1 +- #size-cells: should be set to 1 + +Example: + +gpmc: gpmc@6e000000 { + compatible = "ti,omap3430-gpmc", "simple-bus"; + ti,hwmods = "gpmc"; + reg = <0x6e000000 0x1000>; + interrupts = <20>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0 0 0x10000000 0x08000000>; + + nor@0,0 { + compatible = "cfi-flash"; + linux,mtd-name= "intel,pf48f6000m0y1be"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x08000000>; + bank-width = <2>; + + gpmc,mux-add-data; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <186>; + gpmc,cs-wr-off-ns = <186>; + gpmc,adv-on-ns = <12>; + gpmc,adv-rd-off-ns = <48>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <114>; + gpmc,page-burst-access-ns = <6>; + gpmc,bus-turnaround-ns = <12>; + gpmc,cycle2cycle-delay-ns = <18>; + gpmc,wr-data-mux-bus-ns = <90>; + gpmc,wr-access-ns = <186>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + + partition@0 { + label = "bootloader-nor"; + reg = <0 0x40000>; + }; + partition@0x40000 { + label = "params-nor"; + reg = <0x40000 0x40000>; + }; + partition@0x80000 { + label = "kernel-nor"; + reg = <0x80000 0x200000>; + }; + partition@0x280000 { + label = "filesystem-nor"; + reg = <0x240000 0x7d80000>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt index deec9da224a..b7529424ac8 100644 --- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt @@ -10,6 +10,8 @@ Documentation/devicetree/bindings/bus/ti-gpmc.txt Required properties: - reg: The CS line the peripheral is connected to + - gpmc,device-width Width of the ONENAND device connected to the GPMC + in bytes. Must be 1 or 2. Optional properties: @@ -34,6 +36,7 @@ Example for an OMAP3430 board: onenand@0 { reg = <0 0 0>; /* CS0, offset 0 */ + gpmc,device-width = <2>; #address-cells = <1>; #size-cells = <1>; diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt index 3fb3f901536..551b2a179d0 100644 --- a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt @@ -7,10 +7,12 @@ Required properties: - compatible : should be "fsl,<chip>-gpmi-nand" - reg : should contain registers location and length for gpmi and bch. - reg-names: Should contain the reg names "gpmi-nand" and "bch" - - interrupts : The first is the DMA interrupt number for GPMI. - The second is the BCH interrupt number. - - interrupt-names : The interrupt names "gpmi-dma", "bch"; - - fsl,gpmi-dma-channel : Should contain the dma channel it uses. + - interrupts : BCH interrupt number. + - interrupt-names : Should be "bch". + - dmas: DMA specifier, consisting of a phandle to DMA controller node + and GPMI DMA channel ID. + Refer to dma.txt and fsl-mxs-dma.txt for details. + - dma-names: Must be "rx-tx". Optional properties: - nand-on-flash-bbt: boolean to enable on flash bbt option if not @@ -27,9 +29,10 @@ gpmi-nand@8000c000 { #size-cells = <1>; reg = <0x8000c000 2000>, <0x8000a000 2000>; reg-names = "gpmi-nand", "bch"; - interrupts = <88>, <41>; - interrupt-names = "gpmi-dma", "bch"; - fsl,gpmi-dma-channel = <4>; + interrupts = <41>; + interrupt-names = "bch"; + dmas = <&dma_apbh 4>; + dma-names = "rx-tx"; partition@0 { ... diff --git a/Documentation/devicetree/bindings/mtd/partition.txt b/Documentation/devicetree/bindings/mtd/partition.txt index 6e1f61f1e78..9315ac96b49 100644 --- a/Documentation/devicetree/bindings/mtd/partition.txt +++ b/Documentation/devicetree/bindings/mtd/partition.txt @@ -5,8 +5,12 @@ on platforms which have strong conventions about which portions of a flash are used for what purposes, but which don't use an on-flash partition table such as RedBoot. -#address-cells & #size-cells must both be present in the mtd device and be -equal to 1. +#address-cells & #size-cells must both be present in the mtd device. There are +two valid values for both: +<1>: for partitions that require a single 32-bit cell to represent their + size/address (aka the value is below 4 GiB) +<2>: for partitions that require two 32-bit cells to represent their + size/address (aka the value is 4 GiB or greater). Required properties: - reg : The partition's offset and size within the mtd bank. @@ -36,3 +40,31 @@ flash@0 { reg = <0x0100000 0x200000>; }; }; + +flash@1 { + #address-cells = <1>; + #size-cells = <2>; + + /* a 4 GiB partition */ + partition@0 { + label = "filesystem"; + reg = <0x00000000 0x1 0x00000000>; + }; +}; + +flash@2 { + #address-cells = <2>; + #size-cells = <2>; + + /* an 8 GiB partition */ + partition@0 { + label = "filesystem #1"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; + + /* a 4 GiB partition */ + partition@200000000 { + label = "filesystem #2"; + reg = <0x2 0x00000000 0x1 0x00000000>; + }; +}; diff --git a/Documentation/devicetree/bindings/net/can/atmel-can.txt b/Documentation/devicetree/bindings/net/can/atmel-can.txt new file mode 100644 index 00000000000..72cf0c5daff --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/atmel-can.txt @@ -0,0 +1,14 @@ +* AT91 CAN * + +Required properties: + - compatible: Should be "atmel,at91sam9263-can" or "atmel,at91sam9x5-can" + - reg: Should contain CAN controller registers location and length + - interrupts: Should contain IRQ line for the CAN controller + +Example: + + can0: can@f000c000 { + compatbile = "atmel,at91sam9x5-can"; + reg = <0xf000c000 0x300>; + interrupts = <40 4 5> + }; diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt index ecfdf756d10..4f2ca6b4a18 100644 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ b/Documentation/devicetree/bindings/net/cpsw.txt @@ -15,16 +15,22 @@ Required properties: - mac_control : Specifies Default MAC control register content for the specific platform - slaves : Specifies number for slaves -- cpts_active_slave : Specifies the slave to use for time stamping +- active_slave : Specifies the slave to use for time stamping, + ethtool and SIOCGMIIPHY - cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds - cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds -- phy_id : Specifies slave phy id -- mac-address : Specifies slave MAC address Optional properties: - ti,hwmods : Must be "cpgmac0" - no_bd_ram : Must be 0 or 1 - dual_emac : Specifies Switch to act as Dual EMAC + +Slave Properties: +Required properties: +- phy_id : Specifies slave phy id +- mac-address : Specifies slave MAC address + +Optional properties: - dual_emac_res_vlan : Specifies VID to be used to segregate the ports Note: "ti,hwmods" field is used to fetch the base address and irq @@ -47,7 +53,7 @@ Examples: rx_descs = <64>; mac_control = <0x20>; slaves = <2>; - cpts_active_slave = <0>; + active_slave = <0>; cpts_clock_mult = <0x80000000>; cpts_clock_shift = <29>; cpsw_emac0: slave@0 { @@ -73,7 +79,7 @@ Examples: rx_descs = <64>; mac_control = <0x20>; slaves = <2>; - cpts_active_slave = <0>; + active_slave = <0>; cpts_clock_mult = <0x80000000>; cpts_clock_shift = <29>; cpsw_emac0: slave@0 { diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt new file mode 100644 index 00000000000..49f4f7ae3f5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/dsa.txt @@ -0,0 +1,91 @@ +Marvell Distributed Switch Architecture Device Tree Bindings +------------------------------------------------------------ + +Required properties: +- compatible : Should be "marvell,dsa" +- #address-cells : Must be 2, first cell is the address on the MDIO bus + and second cell is the address in the switch tree. + Second cell is used only when cascading/chaining. +- #size-cells : Must be 0 +- dsa,ethernet : Should be a phandle to a valid Ethernet device node +- dsa,mii-bus : Should be a phandle to a valid MDIO bus device node + +Optionnal properties: +- interrupts : property with a value describing the switch + interrupt number (not supported by the driver) + +A DSA node can contain multiple switch chips which are therefore child nodes of +the parent DSA node. The maximum number of allowed child nodes is 4 +(DSA_MAX_SWITCHES). +Each of these switch child nodes should have the following required properties: + +- reg : Describes the switch address on the MII bus +- #address-cells : Must be 1 +- #size-cells : Must be 0 + +A switch may have multiple "port" children nodes + +Each port children node must have the following mandatory properties: +- reg : Describes the port address in the switch +- label : Describes the label associated with this port, special + labels are "cpu" to indicate a CPU port and "dsa" to + indicate an uplink/downlink port. + +Note that a port labelled "dsa" will imply checking for the uplink phandle +described below. + +Optionnal property: +- link : Should be a phandle to another switch's DSA port. + This property is only used when switches are being + chained/cascaded together. + +Example: + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + interrupts = <10>; + dsa,ethernet = <ðernet0>; + dsa,mii-bus = <&mii_bus0>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <16 0>; /* MDIO address 16, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + + switch0uplink: port@6 { + reg = <6>; + label = "dsa"; + link = <&switch1uplink>; + }; + }; + + switch@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <17 1>; /* MDIO address 17, switch 1 in tree */ + + switch1uplink: port@0 { + reg = <0>; + label = "dsa"; + link = <&switch0uplink>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/gpmc-eth.txt b/Documentation/devicetree/bindings/net/gpmc-eth.txt new file mode 100644 index 00000000000..24cb4e46f67 --- /dev/null +++ b/Documentation/devicetree/bindings/net/gpmc-eth.txt @@ -0,0 +1,97 @@ +Device tree bindings for Ethernet chip connected to TI GPMC + +Besides being used to interface with external memory devices, the +General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices +such as ethernet controllers to processors using the TI GPMC as a data bus. + +Ethernet controllers connected to TI GPMC are represented as child nodes of +the GPMC controller with an "ethernet" name. + +All timing relevant properties as well as generic GPMC child properties are +explained in a separate documents. Please refer to +Documentation/devicetree/bindings/bus/ti-gpmc.txt + +For the properties relevant to the ethernet controller connected to the GPMC +refer to the binding documentation of the device. For example, the documentation +for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt + +Child nodes need to specify the GPMC bus address width using the "bank-width" +property but is possible that an ethernet controller also has a property to +specify the I/O registers address width. Even when the GPMC has a maximum 16-bit +address width, it supports devices with 32-bit word registers. +For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an +OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;". + +Required properties: +- bank-width: Address width of the device in bytes. GPMC supports 8-bit + and 16-bit devices and so must be either 1 or 2 bytes. +- compatible: Compatible string property for the ethernet child device. +- gpmc,cs-on: Chip-select assertion time +- gpmc,cs-rd-off: Chip-select de-assertion time for reads +- gpmc,cs-wr-off: Chip-select de-assertion time for writes +- gpmc,oe-on: Output-enable assertion time +- gpmc,oe-off Output-enable de-assertion time +- gpmc,we-on: Write-enable assertion time +- gpmc,we-off: Write-enable de-assertion time +- gpmc,access: Start cycle to first data capture (read access) +- gpmc,rd-cycle: Total read cycle time +- gpmc,wr-cycle: Total write cycle time +- reg: Chip-select, base address (relative to chip-select) + and size of the memory mapped for the device. + Note that base address will be typically 0 as this + is the start of the chip-select. + +Optional properties: +- gpmc,XXX Additional GPMC timings and settings parameters. See + Documentation/devicetree/bindings/bus/ti-gpmc.txt + +Example: + +gpmc: gpmc@6e000000 { + compatible = "ti,omap3430-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x6e000000 0x1000>; + interrupts = <20>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <5 0 0x2c000000 0x1000000>; + + ethernet@5,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <5 0 0xff>; + bank-width = <2>; + + gpmc,mux-add-data; + gpmc,cs-on = <0>; + gpmc,cs-rd-off = <186>; + gpmc,cs-wr-off = <186>; + gpmc,adv-on = <12>; + gpmc,adv-rd-off = <48>; + gpmc,adv-wr-off = <48>; + gpmc,oe-on = <54>; + gpmc,oe-off = <168>; + gpmc,we-on = <54>; + gpmc,we-off = <168>; + gpmc,rd-cycle = <186>; + gpmc,wr-cycle = <186>; + gpmc,access = <114>; + gpmc,page-burst-access = <6>; + gpmc,bus-turnaround = <12>; + gpmc,cycle2cycle-delay = <18>; + gpmc,wr-data-mux-bus = <90>; + gpmc,wr-access = <186>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + + interrupt-parent = <&gpio6>; + interrupts = <16>; + vmmc-supply = <&vddvario>; + vmmc_aux-supply = <&vdd33a>; + reg-io-width = <4>; + + smsc,save-mac-address; + }; +}; diff --git a/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt b/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt index 34e7aafa321..9417e54c26c 100644 --- a/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt +++ b/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt @@ -9,6 +9,10 @@ Required properties: - compatible: "marvell,orion-mdio" - reg: address and length of the SMI register +Optional properties: +- interrupts: interrupt line number for the SMI error/done interrupt +- clocks: Phandle to the clock control device and gate bit + The child nodes of the MDIO driver are the individual PHY devices connected to this MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus. diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index bc50899e0c8..648d60eb9fd 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -1,6 +1,6 @@ * Atmel AT91 Pinmux Controller -The AT91 Pinmux Controler, enables the IC +The AT91 Pinmux Controller, enables the IC to share one PAD to several functional blocks. The sharing is done by multiplexing the PAD input/output signals. For each PAD there are up to 8 muxing options (called periph modes). Since different modules require diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt index 8edc20e1b09..2569866c692 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt @@ -5,7 +5,7 @@ controller, and pinmux/control device. Required properties: - compatible: "brcm,bcm2835-gpio" -- reg: Should contain the physical address of the GPIO module's registes. +- reg: Should contain the physical address of the GPIO module's registers. - gpio-controller: Marks the device node as a GPIO controller. - #gpio-cells : Should be two. The first cell is the pin number and the second cell is used to specify optional parameters: diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt index ab19e6bc7d3..bcfdab5d442 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt @@ -24,9 +24,9 @@ Required properties for iomux controller: Required properties for pin configuration node: - fsl,pins: two integers array, represents a group of pins mux and config setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid - pins and functions of each SoC. + pin working on a specific function, which consists of a tuple of + <mux_reg conf_reg input_reg mux_val input_val>. CONFIG is the pad setting + value like pull-up on this pin. Bits used for CONFIG: NO_PAD_CTL(1 << 31): indicate this pin does not need config. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt index 1183f1a3be3..c083dfd25db 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt @@ -29,956 +29,5 @@ PAD_CTL_DSE_MAX (2 << 1) PAD_CTL_SRE_FAST (1 << 0) PAD_CTL_SRE_SLOW (0 << 0) -See below for available PIN_FUNC_ID for imx35: -0 MX35_PAD_CAPTURE__GPT_CAPIN1 -1 MX35_PAD_CAPTURE__GPT_CMPOUT2 -2 MX35_PAD_CAPTURE__CSPI2_SS1 -3 MX35_PAD_CAPTURE__EPIT1_EPITO -4 MX35_PAD_CAPTURE__CCM_CLK32K -5 MX35_PAD_CAPTURE__GPIO1_4 -6 MX35_PAD_COMPARE__GPT_CMPOUT1 -7 MX35_PAD_COMPARE__GPT_CAPIN2 -8 MX35_PAD_COMPARE__GPT_CMPOUT3 -9 MX35_PAD_COMPARE__EPIT2_EPITO -10 MX35_PAD_COMPARE__GPIO1_5 -11 MX35_PAD_COMPARE__SDMA_EXTDMA_2 -12 MX35_PAD_WDOG_RST__WDOG_WDOG_B -13 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE -14 MX35_PAD_WDOG_RST__GPIO1_6 -15 MX35_PAD_GPIO1_0__GPIO1_0 -16 MX35_PAD_GPIO1_0__CCM_PMIC_RDY -17 MX35_PAD_GPIO1_0__OWIRE_LINE -18 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 -19 MX35_PAD_GPIO1_1__GPIO1_1 -20 MX35_PAD_GPIO1_1__PWM_PWMO -21 MX35_PAD_GPIO1_1__CSPI1_SS2 -22 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT -23 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 -24 MX35_PAD_GPIO2_0__GPIO2_0 -25 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK -26 MX35_PAD_GPIO3_0__GPIO3_0 -27 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK -28 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B -29 MX35_PAD_POR_B__CCM_POR_B -30 MX35_PAD_CLKO__CCM_CLKO -31 MX35_PAD_CLKO__GPIO1_8 -32 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 -33 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 -34 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 -35 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 -36 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 -37 MX35_PAD_VSTBY__CCM_VSTBY -38 MX35_PAD_VSTBY__GPIO1_7 -39 MX35_PAD_A0__EMI_EIM_DA_L_0 -40 MX35_PAD_A1__EMI_EIM_DA_L_1 -41 MX35_PAD_A2__EMI_EIM_DA_L_2 -42 MX35_PAD_A3__EMI_EIM_DA_L_3 -43 MX35_PAD_A4__EMI_EIM_DA_L_4 -44 MX35_PAD_A5__EMI_EIM_DA_L_5 -45 MX35_PAD_A6__EMI_EIM_DA_L_6 -46 MX35_PAD_A7__EMI_EIM_DA_L_7 -47 MX35_PAD_A8__EMI_EIM_DA_H_8 -48 MX35_PAD_A9__EMI_EIM_DA_H_9 -49 MX35_PAD_A10__EMI_EIM_DA_H_10 -50 MX35_PAD_MA10__EMI_MA10 -51 MX35_PAD_A11__EMI_EIM_DA_H_11 -52 MX35_PAD_A12__EMI_EIM_DA_H_12 -53 MX35_PAD_A13__EMI_EIM_DA_H_13 -54 MX35_PAD_A14__EMI_EIM_DA_H2_14 -55 MX35_PAD_A15__EMI_EIM_DA_H2_15 -56 MX35_PAD_A16__EMI_EIM_A_16 -57 MX35_PAD_A17__EMI_EIM_A_17 -58 MX35_PAD_A18__EMI_EIM_A_18 -59 MX35_PAD_A19__EMI_EIM_A_19 -60 MX35_PAD_A20__EMI_EIM_A_20 -61 MX35_PAD_A21__EMI_EIM_A_21 -62 MX35_PAD_A22__EMI_EIM_A_22 -63 MX35_PAD_A23__EMI_EIM_A_23 -64 MX35_PAD_A24__EMI_EIM_A_24 -65 MX35_PAD_A25__EMI_EIM_A_25 -66 MX35_PAD_SDBA1__EMI_EIM_SDBA1 -67 MX35_PAD_SDBA0__EMI_EIM_SDBA0 -68 MX35_PAD_SD0__EMI_DRAM_D_0 -69 MX35_PAD_SD1__EMI_DRAM_D_1 -70 MX35_PAD_SD2__EMI_DRAM_D_2 -71 MX35_PAD_SD3__EMI_DRAM_D_3 -72 MX35_PAD_SD4__EMI_DRAM_D_4 -73 MX35_PAD_SD5__EMI_DRAM_D_5 -74 MX35_PAD_SD6__EMI_DRAM_D_6 -75 MX35_PAD_SD7__EMI_DRAM_D_7 -76 MX35_PAD_SD8__EMI_DRAM_D_8 -77 MX35_PAD_SD9__EMI_DRAM_D_9 -78 MX35_PAD_SD10__EMI_DRAM_D_10 -79 MX35_PAD_SD11__EMI_DRAM_D_11 -80 MX35_PAD_SD12__EMI_DRAM_D_12 -81 MX35_PAD_SD13__EMI_DRAM_D_13 -82 MX35_PAD_SD14__EMI_DRAM_D_14 -83 MX35_PAD_SD15__EMI_DRAM_D_15 -84 MX35_PAD_SD16__EMI_DRAM_D_16 -85 MX35_PAD_SD17__EMI_DRAM_D_17 -86 MX35_PAD_SD18__EMI_DRAM_D_18 -87 MX35_PAD_SD19__EMI_DRAM_D_19 -88 MX35_PAD_SD20__EMI_DRAM_D_20 -89 MX35_PAD_SD21__EMI_DRAM_D_21 -90 MX35_PAD_SD22__EMI_DRAM_D_22 -91 MX35_PAD_SD23__EMI_DRAM_D_23 -92 MX35_PAD_SD24__EMI_DRAM_D_24 -93 MX35_PAD_SD25__EMI_DRAM_D_25 -94 MX35_PAD_SD26__EMI_DRAM_D_26 -95 MX35_PAD_SD27__EMI_DRAM_D_27 -96 MX35_PAD_SD28__EMI_DRAM_D_28 -97 MX35_PAD_SD29__EMI_DRAM_D_29 -98 MX35_PAD_SD30__EMI_DRAM_D_30 -99 MX35_PAD_SD31__EMI_DRAM_D_31 -100 MX35_PAD_DQM0__EMI_DRAM_DQM_0 -101 MX35_PAD_DQM1__EMI_DRAM_DQM_1 -102 MX35_PAD_DQM2__EMI_DRAM_DQM_2 -103 MX35_PAD_DQM3__EMI_DRAM_DQM_3 -104 MX35_PAD_EB0__EMI_EIM_EB0_B -105 MX35_PAD_EB1__EMI_EIM_EB1_B -106 MX35_PAD_OE__EMI_EIM_OE -107 MX35_PAD_CS0__EMI_EIM_CS0 -108 MX35_PAD_CS1__EMI_EIM_CS1 -109 MX35_PAD_CS1__EMI_NANDF_CE3 -110 MX35_PAD_CS2__EMI_EIM_CS2 -111 MX35_PAD_CS3__EMI_EIM_CS3 -112 MX35_PAD_CS4__EMI_EIM_CS4 -113 MX35_PAD_CS4__EMI_DTACK_B -114 MX35_PAD_CS4__EMI_NANDF_CE1 -115 MX35_PAD_CS4__GPIO1_20 -116 MX35_PAD_CS5__EMI_EIM_CS5 -117 MX35_PAD_CS5__CSPI2_SS2 -118 MX35_PAD_CS5__CSPI1_SS2 -119 MX35_PAD_CS5__EMI_NANDF_CE2 -120 MX35_PAD_CS5__GPIO1_21 -121 MX35_PAD_NF_CE0__EMI_NANDF_CE0 -122 MX35_PAD_NF_CE0__GPIO1_22 -123 MX35_PAD_ECB__EMI_EIM_ECB -124 MX35_PAD_LBA__EMI_EIM_LBA -125 MX35_PAD_BCLK__EMI_EIM_BCLK -126 MX35_PAD_RW__EMI_EIM_RW -127 MX35_PAD_RAS__EMI_DRAM_RAS -128 MX35_PAD_CAS__EMI_DRAM_CAS -129 MX35_PAD_SDWE__EMI_DRAM_SDWE -130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 -131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 -132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK -133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 -134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 -135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 -136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 -137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B -138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 -139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC -140 MX35_PAD_NFWE_B__GPIO2_18 -141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 -142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B -143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR -144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK -145 MX35_PAD_NFRE_B__GPIO2_19 -146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 -147 MX35_PAD_NFALE__EMI_NANDF_ALE -148 MX35_PAD_NFALE__USB_TOP_USBH2_STP -149 MX35_PAD_NFALE__IPU_DISPB_CS0 -150 MX35_PAD_NFALE__GPIO2_20 -151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 -152 MX35_PAD_NFCLE__EMI_NANDF_CLE -153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT -154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS -155 MX35_PAD_NFCLE__GPIO2_21 -156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 -157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B -158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 -159 MX35_PAD_NFWP_B__IPU_DISPB_WR -160 MX35_PAD_NFWP_B__GPIO2_22 -161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL -162 MX35_PAD_NFRB__EMI_NANDF_RB -163 MX35_PAD_NFRB__IPU_DISPB_RD -164 MX35_PAD_NFRB__GPIO2_23 -165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK -166 MX35_PAD_D15__EMI_EIM_D_15 -167 MX35_PAD_D14__EMI_EIM_D_14 -168 MX35_PAD_D13__EMI_EIM_D_13 -169 MX35_PAD_D12__EMI_EIM_D_12 -170 MX35_PAD_D11__EMI_EIM_D_11 -171 MX35_PAD_D10__EMI_EIM_D_10 -172 MX35_PAD_D9__EMI_EIM_D_9 -173 MX35_PAD_D8__EMI_EIM_D_8 -174 MX35_PAD_D7__EMI_EIM_D_7 -175 MX35_PAD_D6__EMI_EIM_D_6 -176 MX35_PAD_D5__EMI_EIM_D_5 -177 MX35_PAD_D4__EMI_EIM_D_4 -178 MX35_PAD_D3__EMI_EIM_D_3 -179 MX35_PAD_D2__EMI_EIM_D_2 -180 MX35_PAD_D1__EMI_EIM_D_1 -181 MX35_PAD_D0__EMI_EIM_D_0 -182 MX35_PAD_CSI_D8__IPU_CSI_D_8 -183 MX35_PAD_CSI_D8__KPP_COL_0 -184 MX35_PAD_CSI_D8__GPIO1_20 -185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 -186 MX35_PAD_CSI_D9__IPU_CSI_D_9 -187 MX35_PAD_CSI_D9__KPP_COL_1 -188 MX35_PAD_CSI_D9__GPIO1_21 -189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 -190 MX35_PAD_CSI_D10__IPU_CSI_D_10 -191 MX35_PAD_CSI_D10__KPP_COL_2 -192 MX35_PAD_CSI_D10__GPIO1_22 -193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 -194 MX35_PAD_CSI_D11__IPU_CSI_D_11 -195 MX35_PAD_CSI_D11__KPP_COL_3 -196 MX35_PAD_CSI_D11__GPIO1_23 -197 MX35_PAD_CSI_D12__IPU_CSI_D_12 -198 MX35_PAD_CSI_D12__KPP_ROW_0 -199 MX35_PAD_CSI_D12__GPIO1_24 -200 MX35_PAD_CSI_D13__IPU_CSI_D_13 -201 MX35_PAD_CSI_D13__KPP_ROW_1 -202 MX35_PAD_CSI_D13__GPIO1_25 -203 MX35_PAD_CSI_D14__IPU_CSI_D_14 -204 MX35_PAD_CSI_D14__KPP_ROW_2 -205 MX35_PAD_CSI_D14__GPIO1_26 -206 MX35_PAD_CSI_D15__IPU_CSI_D_15 -207 MX35_PAD_CSI_D15__KPP_ROW_3 -208 MX35_PAD_CSI_D15__GPIO1_27 -209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK -210 MX35_PAD_CSI_MCLK__GPIO1_28 -211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC -212 MX35_PAD_CSI_VSYNC__GPIO1_29 -213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC -214 MX35_PAD_CSI_HSYNC__GPIO1_30 -215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK -216 MX35_PAD_CSI_PIXCLK__GPIO1_31 -217 MX35_PAD_I2C1_CLK__I2C1_SCL -218 MX35_PAD_I2C1_CLK__GPIO2_24 -219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK -220 MX35_PAD_I2C1_DAT__I2C1_SDA -221 MX35_PAD_I2C1_DAT__GPIO2_25 -222 MX35_PAD_I2C2_CLK__I2C2_SCL -223 MX35_PAD_I2C2_CLK__CAN1_TXCAN -224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR -225 MX35_PAD_I2C2_CLK__GPIO2_26 -226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 -227 MX35_PAD_I2C2_DAT__I2C2_SDA -228 MX35_PAD_I2C2_DAT__CAN1_RXCAN -229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC -230 MX35_PAD_I2C2_DAT__GPIO2_27 -231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 -232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD -233 MX35_PAD_STXD4__GPIO2_28 -234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 -235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD -236 MX35_PAD_SRXD4__GPIO2_29 -237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 -238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC -239 MX35_PAD_SCK4__GPIO2_30 -240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 -241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS -242 MX35_PAD_STXFS4__GPIO2_31 -243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 -244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD -245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 -246 MX35_PAD_STXD5__CSPI2_MOSI -247 MX35_PAD_STXD5__GPIO1_0 -248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 -249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD -250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 -251 MX35_PAD_SRXD5__CSPI2_MISO -252 MX35_PAD_SRXD5__GPIO1_1 -253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 -254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC -255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK -256 MX35_PAD_SCK5__CSPI2_SCLK -257 MX35_PAD_SCK5__GPIO1_2 -258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 -259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS -260 MX35_PAD_STXFS5__CSPI2_RDY -261 MX35_PAD_STXFS5__GPIO1_3 -262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 -263 MX35_PAD_SCKR__ESAI_SCKR -264 MX35_PAD_SCKR__GPIO1_4 -265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 -266 MX35_PAD_FSR__ESAI_FSR -267 MX35_PAD_FSR__GPIO1_5 -268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 -269 MX35_PAD_HCKR__ESAI_HCKR -270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS -271 MX35_PAD_HCKR__CSPI2_SS0 -272 MX35_PAD_HCKR__IPU_FLASH_STROBE -273 MX35_PAD_HCKR__GPIO1_6 -274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 -275 MX35_PAD_SCKT__ESAI_SCKT -276 MX35_PAD_SCKT__GPIO1_7 -277 MX35_PAD_SCKT__IPU_CSI_D_0 -278 MX35_PAD_SCKT__KPP_ROW_2 -279 MX35_PAD_FST__ESAI_FST -280 MX35_PAD_FST__GPIO1_8 -281 MX35_PAD_FST__IPU_CSI_D_1 -282 MX35_PAD_FST__KPP_ROW_3 -283 MX35_PAD_HCKT__ESAI_HCKT -284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC -285 MX35_PAD_HCKT__GPIO1_9 -286 MX35_PAD_HCKT__IPU_CSI_D_2 -287 MX35_PAD_HCKT__KPP_COL_3 -288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0 -289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC -290 MX35_PAD_TX5_RX0__CSPI2_SS2 -291 MX35_PAD_TX5_RX0__CAN2_TXCAN -292 MX35_PAD_TX5_RX0__UART2_DTR -293 MX35_PAD_TX5_RX0__GPIO1_10 -294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 -295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1 -296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS -297 MX35_PAD_TX4_RX1__CSPI2_SS3 -298 MX35_PAD_TX4_RX1__CAN2_RXCAN -299 MX35_PAD_TX4_RX1__UART2_DSR -300 MX35_PAD_TX4_RX1__GPIO1_11 -301 MX35_PAD_TX4_RX1__IPU_CSI_D_3 -302 MX35_PAD_TX4_RX1__KPP_ROW_0 -303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2 -304 MX35_PAD_TX3_RX2__I2C3_SCL -305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1 -306 MX35_PAD_TX3_RX2__GPIO1_12 -307 MX35_PAD_TX3_RX2__IPU_CSI_D_4 -308 MX35_PAD_TX3_RX2__KPP_ROW_1 -309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3 -310 MX35_PAD_TX2_RX3__I2C3_SDA -311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2 -312 MX35_PAD_TX2_RX3__GPIO1_13 -313 MX35_PAD_TX2_RX3__IPU_CSI_D_5 -314 MX35_PAD_TX2_RX3__KPP_COL_0 -315 MX35_PAD_TX1__ESAI_TX1 -316 MX35_PAD_TX1__CCM_PMIC_RDY -317 MX35_PAD_TX1__CSPI1_SS2 -318 MX35_PAD_TX1__EMI_NANDF_CE3 -319 MX35_PAD_TX1__UART2_RI -320 MX35_PAD_TX1__GPIO1_14 -321 MX35_PAD_TX1__IPU_CSI_D_6 -322 MX35_PAD_TX1__KPP_COL_1 -323 MX35_PAD_TX0__ESAI_TX0 -324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK -325 MX35_PAD_TX0__CSPI1_SS3 -326 MX35_PAD_TX0__EMI_DTACK_B -327 MX35_PAD_TX0__UART2_DCD -328 MX35_PAD_TX0__GPIO1_15 -329 MX35_PAD_TX0__IPU_CSI_D_7 -330 MX35_PAD_TX0__KPP_COL_2 -331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI -332 MX35_PAD_CSPI1_MOSI__GPIO1_16 -333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 -334 MX35_PAD_CSPI1_MISO__CSPI1_MISO -335 MX35_PAD_CSPI1_MISO__GPIO1_17 -336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 -337 MX35_PAD_CSPI1_SS0__CSPI1_SS0 -338 MX35_PAD_CSPI1_SS0__OWIRE_LINE -339 MX35_PAD_CSPI1_SS0__CSPI2_SS3 -340 MX35_PAD_CSPI1_SS0__GPIO1_18 -341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 -342 MX35_PAD_CSPI1_SS1__CSPI1_SS1 -343 MX35_PAD_CSPI1_SS1__PWM_PWMO -344 MX35_PAD_CSPI1_SS1__CCM_CLK32K -345 MX35_PAD_CSPI1_SS1__GPIO1_19 -346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 -347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 -348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK -349 MX35_PAD_CSPI1_SCLK__GPIO3_4 -350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 -351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 -352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY -353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 -354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 -355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 -356 MX35_PAD_RXD1__UART1_RXD_MUX -357 MX35_PAD_RXD1__CSPI2_MOSI -358 MX35_PAD_RXD1__KPP_COL_4 -359 MX35_PAD_RXD1__GPIO3_6 -360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 -361 MX35_PAD_TXD1__UART1_TXD_MUX -362 MX35_PAD_TXD1__CSPI2_MISO -363 MX35_PAD_TXD1__KPP_COL_5 -364 MX35_PAD_TXD1__GPIO3_7 -365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 -366 MX35_PAD_RTS1__UART1_RTS -367 MX35_PAD_RTS1__CSPI2_SCLK -368 MX35_PAD_RTS1__I2C3_SCL -369 MX35_PAD_RTS1__IPU_CSI_D_0 -370 MX35_PAD_RTS1__KPP_COL_6 -371 MX35_PAD_RTS1__GPIO3_8 -372 MX35_PAD_RTS1__EMI_NANDF_CE1 -373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 -374 MX35_PAD_CTS1__UART1_CTS -375 MX35_PAD_CTS1__CSPI2_RDY -376 MX35_PAD_CTS1__I2C3_SDA -377 MX35_PAD_CTS1__IPU_CSI_D_1 -378 MX35_PAD_CTS1__KPP_COL_7 -379 MX35_PAD_CTS1__GPIO3_9 -380 MX35_PAD_CTS1__EMI_NANDF_CE2 -381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 -382 MX35_PAD_RXD2__UART2_RXD_MUX -383 MX35_PAD_RXD2__KPP_ROW_4 -384 MX35_PAD_RXD2__GPIO3_10 -385 MX35_PAD_TXD2__UART2_TXD_MUX -386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK -387 MX35_PAD_TXD2__KPP_ROW_5 -388 MX35_PAD_TXD2__GPIO3_11 -389 MX35_PAD_RTS2__UART2_RTS -390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1 -391 MX35_PAD_RTS2__CAN2_RXCAN -392 MX35_PAD_RTS2__IPU_CSI_D_2 -393 MX35_PAD_RTS2__KPP_ROW_6 -394 MX35_PAD_RTS2__GPIO3_12 -395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC -396 MX35_PAD_RTS2__UART3_RXD_MUX -397 MX35_PAD_CTS2__UART2_CTS -398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 -399 MX35_PAD_CTS2__CAN2_TXCAN -400 MX35_PAD_CTS2__IPU_CSI_D_3 -401 MX35_PAD_CTS2__KPP_ROW_7 -402 MX35_PAD_CTS2__GPIO3_13 -403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS -404 MX35_PAD_CTS2__UART3_TXD_MUX -405 MX35_PAD_RTCK__ARM11P_TOP_RTCK -406 MX35_PAD_TCK__SJC_TCK -407 MX35_PAD_TMS__SJC_TMS -408 MX35_PAD_TDI__SJC_TDI -409 MX35_PAD_TDO__SJC_TDO -410 MX35_PAD_TRSTB__SJC_TRSTB -411 MX35_PAD_DE_B__SJC_DE_B -412 MX35_PAD_SJC_MOD__SJC_MOD -413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR -414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR -415 MX35_PAD_USBOTG_PWR__GPIO3_14 -416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC -417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC -418 MX35_PAD_USBOTG_OC__GPIO3_15 -419 MX35_PAD_LD0__IPU_DISPB_DAT_0 -420 MX35_PAD_LD0__GPIO2_0 -421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 -422 MX35_PAD_LD1__IPU_DISPB_DAT_1 -423 MX35_PAD_LD1__GPIO2_1 -424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 -425 MX35_PAD_LD2__IPU_DISPB_DAT_2 -426 MX35_PAD_LD2__GPIO2_2 -427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 -428 MX35_PAD_LD3__IPU_DISPB_DAT_3 -429 MX35_PAD_LD3__GPIO2_3 -430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 -431 MX35_PAD_LD4__IPU_DISPB_DAT_4 -432 MX35_PAD_LD4__GPIO2_4 -433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 -434 MX35_PAD_LD5__IPU_DISPB_DAT_5 -435 MX35_PAD_LD5__GPIO2_5 -436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 -437 MX35_PAD_LD6__IPU_DISPB_DAT_6 -438 MX35_PAD_LD6__GPIO2_6 -439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 -440 MX35_PAD_LD7__IPU_DISPB_DAT_7 -441 MX35_PAD_LD7__GPIO2_7 -442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 -443 MX35_PAD_LD8__IPU_DISPB_DAT_8 -444 MX35_PAD_LD8__GPIO2_8 -445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 -446 MX35_PAD_LD9__IPU_DISPB_DAT_9 -447 MX35_PAD_LD9__GPIO2_9 -448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 -449 MX35_PAD_LD10__IPU_DISPB_DAT_10 -450 MX35_PAD_LD10__GPIO2_10 -451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 -452 MX35_PAD_LD11__IPU_DISPB_DAT_11 -453 MX35_PAD_LD11__GPIO2_11 -454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 -455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4 -456 MX35_PAD_LD12__IPU_DISPB_DAT_12 -457 MX35_PAD_LD12__GPIO2_12 -458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 -459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5 -460 MX35_PAD_LD13__IPU_DISPB_DAT_13 -461 MX35_PAD_LD13__GPIO2_13 -462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 -463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6 -464 MX35_PAD_LD14__IPU_DISPB_DAT_14 -465 MX35_PAD_LD14__GPIO2_14 -466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 -467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7 -468 MX35_PAD_LD15__IPU_DISPB_DAT_15 -469 MX35_PAD_LD15__GPIO2_15 -470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 -471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8 -472 MX35_PAD_LD16__IPU_DISPB_DAT_16 -473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC -474 MX35_PAD_LD16__GPIO2_16 -475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 -476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9 -477 MX35_PAD_LD17__IPU_DISPB_DAT_17 -478 MX35_PAD_LD17__IPU_DISPB_CS2 -479 MX35_PAD_LD17__GPIO2_17 -480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 -481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10 -482 MX35_PAD_LD18__IPU_DISPB_DAT_18 -483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC -484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC -485 MX35_PAD_LD18__ESDHC3_CMD -486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 -487 MX35_PAD_LD18__GPIO3_24 -488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 -489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11 -490 MX35_PAD_LD19__IPU_DISPB_DAT_19 -491 MX35_PAD_LD19__IPU_DISPB_BCLK -492 MX35_PAD_LD19__IPU_DISPB_CS1 -493 MX35_PAD_LD19__ESDHC3_CLK -494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR -495 MX35_PAD_LD19__GPIO3_25 -496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 -497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12 -498 MX35_PAD_LD20__IPU_DISPB_DAT_20 -499 MX35_PAD_LD20__IPU_DISPB_CS0 -500 MX35_PAD_LD20__IPU_DISPB_SD_CLK -501 MX35_PAD_LD20__ESDHC3_DAT0 -502 MX35_PAD_LD20__GPIO3_26 -503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 -504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13 -505 MX35_PAD_LD21__IPU_DISPB_DAT_21 -506 MX35_PAD_LD21__IPU_DISPB_PAR_RS -507 MX35_PAD_LD21__IPU_DISPB_SER_RS -508 MX35_PAD_LD21__ESDHC3_DAT1 -509 MX35_PAD_LD21__USB_TOP_USBOTG_STP -510 MX35_PAD_LD21__GPIO3_27 -511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL -512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14 -513 MX35_PAD_LD22__IPU_DISPB_DAT_22 -514 MX35_PAD_LD22__IPU_DISPB_WR -515 MX35_PAD_LD22__IPU_DISPB_SD_D_I -516 MX35_PAD_LD22__ESDHC3_DAT2 -517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT -518 MX35_PAD_LD22__GPIO3_28 -519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR -520 MX35_PAD_LD22__ARM11P_TOP_TRCTL -521 MX35_PAD_LD23__IPU_DISPB_DAT_23 -522 MX35_PAD_LD23__IPU_DISPB_RD -523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO -524 MX35_PAD_LD23__ESDHC3_DAT3 -525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 -526 MX35_PAD_LD23__GPIO3_29 -527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS -528 MX35_PAD_LD23__ARM11P_TOP_TRCLK -529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC -530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO -531 MX35_PAD_D3_HSYNC__GPIO3_30 -532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE -533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 -534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK -535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK -536 MX35_PAD_D3_FPSHIFT__GPIO3_31 -537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 -538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 -539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY -540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O -541 MX35_PAD_D3_DRDY__GPIO1_0 -542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 -543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 -544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR -545 MX35_PAD_CONTRAST__GPIO1_1 -546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 -547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 -548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC -549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 -550 MX35_PAD_D3_VSYNC__GPIO1_2 -551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD -552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 -553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV -554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS -555 MX35_PAD_D3_REV__GPIO1_3 -556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB -557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 -558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS -559 MX35_PAD_D3_CLS__IPU_DISPB_CS2 -560 MX35_PAD_D3_CLS__GPIO1_4 -561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 -562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 -563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL -564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC -565 MX35_PAD_D3_SPL__GPIO1_5 -566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 -567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 -568 MX35_PAD_SD1_CMD__ESDHC1_CMD -569 MX35_PAD_SD1_CMD__MSHC_SCLK -570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC -571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 -572 MX35_PAD_SD1_CMD__GPIO1_6 -573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL -574 MX35_PAD_SD1_CLK__ESDHC1_CLK -575 MX35_PAD_SD1_CLK__MSHC_BS -576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK -577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 -578 MX35_PAD_SD1_CLK__GPIO1_7 -579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK -580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0 -581 MX35_PAD_SD1_DATA0__MSHC_DATA_0 -582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 -583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 -584 MX35_PAD_SD1_DATA0__GPIO1_8 -585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 -586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1 -587 MX35_PAD_SD1_DATA1__MSHC_DATA_1 -588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS -589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 -590 MX35_PAD_SD1_DATA1__GPIO1_9 -591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 -592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2 -593 MX35_PAD_SD1_DATA2__MSHC_DATA_2 -594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR -595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 -596 MX35_PAD_SD1_DATA2__GPIO1_10 -597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 -598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3 -599 MX35_PAD_SD1_DATA3__MSHC_DATA_3 -600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD -601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 -602 MX35_PAD_SD1_DATA3__GPIO1_11 -603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 -604 MX35_PAD_SD2_CMD__ESDHC2_CMD -605 MX35_PAD_SD2_CMD__I2C3_SCL -606 MX35_PAD_SD2_CMD__ESDHC1_DAT4 -607 MX35_PAD_SD2_CMD__IPU_CSI_D_2 -608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 -609 MX35_PAD_SD2_CMD__GPIO2_0 -610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 -611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC -612 MX35_PAD_SD2_CLK__ESDHC2_CLK -613 MX35_PAD_SD2_CLK__I2C3_SDA -614 MX35_PAD_SD2_CLK__ESDHC1_DAT5 -615 MX35_PAD_SD2_CLK__IPU_CSI_D_3 -616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 -617 MX35_PAD_SD2_CLK__GPIO2_1 -618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 -619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2 -620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0 -621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX -622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6 -623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4 -624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 -625 MX35_PAD_SD2_DATA0__GPIO2_2 -626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK -627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1 -628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX -629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7 -630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5 -631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 -632 MX35_PAD_SD2_DATA1__GPIO2_3 -633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2 -634 MX35_PAD_SD2_DATA2__UART3_RTS -635 MX35_PAD_SD2_DATA2__CAN1_RXCAN -636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6 -637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 -638 MX35_PAD_SD2_DATA2__GPIO2_4 -639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3 -640 MX35_PAD_SD2_DATA3__UART3_CTS -641 MX35_PAD_SD2_DATA3__CAN1_TXCAN -642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7 -643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 -644 MX35_PAD_SD2_DATA3__GPIO2_5 -645 MX35_PAD_ATA_CS0__ATA_CS0 -646 MX35_PAD_ATA_CS0__CSPI1_SS3 -647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1 -648 MX35_PAD_ATA_CS0__GPIO2_6 -649 MX35_PAD_ATA_CS0__IPU_DIAGB_0 -650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 -651 MX35_PAD_ATA_CS1__ATA_CS1 -652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2 -653 MX35_PAD_ATA_CS1__CSPI2_SS0 -654 MX35_PAD_ATA_CS1__GPIO2_7 -655 MX35_PAD_ATA_CS1__IPU_DIAGB_1 -656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 -657 MX35_PAD_ATA_DIOR__ATA_DIOR -658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0 -659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR -660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 -661 MX35_PAD_ATA_DIOR__CSPI2_SS1 -662 MX35_PAD_ATA_DIOR__GPIO2_8 -663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2 -664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 -665 MX35_PAD_ATA_DIOW__ATA_DIOW -666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1 -667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP -668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 -669 MX35_PAD_ATA_DIOW__CSPI2_MOSI -670 MX35_PAD_ATA_DIOW__GPIO2_9 -671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3 -672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 -673 MX35_PAD_ATA_DMACK__ATA_DMACK -674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2 -675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT -676 MX35_PAD_ATA_DMACK__CSPI2_MISO -677 MX35_PAD_ATA_DMACK__GPIO2_10 -678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4 -679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 -680 MX35_PAD_ATA_RESET_B__ATA_RESET_B -681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 -682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 -683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O -684 MX35_PAD_ATA_RESET_B__CSPI2_RDY -685 MX35_PAD_ATA_RESET_B__GPIO2_11 -686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 -687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 -688 MX35_PAD_ATA_IORDY__ATA_IORDY -689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4 -690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 -691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO -692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4 -693 MX35_PAD_ATA_IORDY__GPIO2_12 -694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6 -695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 -696 MX35_PAD_ATA_DATA0__ATA_DATA_0 -697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5 -698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 -699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC -700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5 -701 MX35_PAD_ATA_DATA0__GPIO2_13 -702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7 -703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 -704 MX35_PAD_ATA_DATA1__ATA_DATA_1 -705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6 -706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 -707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK -708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6 -709 MX35_PAD_ATA_DATA1__GPIO2_14 -710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8 -711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 -712 MX35_PAD_ATA_DATA2__ATA_DATA_2 -713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7 -714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 -715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS -716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7 -717 MX35_PAD_ATA_DATA2__GPIO2_15 -718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9 -719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 -720 MX35_PAD_ATA_DATA3__ATA_DATA_3 -721 MX35_PAD_ATA_DATA3__ESDHC3_CLK -722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 -723 MX35_PAD_ATA_DATA3__CSPI2_SCLK -724 MX35_PAD_ATA_DATA3__GPIO2_16 -725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10 -726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 -727 MX35_PAD_ATA_DATA4__ATA_DATA_4 -728 MX35_PAD_ATA_DATA4__ESDHC3_CMD -729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 -730 MX35_PAD_ATA_DATA4__GPIO2_17 -731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11 -732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 -733 MX35_PAD_ATA_DATA5__ATA_DATA_5 -734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 -735 MX35_PAD_ATA_DATA5__GPIO2_18 -736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12 -737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 -738 MX35_PAD_ATA_DATA6__ATA_DATA_6 -739 MX35_PAD_ATA_DATA6__CAN1_TXCAN -740 MX35_PAD_ATA_DATA6__UART1_DTR -741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD -742 MX35_PAD_ATA_DATA6__GPIO2_19 -743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13 -744 MX35_PAD_ATA_DATA7__ATA_DATA_7 -745 MX35_PAD_ATA_DATA7__CAN1_RXCAN -746 MX35_PAD_ATA_DATA7__UART1_DSR -747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD -748 MX35_PAD_ATA_DATA7__GPIO2_20 -749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14 -750 MX35_PAD_ATA_DATA8__ATA_DATA_8 -751 MX35_PAD_ATA_DATA8__UART3_RTS -752 MX35_PAD_ATA_DATA8__UART1_RI -753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC -754 MX35_PAD_ATA_DATA8__GPIO2_21 -755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15 -756 MX35_PAD_ATA_DATA9__ATA_DATA_9 -757 MX35_PAD_ATA_DATA9__UART3_CTS -758 MX35_PAD_ATA_DATA9__UART1_DCD -759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS -760 MX35_PAD_ATA_DATA9__GPIO2_22 -761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16 -762 MX35_PAD_ATA_DATA10__ATA_DATA_10 -763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX -764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC -765 MX35_PAD_ATA_DATA10__GPIO2_23 -766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17 -767 MX35_PAD_ATA_DATA11__ATA_DATA_11 -768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX -769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS -770 MX35_PAD_ATA_DATA11__GPIO2_24 -771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18 -772 MX35_PAD_ATA_DATA12__ATA_DATA_12 -773 MX35_PAD_ATA_DATA12__I2C3_SCL -774 MX35_PAD_ATA_DATA12__GPIO2_25 -775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19 -776 MX35_PAD_ATA_DATA13__ATA_DATA_13 -777 MX35_PAD_ATA_DATA13__I2C3_SDA -778 MX35_PAD_ATA_DATA13__GPIO2_26 -779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20 -780 MX35_PAD_ATA_DATA14__ATA_DATA_14 -781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0 -782 MX35_PAD_ATA_DATA14__KPP_ROW_0 -783 MX35_PAD_ATA_DATA14__GPIO2_27 -784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21 -785 MX35_PAD_ATA_DATA15__ATA_DATA_15 -786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1 -787 MX35_PAD_ATA_DATA15__KPP_ROW_1 -788 MX35_PAD_ATA_DATA15__GPIO2_28 -789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22 -790 MX35_PAD_ATA_INTRQ__ATA_INTRQ -791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 -792 MX35_PAD_ATA_INTRQ__KPP_ROW_2 -793 MX35_PAD_ATA_INTRQ__GPIO2_29 -794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 -795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN -796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 -797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 -798 MX35_PAD_ATA_BUFF_EN__GPIO2_30 -799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 -800 MX35_PAD_ATA_DMARQ__ATA_DMARQ -801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 -802 MX35_PAD_ATA_DMARQ__KPP_COL_0 -803 MX35_PAD_ATA_DMARQ__GPIO2_31 -804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 -805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 -806 MX35_PAD_ATA_DA0__ATA_DA_0 -807 MX35_PAD_ATA_DA0__IPU_CSI_D_5 -808 MX35_PAD_ATA_DA0__KPP_COL_1 -809 MX35_PAD_ATA_DA0__GPIO3_0 -810 MX35_PAD_ATA_DA0__IPU_DIAGB_26 -811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 -812 MX35_PAD_ATA_DA1__ATA_DA_1 -813 MX35_PAD_ATA_DA1__IPU_CSI_D_6 -814 MX35_PAD_ATA_DA1__KPP_COL_2 -815 MX35_PAD_ATA_DA1__GPIO3_1 -816 MX35_PAD_ATA_DA1__IPU_DIAGB_27 -817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 -818 MX35_PAD_ATA_DA2__ATA_DA_2 -819 MX35_PAD_ATA_DA2__IPU_CSI_D_7 -820 MX35_PAD_ATA_DA2__KPP_COL_3 -821 MX35_PAD_ATA_DA2__GPIO3_2 -822 MX35_PAD_ATA_DA2__IPU_DIAGB_28 -823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 -824 MX35_PAD_MLB_CLK__MLB_MLBCLK -825 MX35_PAD_MLB_CLK__GPIO3_3 -826 MX35_PAD_MLB_DAT__MLB_MLBDAT -827 MX35_PAD_MLB_DAT__GPIO3_4 -828 MX35_PAD_MLB_SIG__MLB_MLBSIG -829 MX35_PAD_MLB_SIG__GPIO3_5 -830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK -831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 -832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX -833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR -834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI -835 MX35_PAD_FEC_TX_CLK__GPIO3_6 -836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC -837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 -838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK -839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 -840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX -841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP -842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO -843 MX35_PAD_FEC_RX_CLK__GPIO3_7 -844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I -845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 -846 MX35_PAD_FEC_RX_DV__FEC_RX_DV -847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 -848 MX35_PAD_FEC_RX_DV__UART3_RTS -849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT -850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK -851 MX35_PAD_FEC_RX_DV__GPIO3_8 -852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK -853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 -854 MX35_PAD_FEC_COL__FEC_COL -855 MX35_PAD_FEC_COL__ESDHC1_DAT7 -856 MX35_PAD_FEC_COL__UART3_CTS -857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 -858 MX35_PAD_FEC_COL__CSPI2_RDY -859 MX35_PAD_FEC_COL__GPIO3_9 -860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS -861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 -862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0 -863 MX35_PAD_FEC_RDATA0__PWM_PWMO -864 MX35_PAD_FEC_RDATA0__UART3_DTR -865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 -866 MX35_PAD_FEC_RDATA0__CSPI2_SS0 -867 MX35_PAD_FEC_RDATA0__GPIO3_10 -868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 -869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 -870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0 -871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 -872 MX35_PAD_FEC_TDATA0__UART3_DSR -873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 -874 MX35_PAD_FEC_TDATA0__CSPI2_SS1 -875 MX35_PAD_FEC_TDATA0__GPIO3_11 -876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 -877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 -878 MX35_PAD_FEC_TX_EN__FEC_TX_EN -879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 -880 MX35_PAD_FEC_TX_EN__UART3_RI -881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 -882 MX35_PAD_FEC_TX_EN__GPIO3_12 -883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS -884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 -885 MX35_PAD_FEC_MDC__FEC_MDC -886 MX35_PAD_FEC_MDC__CAN2_TXCAN -887 MX35_PAD_FEC_MDC__UART3_DCD -888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 -889 MX35_PAD_FEC_MDC__GPIO3_13 -890 MX35_PAD_FEC_MDC__IPU_DISPB_WR -891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 -892 MX35_PAD_FEC_MDIO__FEC_MDIO -893 MX35_PAD_FEC_MDIO__CAN2_RXCAN -894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 -895 MX35_PAD_FEC_MDIO__GPIO3_14 -896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD -897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 -898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR -899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE -900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK -901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 -902 MX35_PAD_FEC_TX_ERR__GPIO3_15 -903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC -904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 -905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR -906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 -907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 -908 MX35_PAD_FEC_RX_ERR__KPP_COL_4 -909 MX35_PAD_FEC_RX_ERR__GPIO3_16 -910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO -911 MX35_PAD_FEC_CRS__FEC_CRS -912 MX35_PAD_FEC_CRS__IPU_CSI_D_1 -913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR -914 MX35_PAD_FEC_CRS__KPP_COL_5 -915 MX35_PAD_FEC_CRS__GPIO3_17 -916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE -917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1 -918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 -919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC -920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC -921 MX35_PAD_FEC_RDATA1__KPP_COL_6 -922 MX35_PAD_FEC_RDATA1__GPIO3_18 -923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 -924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1 -925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 -926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS -927 MX35_PAD_FEC_TDATA1__KPP_COL_7 -928 MX35_PAD_FEC_TDATA1__GPIO3_19 -929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 -930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2 -931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 -932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD -933 MX35_PAD_FEC_RDATA2__KPP_ROW_4 -934 MX35_PAD_FEC_RDATA2__GPIO3_20 -935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2 -936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 -937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD -938 MX35_PAD_FEC_TDATA2__KPP_ROW_5 -939 MX35_PAD_FEC_TDATA2__GPIO3_21 -940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3 -941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 -942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC -943 MX35_PAD_FEC_RDATA3__KPP_ROW_6 -944 MX35_PAD_FEC_RDATA3__GPIO3_22 -945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3 -946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 -947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS -948 MX35_PAD_FEC_TDATA3__KPP_ROW_7 -949 MX35_PAD_FEC_TDATA3__GPIO3_23 -950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK -951 MX35_PAD_TEST_MODE__TCU_TEST_MODE +Refer to imx35-pinfunc.h in device tree source folder for all available +imx35 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt index b96fa4c3174..4d1408fcc99 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt @@ -28,760 +28,5 @@ PAD_CTL_DSE_MAX (3 << 1) PAD_CTL_SRE_FAST (1 << 0) PAD_CTL_SRE_SLOW (0 << 0) -See below for available PIN_FUNC_ID for imx51: -MX51_PAD_EIM_D16__AUD4_RXFS 0 -MX51_PAD_EIM_D16__AUD5_TXD 1 -MX51_PAD_EIM_D16__EIM_D16 2 -MX51_PAD_EIM_D16__GPIO2_0 3 -MX51_PAD_EIM_D16__I2C1_SDA 4 -MX51_PAD_EIM_D16__UART2_CTS 5 -MX51_PAD_EIM_D16__USBH2_DATA0 6 -MX51_PAD_EIM_D17__AUD5_RXD 7 -MX51_PAD_EIM_D17__EIM_D17 8 -MX51_PAD_EIM_D17__GPIO2_1 9 -MX51_PAD_EIM_D17__UART2_RXD 10 -MX51_PAD_EIM_D17__UART3_CTS 11 -MX51_PAD_EIM_D17__USBH2_DATA1 12 -MX51_PAD_EIM_D18__AUD5_TXC 13 -MX51_PAD_EIM_D18__EIM_D18 14 -MX51_PAD_EIM_D18__GPIO2_2 15 -MX51_PAD_EIM_D18__UART2_TXD 16 -MX51_PAD_EIM_D18__UART3_RTS 17 -MX51_PAD_EIM_D18__USBH2_DATA2 18 -MX51_PAD_EIM_D19__AUD4_RXC 19 -MX51_PAD_EIM_D19__AUD5_TXFS 20 -MX51_PAD_EIM_D19__EIM_D19 21 -MX51_PAD_EIM_D19__GPIO2_3 22 -MX51_PAD_EIM_D19__I2C1_SCL 23 -MX51_PAD_EIM_D19__UART2_RTS 24 -MX51_PAD_EIM_D19__USBH2_DATA3 25 -MX51_PAD_EIM_D20__AUD4_TXD 26 -MX51_PAD_EIM_D20__EIM_D20 27 -MX51_PAD_EIM_D20__GPIO2_4 28 -MX51_PAD_EIM_D20__SRTC_ALARM_DEB 29 -MX51_PAD_EIM_D20__USBH2_DATA4 30 -MX51_PAD_EIM_D21__AUD4_RXD 31 -MX51_PAD_EIM_D21__EIM_D21 32 -MX51_PAD_EIM_D21__GPIO2_5 33 -MX51_PAD_EIM_D21__SRTC_ALARM_DEB 34 -MX51_PAD_EIM_D21__USBH2_DATA5 35 -MX51_PAD_EIM_D22__AUD4_TXC 36 -MX51_PAD_EIM_D22__EIM_D22 37 -MX51_PAD_EIM_D22__GPIO2_6 38 -MX51_PAD_EIM_D22__USBH2_DATA6 39 -MX51_PAD_EIM_D23__AUD4_TXFS 40 -MX51_PAD_EIM_D23__EIM_D23 41 -MX51_PAD_EIM_D23__GPIO2_7 42 -MX51_PAD_EIM_D23__SPDIF_OUT1 43 -MX51_PAD_EIM_D23__USBH2_DATA7 44 -MX51_PAD_EIM_D24__AUD6_RXFS 45 -MX51_PAD_EIM_D24__EIM_D24 46 -MX51_PAD_EIM_D24__GPIO2_8 47 -MX51_PAD_EIM_D24__I2C2_SDA 48 -MX51_PAD_EIM_D24__UART3_CTS 49 -MX51_PAD_EIM_D24__USBOTG_DATA0 50 -MX51_PAD_EIM_D25__EIM_D25 51 -MX51_PAD_EIM_D25__KEY_COL6 52 -MX51_PAD_EIM_D25__UART2_CTS 53 -MX51_PAD_EIM_D25__UART3_RXD 54 -MX51_PAD_EIM_D25__USBOTG_DATA1 55 -MX51_PAD_EIM_D26__EIM_D26 56 -MX51_PAD_EIM_D26__KEY_COL7 57 -MX51_PAD_EIM_D26__UART2_RTS 58 -MX51_PAD_EIM_D26__UART3_TXD 59 -MX51_PAD_EIM_D26__USBOTG_DATA2 60 -MX51_PAD_EIM_D27__AUD6_RXC 61 -MX51_PAD_EIM_D27__EIM_D27 62 -MX51_PAD_EIM_D27__GPIO2_9 63 -MX51_PAD_EIM_D27__I2C2_SCL 64 -MX51_PAD_EIM_D27__UART3_RTS 65 -MX51_PAD_EIM_D27__USBOTG_DATA3 66 -MX51_PAD_EIM_D28__AUD6_TXD 67 -MX51_PAD_EIM_D28__EIM_D28 68 -MX51_PAD_EIM_D28__KEY_ROW4 69 -MX51_PAD_EIM_D28__USBOTG_DATA4 70 -MX51_PAD_EIM_D29__AUD6_RXD 71 -MX51_PAD_EIM_D29__EIM_D29 72 -MX51_PAD_EIM_D29__KEY_ROW5 73 -MX51_PAD_EIM_D29__USBOTG_DATA5 74 -MX51_PAD_EIM_D30__AUD6_TXC 75 -MX51_PAD_EIM_D30__EIM_D30 76 -MX51_PAD_EIM_D30__KEY_ROW6 77 -MX51_PAD_EIM_D30__USBOTG_DATA6 78 -MX51_PAD_EIM_D31__AUD6_TXFS 79 -MX51_PAD_EIM_D31__EIM_D31 80 -MX51_PAD_EIM_D31__KEY_ROW7 81 -MX51_PAD_EIM_D31__USBOTG_DATA7 82 -MX51_PAD_EIM_A16__EIM_A16 83 -MX51_PAD_EIM_A16__GPIO2_10 84 -MX51_PAD_EIM_A16__OSC_FREQ_SEL0 85 -MX51_PAD_EIM_A17__EIM_A17 86 -MX51_PAD_EIM_A17__GPIO2_11 87 -MX51_PAD_EIM_A17__OSC_FREQ_SEL1 88 -MX51_PAD_EIM_A18__BOOT_LPB0 89 -MX51_PAD_EIM_A18__EIM_A18 90 -MX51_PAD_EIM_A18__GPIO2_12 91 -MX51_PAD_EIM_A19__BOOT_LPB1 92 -MX51_PAD_EIM_A19__EIM_A19 93 -MX51_PAD_EIM_A19__GPIO2_13 94 -MX51_PAD_EIM_A20__BOOT_UART_SRC0 95 -MX51_PAD_EIM_A20__EIM_A20 96 -MX51_PAD_EIM_A20__GPIO2_14 97 -MX51_PAD_EIM_A21__BOOT_UART_SRC1 98 -MX51_PAD_EIM_A21__EIM_A21 99 -MX51_PAD_EIM_A21__GPIO2_15 100 -MX51_PAD_EIM_A22__EIM_A22 101 -MX51_PAD_EIM_A22__GPIO2_16 102 -MX51_PAD_EIM_A23__BOOT_HPN_EN 103 -MX51_PAD_EIM_A23__EIM_A23 104 -MX51_PAD_EIM_A23__GPIO2_17 105 -MX51_PAD_EIM_A24__EIM_A24 106 -MX51_PAD_EIM_A24__GPIO2_18 107 -MX51_PAD_EIM_A24__USBH2_CLK 108 -MX51_PAD_EIM_A25__DISP1_PIN4 109 -MX51_PAD_EIM_A25__EIM_A25 110 -MX51_PAD_EIM_A25__GPIO2_19 111 -MX51_PAD_EIM_A25__USBH2_DIR 112 -MX51_PAD_EIM_A26__CSI1_DATA_EN 113 -MX51_PAD_EIM_A26__DISP2_EXT_CLK 114 -MX51_PAD_EIM_A26__EIM_A26 115 -MX51_PAD_EIM_A26__GPIO2_20 116 -MX51_PAD_EIM_A26__USBH2_STP 117 -MX51_PAD_EIM_A27__CSI2_DATA_EN 118 -MX51_PAD_EIM_A27__DISP1_PIN1 119 -MX51_PAD_EIM_A27__EIM_A27 120 -MX51_PAD_EIM_A27__GPIO2_21 121 -MX51_PAD_EIM_A27__USBH2_NXT 122 -MX51_PAD_EIM_EB0__EIM_EB0 123 -MX51_PAD_EIM_EB1__EIM_EB1 124 -MX51_PAD_EIM_EB2__AUD5_RXFS 125 -MX51_PAD_EIM_EB2__CSI1_D2 126 -MX51_PAD_EIM_EB2__EIM_EB2 127 -MX51_PAD_EIM_EB2__FEC_MDIO 128 -MX51_PAD_EIM_EB2__GPIO2_22 129 -MX51_PAD_EIM_EB2__GPT_CMPOUT1 130 -MX51_PAD_EIM_EB3__AUD5_RXC 131 -MX51_PAD_EIM_EB3__CSI1_D3 132 -MX51_PAD_EIM_EB3__EIM_EB3 133 -MX51_PAD_EIM_EB3__FEC_RDATA1 134 -MX51_PAD_EIM_EB3__GPIO2_23 135 -MX51_PAD_EIM_EB3__GPT_CMPOUT2 136 -MX51_PAD_EIM_OE__EIM_OE 137 -MX51_PAD_EIM_OE__GPIO2_24 138 -MX51_PAD_EIM_CS0__EIM_CS0 139 -MX51_PAD_EIM_CS0__GPIO2_25 140 -MX51_PAD_EIM_CS1__EIM_CS1 141 -MX51_PAD_EIM_CS1__GPIO2_26 142 -MX51_PAD_EIM_CS2__AUD5_TXD 143 -MX51_PAD_EIM_CS2__CSI1_D4 144 -MX51_PAD_EIM_CS2__EIM_CS2 145 -MX51_PAD_EIM_CS2__FEC_RDATA2 146 -MX51_PAD_EIM_CS2__GPIO2_27 147 -MX51_PAD_EIM_CS2__USBOTG_STP 148 -MX51_PAD_EIM_CS3__AUD5_RXD 149 -MX51_PAD_EIM_CS3__CSI1_D5 150 -MX51_PAD_EIM_CS3__EIM_CS3 151 -MX51_PAD_EIM_CS3__FEC_RDATA3 152 -MX51_PAD_EIM_CS3__GPIO2_28 153 -MX51_PAD_EIM_CS3__USBOTG_NXT 154 -MX51_PAD_EIM_CS4__AUD5_TXC 155 -MX51_PAD_EIM_CS4__CSI1_D6 156 -MX51_PAD_EIM_CS4__EIM_CS4 157 -MX51_PAD_EIM_CS4__FEC_RX_ER 158 -MX51_PAD_EIM_CS4__GPIO2_29 159 -MX51_PAD_EIM_CS4__USBOTG_CLK 160 -MX51_PAD_EIM_CS5__AUD5_TXFS 161 -MX51_PAD_EIM_CS5__CSI1_D7 162 -MX51_PAD_EIM_CS5__DISP1_EXT_CLK 163 -MX51_PAD_EIM_CS5__EIM_CS5 164 -MX51_PAD_EIM_CS5__FEC_CRS 165 -MX51_PAD_EIM_CS5__GPIO2_30 166 -MX51_PAD_EIM_CS5__USBOTG_DIR 167 -MX51_PAD_EIM_DTACK__EIM_DTACK 168 -MX51_PAD_EIM_DTACK__GPIO2_31 169 -MX51_PAD_EIM_LBA__EIM_LBA 170 -MX51_PAD_EIM_LBA__GPIO3_1 171 -MX51_PAD_EIM_CRE__EIM_CRE 172 -MX51_PAD_EIM_CRE__GPIO3_2 173 -MX51_PAD_DRAM_CS1__DRAM_CS1 174 -MX51_PAD_NANDF_WE_B__GPIO3_3 175 -MX51_PAD_NANDF_WE_B__NANDF_WE_B 176 -MX51_PAD_NANDF_WE_B__PATA_DIOW 177 -MX51_PAD_NANDF_WE_B__SD3_DATA0 178 -MX51_PAD_NANDF_RE_B__GPIO3_4 179 -MX51_PAD_NANDF_RE_B__NANDF_RE_B 180 -MX51_PAD_NANDF_RE_B__PATA_DIOR 181 -MX51_PAD_NANDF_RE_B__SD3_DATA1 182 -MX51_PAD_NANDF_ALE__GPIO3_5 183 -MX51_PAD_NANDF_ALE__NANDF_ALE 184 -MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 185 -MX51_PAD_NANDF_CLE__GPIO3_6 186 -MX51_PAD_NANDF_CLE__NANDF_CLE 187 -MX51_PAD_NANDF_CLE__PATA_RESET_B 188 -MX51_PAD_NANDF_WP_B__GPIO3_7 189 -MX51_PAD_NANDF_WP_B__NANDF_WP_B 190 -MX51_PAD_NANDF_WP_B__PATA_DMACK 191 -MX51_PAD_NANDF_WP_B__SD3_DATA2 192 -MX51_PAD_NANDF_RB0__ECSPI2_SS1 193 -MX51_PAD_NANDF_RB0__GPIO3_8 194 -MX51_PAD_NANDF_RB0__NANDF_RB0 195 -MX51_PAD_NANDF_RB0__PATA_DMARQ 196 -MX51_PAD_NANDF_RB0__SD3_DATA3 197 -MX51_PAD_NANDF_RB1__CSPI_MOSI 198 -MX51_PAD_NANDF_RB1__ECSPI2_RDY 199 -MX51_PAD_NANDF_RB1__GPIO3_9 200 -MX51_PAD_NANDF_RB1__NANDF_RB1 201 -MX51_PAD_NANDF_RB1__PATA_IORDY 202 -MX51_PAD_NANDF_RB1__SD4_CMD 203 -MX51_PAD_NANDF_RB2__DISP2_WAIT 204 -MX51_PAD_NANDF_RB2__ECSPI2_SCLK 205 -MX51_PAD_NANDF_RB2__FEC_COL 206 -MX51_PAD_NANDF_RB2__GPIO3_10 207 -MX51_PAD_NANDF_RB2__NANDF_RB2 208 -MX51_PAD_NANDF_RB2__USBH3_H3_DP 209 -MX51_PAD_NANDF_RB2__USBH3_NXT 210 -MX51_PAD_NANDF_RB3__DISP1_WAIT 211 -MX51_PAD_NANDF_RB3__ECSPI2_MISO 212 -MX51_PAD_NANDF_RB3__FEC_RX_CLK 213 -MX51_PAD_NANDF_RB3__GPIO3_11 214 -MX51_PAD_NANDF_RB3__NANDF_RB3 215 -MX51_PAD_NANDF_RB3__USBH3_CLK 216 -MX51_PAD_NANDF_RB3__USBH3_H3_DM 217 -MX51_PAD_GPIO_NAND__GPIO_NAND 218 -MX51_PAD_GPIO_NAND__PATA_INTRQ 219 -MX51_PAD_NANDF_CS0__GPIO3_16 220 -MX51_PAD_NANDF_CS0__NANDF_CS0 221 -MX51_PAD_NANDF_CS1__GPIO3_17 222 -MX51_PAD_NANDF_CS1__NANDF_CS1 223 -MX51_PAD_NANDF_CS2__CSPI_SCLK 224 -MX51_PAD_NANDF_CS2__FEC_TX_ER 225 -MX51_PAD_NANDF_CS2__GPIO3_18 226 -MX51_PAD_NANDF_CS2__NANDF_CS2 227 -MX51_PAD_NANDF_CS2__PATA_CS_0 228 -MX51_PAD_NANDF_CS2__SD4_CLK 229 -MX51_PAD_NANDF_CS2__USBH3_H1_DP 230 -MX51_PAD_NANDF_CS3__FEC_MDC 231 -MX51_PAD_NANDF_CS3__GPIO3_19 232 -MX51_PAD_NANDF_CS3__NANDF_CS3 233 -MX51_PAD_NANDF_CS3__PATA_CS_1 234 -MX51_PAD_NANDF_CS3__SD4_DAT0 235 -MX51_PAD_NANDF_CS3__USBH3_H1_DM 236 -MX51_PAD_NANDF_CS4__FEC_TDATA1 237 -MX51_PAD_NANDF_CS4__GPIO3_20 238 -MX51_PAD_NANDF_CS4__NANDF_CS4 239 -MX51_PAD_NANDF_CS4__PATA_DA_0 240 -MX51_PAD_NANDF_CS4__SD4_DAT1 241 -MX51_PAD_NANDF_CS4__USBH3_STP 242 -MX51_PAD_NANDF_CS5__FEC_TDATA2 243 -MX51_PAD_NANDF_CS5__GPIO3_21 244 -MX51_PAD_NANDF_CS5__NANDF_CS5 245 -MX51_PAD_NANDF_CS5__PATA_DA_1 246 -MX51_PAD_NANDF_CS5__SD4_DAT2 247 -MX51_PAD_NANDF_CS5__USBH3_DIR 248 -MX51_PAD_NANDF_CS6__CSPI_SS3 249 -MX51_PAD_NANDF_CS6__FEC_TDATA3 250 -MX51_PAD_NANDF_CS6__GPIO3_22 251 -MX51_PAD_NANDF_CS6__NANDF_CS6 252 -MX51_PAD_NANDF_CS6__PATA_DA_2 253 -MX51_PAD_NANDF_CS6__SD4_DAT3 254 -MX51_PAD_NANDF_CS7__FEC_TX_EN 255 -MX51_PAD_NANDF_CS7__GPIO3_23 256 -MX51_PAD_NANDF_CS7__NANDF_CS7 257 -MX51_PAD_NANDF_CS7__SD3_CLK 258 -MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 259 -MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 260 -MX51_PAD_NANDF_RDY_INT__GPIO3_24 261 -MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 262 -MX51_PAD_NANDF_RDY_INT__SD3_CMD 263 -MX51_PAD_NANDF_D15__ECSPI2_MOSI 264 -MX51_PAD_NANDF_D15__GPIO3_25 265 -MX51_PAD_NANDF_D15__NANDF_D15 266 -MX51_PAD_NANDF_D15__PATA_DATA15 267 -MX51_PAD_NANDF_D15__SD3_DAT7 268 -MX51_PAD_NANDF_D14__ECSPI2_SS3 269 -MX51_PAD_NANDF_D14__GPIO3_26 270 -MX51_PAD_NANDF_D14__NANDF_D14 271 -MX51_PAD_NANDF_D14__PATA_DATA14 272 -MX51_PAD_NANDF_D14__SD3_DAT6 273 -MX51_PAD_NANDF_D13__ECSPI2_SS2 274 -MX51_PAD_NANDF_D13__GPIO3_27 275 -MX51_PAD_NANDF_D13__NANDF_D13 276 -MX51_PAD_NANDF_D13__PATA_DATA13 277 -MX51_PAD_NANDF_D13__SD3_DAT5 278 -MX51_PAD_NANDF_D12__ECSPI2_SS1 279 -MX51_PAD_NANDF_D12__GPIO3_28 280 -MX51_PAD_NANDF_D12__NANDF_D12 281 -MX51_PAD_NANDF_D12__PATA_DATA12 282 -MX51_PAD_NANDF_D12__SD3_DAT4 283 -MX51_PAD_NANDF_D11__FEC_RX_DV 284 -MX51_PAD_NANDF_D11__GPIO3_29 285 -MX51_PAD_NANDF_D11__NANDF_D11 286 -MX51_PAD_NANDF_D11__PATA_DATA11 287 -MX51_PAD_NANDF_D11__SD3_DATA3 288 -MX51_PAD_NANDF_D10__GPIO3_30 289 -MX51_PAD_NANDF_D10__NANDF_D10 290 -MX51_PAD_NANDF_D10__PATA_DATA10 291 -MX51_PAD_NANDF_D10__SD3_DATA2 292 -MX51_PAD_NANDF_D9__FEC_RDATA0 293 -MX51_PAD_NANDF_D9__GPIO3_31 294 -MX51_PAD_NANDF_D9__NANDF_D9 295 -MX51_PAD_NANDF_D9__PATA_DATA9 296 -MX51_PAD_NANDF_D9__SD3_DATA1 297 -MX51_PAD_NANDF_D8__FEC_TDATA0 298 -MX51_PAD_NANDF_D8__GPIO4_0 299 -MX51_PAD_NANDF_D8__NANDF_D8 300 -MX51_PAD_NANDF_D8__PATA_DATA8 301 -MX51_PAD_NANDF_D8__SD3_DATA0 302 -MX51_PAD_NANDF_D7__GPIO4_1 303 -MX51_PAD_NANDF_D7__NANDF_D7 304 -MX51_PAD_NANDF_D7__PATA_DATA7 305 -MX51_PAD_NANDF_D7__USBH3_DATA0 306 -MX51_PAD_NANDF_D6__GPIO4_2 307 -MX51_PAD_NANDF_D6__NANDF_D6 308 -MX51_PAD_NANDF_D6__PATA_DATA6 309 -MX51_PAD_NANDF_D6__SD4_LCTL 310 -MX51_PAD_NANDF_D6__USBH3_DATA1 311 -MX51_PAD_NANDF_D5__GPIO4_3 312 -MX51_PAD_NANDF_D5__NANDF_D5 313 -MX51_PAD_NANDF_D5__PATA_DATA5 314 -MX51_PAD_NANDF_D5__SD4_WP 315 -MX51_PAD_NANDF_D5__USBH3_DATA2 316 -MX51_PAD_NANDF_D4__GPIO4_4 317 -MX51_PAD_NANDF_D4__NANDF_D4 318 -MX51_PAD_NANDF_D4__PATA_DATA4 319 -MX51_PAD_NANDF_D4__SD4_CD 320 -MX51_PAD_NANDF_D4__USBH3_DATA3 321 -MX51_PAD_NANDF_D3__GPIO4_5 322 -MX51_PAD_NANDF_D3__NANDF_D3 323 -MX51_PAD_NANDF_D3__PATA_DATA3 324 -MX51_PAD_NANDF_D3__SD4_DAT4 325 -MX51_PAD_NANDF_D3__USBH3_DATA4 326 -MX51_PAD_NANDF_D2__GPIO4_6 327 -MX51_PAD_NANDF_D2__NANDF_D2 328 -MX51_PAD_NANDF_D2__PATA_DATA2 329 -MX51_PAD_NANDF_D2__SD4_DAT5 330 -MX51_PAD_NANDF_D2__USBH3_DATA5 331 -MX51_PAD_NANDF_D1__GPIO4_7 332 -MX51_PAD_NANDF_D1__NANDF_D1 333 -MX51_PAD_NANDF_D1__PATA_DATA1 334 -MX51_PAD_NANDF_D1__SD4_DAT6 335 -MX51_PAD_NANDF_D1__USBH3_DATA6 336 -MX51_PAD_NANDF_D0__GPIO4_8 337 -MX51_PAD_NANDF_D0__NANDF_D0 338 -MX51_PAD_NANDF_D0__PATA_DATA0 339 -MX51_PAD_NANDF_D0__SD4_DAT7 340 -MX51_PAD_NANDF_D0__USBH3_DATA7 341 -MX51_PAD_CSI1_D8__CSI1_D8 342 -MX51_PAD_CSI1_D8__GPIO3_12 343 -MX51_PAD_CSI1_D9__CSI1_D9 344 -MX51_PAD_CSI1_D9__GPIO3_13 345 -MX51_PAD_CSI1_D10__CSI1_D10 346 -MX51_PAD_CSI1_D11__CSI1_D11 347 -MX51_PAD_CSI1_D12__CSI1_D12 348 -MX51_PAD_CSI1_D13__CSI1_D13 349 -MX51_PAD_CSI1_D14__CSI1_D14 350 -MX51_PAD_CSI1_D15__CSI1_D15 351 -MX51_PAD_CSI1_D16__CSI1_D16 352 -MX51_PAD_CSI1_D17__CSI1_D17 353 -MX51_PAD_CSI1_D18__CSI1_D18 354 -MX51_PAD_CSI1_D19__CSI1_D19 355 -MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 356 -MX51_PAD_CSI1_VSYNC__GPIO3_14 357 -MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 358 -MX51_PAD_CSI1_HSYNC__GPIO3_15 359 -MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 360 -MX51_PAD_CSI1_MCLK__CSI1_MCLK 361 -MX51_PAD_CSI2_D12__CSI2_D12 362 -MX51_PAD_CSI2_D12__GPIO4_9 363 -MX51_PAD_CSI2_D13__CSI2_D13 364 -MX51_PAD_CSI2_D13__GPIO4_10 365 -MX51_PAD_CSI2_D14__CSI2_D14 366 -MX51_PAD_CSI2_D15__CSI2_D15 367 -MX51_PAD_CSI2_D16__CSI2_D16 368 -MX51_PAD_CSI2_D17__CSI2_D17 369 -MX51_PAD_CSI2_D18__CSI2_D18 370 -MX51_PAD_CSI2_D18__GPIO4_11 371 -MX51_PAD_CSI2_D19__CSI2_D19 372 -MX51_PAD_CSI2_D19__GPIO4_12 373 -MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 374 -MX51_PAD_CSI2_VSYNC__GPIO4_13 375 -MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 376 -MX51_PAD_CSI2_HSYNC__GPIO4_14 377 -MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 378 -MX51_PAD_CSI2_PIXCLK__GPIO4_15 379 -MX51_PAD_I2C1_CLK__GPIO4_16 380 -MX51_PAD_I2C1_CLK__I2C1_CLK 381 -MX51_PAD_I2C1_DAT__GPIO4_17 382 -MX51_PAD_I2C1_DAT__I2C1_DAT 383 -MX51_PAD_AUD3_BB_TXD__AUD3_TXD 384 -MX51_PAD_AUD3_BB_TXD__GPIO4_18 385 -MX51_PAD_AUD3_BB_RXD__AUD3_RXD 386 -MX51_PAD_AUD3_BB_RXD__GPIO4_19 387 -MX51_PAD_AUD3_BB_RXD__UART3_RXD 388 -MX51_PAD_AUD3_BB_CK__AUD3_TXC 389 -MX51_PAD_AUD3_BB_CK__GPIO4_20 390 -MX51_PAD_AUD3_BB_FS__AUD3_TXFS 391 -MX51_PAD_AUD3_BB_FS__GPIO4_21 392 -MX51_PAD_AUD3_BB_FS__UART3_TXD 393 -MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 394 -MX51_PAD_CSPI1_MOSI__GPIO4_22 395 -MX51_PAD_CSPI1_MOSI__I2C1_SDA 396 -MX51_PAD_CSPI1_MISO__AUD4_RXD 397 -MX51_PAD_CSPI1_MISO__ECSPI1_MISO 398 -MX51_PAD_CSPI1_MISO__GPIO4_23 399 -MX51_PAD_CSPI1_SS0__AUD4_TXC 400 -MX51_PAD_CSPI1_SS0__ECSPI1_SS0 401 -MX51_PAD_CSPI1_SS0__GPIO4_24 402 -MX51_PAD_CSPI1_SS1__AUD4_TXD 403 -MX51_PAD_CSPI1_SS1__ECSPI1_SS1 404 -MX51_PAD_CSPI1_SS1__GPIO4_25 405 -MX51_PAD_CSPI1_RDY__AUD4_TXFS 406 -MX51_PAD_CSPI1_RDY__ECSPI1_RDY 407 -MX51_PAD_CSPI1_RDY__GPIO4_26 408 -MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 409 -MX51_PAD_CSPI1_SCLK__GPIO4_27 410 -MX51_PAD_CSPI1_SCLK__I2C1_SCL 411 -MX51_PAD_UART1_RXD__GPIO4_28 412 -MX51_PAD_UART1_RXD__UART1_RXD 413 -MX51_PAD_UART1_TXD__GPIO4_29 414 -MX51_PAD_UART1_TXD__PWM2_PWMO 415 -MX51_PAD_UART1_TXD__UART1_TXD 416 -MX51_PAD_UART1_RTS__GPIO4_30 417 -MX51_PAD_UART1_RTS__UART1_RTS 418 -MX51_PAD_UART1_CTS__GPIO4_31 419 -MX51_PAD_UART1_CTS__UART1_CTS 420 -MX51_PAD_UART2_RXD__FIRI_TXD 421 -MX51_PAD_UART2_RXD__GPIO1_20 422 -MX51_PAD_UART2_RXD__UART2_RXD 423 -MX51_PAD_UART2_TXD__FIRI_RXD 424 -MX51_PAD_UART2_TXD__GPIO1_21 425 -MX51_PAD_UART2_TXD__UART2_TXD 426 -MX51_PAD_UART3_RXD__CSI1_D0 427 -MX51_PAD_UART3_RXD__GPIO1_22 428 -MX51_PAD_UART3_RXD__UART1_DTR 429 -MX51_PAD_UART3_RXD__UART3_RXD 430 -MX51_PAD_UART3_TXD__CSI1_D1 431 -MX51_PAD_UART3_TXD__GPIO1_23 432 -MX51_PAD_UART3_TXD__UART1_DSR 433 -MX51_PAD_UART3_TXD__UART3_TXD 434 -MX51_PAD_OWIRE_LINE__GPIO1_24 435 -MX51_PAD_OWIRE_LINE__OWIRE_LINE 436 -MX51_PAD_OWIRE_LINE__SPDIF_OUT 437 -MX51_PAD_KEY_ROW0__KEY_ROW0 438 -MX51_PAD_KEY_ROW1__KEY_ROW1 439 -MX51_PAD_KEY_ROW2__KEY_ROW2 440 -MX51_PAD_KEY_ROW3__KEY_ROW3 441 -MX51_PAD_KEY_COL0__KEY_COL0 442 -MX51_PAD_KEY_COL0__PLL1_BYP 443 -MX51_PAD_KEY_COL1__KEY_COL1 444 -MX51_PAD_KEY_COL1__PLL2_BYP 445 -MX51_PAD_KEY_COL2__KEY_COL2 446 -MX51_PAD_KEY_COL2__PLL3_BYP 447 -MX51_PAD_KEY_COL3__KEY_COL3 448 -MX51_PAD_KEY_COL4__I2C2_SCL 449 -MX51_PAD_KEY_COL4__KEY_COL4 450 -MX51_PAD_KEY_COL4__SPDIF_OUT1 451 -MX51_PAD_KEY_COL4__UART1_RI 452 -MX51_PAD_KEY_COL4__UART3_RTS 453 -MX51_PAD_KEY_COL5__I2C2_SDA 454 -MX51_PAD_KEY_COL5__KEY_COL5 455 -MX51_PAD_KEY_COL5__UART1_DCD 456 -MX51_PAD_KEY_COL5__UART3_CTS 457 -MX51_PAD_USBH1_CLK__CSPI_SCLK 458 -MX51_PAD_USBH1_CLK__GPIO1_25 459 -MX51_PAD_USBH1_CLK__I2C2_SCL 460 -MX51_PAD_USBH1_CLK__USBH1_CLK 461 -MX51_PAD_USBH1_DIR__CSPI_MOSI 462 -MX51_PAD_USBH1_DIR__GPIO1_26 463 -MX51_PAD_USBH1_DIR__I2C2_SDA 464 -MX51_PAD_USBH1_DIR__USBH1_DIR 465 -MX51_PAD_USBH1_STP__CSPI_RDY 466 -MX51_PAD_USBH1_STP__GPIO1_27 467 -MX51_PAD_USBH1_STP__UART3_RXD 468 -MX51_PAD_USBH1_STP__USBH1_STP 469 -MX51_PAD_USBH1_NXT__CSPI_MISO 470 -MX51_PAD_USBH1_NXT__GPIO1_28 471 -MX51_PAD_USBH1_NXT__UART3_TXD 472 -MX51_PAD_USBH1_NXT__USBH1_NXT 473 -MX51_PAD_USBH1_DATA0__GPIO1_11 474 -MX51_PAD_USBH1_DATA0__UART2_CTS 475 -MX51_PAD_USBH1_DATA0__USBH1_DATA0 476 -MX51_PAD_USBH1_DATA1__GPIO1_12 477 -MX51_PAD_USBH1_DATA1__UART2_RXD 478 -MX51_PAD_USBH1_DATA1__USBH1_DATA1 479 -MX51_PAD_USBH1_DATA2__GPIO1_13 480 -MX51_PAD_USBH1_DATA2__UART2_TXD 481 -MX51_PAD_USBH1_DATA2__USBH1_DATA2 482 -MX51_PAD_USBH1_DATA3__GPIO1_14 483 -MX51_PAD_USBH1_DATA3__UART2_RTS 484 -MX51_PAD_USBH1_DATA3__USBH1_DATA3 485 -MX51_PAD_USBH1_DATA4__CSPI_SS0 486 -MX51_PAD_USBH1_DATA4__GPIO1_15 487 -MX51_PAD_USBH1_DATA4__USBH1_DATA4 488 -MX51_PAD_USBH1_DATA5__CSPI_SS1 489 -MX51_PAD_USBH1_DATA5__GPIO1_16 490 -MX51_PAD_USBH1_DATA5__USBH1_DATA5 491 -MX51_PAD_USBH1_DATA6__CSPI_SS3 492 -MX51_PAD_USBH1_DATA6__GPIO1_17 493 -MX51_PAD_USBH1_DATA6__USBH1_DATA6 494 -MX51_PAD_USBH1_DATA7__ECSPI1_SS3 495 -MX51_PAD_USBH1_DATA7__ECSPI2_SS3 496 -MX51_PAD_USBH1_DATA7__GPIO1_18 497 -MX51_PAD_USBH1_DATA7__USBH1_DATA7 498 -MX51_PAD_DI1_PIN11__DI1_PIN11 499 -MX51_PAD_DI1_PIN11__ECSPI1_SS2 500 -MX51_PAD_DI1_PIN11__GPIO3_0 501 -MX51_PAD_DI1_PIN12__DI1_PIN12 502 -MX51_PAD_DI1_PIN12__GPIO3_1 503 -MX51_PAD_DI1_PIN13__DI1_PIN13 504 -MX51_PAD_DI1_PIN13__GPIO3_2 505 -MX51_PAD_DI1_D0_CS__DI1_D0_CS 506 -MX51_PAD_DI1_D0_CS__GPIO3_3 507 -MX51_PAD_DI1_D1_CS__DI1_D1_CS 508 -MX51_PAD_DI1_D1_CS__DISP1_PIN14 509 -MX51_PAD_DI1_D1_CS__DISP1_PIN5 510 -MX51_PAD_DI1_D1_CS__GPIO3_4 511 -MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 512 -MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 513 -MX51_PAD_DISPB2_SER_DIN__GPIO3_5 514 -MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 515 -MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 516 -MX51_PAD_DISPB2_SER_DIO__GPIO3_6 517 -MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 518 -MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 519 -MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 520 -MX51_PAD_DISPB2_SER_CLK__GPIO3_7 521 -MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 522 -MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 523 -MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 524 -MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 525 -MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 526 -MX51_PAD_DISPB2_SER_RS__GPIO3_8 527 -MX51_PAD_DISP1_DAT0__DISP1_DAT0 528 -MX51_PAD_DISP1_DAT1__DISP1_DAT1 529 -MX51_PAD_DISP1_DAT2__DISP1_DAT2 530 -MX51_PAD_DISP1_DAT3__DISP1_DAT3 531 -MX51_PAD_DISP1_DAT4__DISP1_DAT4 532 -MX51_PAD_DISP1_DAT5__DISP1_DAT5 533 -MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 534 -MX51_PAD_DISP1_DAT6__DISP1_DAT6 535 -MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 536 -MX51_PAD_DISP1_DAT7__DISP1_DAT7 537 -MX51_PAD_DISP1_DAT8__BOOT_SRC0 538 -MX51_PAD_DISP1_DAT8__DISP1_DAT8 539 -MX51_PAD_DISP1_DAT9__BOOT_SRC1 540 -MX51_PAD_DISP1_DAT9__DISP1_DAT9 541 -MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 542 -MX51_PAD_DISP1_DAT10__DISP1_DAT10 543 -MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 544 -MX51_PAD_DISP1_DAT11__DISP1_DAT11 545 -MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 546 -MX51_PAD_DISP1_DAT12__DISP1_DAT12 547 -MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 548 -MX51_PAD_DISP1_DAT13__DISP1_DAT13 549 -MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 550 -MX51_PAD_DISP1_DAT14__DISP1_DAT14 551 -MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 552 -MX51_PAD_DISP1_DAT15__DISP1_DAT15 553 -MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 554 -MX51_PAD_DISP1_DAT16__DISP1_DAT16 555 -MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 556 -MX51_PAD_DISP1_DAT17__DISP1_DAT17 557 -MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 558 -MX51_PAD_DISP1_DAT18__DISP1_DAT18 559 -MX51_PAD_DISP1_DAT18__DISP2_PIN11 560 -MX51_PAD_DISP1_DAT18__DISP2_PIN5 561 -MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 562 -MX51_PAD_DISP1_DAT19__DISP1_DAT19 563 -MX51_PAD_DISP1_DAT19__DISP2_PIN12 564 -MX51_PAD_DISP1_DAT19__DISP2_PIN6 565 -MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 566 -MX51_PAD_DISP1_DAT20__DISP1_DAT20 567 -MX51_PAD_DISP1_DAT20__DISP2_PIN13 568 -MX51_PAD_DISP1_DAT20__DISP2_PIN7 569 -MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 570 -MX51_PAD_DISP1_DAT21__DISP1_DAT21 571 -MX51_PAD_DISP1_DAT21__DISP2_PIN14 572 -MX51_PAD_DISP1_DAT21__DISP2_PIN8 573 -MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 574 -MX51_PAD_DISP1_DAT22__DISP1_DAT22 575 -MX51_PAD_DISP1_DAT22__DISP2_D0_CS 576 -MX51_PAD_DISP1_DAT22__DISP2_DAT16 577 -MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 578 -MX51_PAD_DISP1_DAT23__DISP1_DAT23 579 -MX51_PAD_DISP1_DAT23__DISP2_D1_CS 580 -MX51_PAD_DISP1_DAT23__DISP2_DAT17 581 -MX51_PAD_DISP1_DAT23__DISP2_SER_CS 582 -MX51_PAD_DI1_PIN3__DI1_PIN3 583 -MX51_PAD_DI1_PIN2__DI1_PIN2 584 -MX51_PAD_DI_GP2__DISP1_SER_CLK 585 -MX51_PAD_DI_GP2__DISP2_WAIT 586 -MX51_PAD_DI_GP3__CSI1_DATA_EN 587 -MX51_PAD_DI_GP3__DISP1_SER_DIO 588 -MX51_PAD_DI_GP3__FEC_TX_ER 589 -MX51_PAD_DI2_PIN4__CSI2_DATA_EN 590 -MX51_PAD_DI2_PIN4__DI2_PIN4 591 -MX51_PAD_DI2_PIN4__FEC_CRS 592 -MX51_PAD_DI2_PIN2__DI2_PIN2 593 -MX51_PAD_DI2_PIN2__FEC_MDC 594 -MX51_PAD_DI2_PIN3__DI2_PIN3 595 -MX51_PAD_DI2_PIN3__FEC_MDIO 596 -MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 597 -MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 598 -MX51_PAD_DI_GP4__DI2_PIN15 599 -MX51_PAD_DI_GP4__DISP1_SER_DIN 600 -MX51_PAD_DI_GP4__DISP2_PIN1 601 -MX51_PAD_DI_GP4__FEC_RDATA2 602 -MX51_PAD_DISP2_DAT0__DISP2_DAT0 603 -MX51_PAD_DISP2_DAT0__FEC_RDATA3 604 -MX51_PAD_DISP2_DAT0__KEY_COL6 605 -MX51_PAD_DISP2_DAT0__UART3_RXD 606 -MX51_PAD_DISP2_DAT0__USBH3_CLK 607 -MX51_PAD_DISP2_DAT1__DISP2_DAT1 608 -MX51_PAD_DISP2_DAT1__FEC_RX_ER 609 -MX51_PAD_DISP2_DAT1__KEY_COL7 610 -MX51_PAD_DISP2_DAT1__UART3_TXD 611 -MX51_PAD_DISP2_DAT1__USBH3_DIR 612 -MX51_PAD_DISP2_DAT2__DISP2_DAT2 613 -MX51_PAD_DISP2_DAT3__DISP2_DAT3 614 -MX51_PAD_DISP2_DAT4__DISP2_DAT4 615 -MX51_PAD_DISP2_DAT5__DISP2_DAT5 616 -MX51_PAD_DISP2_DAT6__DISP2_DAT6 617 -MX51_PAD_DISP2_DAT6__FEC_TDATA1 618 -MX51_PAD_DISP2_DAT6__GPIO1_19 619 -MX51_PAD_DISP2_DAT6__KEY_ROW4 620 -MX51_PAD_DISP2_DAT6__USBH3_STP 621 -MX51_PAD_DISP2_DAT7__DISP2_DAT7 622 -MX51_PAD_DISP2_DAT7__FEC_TDATA2 623 -MX51_PAD_DISP2_DAT7__GPIO1_29 624 -MX51_PAD_DISP2_DAT7__KEY_ROW5 625 -MX51_PAD_DISP2_DAT7__USBH3_NXT 626 -MX51_PAD_DISP2_DAT8__DISP2_DAT8 627 -MX51_PAD_DISP2_DAT8__FEC_TDATA3 628 -MX51_PAD_DISP2_DAT8__GPIO1_30 629 -MX51_PAD_DISP2_DAT8__KEY_ROW6 630 -MX51_PAD_DISP2_DAT8__USBH3_DATA0 631 -MX51_PAD_DISP2_DAT9__AUD6_RXC 632 -MX51_PAD_DISP2_DAT9__DISP2_DAT9 633 -MX51_PAD_DISP2_DAT9__FEC_TX_EN 634 -MX51_PAD_DISP2_DAT9__GPIO1_31 635 -MX51_PAD_DISP2_DAT9__USBH3_DATA1 636 -MX51_PAD_DISP2_DAT10__DISP2_DAT10 637 -MX51_PAD_DISP2_DAT10__DISP2_SER_CS 638 -MX51_PAD_DISP2_DAT10__FEC_COL 639 -MX51_PAD_DISP2_DAT10__KEY_ROW7 640 -MX51_PAD_DISP2_DAT10__USBH3_DATA2 641 -MX51_PAD_DISP2_DAT11__AUD6_TXD 642 -MX51_PAD_DISP2_DAT11__DISP2_DAT11 643 -MX51_PAD_DISP2_DAT11__FEC_RX_CLK 644 -MX51_PAD_DISP2_DAT11__GPIO1_10 645 -MX51_PAD_DISP2_DAT11__USBH3_DATA3 646 -MX51_PAD_DISP2_DAT12__AUD6_RXD 647 -MX51_PAD_DISP2_DAT12__DISP2_DAT12 648 -MX51_PAD_DISP2_DAT12__FEC_RX_DV 649 -MX51_PAD_DISP2_DAT12__USBH3_DATA4 650 -MX51_PAD_DISP2_DAT13__AUD6_TXC 651 -MX51_PAD_DISP2_DAT13__DISP2_DAT13 652 -MX51_PAD_DISP2_DAT13__FEC_TX_CLK 653 -MX51_PAD_DISP2_DAT13__USBH3_DATA5 654 -MX51_PAD_DISP2_DAT14__AUD6_TXFS 655 -MX51_PAD_DISP2_DAT14__DISP2_DAT14 656 -MX51_PAD_DISP2_DAT14__FEC_RDATA0 657 -MX51_PAD_DISP2_DAT14__USBH3_DATA6 658 -MX51_PAD_DISP2_DAT15__AUD6_RXFS 659 -MX51_PAD_DISP2_DAT15__DISP1_SER_CS 660 -MX51_PAD_DISP2_DAT15__DISP2_DAT15 661 -MX51_PAD_DISP2_DAT15__FEC_TDATA0 662 -MX51_PAD_DISP2_DAT15__USBH3_DATA7 663 -MX51_PAD_SD1_CMD__AUD5_RXFS 664 -MX51_PAD_SD1_CMD__CSPI_MOSI 665 -MX51_PAD_SD1_CMD__SD1_CMD 666 -MX51_PAD_SD1_CLK__AUD5_RXC 667 -MX51_PAD_SD1_CLK__CSPI_SCLK 668 -MX51_PAD_SD1_CLK__SD1_CLK 669 -MX51_PAD_SD1_DATA0__AUD5_TXD 670 -MX51_PAD_SD1_DATA0__CSPI_MISO 671 -MX51_PAD_SD1_DATA0__SD1_DATA0 672 -MX51_PAD_EIM_DA0__EIM_DA0 673 -MX51_PAD_EIM_DA1__EIM_DA1 674 -MX51_PAD_EIM_DA2__EIM_DA2 675 -MX51_PAD_EIM_DA3__EIM_DA3 676 -MX51_PAD_SD1_DATA1__AUD5_RXD 677 -MX51_PAD_SD1_DATA1__SD1_DATA1 678 -MX51_PAD_EIM_DA4__EIM_DA4 679 -MX51_PAD_EIM_DA5__EIM_DA5 680 -MX51_PAD_EIM_DA6__EIM_DA6 681 -MX51_PAD_EIM_DA7__EIM_DA7 682 -MX51_PAD_SD1_DATA2__AUD5_TXC 683 -MX51_PAD_SD1_DATA2__SD1_DATA2 684 -MX51_PAD_EIM_DA10__EIM_DA10 685 -MX51_PAD_EIM_DA11__EIM_DA11 686 -MX51_PAD_EIM_DA8__EIM_DA8 687 -MX51_PAD_EIM_DA9__EIM_DA9 688 -MX51_PAD_SD1_DATA3__AUD5_TXFS 689 -MX51_PAD_SD1_DATA3__CSPI_SS1 690 -MX51_PAD_SD1_DATA3__SD1_DATA3 691 -MX51_PAD_GPIO1_0__CSPI_SS2 692 -MX51_PAD_GPIO1_0__GPIO1_0 693 -MX51_PAD_GPIO1_0__SD1_CD 694 -MX51_PAD_GPIO1_1__CSPI_MISO 695 -MX51_PAD_GPIO1_1__GPIO1_1 696 -MX51_PAD_GPIO1_1__SD1_WP 697 -MX51_PAD_EIM_DA12__EIM_DA12 698 -MX51_PAD_EIM_DA13__EIM_DA13 699 -MX51_PAD_EIM_DA14__EIM_DA14 700 -MX51_PAD_EIM_DA15__EIM_DA15 701 -MX51_PAD_SD2_CMD__CSPI_MOSI 702 -MX51_PAD_SD2_CMD__I2C1_SCL 703 -MX51_PAD_SD2_CMD__SD2_CMD 704 -MX51_PAD_SD2_CLK__CSPI_SCLK 705 -MX51_PAD_SD2_CLK__I2C1_SDA 706 -MX51_PAD_SD2_CLK__SD2_CLK 707 -MX51_PAD_SD2_DATA0__CSPI_MISO 708 -MX51_PAD_SD2_DATA0__SD1_DAT4 709 -MX51_PAD_SD2_DATA0__SD2_DATA0 710 -MX51_PAD_SD2_DATA1__SD1_DAT5 711 -MX51_PAD_SD2_DATA1__SD2_DATA1 712 -MX51_PAD_SD2_DATA1__USBH3_H2_DP 713 -MX51_PAD_SD2_DATA2__SD1_DAT6 714 -MX51_PAD_SD2_DATA2__SD2_DATA2 715 -MX51_PAD_SD2_DATA2__USBH3_H2_DM 716 -MX51_PAD_SD2_DATA3__CSPI_SS2 717 -MX51_PAD_SD2_DATA3__SD1_DAT7 718 -MX51_PAD_SD2_DATA3__SD2_DATA3 719 -MX51_PAD_GPIO1_2__CCM_OUT_2 720 -MX51_PAD_GPIO1_2__GPIO1_2 721 -MX51_PAD_GPIO1_2__I2C2_SCL 722 -MX51_PAD_GPIO1_2__PLL1_BYP 723 -MX51_PAD_GPIO1_2__PWM1_PWMO 724 -MX51_PAD_GPIO1_3__GPIO1_3 725 -MX51_PAD_GPIO1_3__I2C2_SDA 726 -MX51_PAD_GPIO1_3__PLL2_BYP 727 -MX51_PAD_GPIO1_3__PWM2_PWMO 728 -MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 729 -MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 730 -MX51_PAD_GPIO1_4__DISP2_EXT_CLK 731 -MX51_PAD_GPIO1_4__EIM_RDY 732 -MX51_PAD_GPIO1_4__GPIO1_4 733 -MX51_PAD_GPIO1_4__WDOG1_WDOG_B 734 -MX51_PAD_GPIO1_5__CSI2_MCLK 735 -MX51_PAD_GPIO1_5__DISP2_PIN16 736 -MX51_PAD_GPIO1_5__GPIO1_5 737 -MX51_PAD_GPIO1_5__WDOG2_WDOG_B 738 -MX51_PAD_GPIO1_6__DISP2_PIN17 739 -MX51_PAD_GPIO1_6__GPIO1_6 740 -MX51_PAD_GPIO1_6__REF_EN_B 741 -MX51_PAD_GPIO1_7__CCM_OUT_0 742 -MX51_PAD_GPIO1_7__GPIO1_7 743 -MX51_PAD_GPIO1_7__SD2_WP 744 -MX51_PAD_GPIO1_7__SPDIF_OUT1 745 -MX51_PAD_GPIO1_8__CSI2_DATA_EN 746 -MX51_PAD_GPIO1_8__GPIO1_8 747 -MX51_PAD_GPIO1_8__SD2_CD 748 -MX51_PAD_GPIO1_8__USBH3_PWR 749 -MX51_PAD_GPIO1_9__CCM_OUT_1 750 -MX51_PAD_GPIO1_9__DISP2_D1_CS 751 -MX51_PAD_GPIO1_9__DISP2_SER_CS 752 -MX51_PAD_GPIO1_9__GPIO1_9 753 -MX51_PAD_GPIO1_9__SD2_LCTL 754 -MX51_PAD_GPIO1_9__USBH3_OC 755 +Refer to imx51-pinfunc.h in device tree source folder for all available +imx51 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt index ca85ca432ef..25dcb77cfaf 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt @@ -28,1175 +28,5 @@ PAD_CTL_DSE_MAX (3 << 1) PAD_CTL_SRE_FAST (1 << 0) PAD_CTL_SRE_SLOW (0 << 0) -See below for available PIN_FUNC_ID for imx53: -MX53_PAD_GPIO_19__KPP_COL_5 0 -MX53_PAD_GPIO_19__GPIO4_5 1 -MX53_PAD_GPIO_19__CCM_CLKO 2 -MX53_PAD_GPIO_19__SPDIF_OUT1 3 -MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 4 -MX53_PAD_GPIO_19__ECSPI1_RDY 5 -MX53_PAD_GPIO_19__FEC_TDATA_3 6 -MX53_PAD_GPIO_19__SRC_INT_BOOT 7 -MX53_PAD_KEY_COL0__KPP_COL_0 8 -MX53_PAD_KEY_COL0__GPIO4_6 9 -MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 10 -MX53_PAD_KEY_COL0__UART4_TXD_MUX 11 -MX53_PAD_KEY_COL0__ECSPI1_SCLK 12 -MX53_PAD_KEY_COL0__FEC_RDATA_3 13 -MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 14 -MX53_PAD_KEY_ROW0__KPP_ROW_0 15 -MX53_PAD_KEY_ROW0__GPIO4_7 16 -MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 17 -MX53_PAD_KEY_ROW0__UART4_RXD_MUX 18 -MX53_PAD_KEY_ROW0__ECSPI1_MOSI 19 -MX53_PAD_KEY_ROW0__FEC_TX_ER 20 -MX53_PAD_KEY_COL1__KPP_COL_1 21 -MX53_PAD_KEY_COL1__GPIO4_8 22 -MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 23 -MX53_PAD_KEY_COL1__UART5_TXD_MUX 24 -MX53_PAD_KEY_COL1__ECSPI1_MISO 25 -MX53_PAD_KEY_COL1__FEC_RX_CLK 26 -MX53_PAD_KEY_COL1__USBPHY1_TXREADY 27 -MX53_PAD_KEY_ROW1__KPP_ROW_1 28 -MX53_PAD_KEY_ROW1__GPIO4_9 29 -MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 30 -MX53_PAD_KEY_ROW1__UART5_RXD_MUX 31 -MX53_PAD_KEY_ROW1__ECSPI1_SS0 32 -MX53_PAD_KEY_ROW1__FEC_COL 33 -MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 34 -MX53_PAD_KEY_COL2__KPP_COL_2 35 -MX53_PAD_KEY_COL2__GPIO4_10 36 -MX53_PAD_KEY_COL2__CAN1_TXCAN 37 -MX53_PAD_KEY_COL2__FEC_MDIO 38 -MX53_PAD_KEY_COL2__ECSPI1_SS1 39 -MX53_PAD_KEY_COL2__FEC_RDATA_2 40 -MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 41 -MX53_PAD_KEY_ROW2__KPP_ROW_2 42 -MX53_PAD_KEY_ROW2__GPIO4_11 43 -MX53_PAD_KEY_ROW2__CAN1_RXCAN 44 -MX53_PAD_KEY_ROW2__FEC_MDC 45 -MX53_PAD_KEY_ROW2__ECSPI1_SS2 46 -MX53_PAD_KEY_ROW2__FEC_TDATA_2 47 -MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 48 -MX53_PAD_KEY_COL3__KPP_COL_3 49 -MX53_PAD_KEY_COL3__GPIO4_12 50 -MX53_PAD_KEY_COL3__USBOH3_H2_DP 51 -MX53_PAD_KEY_COL3__SPDIF_IN1 52 -MX53_PAD_KEY_COL3__I2C2_SCL 53 -MX53_PAD_KEY_COL3__ECSPI1_SS3 54 -MX53_PAD_KEY_COL3__FEC_CRS 55 -MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 56 -MX53_PAD_KEY_ROW3__KPP_ROW_3 57 -MX53_PAD_KEY_ROW3__GPIO4_13 58 -MX53_PAD_KEY_ROW3__USBOH3_H2_DM 59 -MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 60 -MX53_PAD_KEY_ROW3__I2C2_SDA 61 -MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 62 -MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 63 -MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 64 -MX53_PAD_KEY_COL4__KPP_COL_4 65 -MX53_PAD_KEY_COL4__GPIO4_14 66 -MX53_PAD_KEY_COL4__CAN2_TXCAN 67 -MX53_PAD_KEY_COL4__IPU_SISG_4 68 -MX53_PAD_KEY_COL4__UART5_RTS 69 -MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 70 -MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 71 -MX53_PAD_KEY_ROW4__KPP_ROW_4 72 -MX53_PAD_KEY_ROW4__GPIO4_15 73 -MX53_PAD_KEY_ROW4__CAN2_RXCAN 74 -MX53_PAD_KEY_ROW4__IPU_SISG_5 75 -MX53_PAD_KEY_ROW4__UART5_CTS 76 -MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 77 -MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 78 -MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 79 -MX53_PAD_DI0_DISP_CLK__GPIO4_16 80 -MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 81 -MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 82 -MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 83 -MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 84 -MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 85 -MX53_PAD_DI0_PIN15__GPIO4_17 86 -MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 87 -MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 88 -MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 89 -MX53_PAD_DI0_PIN15__USBPHY1_BVALID 90 -MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 91 -MX53_PAD_DI0_PIN2__GPIO4_18 92 -MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 93 -MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 94 -MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 95 -MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 96 -MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 97 -MX53_PAD_DI0_PIN3__GPIO4_19 98 -MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 99 -MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 100 -MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 101 -MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 102 -MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 103 -MX53_PAD_DI0_PIN4__GPIO4_20 104 -MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 105 -MX53_PAD_DI0_PIN4__ESDHC1_WP 106 -MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 107 -MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 108 -MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 109 -MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 110 -MX53_PAD_DISP0_DAT0__GPIO4_21 111 -MX53_PAD_DISP0_DAT0__CSPI_SCLK 112 -MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 113 -MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 114 -MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 115 -MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 116 -MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 117 -MX53_PAD_DISP0_DAT1__GPIO4_22 118 -MX53_PAD_DISP0_DAT1__CSPI_MOSI 119 -MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 120 -MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 121 -MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 122 -MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 123 -MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 124 -MX53_PAD_DISP0_DAT2__GPIO4_23 125 -MX53_PAD_DISP0_DAT2__CSPI_MISO 126 -MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 127 -MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 128 -MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 129 -MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 130 -MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 131 -MX53_PAD_DISP0_DAT3__GPIO4_24 132 -MX53_PAD_DISP0_DAT3__CSPI_SS0 133 -MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 134 -MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 135 -MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 136 -MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 137 -MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 138 -MX53_PAD_DISP0_DAT4__GPIO4_25 139 -MX53_PAD_DISP0_DAT4__CSPI_SS1 140 -MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 141 -MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 142 -MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 143 -MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 144 -MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 145 -MX53_PAD_DISP0_DAT5__GPIO4_26 146 -MX53_PAD_DISP0_DAT5__CSPI_SS2 147 -MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 148 -MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 149 -MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 150 -MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 151 -MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 152 -MX53_PAD_DISP0_DAT6__GPIO4_27 153 -MX53_PAD_DISP0_DAT6__CSPI_SS3 154 -MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 155 -MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 156 -MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 157 -MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 158 -MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 159 -MX53_PAD_DISP0_DAT7__GPIO4_28 160 -MX53_PAD_DISP0_DAT7__CSPI_RDY 161 -MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 162 -MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 163 -MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 164 -MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 165 -MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 166 -MX53_PAD_DISP0_DAT8__GPIO4_29 167 -MX53_PAD_DISP0_DAT8__PWM1_PWMO 168 -MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 169 -MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 170 -MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 171 -MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 172 -MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 173 -MX53_PAD_DISP0_DAT9__GPIO4_30 174 -MX53_PAD_DISP0_DAT9__PWM2_PWMO 175 -MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 176 -MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 177 -MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 178 -MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 179 -MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 180 -MX53_PAD_DISP0_DAT10__GPIO4_31 181 -MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 182 -MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 183 -MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 184 -MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 185 -MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 186 -MX53_PAD_DISP0_DAT11__GPIO5_5 187 -MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 188 -MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 189 -MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 190 -MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 191 -MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 192 -MX53_PAD_DISP0_DAT12__GPIO5_6 193 -MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 194 -MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 195 -MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 196 -MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 197 -MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 198 -MX53_PAD_DISP0_DAT13__GPIO5_7 199 -MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 200 -MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 201 -MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 202 -MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 203 -MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 204 -MX53_PAD_DISP0_DAT14__GPIO5_8 205 -MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 206 -MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 207 -MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 208 -MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 209 -MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 210 -MX53_PAD_DISP0_DAT15__GPIO5_9 211 -MX53_PAD_DISP0_DAT15__ECSPI1_SS1 212 -MX53_PAD_DISP0_DAT15__ECSPI2_SS1 213 -MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 214 -MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 215 -MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 216 -MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 217 -MX53_PAD_DISP0_DAT16__GPIO5_10 218 -MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 219 -MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 220 -MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 221 -MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 222 -MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 223 -MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 224 -MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 225 -MX53_PAD_DISP0_DAT17__GPIO5_11 226 -MX53_PAD_DISP0_DAT17__ECSPI2_MISO 227 -MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 228 -MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 229 -MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 230 -MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 231 -MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 232 -MX53_PAD_DISP0_DAT18__GPIO5_12 233 -MX53_PAD_DISP0_DAT18__ECSPI2_SS0 234 -MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 235 -MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 236 -MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 237 -MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 238 -MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 239 -MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 240 -MX53_PAD_DISP0_DAT19__GPIO5_13 241 -MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 242 -MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 243 -MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 244 -MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 245 -MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 246 -MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 247 -MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 248 -MX53_PAD_DISP0_DAT20__GPIO5_14 249 -MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 250 -MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 251 -MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 252 -MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 253 -MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 254 -MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 255 -MX53_PAD_DISP0_DAT21__GPIO5_15 256 -MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 257 -MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 258 -MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 259 -MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 260 -MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 261 -MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 262 -MX53_PAD_DISP0_DAT22__GPIO5_16 263 -MX53_PAD_DISP0_DAT22__ECSPI1_MISO 264 -MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 265 -MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 266 -MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 267 -MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 268 -MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 269 -MX53_PAD_DISP0_DAT23__GPIO5_17 270 -MX53_PAD_DISP0_DAT23__ECSPI1_SS0 271 -MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 272 -MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 273 -MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 274 -MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 275 -MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 276 -MX53_PAD_CSI0_PIXCLK__GPIO5_18 277 -MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 278 -MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 279 -MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 280 -MX53_PAD_CSI0_MCLK__GPIO5_19 281 -MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 282 -MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 283 -MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 284 -MX53_PAD_CSI0_MCLK__TPIU_TRCTL 285 -MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 286 -MX53_PAD_CSI0_DATA_EN__GPIO5_20 287 -MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 288 -MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 289 -MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 290 -MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 291 -MX53_PAD_CSI0_VSYNC__GPIO5_21 292 -MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 293 -MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 294 -MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 295 -MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 296 -MX53_PAD_CSI0_DAT4__GPIO5_22 297 -MX53_PAD_CSI0_DAT4__KPP_COL_5 298 -MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 299 -MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 300 -MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 301 -MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 302 -MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 303 -MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 304 -MX53_PAD_CSI0_DAT5__GPIO5_23 305 -MX53_PAD_CSI0_DAT5__KPP_ROW_5 306 -MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 307 -MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 308 -MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 309 -MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 310 -MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 311 -MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 312 -MX53_PAD_CSI0_DAT6__GPIO5_24 313 -MX53_PAD_CSI0_DAT6__KPP_COL_6 314 -MX53_PAD_CSI0_DAT6__ECSPI1_MISO 315 -MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 316 -MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 317 -MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 318 -MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 319 -MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 320 -MX53_PAD_CSI0_DAT7__GPIO5_25 321 -MX53_PAD_CSI0_DAT7__KPP_ROW_6 322 -MX53_PAD_CSI0_DAT7__ECSPI1_SS0 323 -MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 324 -MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 325 -MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 326 -MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 327 -MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 328 -MX53_PAD_CSI0_DAT8__GPIO5_26 329 -MX53_PAD_CSI0_DAT8__KPP_COL_7 330 -MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 331 -MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 332 -MX53_PAD_CSI0_DAT8__I2C1_SDA 333 -MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 334 -MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 335 -MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 336 -MX53_PAD_CSI0_DAT9__GPIO5_27 337 -MX53_PAD_CSI0_DAT9__KPP_ROW_7 338 -MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 339 -MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 340 -MX53_PAD_CSI0_DAT9__I2C1_SCL 341 -MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 342 -MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 343 -MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 344 -MX53_PAD_CSI0_DAT10__GPIO5_28 345 -MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 346 -MX53_PAD_CSI0_DAT10__ECSPI2_MISO 347 -MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 348 -MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 349 -MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 350 -MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 351 -MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 352 -MX53_PAD_CSI0_DAT11__GPIO5_29 353 -MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 354 -MX53_PAD_CSI0_DAT11__ECSPI2_SS0 355 -MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 356 -MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 357 -MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 358 -MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 359 -MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 360 -MX53_PAD_CSI0_DAT12__GPIO5_30 361 -MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 362 -MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 363 -MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 364 -MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 365 -MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 366 -MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 367 -MX53_PAD_CSI0_DAT13__GPIO5_31 368 -MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 369 -MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 370 -MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 371 -MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 372 -MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 373 -MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 374 -MX53_PAD_CSI0_DAT14__GPIO6_0 375 -MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 376 -MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 377 -MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 378 -MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 379 -MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 380 -MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 381 -MX53_PAD_CSI0_DAT15__GPIO6_1 382 -MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 383 -MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 384 -MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 385 -MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 386 -MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 387 -MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 388 -MX53_PAD_CSI0_DAT16__GPIO6_2 389 -MX53_PAD_CSI0_DAT16__UART4_RTS 390 -MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 391 -MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 392 -MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 393 -MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 394 -MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 395 -MX53_PAD_CSI0_DAT17__GPIO6_3 396 -MX53_PAD_CSI0_DAT17__UART4_CTS 397 -MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 398 -MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 399 -MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 400 -MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 401 -MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 402 -MX53_PAD_CSI0_DAT18__GPIO6_4 403 -MX53_PAD_CSI0_DAT18__UART5_RTS 404 -MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 405 -MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 406 -MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 407 -MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 408 -MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 409 -MX53_PAD_CSI0_DAT19__GPIO6_5 410 -MX53_PAD_CSI0_DAT19__UART5_CTS 411 -MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 412 -MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 413 -MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 414 -MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 415 -MX53_PAD_EIM_A25__EMI_WEIM_A_25 416 -MX53_PAD_EIM_A25__GPIO5_2 417 -MX53_PAD_EIM_A25__ECSPI2_RDY 418 -MX53_PAD_EIM_A25__IPU_DI1_PIN12 419 -MX53_PAD_EIM_A25__CSPI_SS1 420 -MX53_PAD_EIM_A25__IPU_DI0_D1_CS 421 -MX53_PAD_EIM_A25__USBPHY1_BISTOK 422 -MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 423 -MX53_PAD_EIM_EB2__GPIO2_30 424 -MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 425 -MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 426 -MX53_PAD_EIM_EB2__ECSPI1_SS0 427 -MX53_PAD_EIM_EB2__I2C2_SCL 428 -MX53_PAD_EIM_D16__EMI_WEIM_D_16 429 -MX53_PAD_EIM_D16__GPIO3_16 430 -MX53_PAD_EIM_D16__IPU_DI0_PIN5 431 -MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 432 -MX53_PAD_EIM_D16__ECSPI1_SCLK 433 -MX53_PAD_EIM_D16__I2C2_SDA 434 -MX53_PAD_EIM_D17__EMI_WEIM_D_17 435 -MX53_PAD_EIM_D17__GPIO3_17 436 -MX53_PAD_EIM_D17__IPU_DI0_PIN6 437 -MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 438 -MX53_PAD_EIM_D17__ECSPI1_MISO 439 -MX53_PAD_EIM_D17__I2C3_SCL 440 -MX53_PAD_EIM_D18__EMI_WEIM_D_18 441 -MX53_PAD_EIM_D18__GPIO3_18 442 -MX53_PAD_EIM_D18__IPU_DI0_PIN7 443 -MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 444 -MX53_PAD_EIM_D18__ECSPI1_MOSI 445 -MX53_PAD_EIM_D18__I2C3_SDA 446 -MX53_PAD_EIM_D18__IPU_DI1_D0_CS 447 -MX53_PAD_EIM_D19__EMI_WEIM_D_19 448 -MX53_PAD_EIM_D19__GPIO3_19 449 -MX53_PAD_EIM_D19__IPU_DI0_PIN8 450 -MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 451 -MX53_PAD_EIM_D19__ECSPI1_SS1 452 -MX53_PAD_EIM_D19__EPIT1_EPITO 453 -MX53_PAD_EIM_D19__UART1_CTS 454 -MX53_PAD_EIM_D19__USBOH3_USBH2_OC 455 -MX53_PAD_EIM_D20__EMI_WEIM_D_20 456 -MX53_PAD_EIM_D20__GPIO3_20 457 -MX53_PAD_EIM_D20__IPU_DI0_PIN16 458 -MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 459 -MX53_PAD_EIM_D20__CSPI_SS0 460 -MX53_PAD_EIM_D20__EPIT2_EPITO 461 -MX53_PAD_EIM_D20__UART1_RTS 462 -MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 463 -MX53_PAD_EIM_D21__EMI_WEIM_D_21 464 -MX53_PAD_EIM_D21__GPIO3_21 465 -MX53_PAD_EIM_D21__IPU_DI0_PIN17 466 -MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 467 -MX53_PAD_EIM_D21__CSPI_SCLK 468 -MX53_PAD_EIM_D21__I2C1_SCL 469 -MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 470 -MX53_PAD_EIM_D22__EMI_WEIM_D_22 471 -MX53_PAD_EIM_D22__GPIO3_22 472 -MX53_PAD_EIM_D22__IPU_DI0_PIN1 473 -MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 474 -MX53_PAD_EIM_D22__CSPI_MISO 475 -MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 476 -MX53_PAD_EIM_D23__EMI_WEIM_D_23 477 -MX53_PAD_EIM_D23__GPIO3_23 478 -MX53_PAD_EIM_D23__UART3_CTS 479 -MX53_PAD_EIM_D23__UART1_DCD 480 -MX53_PAD_EIM_D23__IPU_DI0_D0_CS 481 -MX53_PAD_EIM_D23__IPU_DI1_PIN2 482 -MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 483 -MX53_PAD_EIM_D23__IPU_DI1_PIN14 484 -MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 485 -MX53_PAD_EIM_EB3__GPIO2_31 486 -MX53_PAD_EIM_EB3__UART3_RTS 487 -MX53_PAD_EIM_EB3__UART1_RI 488 -MX53_PAD_EIM_EB3__IPU_DI1_PIN3 489 -MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 490 -MX53_PAD_EIM_EB3__IPU_DI1_PIN16 491 -MX53_PAD_EIM_D24__EMI_WEIM_D_24 492 -MX53_PAD_EIM_D24__GPIO3_24 493 -MX53_PAD_EIM_D24__UART3_TXD_MUX 494 -MX53_PAD_EIM_D24__ECSPI1_SS2 495 -MX53_PAD_EIM_D24__CSPI_SS2 496 -MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 497 -MX53_PAD_EIM_D24__ECSPI2_SS2 498 -MX53_PAD_EIM_D24__UART1_DTR 499 -MX53_PAD_EIM_D25__EMI_WEIM_D_25 500 -MX53_PAD_EIM_D25__GPIO3_25 501 -MX53_PAD_EIM_D25__UART3_RXD_MUX 502 -MX53_PAD_EIM_D25__ECSPI1_SS3 503 -MX53_PAD_EIM_D25__CSPI_SS3 504 -MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 505 -MX53_PAD_EIM_D25__ECSPI2_SS3 506 -MX53_PAD_EIM_D25__UART1_DSR 507 -MX53_PAD_EIM_D26__EMI_WEIM_D_26 508 -MX53_PAD_EIM_D26__GPIO3_26 509 -MX53_PAD_EIM_D26__UART2_TXD_MUX 510 -MX53_PAD_EIM_D26__FIRI_RXD 511 -MX53_PAD_EIM_D26__IPU_CSI0_D_1 512 -MX53_PAD_EIM_D26__IPU_DI1_PIN11 513 -MX53_PAD_EIM_D26__IPU_SISG_2 514 -MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 515 -MX53_PAD_EIM_D27__EMI_WEIM_D_27 516 -MX53_PAD_EIM_D27__GPIO3_27 517 -MX53_PAD_EIM_D27__UART2_RXD_MUX 518 -MX53_PAD_EIM_D27__FIRI_TXD 519 -MX53_PAD_EIM_D27__IPU_CSI0_D_0 520 -MX53_PAD_EIM_D27__IPU_DI1_PIN13 521 -MX53_PAD_EIM_D27__IPU_SISG_3 522 -MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 523 -MX53_PAD_EIM_D28__EMI_WEIM_D_28 524 -MX53_PAD_EIM_D28__GPIO3_28 525 -MX53_PAD_EIM_D28__UART2_CTS 526 -MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 527 -MX53_PAD_EIM_D28__CSPI_MOSI 528 -MX53_PAD_EIM_D28__I2C1_SDA 529 -MX53_PAD_EIM_D28__IPU_EXT_TRIG 530 -MX53_PAD_EIM_D28__IPU_DI0_PIN13 531 -MX53_PAD_EIM_D29__EMI_WEIM_D_29 532 -MX53_PAD_EIM_D29__GPIO3_29 533 -MX53_PAD_EIM_D29__UART2_RTS 534 -MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 535 -MX53_PAD_EIM_D29__CSPI_SS0 536 -MX53_PAD_EIM_D29__IPU_DI1_PIN15 537 -MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 538 -MX53_PAD_EIM_D29__IPU_DI0_PIN14 539 -MX53_PAD_EIM_D30__EMI_WEIM_D_30 540 -MX53_PAD_EIM_D30__GPIO3_30 541 -MX53_PAD_EIM_D30__UART3_CTS 542 -MX53_PAD_EIM_D30__IPU_CSI0_D_3 543 -MX53_PAD_EIM_D30__IPU_DI0_PIN11 544 -MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 545 -MX53_PAD_EIM_D30__USBOH3_USBH1_OC 546 -MX53_PAD_EIM_D30__USBOH3_USBH2_OC 547 -MX53_PAD_EIM_D31__EMI_WEIM_D_31 548 -MX53_PAD_EIM_D31__GPIO3_31 549 -MX53_PAD_EIM_D31__UART3_RTS 550 -MX53_PAD_EIM_D31__IPU_CSI0_D_2 551 -MX53_PAD_EIM_D31__IPU_DI0_PIN12 552 -MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 553 -MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 554 -MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 555 -MX53_PAD_EIM_A24__EMI_WEIM_A_24 556 -MX53_PAD_EIM_A24__GPIO5_4 557 -MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 558 -MX53_PAD_EIM_A24__IPU_CSI1_D_19 559 -MX53_PAD_EIM_A24__IPU_SISG_2 560 -MX53_PAD_EIM_A24__USBPHY2_BVALID 561 -MX53_PAD_EIM_A23__EMI_WEIM_A_23 562 -MX53_PAD_EIM_A23__GPIO6_6 563 -MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 564 -MX53_PAD_EIM_A23__IPU_CSI1_D_18 565 -MX53_PAD_EIM_A23__IPU_SISG_3 566 -MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 567 -MX53_PAD_EIM_A22__EMI_WEIM_A_22 568 -MX53_PAD_EIM_A22__GPIO2_16 569 -MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 570 -MX53_PAD_EIM_A22__IPU_CSI1_D_17 571 -MX53_PAD_EIM_A22__SRC_BT_CFG1_7 572 -MX53_PAD_EIM_A21__EMI_WEIM_A_21 573 -MX53_PAD_EIM_A21__GPIO2_17 574 -MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 575 -MX53_PAD_EIM_A21__IPU_CSI1_D_16 576 -MX53_PAD_EIM_A21__SRC_BT_CFG1_6 577 -MX53_PAD_EIM_A20__EMI_WEIM_A_20 578 -MX53_PAD_EIM_A20__GPIO2_18 579 -MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 580 -MX53_PAD_EIM_A20__IPU_CSI1_D_15 581 -MX53_PAD_EIM_A20__SRC_BT_CFG1_5 582 -MX53_PAD_EIM_A19__EMI_WEIM_A_19 583 -MX53_PAD_EIM_A19__GPIO2_19 584 -MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 585 -MX53_PAD_EIM_A19__IPU_CSI1_D_14 586 -MX53_PAD_EIM_A19__SRC_BT_CFG1_4 587 -MX53_PAD_EIM_A18__EMI_WEIM_A_18 588 -MX53_PAD_EIM_A18__GPIO2_20 589 -MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 590 -MX53_PAD_EIM_A18__IPU_CSI1_D_13 591 -MX53_PAD_EIM_A18__SRC_BT_CFG1_3 592 -MX53_PAD_EIM_A17__EMI_WEIM_A_17 593 -MX53_PAD_EIM_A17__GPIO2_21 594 -MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 595 -MX53_PAD_EIM_A17__IPU_CSI1_D_12 596 -MX53_PAD_EIM_A17__SRC_BT_CFG1_2 597 -MX53_PAD_EIM_A16__EMI_WEIM_A_16 598 -MX53_PAD_EIM_A16__GPIO2_22 599 -MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 600 -MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 601 -MX53_PAD_EIM_A16__SRC_BT_CFG1_1 602 -MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 603 -MX53_PAD_EIM_CS0__GPIO2_23 604 -MX53_PAD_EIM_CS0__ECSPI2_SCLK 605 -MX53_PAD_EIM_CS0__IPU_DI1_PIN5 606 -MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 607 -MX53_PAD_EIM_CS1__GPIO2_24 608 -MX53_PAD_EIM_CS1__ECSPI2_MOSI 609 -MX53_PAD_EIM_CS1__IPU_DI1_PIN6 610 -MX53_PAD_EIM_OE__EMI_WEIM_OE 611 -MX53_PAD_EIM_OE__GPIO2_25 612 -MX53_PAD_EIM_OE__ECSPI2_MISO 613 -MX53_PAD_EIM_OE__IPU_DI1_PIN7 614 -MX53_PAD_EIM_OE__USBPHY2_IDDIG 615 -MX53_PAD_EIM_RW__EMI_WEIM_RW 616 -MX53_PAD_EIM_RW__GPIO2_26 617 -MX53_PAD_EIM_RW__ECSPI2_SS0 618 -MX53_PAD_EIM_RW__IPU_DI1_PIN8 619 -MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 620 -MX53_PAD_EIM_LBA__EMI_WEIM_LBA 621 -MX53_PAD_EIM_LBA__GPIO2_27 622 -MX53_PAD_EIM_LBA__ECSPI2_SS1 623 -MX53_PAD_EIM_LBA__IPU_DI1_PIN17 624 -MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 625 -MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 626 -MX53_PAD_EIM_EB0__GPIO2_28 627 -MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 628 -MX53_PAD_EIM_EB0__IPU_CSI1_D_11 629 -MX53_PAD_EIM_EB0__GPC_PMIC_RDY 630 -MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 631 -MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 632 -MX53_PAD_EIM_EB1__GPIO2_29 633 -MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 634 -MX53_PAD_EIM_EB1__IPU_CSI1_D_10 635 -MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 636 -MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 637 -MX53_PAD_EIM_DA0__GPIO3_0 638 -MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 639 -MX53_PAD_EIM_DA0__IPU_CSI1_D_9 640 -MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 641 -MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 642 -MX53_PAD_EIM_DA1__GPIO3_1 643 -MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 644 -MX53_PAD_EIM_DA1__IPU_CSI1_D_8 645 -MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 646 -MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 647 -MX53_PAD_EIM_DA2__GPIO3_2 648 -MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 649 -MX53_PAD_EIM_DA2__IPU_CSI1_D_7 650 -MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 651 -MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 652 -MX53_PAD_EIM_DA3__GPIO3_3 653 -MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 654 -MX53_PAD_EIM_DA3__IPU_CSI1_D_6 655 -MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 656 -MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 657 -MX53_PAD_EIM_DA4__GPIO3_4 658 -MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 659 -MX53_PAD_EIM_DA4__IPU_CSI1_D_5 660 -MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 661 -MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 662 -MX53_PAD_EIM_DA5__GPIO3_5 663 -MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 664 -MX53_PAD_EIM_DA5__IPU_CSI1_D_4 665 -MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 666 -MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 667 -MX53_PAD_EIM_DA6__GPIO3_6 668 -MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 669 -MX53_PAD_EIM_DA6__IPU_CSI1_D_3 670 -MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 671 -MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 672 -MX53_PAD_EIM_DA7__GPIO3_7 673 -MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 674 -MX53_PAD_EIM_DA7__IPU_CSI1_D_2 675 -MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 676 -MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 677 -MX53_PAD_EIM_DA8__GPIO3_8 678 -MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 679 -MX53_PAD_EIM_DA8__IPU_CSI1_D_1 680 -MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 681 -MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 682 -MX53_PAD_EIM_DA9__GPIO3_9 683 -MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 684 -MX53_PAD_EIM_DA9__IPU_CSI1_D_0 685 -MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 686 -MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 687 -MX53_PAD_EIM_DA10__GPIO3_10 688 -MX53_PAD_EIM_DA10__IPU_DI1_PIN15 689 -MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 690 -MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 691 -MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 692 -MX53_PAD_EIM_DA11__GPIO3_11 693 -MX53_PAD_EIM_DA11__IPU_DI1_PIN2 694 -MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 695 -MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 696 -MX53_PAD_EIM_DA12__GPIO3_12 697 -MX53_PAD_EIM_DA12__IPU_DI1_PIN3 698 -MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 699 -MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 700 -MX53_PAD_EIM_DA13__GPIO3_13 701 -MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 702 -MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 703 -MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 704 -MX53_PAD_EIM_DA14__GPIO3_14 705 -MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 706 -MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 707 -MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 708 -MX53_PAD_EIM_DA15__GPIO3_15 709 -MX53_PAD_EIM_DA15__IPU_DI1_PIN1 710 -MX53_PAD_EIM_DA15__IPU_DI1_PIN4 711 -MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 712 -MX53_PAD_NANDF_WE_B__GPIO6_12 713 -MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 714 -MX53_PAD_NANDF_RE_B__GPIO6_13 715 -MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 716 -MX53_PAD_EIM_WAIT__GPIO5_0 717 -MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 718 -MX53_PAD_LVDS1_TX3_P__GPIO6_22 719 -MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 720 -MX53_PAD_LVDS1_TX2_P__GPIO6_24 721 -MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 722 -MX53_PAD_LVDS1_CLK_P__GPIO6_26 723 -MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 724 -MX53_PAD_LVDS1_TX1_P__GPIO6_28 725 -MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 726 -MX53_PAD_LVDS1_TX0_P__GPIO6_30 727 -MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 728 -MX53_PAD_LVDS0_TX3_P__GPIO7_22 729 -MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 730 -MX53_PAD_LVDS0_CLK_P__GPIO7_24 731 -MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 732 -MX53_PAD_LVDS0_TX2_P__GPIO7_26 733 -MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 734 -MX53_PAD_LVDS0_TX1_P__GPIO7_28 735 -MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 736 -MX53_PAD_LVDS0_TX0_P__GPIO7_30 737 -MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 738 -MX53_PAD_GPIO_10__GPIO4_0 739 -MX53_PAD_GPIO_10__OSC32k_32K_OUT 740 -MX53_PAD_GPIO_11__GPIO4_1 741 -MX53_PAD_GPIO_12__GPIO4_2 742 -MX53_PAD_GPIO_13__GPIO4_3 743 -MX53_PAD_GPIO_14__GPIO4_4 744 -MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 745 -MX53_PAD_NANDF_CLE__GPIO6_7 746 -MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 747 -MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 748 -MX53_PAD_NANDF_ALE__GPIO6_8 749 -MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 750 -MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 751 -MX53_PAD_NANDF_WP_B__GPIO6_9 752 -MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 753 -MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 754 -MX53_PAD_NANDF_RB0__GPIO6_10 755 -MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 756 -MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 757 -MX53_PAD_NANDF_CS0__GPIO6_11 758 -MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 759 -MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 760 -MX53_PAD_NANDF_CS1__GPIO6_14 761 -MX53_PAD_NANDF_CS1__MLB_MLBCLK 762 -MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 763 -MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 764 -MX53_PAD_NANDF_CS2__GPIO6_15 765 -MX53_PAD_NANDF_CS2__IPU_SISG_0 766 -MX53_PAD_NANDF_CS2__ESAI1_TX0 767 -MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 768 -MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 769 -MX53_PAD_NANDF_CS2__MLB_MLBSIG 770 -MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 771 -MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 772 -MX53_PAD_NANDF_CS3__GPIO6_16 773 -MX53_PAD_NANDF_CS3__IPU_SISG_1 774 -MX53_PAD_NANDF_CS3__ESAI1_TX1 775 -MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 776 -MX53_PAD_NANDF_CS3__MLB_MLBDAT 777 -MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 778 -MX53_PAD_FEC_MDIO__FEC_MDIO 779 -MX53_PAD_FEC_MDIO__GPIO1_22 780 -MX53_PAD_FEC_MDIO__ESAI1_SCKR 781 -MX53_PAD_FEC_MDIO__FEC_COL 782 -MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 783 -MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 784 -MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 785 -MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 786 -MX53_PAD_FEC_REF_CLK__GPIO1_23 787 -MX53_PAD_FEC_REF_CLK__ESAI1_FSR 788 -MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 789 -MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 790 -MX53_PAD_FEC_RX_ER__FEC_RX_ER 791 -MX53_PAD_FEC_RX_ER__GPIO1_24 792 -MX53_PAD_FEC_RX_ER__ESAI1_HCKR 793 -MX53_PAD_FEC_RX_ER__FEC_RX_CLK 794 -MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 795 -MX53_PAD_FEC_CRS_DV__FEC_RX_DV 796 -MX53_PAD_FEC_CRS_DV__GPIO1_25 797 -MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 798 -MX53_PAD_FEC_RXD1__FEC_RDATA_1 799 -MX53_PAD_FEC_RXD1__GPIO1_26 800 -MX53_PAD_FEC_RXD1__ESAI1_FST 801 -MX53_PAD_FEC_RXD1__MLB_MLBSIG 802 -MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 803 -MX53_PAD_FEC_RXD0__FEC_RDATA_0 804 -MX53_PAD_FEC_RXD0__GPIO1_27 805 -MX53_PAD_FEC_RXD0__ESAI1_HCKT 806 -MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 807 -MX53_PAD_FEC_TX_EN__FEC_TX_EN 808 -MX53_PAD_FEC_TX_EN__GPIO1_28 809 -MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 810 -MX53_PAD_FEC_TXD1__FEC_TDATA_1 811 -MX53_PAD_FEC_TXD1__GPIO1_29 812 -MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 813 -MX53_PAD_FEC_TXD1__MLB_MLBCLK 814 -MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 815 -MX53_PAD_FEC_TXD0__FEC_TDATA_0 816 -MX53_PAD_FEC_TXD0__GPIO1_30 817 -MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 818 -MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 819 -MX53_PAD_FEC_MDC__FEC_MDC 820 -MX53_PAD_FEC_MDC__GPIO1_31 821 -MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 822 -MX53_PAD_FEC_MDC__MLB_MLBDAT 823 -MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 824 -MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 825 -MX53_PAD_PATA_DIOW__PATA_DIOW 826 -MX53_PAD_PATA_DIOW__GPIO6_17 827 -MX53_PAD_PATA_DIOW__UART1_TXD_MUX 828 -MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 829 -MX53_PAD_PATA_DMACK__PATA_DMACK 830 -MX53_PAD_PATA_DMACK__GPIO6_18 831 -MX53_PAD_PATA_DMACK__UART1_RXD_MUX 832 -MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 833 -MX53_PAD_PATA_DMARQ__PATA_DMARQ 834 -MX53_PAD_PATA_DMARQ__GPIO7_0 835 -MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 836 -MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 837 -MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 838 -MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 839 -MX53_PAD_PATA_BUFFER_EN__GPIO7_1 840 -MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 841 -MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 842 -MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 843 -MX53_PAD_PATA_INTRQ__PATA_INTRQ 844 -MX53_PAD_PATA_INTRQ__GPIO7_2 845 -MX53_PAD_PATA_INTRQ__UART2_CTS 846 -MX53_PAD_PATA_INTRQ__CAN1_TXCAN 847 -MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 848 -MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 849 -MX53_PAD_PATA_DIOR__PATA_DIOR 850 -MX53_PAD_PATA_DIOR__GPIO7_3 851 -MX53_PAD_PATA_DIOR__UART2_RTS 852 -MX53_PAD_PATA_DIOR__CAN1_RXCAN 853 -MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 854 -MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 855 -MX53_PAD_PATA_RESET_B__GPIO7_4 856 -MX53_PAD_PATA_RESET_B__ESDHC3_CMD 857 -MX53_PAD_PATA_RESET_B__UART1_CTS 858 -MX53_PAD_PATA_RESET_B__CAN2_TXCAN 859 -MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 860 -MX53_PAD_PATA_IORDY__PATA_IORDY 861 -MX53_PAD_PATA_IORDY__GPIO7_5 862 -MX53_PAD_PATA_IORDY__ESDHC3_CLK 863 -MX53_PAD_PATA_IORDY__UART1_RTS 864 -MX53_PAD_PATA_IORDY__CAN2_RXCAN 865 -MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 866 -MX53_PAD_PATA_DA_0__PATA_DA_0 867 -MX53_PAD_PATA_DA_0__GPIO7_6 868 -MX53_PAD_PATA_DA_0__ESDHC3_RST 869 -MX53_PAD_PATA_DA_0__OWIRE_LINE 870 -MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 871 -MX53_PAD_PATA_DA_1__PATA_DA_1 872 -MX53_PAD_PATA_DA_1__GPIO7_7 873 -MX53_PAD_PATA_DA_1__ESDHC4_CMD 874 -MX53_PAD_PATA_DA_1__UART3_CTS 875 -MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 876 -MX53_PAD_PATA_DA_2__PATA_DA_2 877 -MX53_PAD_PATA_DA_2__GPIO7_8 878 -MX53_PAD_PATA_DA_2__ESDHC4_CLK 879 -MX53_PAD_PATA_DA_2__UART3_RTS 880 -MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 881 -MX53_PAD_PATA_CS_0__PATA_CS_0 882 -MX53_PAD_PATA_CS_0__GPIO7_9 883 -MX53_PAD_PATA_CS_0__UART3_TXD_MUX 884 -MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 885 -MX53_PAD_PATA_CS_1__PATA_CS_1 886 -MX53_PAD_PATA_CS_1__GPIO7_10 887 -MX53_PAD_PATA_CS_1__UART3_RXD_MUX 888 -MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 889 -MX53_PAD_PATA_DATA0__PATA_DATA_0 890 -MX53_PAD_PATA_DATA0__GPIO2_0 891 -MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 892 -MX53_PAD_PATA_DATA0__ESDHC3_DAT4 893 -MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 894 -MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 895 -MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 896 -MX53_PAD_PATA_DATA1__PATA_DATA_1 897 -MX53_PAD_PATA_DATA1__GPIO2_1 898 -MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 899 -MX53_PAD_PATA_DATA1__ESDHC3_DAT5 900 -MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 901 -MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 902 -MX53_PAD_PATA_DATA2__PATA_DATA_2 903 -MX53_PAD_PATA_DATA2__GPIO2_2 904 -MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 905 -MX53_PAD_PATA_DATA2__ESDHC3_DAT6 906 -MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 907 -MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 908 -MX53_PAD_PATA_DATA3__PATA_DATA_3 909 -MX53_PAD_PATA_DATA3__GPIO2_3 910 -MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 911 -MX53_PAD_PATA_DATA3__ESDHC3_DAT7 912 -MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 913 -MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 914 -MX53_PAD_PATA_DATA4__PATA_DATA_4 915 -MX53_PAD_PATA_DATA4__GPIO2_4 916 -MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 917 -MX53_PAD_PATA_DATA4__ESDHC4_DAT4 918 -MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 919 -MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 920 -MX53_PAD_PATA_DATA5__PATA_DATA_5 921 -MX53_PAD_PATA_DATA5__GPIO2_5 922 -MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 923 -MX53_PAD_PATA_DATA5__ESDHC4_DAT5 924 -MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 925 -MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 926 -MX53_PAD_PATA_DATA6__PATA_DATA_6 927 -MX53_PAD_PATA_DATA6__GPIO2_6 928 -MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 929 -MX53_PAD_PATA_DATA6__ESDHC4_DAT6 930 -MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 931 -MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 932 -MX53_PAD_PATA_DATA7__PATA_DATA_7 933 -MX53_PAD_PATA_DATA7__GPIO2_7 934 -MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 935 -MX53_PAD_PATA_DATA7__ESDHC4_DAT7 936 -MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 937 -MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 938 -MX53_PAD_PATA_DATA8__PATA_DATA_8 939 -MX53_PAD_PATA_DATA8__GPIO2_8 940 -MX53_PAD_PATA_DATA8__ESDHC1_DAT4 941 -MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 942 -MX53_PAD_PATA_DATA8__ESDHC3_DAT0 943 -MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 944 -MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 945 -MX53_PAD_PATA_DATA9__PATA_DATA_9 946 -MX53_PAD_PATA_DATA9__GPIO2_9 947 -MX53_PAD_PATA_DATA9__ESDHC1_DAT5 948 -MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 949 -MX53_PAD_PATA_DATA9__ESDHC3_DAT1 950 -MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 951 -MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 952 -MX53_PAD_PATA_DATA10__PATA_DATA_10 953 -MX53_PAD_PATA_DATA10__GPIO2_10 954 -MX53_PAD_PATA_DATA10__ESDHC1_DAT6 955 -MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 956 -MX53_PAD_PATA_DATA10__ESDHC3_DAT2 957 -MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 958 -MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 959 -MX53_PAD_PATA_DATA11__PATA_DATA_11 960 -MX53_PAD_PATA_DATA11__GPIO2_11 961 -MX53_PAD_PATA_DATA11__ESDHC1_DAT7 962 -MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 963 -MX53_PAD_PATA_DATA11__ESDHC3_DAT3 964 -MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 965 -MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 966 -MX53_PAD_PATA_DATA12__PATA_DATA_12 967 -MX53_PAD_PATA_DATA12__GPIO2_12 968 -MX53_PAD_PATA_DATA12__ESDHC2_DAT4 969 -MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 970 -MX53_PAD_PATA_DATA12__ESDHC4_DAT0 971 -MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 972 -MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 973 -MX53_PAD_PATA_DATA13__PATA_DATA_13 974 -MX53_PAD_PATA_DATA13__GPIO2_13 975 -MX53_PAD_PATA_DATA13__ESDHC2_DAT5 976 -MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 977 -MX53_PAD_PATA_DATA13__ESDHC4_DAT1 978 -MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 979 -MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 980 -MX53_PAD_PATA_DATA14__PATA_DATA_14 981 -MX53_PAD_PATA_DATA14__GPIO2_14 982 -MX53_PAD_PATA_DATA14__ESDHC2_DAT6 983 -MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 984 -MX53_PAD_PATA_DATA14__ESDHC4_DAT2 985 -MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 986 -MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 987 -MX53_PAD_PATA_DATA15__PATA_DATA_15 988 -MX53_PAD_PATA_DATA15__GPIO2_15 989 -MX53_PAD_PATA_DATA15__ESDHC2_DAT7 990 -MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 991 -MX53_PAD_PATA_DATA15__ESDHC4_DAT3 992 -MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 993 -MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 994 -MX53_PAD_SD1_DATA0__ESDHC1_DAT0 995 -MX53_PAD_SD1_DATA0__GPIO1_16 996 -MX53_PAD_SD1_DATA0__GPT_CAPIN1 997 -MX53_PAD_SD1_DATA0__CSPI_MISO 998 -MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 999 -MX53_PAD_SD1_DATA1__ESDHC1_DAT1 1000 -MX53_PAD_SD1_DATA1__GPIO1_17 1001 -MX53_PAD_SD1_DATA1__GPT_CAPIN2 1002 -MX53_PAD_SD1_DATA1__CSPI_SS0 1003 -MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 1004 -MX53_PAD_SD1_CMD__ESDHC1_CMD 1005 -MX53_PAD_SD1_CMD__GPIO1_18 1006 -MX53_PAD_SD1_CMD__GPT_CMPOUT1 1007 -MX53_PAD_SD1_CMD__CSPI_MOSI 1008 -MX53_PAD_SD1_CMD__CCM_PLL1_BYP 1009 -MX53_PAD_SD1_DATA2__ESDHC1_DAT2 1010 -MX53_PAD_SD1_DATA2__GPIO1_19 1011 -MX53_PAD_SD1_DATA2__GPT_CMPOUT2 1012 -MX53_PAD_SD1_DATA2__PWM2_PWMO 1013 -MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 1014 -MX53_PAD_SD1_DATA2__CSPI_SS1 1015 -MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 1016 -MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 1017 -MX53_PAD_SD1_CLK__ESDHC1_CLK 1018 -MX53_PAD_SD1_CLK__GPIO1_20 1019 -MX53_PAD_SD1_CLK__OSC32k_32K_OUT 1020 -MX53_PAD_SD1_CLK__GPT_CLKIN 1021 -MX53_PAD_SD1_CLK__CSPI_SCLK 1022 -MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 1023 -MX53_PAD_SD1_DATA3__ESDHC1_DAT3 1024 -MX53_PAD_SD1_DATA3__GPIO1_21 1025 -MX53_PAD_SD1_DATA3__GPT_CMPOUT3 1026 -MX53_PAD_SD1_DATA3__PWM1_PWMO 1027 -MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 1028 -MX53_PAD_SD1_DATA3__CSPI_SS2 1029 -MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 1030 -MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 1031 -MX53_PAD_SD2_CLK__ESDHC2_CLK 1032 -MX53_PAD_SD2_CLK__GPIO1_10 1033 -MX53_PAD_SD2_CLK__KPP_COL_5 1034 -MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1035 -MX53_PAD_SD2_CLK__CSPI_SCLK 1036 -MX53_PAD_SD2_CLK__SCC_RANDOM_V 1037 -MX53_PAD_SD2_CMD__ESDHC2_CMD 1038 -MX53_PAD_SD2_CMD__GPIO1_11 1039 -MX53_PAD_SD2_CMD__KPP_ROW_5 1040 -MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1041 -MX53_PAD_SD2_CMD__CSPI_MOSI 1042 -MX53_PAD_SD2_CMD__SCC_RANDOM 1043 -MX53_PAD_SD2_DATA3__ESDHC2_DAT3 1044 -MX53_PAD_SD2_DATA3__GPIO1_12 1045 -MX53_PAD_SD2_DATA3__KPP_COL_6 1046 -MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 1047 -MX53_PAD_SD2_DATA3__CSPI_SS2 1048 -MX53_PAD_SD2_DATA3__SJC_DONE 1049 -MX53_PAD_SD2_DATA2__ESDHC2_DAT2 1050 -MX53_PAD_SD2_DATA2__GPIO1_13 1051 -MX53_PAD_SD2_DATA2__KPP_ROW_6 1052 -MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 1053 -MX53_PAD_SD2_DATA2__CSPI_SS1 1054 -MX53_PAD_SD2_DATA2__SJC_FAIL 1055 -MX53_PAD_SD2_DATA1__ESDHC2_DAT1 1056 -MX53_PAD_SD2_DATA1__GPIO1_14 1057 -MX53_PAD_SD2_DATA1__KPP_COL_7 1058 -MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 1059 -MX53_PAD_SD2_DATA1__CSPI_SS0 1060 -MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 1061 -MX53_PAD_SD2_DATA0__ESDHC2_DAT0 1062 -MX53_PAD_SD2_DATA0__GPIO1_15 1063 -MX53_PAD_SD2_DATA0__KPP_ROW_7 1064 -MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 1065 -MX53_PAD_SD2_DATA0__CSPI_MISO 1066 -MX53_PAD_SD2_DATA0__RTIC_DONE_INT 1067 -MX53_PAD_GPIO_0__CCM_CLKO 1068 -MX53_PAD_GPIO_0__GPIO1_0 1069 -MX53_PAD_GPIO_0__KPP_COL_5 1070 -MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 1071 -MX53_PAD_GPIO_0__EPIT1_EPITO 1072 -MX53_PAD_GPIO_0__SRTC_ALARM_DEB 1073 -MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 1074 -MX53_PAD_GPIO_0__CSU_TD 1075 -MX53_PAD_GPIO_1__ESAI1_SCKR 1076 -MX53_PAD_GPIO_1__GPIO1_1 1077 -MX53_PAD_GPIO_1__KPP_ROW_5 1078 -MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 1079 -MX53_PAD_GPIO_1__PWM2_PWMO 1080 -MX53_PAD_GPIO_1__WDOG2_WDOG_B 1081 -MX53_PAD_GPIO_1__ESDHC1_CD 1082 -MX53_PAD_GPIO_1__SRC_TESTER_ACK 1083 -MX53_PAD_GPIO_9__ESAI1_FSR 1084 -MX53_PAD_GPIO_9__GPIO1_9 1085 -MX53_PAD_GPIO_9__KPP_COL_6 1086 -MX53_PAD_GPIO_9__CCM_REF_EN_B 1087 -MX53_PAD_GPIO_9__PWM1_PWMO 1088 -MX53_PAD_GPIO_9__WDOG1_WDOG_B 1089 -MX53_PAD_GPIO_9__ESDHC1_WP 1090 -MX53_PAD_GPIO_9__SCC_FAIL_STATE 1091 -MX53_PAD_GPIO_3__ESAI1_HCKR 1092 -MX53_PAD_GPIO_3__GPIO1_3 1093 -MX53_PAD_GPIO_3__I2C3_SCL 1094 -MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 1095 -MX53_PAD_GPIO_3__CCM_CLKO2 1096 -MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 1097 -MX53_PAD_GPIO_3__USBOH3_USBH1_OC 1098 -MX53_PAD_GPIO_3__MLB_MLBCLK 1099 -MX53_PAD_GPIO_6__ESAI1_SCKT 1100 -MX53_PAD_GPIO_6__GPIO1_6 1101 -MX53_PAD_GPIO_6__I2C3_SDA 1102 -MX53_PAD_GPIO_6__CCM_CCM_OUT_0 1103 -MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 1104 -MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 1105 -MX53_PAD_GPIO_6__ESDHC2_LCTL 1106 -MX53_PAD_GPIO_6__MLB_MLBSIG 1107 -MX53_PAD_GPIO_2__ESAI1_FST 1108 -MX53_PAD_GPIO_2__GPIO1_2 1109 -MX53_PAD_GPIO_2__KPP_ROW_6 1110 -MX53_PAD_GPIO_2__CCM_CCM_OUT_1 1111 -MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 1112 -MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 1113 -MX53_PAD_GPIO_2__ESDHC2_WP 1114 -MX53_PAD_GPIO_2__MLB_MLBDAT 1115 -MX53_PAD_GPIO_4__ESAI1_HCKT 1116 -MX53_PAD_GPIO_4__GPIO1_4 1117 -MX53_PAD_GPIO_4__KPP_COL_7 1118 -MX53_PAD_GPIO_4__CCM_CCM_OUT_2 1119 -MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1120 -MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 1121 -MX53_PAD_GPIO_4__ESDHC2_CD 1122 -MX53_PAD_GPIO_4__SCC_SEC_STATE 1123 -MX53_PAD_GPIO_5__ESAI1_TX2_RX3 1124 -MX53_PAD_GPIO_5__GPIO1_5 1125 -MX53_PAD_GPIO_5__KPP_ROW_7 1126 -MX53_PAD_GPIO_5__CCM_CLKO 1127 -MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1128 -MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 1129 -MX53_PAD_GPIO_5__I2C3_SCL 1130 -MX53_PAD_GPIO_5__CCM_PLL1_BYP 1131 -MX53_PAD_GPIO_7__ESAI1_TX4_RX1 1132 -MX53_PAD_GPIO_7__GPIO1_7 1133 -MX53_PAD_GPIO_7__EPIT1_EPITO 1134 -MX53_PAD_GPIO_7__CAN1_TXCAN 1135 -MX53_PAD_GPIO_7__UART2_TXD_MUX 1136 -MX53_PAD_GPIO_7__FIRI_RXD 1137 -MX53_PAD_GPIO_7__SPDIF_PLOCK 1138 -MX53_PAD_GPIO_7__CCM_PLL2_BYP 1139 -MX53_PAD_GPIO_8__ESAI1_TX5_RX0 1140 -MX53_PAD_GPIO_8__GPIO1_8 1141 -MX53_PAD_GPIO_8__EPIT2_EPITO 1142 -MX53_PAD_GPIO_8__CAN1_RXCAN 1143 -MX53_PAD_GPIO_8__UART2_RXD_MUX 1144 -MX53_PAD_GPIO_8__FIRI_TXD 1145 -MX53_PAD_GPIO_8__SPDIF_SRCLK 1146 -MX53_PAD_GPIO_8__CCM_PLL3_BYP 1147 -MX53_PAD_GPIO_16__ESAI1_TX3_RX2 1148 -MX53_PAD_GPIO_16__GPIO7_11 1149 -MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 1150 -MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 1151 -MX53_PAD_GPIO_16__SPDIF_IN1 1152 -MX53_PAD_GPIO_16__I2C3_SDA 1153 -MX53_PAD_GPIO_16__SJC_DE_B 1154 -MX53_PAD_GPIO_17__ESAI1_TX0 1155 -MX53_PAD_GPIO_17__GPIO7_12 1156 -MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 1157 -MX53_PAD_GPIO_17__GPC_PMIC_RDY 1158 -MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 1159 -MX53_PAD_GPIO_17__SPDIF_OUT1 1160 -MX53_PAD_GPIO_17__IPU_SNOOP2 1161 -MX53_PAD_GPIO_17__SJC_JTAG_ACT 1162 -MX53_PAD_GPIO_18__ESAI1_TX1 1163 -MX53_PAD_GPIO_18__GPIO7_13 1164 -MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 1165 -MX53_PAD_GPIO_18__OWIRE_LINE 1166 -MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 1167 -MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 1168 -MX53_PAD_GPIO_18__ESDHC1_LCTL 1169 -MX53_PAD_GPIO_18__SRC_SYSTEM_RST 1170 +Refer to imx53-pinfunc.h in device tree source folder for all available +imx53 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt new file mode 100644 index 00000000000..0ac5bee8750 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt @@ -0,0 +1,38 @@ +* Freescale IMX6 DualLite/Solo IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx6dl-iomuxc" +- fsl,pins: two integers array, represents a group of pins mux and config + setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a + pin working on a specific function, CONFIG is the pad setting value like + pull-up for this pin. Please refer to imx6dl datasheet for the valid pad + config settings. + +CONFIG bits definition: +PAD_CTL_HYS (1 << 16) +PAD_CTL_PUS_100K_DOWN (0 << 14) +PAD_CTL_PUS_47K_UP (1 << 14) +PAD_CTL_PUS_100K_UP (2 << 14) +PAD_CTL_PUS_22K_UP (3 << 14) +PAD_CTL_PUE (1 << 13) +PAD_CTL_PKE (1 << 12) +PAD_CTL_ODE (1 << 11) +PAD_CTL_SPEED_LOW (1 << 6) +PAD_CTL_SPEED_MED (2 << 6) +PAD_CTL_SPEED_HIGH (3 << 6) +PAD_CTL_DSE_DISABLE (0 << 3) +PAD_CTL_DSE_240ohm (1 << 3) +PAD_CTL_DSE_120ohm (2 << 3) +PAD_CTL_DSE_80ohm (3 << 3) +PAD_CTL_DSE_60ohm (4 << 3) +PAD_CTL_DSE_48ohm (5 << 3) +PAD_CTL_DSE_40ohm (6 << 3) +PAD_CTL_DSE_34ohm (7 << 3) +PAD_CTL_SRE_FAST (1 << 0) +PAD_CTL_SRE_SLOW (0 << 0) + +Refer to imx6dl-pinfunc.h in device tree source folder for all available +imx6dl PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt index a4119f6422d..546610cf2ae 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt @@ -34,1597 +34,5 @@ PAD_CTL_DSE_34ohm (7 << 3) PAD_CTL_SRE_FAST (1 << 0) PAD_CTL_SRE_SLOW (0 << 0) -See below for available PIN_FUNC_ID for imx6q: -MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0 -MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1 -MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2 -MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3 -MX6Q_PAD_SD2_DAT1__KPP_COL_7 4 -MX6Q_PAD_SD2_DAT1__GPIO_1_14 5 -MX6Q_PAD_SD2_DAT1__CCM_WAIT 6 -MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7 -MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8 -MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9 -MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10 -MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11 -MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12 -MX6Q_PAD_SD2_DAT2__GPIO_1_13 13 -MX6Q_PAD_SD2_DAT2__CCM_STOP 14 -MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15 -MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16 -MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17 -MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18 -MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19 -MX6Q_PAD_SD2_DAT0__GPIO_1_15 20 -MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21 -MX6Q_PAD_SD2_DAT0__TESTO_2 22 -MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23 -MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24 -MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25 -MX6Q_PAD_RGMII_TXC__GPIO_6_19 26 -MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27 -MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28 -MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29 -MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30 -MX6Q_PAD_RGMII_TD0__GPIO_6_20 31 -MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32 -MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33 -MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34 -MX6Q_PAD_RGMII_TD1__GPIO_6_21 35 -MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36 -MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37 -MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38 -MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39 -MX6Q_PAD_RGMII_TD2__GPIO_6_22 40 -MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41 -MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42 -MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43 -MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44 -MX6Q_PAD_RGMII_TD3__GPIO_6_23 45 -MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46 -MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47 -MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48 -MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49 -MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50 -MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51 -MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52 -MX6Q_PAD_RGMII_RD0__GPIO_6_25 53 -MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54 -MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55 -MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56 -MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57 -MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58 -MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59 -MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60 -MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61 -MX6Q_PAD_RGMII_RD1__GPIO_6_27 62 -MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63 -MX6Q_PAD_RGMII_RD1__SJC_FAIL 64 -MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65 -MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66 -MX6Q_PAD_RGMII_RD2__GPIO_6_28 67 -MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68 -MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69 -MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70 -MX6Q_PAD_RGMII_RD3__GPIO_6_29 71 -MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72 -MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73 -MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74 -MX6Q_PAD_RGMII_RXC__GPIO_6_30 75 -MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76 -MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77 -MX6Q_PAD_EIM_A25__ECSPI4_SS1 78 -MX6Q_PAD_EIM_A25__ECSPI2_RDY 79 -MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80 -MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81 -MX6Q_PAD_EIM_A25__GPIO_5_2 82 -MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83 -MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84 -MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85 -MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86 -MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87 -MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88 -MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89 -MX6Q_PAD_EIM_EB2__GPIO_2_30 90 -MX6Q_PAD_EIM_EB2__I2C2_SCL 91 -MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92 -MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93 -MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94 -MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95 -MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96 -MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97 -MX6Q_PAD_EIM_D16__GPIO_3_16 98 -MX6Q_PAD_EIM_D16__I2C2_SDA 99 -MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100 -MX6Q_PAD_EIM_D17__ECSPI1_MISO 101 -MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102 -MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103 -MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104 -MX6Q_PAD_EIM_D17__GPIO_3_17 105 -MX6Q_PAD_EIM_D17__I2C3_SCL 106 -MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107 -MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108 -MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109 -MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110 -MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111 -MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112 -MX6Q_PAD_EIM_D18__GPIO_3_18 113 -MX6Q_PAD_EIM_D18__I2C3_SDA 114 -MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115 -MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116 -MX6Q_PAD_EIM_D19__ECSPI1_SS1 117 -MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118 -MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119 -MX6Q_PAD_EIM_D19__UART1_CTS 120 -MX6Q_PAD_EIM_D19__GPIO_3_19 121 -MX6Q_PAD_EIM_D19__EPIT1_EPITO 122 -MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123 -MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124 -MX6Q_PAD_EIM_D20__ECSPI4_SS0 125 -MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126 -MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127 -MX6Q_PAD_EIM_D20__UART1_RTS 128 -MX6Q_PAD_EIM_D20__GPIO_3_20 129 -MX6Q_PAD_EIM_D20__EPIT2_EPITO 130 -MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131 -MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132 -MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133 -MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134 -MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135 -MX6Q_PAD_EIM_D21__GPIO_3_21 136 -MX6Q_PAD_EIM_D21__I2C1_SCL 137 -MX6Q_PAD_EIM_D21__SPDIF_IN1 138 -MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139 -MX6Q_PAD_EIM_D22__ECSPI4_MISO 140 -MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141 -MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142 -MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143 -MX6Q_PAD_EIM_D22__GPIO_3_22 144 -MX6Q_PAD_EIM_D22__SPDIF_OUT1 145 -MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146 -MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147 -MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148 -MX6Q_PAD_EIM_D23__UART3_CTS 149 -MX6Q_PAD_EIM_D23__UART1_DCD 150 -MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151 -MX6Q_PAD_EIM_D23__GPIO_3_23 152 -MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153 -MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154 -MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155 -MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156 -MX6Q_PAD_EIM_EB3__UART3_RTS 157 -MX6Q_PAD_EIM_EB3__UART1_RI 158 -MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159 -MX6Q_PAD_EIM_EB3__GPIO_2_31 160 -MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161 -MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162 -MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163 -MX6Q_PAD_EIM_D24__ECSPI4_SS2 164 -MX6Q_PAD_EIM_D24__UART3_TXD 165 -MX6Q_PAD_EIM_D24__ECSPI1_SS2 166 -MX6Q_PAD_EIM_D24__ECSPI2_SS2 167 -MX6Q_PAD_EIM_D24__GPIO_3_24 168 -MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169 -MX6Q_PAD_EIM_D24__UART1_DTR 170 -MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171 -MX6Q_PAD_EIM_D25__ECSPI4_SS3 172 -MX6Q_PAD_EIM_D25__UART3_RXD 173 -MX6Q_PAD_EIM_D25__ECSPI1_SS3 174 -MX6Q_PAD_EIM_D25__ECSPI2_SS3 175 -MX6Q_PAD_EIM_D25__GPIO_3_25 176 -MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177 -MX6Q_PAD_EIM_D25__UART1_DSR 178 -MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179 -MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180 -MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181 -MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182 -MX6Q_PAD_EIM_D26__UART2_TXD 183 -MX6Q_PAD_EIM_D26__GPIO_3_26 184 -MX6Q_PAD_EIM_D26__IPU1_SISG_2 185 -MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186 -MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187 -MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188 -MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189 -MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190 -MX6Q_PAD_EIM_D27__UART2_RXD 191 -MX6Q_PAD_EIM_D27__GPIO_3_27 192 -MX6Q_PAD_EIM_D27__IPU1_SISG_3 193 -MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194 -MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195 -MX6Q_PAD_EIM_D28__I2C1_SDA 196 -MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197 -MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198 -MX6Q_PAD_EIM_D28__UART2_CTS 199 -MX6Q_PAD_EIM_D28__GPIO_3_28 200 -MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201 -MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202 -MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203 -MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204 -MX6Q_PAD_EIM_D29__ECSPI4_SS0 205 -MX6Q_PAD_EIM_D29__UART2_RTS 206 -MX6Q_PAD_EIM_D29__GPIO_3_29 207 -MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208 -MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209 -MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210 -MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211 -MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212 -MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213 -MX6Q_PAD_EIM_D30__UART3_CTS 214 -MX6Q_PAD_EIM_D30__GPIO_3_30 215 -MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216 -MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217 -MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218 -MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219 -MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220 -MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221 -MX6Q_PAD_EIM_D31__UART3_RTS 222 -MX6Q_PAD_EIM_D31__GPIO_3_31 223 -MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224 -MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225 -MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226 -MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227 -MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228 -MX6Q_PAD_EIM_A24__IPU2_SISG_2 229 -MX6Q_PAD_EIM_A24__IPU1_SISG_2 230 -MX6Q_PAD_EIM_A24__GPIO_5_4 231 -MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232 -MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233 -MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234 -MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235 -MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236 -MX6Q_PAD_EIM_A23__IPU2_SISG_3 237 -MX6Q_PAD_EIM_A23__IPU1_SISG_3 238 -MX6Q_PAD_EIM_A23__GPIO_6_6 239 -MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240 -MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241 -MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242 -MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243 -MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244 -MX6Q_PAD_EIM_A22__GPIO_2_16 245 -MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246 -MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247 -MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248 -MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249 -MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250 -MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251 -MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252 -MX6Q_PAD_EIM_A21__GPIO_2_17 253 -MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254 -MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255 -MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256 -MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257 -MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258 -MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259 -MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260 -MX6Q_PAD_EIM_A20__GPIO_2_18 261 -MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262 -MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263 -MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264 -MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265 -MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266 -MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267 -MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268 -MX6Q_PAD_EIM_A19__GPIO_2_19 269 -MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270 -MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271 -MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272 -MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273 -MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274 -MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275 -MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276 -MX6Q_PAD_EIM_A18__GPIO_2_20 277 -MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278 -MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279 -MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280 -MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281 -MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282 -MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283 -MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284 -MX6Q_PAD_EIM_A17__GPIO_2_21 285 -MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286 -MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287 -MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288 -MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289 -MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290 -MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291 -MX6Q_PAD_EIM_A16__GPIO_2_22 292 -MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293 -MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294 -MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295 -MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296 -MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297 -MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298 -MX6Q_PAD_EIM_CS0__GPIO_2_23 299 -MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300 -MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301 -MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302 -MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303 -MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304 -MX6Q_PAD_EIM_CS1__GPIO_2_24 305 -MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306 -MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307 -MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308 -MX6Q_PAD_EIM_OE__ECSPI2_MISO 309 -MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310 -MX6Q_PAD_EIM_OE__GPIO_2_25 311 -MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312 -MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313 -MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314 -MX6Q_PAD_EIM_RW__ECSPI2_SS0 315 -MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316 -MX6Q_PAD_EIM_RW__GPIO_2_26 317 -MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318 -MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319 -MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320 -MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321 -MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322 -MX6Q_PAD_EIM_LBA__GPIO_2_27 323 -MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324 -MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 325 -MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 326 -MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 327 -MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 328 -MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 329 -MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY 330 -MX6Q_PAD_EIM_EB0__GPIO_2_28 331 -MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 332 -MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 333 -MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 334 -MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 335 -MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 336 -MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 337 -MX6Q_PAD_EIM_EB1__GPIO_2_29 338 -MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 339 -MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 340 -MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 341 -MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 342 -MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 343 -MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 344 -MX6Q_PAD_EIM_DA0__GPIO_3_0 345 -MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 346 -MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 347 -MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 348 -MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 349 -MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 350 -MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 351 -MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE 352 -MX6Q_PAD_EIM_DA1__GPIO_3_1 353 -MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 354 -MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 355 -MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 356 -MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 357 -MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 358 -MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 359 -MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE 360 -MX6Q_PAD_EIM_DA2__GPIO_3_2 361 -MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 362 -MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 363 -MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 364 -MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 365 -MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 366 -MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 367 -MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ 368 -MX6Q_PAD_EIM_DA3__GPIO_3_3 369 -MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 370 -MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 371 -MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 372 -MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 373 -MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 374 -MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 375 -MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN 376 -MX6Q_PAD_EIM_DA4__GPIO_3_4 377 -MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 378 -MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 379 -MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 380 -MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 381 -MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 382 -MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 383 -MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP 384 -MX6Q_PAD_EIM_DA5__GPIO_3_5 385 -MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 386 -MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 387 -MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 388 -MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 389 -MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 390 -MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 391 -MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN 392 -MX6Q_PAD_EIM_DA6__GPIO_3_6 393 -MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 394 -MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 395 -MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 396 -MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 397 -MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 398 -MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 399 -MX6Q_PAD_EIM_DA7__GPIO_3_7 400 -MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 401 -MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 402 -MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 403 -MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 404 -MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 405 -MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 406 -MX6Q_PAD_EIM_DA8__GPIO_3_8 407 -MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 408 -MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 409 -MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 410 -MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 411 -MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 412 -MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 413 -MX6Q_PAD_EIM_DA9__GPIO_3_9 414 -MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 415 -MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 416 -MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 417 -MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 418 -MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 419 -MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 420 -MX6Q_PAD_EIM_DA10__GPIO_3_10 421 -MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 422 -MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 423 -MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 424 -MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 425 -MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 426 -MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 427 -MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 428 -MX6Q_PAD_EIM_DA11__GPIO_3_11 429 -MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 430 -MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 431 -MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 432 -MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 433 -MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 434 -MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 435 -MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 436 -MX6Q_PAD_EIM_DA12__GPIO_3_12 437 -MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 438 -MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 439 -MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 440 -MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 441 -MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK 442 -MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 443 -MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 444 -MX6Q_PAD_EIM_DA13__GPIO_3_13 445 -MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 446 -MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 447 -MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 448 -MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 449 -MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK 450 -MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 451 -MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 452 -MX6Q_PAD_EIM_DA14__GPIO_3_14 453 -MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 454 -MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 455 -MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 456 -MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 457 -MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 458 -MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 459 -MX6Q_PAD_EIM_DA15__GPIO_3_15 460 -MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 461 -MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 462 -MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 463 -MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B 464 -MX6Q_PAD_EIM_WAIT__GPIO_5_0 465 -MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 466 -MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 467 -MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK 468 -MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 469 -MX6Q_PAD_EIM_BCLK__GPIO_6_31 470 -MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 471 -MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK 472 -MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK 473 -MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 474 -MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 475 -MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 476 -MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 477 -MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 478 -MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 479 -MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 480 -MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 481 -MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 482 -MX6Q_PAD_DI0_PIN15__GPIO_4_17 483 -MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 484 -MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 485 -MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 486 -MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 487 -MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 488 -MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 489 -MX6Q_PAD_DI0_PIN2__GPIO_4_18 490 -MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 491 -MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 492 -MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 493 -MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 494 -MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 495 -MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 496 -MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 497 -MX6Q_PAD_DI0_PIN3__GPIO_4_19 498 -MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 499 -MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 500 -MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 501 -MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 502 -MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 503 -MX6Q_PAD_DI0_PIN4__USDHC1_WP 504 -MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 505 -MX6Q_PAD_DI0_PIN4__GPIO_4_20 506 -MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 507 -MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 508 -MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 509 -MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 510 -MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 511 -MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 512 -MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN 513 -MX6Q_PAD_DISP0_DAT0__GPIO_4_21 514 -MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 515 -MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 516 -MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 517 -MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 518 -MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 519 -MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL 520 -MX6Q_PAD_DISP0_DAT1__GPIO_4_22 521 -MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 522 -MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 523 -MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 524 -MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 525 -MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 526 -MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 527 -MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 528 -MX6Q_PAD_DISP0_DAT2__GPIO_4_23 529 -MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 530 -MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 531 -MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 532 -MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 533 -MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 534 -MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 535 -MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR 536 -MX6Q_PAD_DISP0_DAT3__GPIO_4_24 537 -MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 538 -MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 539 -MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 540 -MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 541 -MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 542 -MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 543 -MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 544 -MX6Q_PAD_DISP0_DAT4__GPIO_4_25 545 -MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 546 -MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 547 -MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 548 -MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 549 -MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 550 -MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS 551 -MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS 552 -MX6Q_PAD_DISP0_DAT5__GPIO_4_26 553 -MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 554 -MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 555 -MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 556 -MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 557 -MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 558 -MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC 559 -MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT 560 -MX6Q_PAD_DISP0_DAT6__GPIO_4_27 561 -MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 562 -MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 563 -MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 564 -MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 565 -MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 566 -MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 567 -MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 568 -MX6Q_PAD_DISP0_DAT7__GPIO_4_28 569 -MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 570 -MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 571 -MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 572 -MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 573 -MX6Q_PAD_DISP0_DAT8__PWM1_PWMO 574 -MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B 575 -MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 576 -MX6Q_PAD_DISP0_DAT8__GPIO_4_29 577 -MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 578 -MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 579 -MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 580 -MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 581 -MX6Q_PAD_DISP0_DAT9__PWM2_PWMO 582 -MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B 583 -MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 584 -MX6Q_PAD_DISP0_DAT9__GPIO_4_30 585 -MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 586 -MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 587 -MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 588 -MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 589 -MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 590 -MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 591 -MX6Q_PAD_DISP0_DAT10__GPIO_4_31 592 -MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 593 -MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 594 -MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 595 -MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 596 -MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 597 -MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 598 -MX6Q_PAD_DISP0_DAT11__GPIO_5_5 599 -MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 600 -MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 601 -MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 602 -MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 603 -MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED 604 -MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 605 -MX6Q_PAD_DISP0_DAT12__GPIO_5_6 606 -MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 607 -MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 608 -MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 609 -MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 610 -MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 611 -MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 612 -MX6Q_PAD_DISP0_DAT13__GPIO_5_7 613 -MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 614 -MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 615 -MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 616 -MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 617 -MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 618 -MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 619 -MX6Q_PAD_DISP0_DAT14__GPIO_5_8 620 -MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 621 -MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 622 -MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 623 -MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 624 -MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 625 -MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 626 -MX6Q_PAD_DISP0_DAT15__GPIO_5_9 627 -MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 628 -MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 629 -MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 630 -MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 631 -MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 632 -MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 633 -MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 634 -MX6Q_PAD_DISP0_DAT16__GPIO_5_10 635 -MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 636 -MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 637 -MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 638 -MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 639 -MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 640 -MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 641 -MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 642 -MX6Q_PAD_DISP0_DAT17__GPIO_5_11 643 -MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 644 -MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 645 -MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 646 -MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 647 -MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 648 -MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 649 -MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 650 -MX6Q_PAD_DISP0_DAT18__GPIO_5_12 651 -MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 652 -MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 653 -MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 654 -MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 655 -MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 656 -MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 657 -MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 658 -MX6Q_PAD_DISP0_DAT19__GPIO_5_13 659 -MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 660 -MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 661 -MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 662 -MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 663 -MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 664 -MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 665 -MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 666 -MX6Q_PAD_DISP0_DAT20__GPIO_5_14 667 -MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 668 -MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 669 -MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 670 -MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 671 -MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 672 -MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 673 -MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 674 -MX6Q_PAD_DISP0_DAT21__GPIO_5_15 675 -MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 676 -MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 677 -MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 678 -MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 679 -MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 680 -MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 681 -MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 682 -MX6Q_PAD_DISP0_DAT22__GPIO_5_16 683 -MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 684 -MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 685 -MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 686 -MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 687 -MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 688 -MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 689 -MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 690 -MX6Q_PAD_DISP0_DAT23__GPIO_5_17 691 -MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 692 -MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 693 -MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED 694 -MX6Q_PAD_ENET_MDIO__ENET_MDIO 695 -MX6Q_PAD_ENET_MDIO__ESAI1_SCKR 696 -MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 697 -MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT 698 -MX6Q_PAD_ENET_MDIO__GPIO_1_22 699 -MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK 700 -MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED 701 -MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 702 -MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR 703 -MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 704 -MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 705 -MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK 706 -MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH 707 -MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 708 -MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR 709 -MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 710 -MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT 711 -MX6Q_PAD_ENET_RX_ER__GPIO_1_24 712 -MX6Q_PAD_ENET_RX_ER__PHY_TDI 713 -MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD 714 -MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED 715 -MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 716 -MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT 717 -MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK 718 -MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 719 -MX6Q_PAD_ENET_CRS_DV__PHY_TDO 720 -MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD 721 -MX6Q_PAD_ENET_RXD1__MLB_MLBSIG 722 -MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 723 -MX6Q_PAD_ENET_RXD1__ESAI1_FST 724 -MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT 725 -MX6Q_PAD_ENET_RXD1__GPIO_1_26 726 -MX6Q_PAD_ENET_RXD1__PHY_TCK 727 -MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON 728 -MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT 729 -MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 730 -MX6Q_PAD_ENET_RXD0__ESAI1_HCKT 731 -MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 732 -MX6Q_PAD_ENET_RXD0__GPIO_1_27 733 -MX6Q_PAD_ENET_RXD0__PHY_TMS 734 -MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV 735 -MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED 736 -MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 737 -MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 738 -MX6Q_PAD_ENET_TX_EN__GPIO_1_28 739 -MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI 740 -MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH 741 -MX6Q_PAD_ENET_TXD1__MLB_MLBCLK 742 -MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 743 -MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 744 -MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 745 -MX6Q_PAD_ENET_TXD1__GPIO_1_29 746 -MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO 747 -MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD 748 -MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED 749 -MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 750 -MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 751 -MX6Q_PAD_ENET_TXD0__GPIO_1_30 752 -MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK 753 -MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD 754 -MX6Q_PAD_ENET_MDC__MLB_MLBDAT 755 -MX6Q_PAD_ENET_MDC__ENET_MDC 756 -MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 757 -MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 758 -MX6Q_PAD_ENET_MDC__GPIO_1_31 759 -MX6Q_PAD_ENET_MDC__SATA_PHY_TMS 760 -MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON 761 -MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 762 -MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 763 -MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 764 -MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 765 -MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 766 -MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 767 -MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 768 -MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 769 -MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 770 -MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 771 -MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 772 -MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 773 -MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 774 -MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 775 -MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 776 -MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 777 -MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 778 -MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 779 -MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 780 -MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 781 -MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 782 -MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 783 -MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 784 -MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 785 -MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 786 -MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 787 -MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 788 -MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 789 -MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 790 -MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 791 -MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 792 -MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 793 -MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 794 -MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 795 -MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 796 -MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 797 -MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 798 -MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 799 -MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 800 -MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 801 -MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 802 -MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 803 -MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 804 -MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 805 -MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 806 -MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 807 -MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 808 -MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 809 -MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 810 -MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 811 -MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 812 -MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 813 -MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 814 -MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 815 -MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 816 -MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 817 -MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS 818 -MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 819 -MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 820 -MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS 821 -MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET 822 -MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 823 -MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 824 -MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 825 -MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 826 -MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 827 -MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 828 -MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 829 -MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 830 -MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 831 -MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE 832 -MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 833 -MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 834 -MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 835 -MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 836 -MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 837 -MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 838 -MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 839 -MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 840 -MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 841 -MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 842 -MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 843 -MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 844 -MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 845 -MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 846 -MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 847 -MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 848 -MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 849 -MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 850 -MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 851 -MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 852 -MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 853 -MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 854 -MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 855 -MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 856 -MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 857 -MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 858 -MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 859 -MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 860 -MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 861 -MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 862 -MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 863 -MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 864 -MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 865 -MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 866 -MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 867 -MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 868 -MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 869 -MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 870 -MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 871 -MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 872 -MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 873 -MX6Q_PAD_KEY_COL0__ENET_RDATA_3 874 -MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC 875 -MX6Q_PAD_KEY_COL0__KPP_COL_0 876 -MX6Q_PAD_KEY_COL0__UART4_TXD 877 -MX6Q_PAD_KEY_COL0__GPIO_4_6 878 -MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT 879 -MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST 880 -MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 881 -MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 882 -MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 883 -MX6Q_PAD_KEY_ROW0__KPP_ROW_0 884 -MX6Q_PAD_KEY_ROW0__UART4_RXD 885 -MX6Q_PAD_KEY_ROW0__GPIO_4_7 886 -MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT 887 -MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 888 -MX6Q_PAD_KEY_COL1__ECSPI1_MISO 889 -MX6Q_PAD_KEY_COL1__ENET_MDIO 890 -MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 891 -MX6Q_PAD_KEY_COL1__KPP_COL_1 892 -MX6Q_PAD_KEY_COL1__UART5_TXD 893 -MX6Q_PAD_KEY_COL1__GPIO_4_8 894 -MX6Q_PAD_KEY_COL1__USDHC1_VSELECT 895 -MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 896 -MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 897 -MX6Q_PAD_KEY_ROW1__ENET_COL 898 -MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 899 -MX6Q_PAD_KEY_ROW1__KPP_ROW_1 900 -MX6Q_PAD_KEY_ROW1__UART5_RXD 901 -MX6Q_PAD_KEY_ROW1__GPIO_4_9 902 -MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT 903 -MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 904 -MX6Q_PAD_KEY_COL2__ECSPI1_SS1 905 -MX6Q_PAD_KEY_COL2__ENET_RDATA_2 906 -MX6Q_PAD_KEY_COL2__CAN1_TXCAN 907 -MX6Q_PAD_KEY_COL2__KPP_COL_2 908 -MX6Q_PAD_KEY_COL2__ENET_MDC 909 -MX6Q_PAD_KEY_COL2__GPIO_4_10 910 -MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP 911 -MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 912 -MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 913 -MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 914 -MX6Q_PAD_KEY_ROW2__CAN1_RXCAN 915 -MX6Q_PAD_KEY_ROW2__KPP_ROW_2 916 -MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT 917 -MX6Q_PAD_KEY_ROW2__GPIO_4_11 918 -MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 919 -MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 920 -MX6Q_PAD_KEY_COL3__ECSPI1_SS3 921 -MX6Q_PAD_KEY_COL3__ENET_CRS 922 -MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 923 -MX6Q_PAD_KEY_COL3__KPP_COL_3 924 -MX6Q_PAD_KEY_COL3__I2C2_SCL 925 -MX6Q_PAD_KEY_COL3__GPIO_4_12 926 -MX6Q_PAD_KEY_COL3__SPDIF_IN1 927 -MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 928 -MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT 929 -MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK 930 -MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 931 -MX6Q_PAD_KEY_ROW3__KPP_ROW_3 932 -MX6Q_PAD_KEY_ROW3__I2C2_SDA 933 -MX6Q_PAD_KEY_ROW3__GPIO_4_13 934 -MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT 935 -MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 936 -MX6Q_PAD_KEY_COL4__CAN2_TXCAN 937 -MX6Q_PAD_KEY_COL4__IPU1_SISG_4 938 -MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC 939 -MX6Q_PAD_KEY_COL4__KPP_COL_4 940 -MX6Q_PAD_KEY_COL4__UART5_RTS 941 -MX6Q_PAD_KEY_COL4__GPIO_4_14 942 -MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 943 -MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 944 -MX6Q_PAD_KEY_ROW4__CAN2_RXCAN 945 -MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 946 -MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 947 -MX6Q_PAD_KEY_ROW4__KPP_ROW_4 948 -MX6Q_PAD_KEY_ROW4__UART5_CTS 949 -MX6Q_PAD_KEY_ROW4__GPIO_4_15 950 -MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 951 -MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 952 -MX6Q_PAD_GPIO_0__CCM_CLKO 953 -MX6Q_PAD_GPIO_0__KPP_COL_5 954 -MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK 955 -MX6Q_PAD_GPIO_0__EPIT1_EPITO 956 -MX6Q_PAD_GPIO_0__GPIO_1_0 957 -MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR 958 -MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 959 -MX6Q_PAD_GPIO_1__ESAI1_SCKR 960 -MX6Q_PAD_GPIO_1__WDOG2_WDOG_B 961 -MX6Q_PAD_GPIO_1__KPP_ROW_5 962 -MX6Q_PAD_GPIO_1__PWM2_PWMO 963 -MX6Q_PAD_GPIO_1__GPIO_1_1 964 -MX6Q_PAD_GPIO_1__USDHC1_CD 965 -MX6Q_PAD_GPIO_1__SRC_TESTER_ACK 966 -MX6Q_PAD_GPIO_9__ESAI1_FSR 967 -MX6Q_PAD_GPIO_9__WDOG1_WDOG_B 968 -MX6Q_PAD_GPIO_9__KPP_COL_6 969 -MX6Q_PAD_GPIO_9__CCM_REF_EN_B 970 -MX6Q_PAD_GPIO_9__PWM1_PWMO 971 -MX6Q_PAD_GPIO_9__GPIO_1_9 972 -MX6Q_PAD_GPIO_9__USDHC1_WP 973 -MX6Q_PAD_GPIO_9__SRC_EARLY_RST 974 -MX6Q_PAD_GPIO_3__ESAI1_HCKR 975 -MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 976 -MX6Q_PAD_GPIO_3__I2C3_SCL 977 -MX6Q_PAD_GPIO_3__ANATOP_24M_OUT 978 -MX6Q_PAD_GPIO_3__CCM_CLKO2 979 -MX6Q_PAD_GPIO_3__GPIO_1_3 980 -MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC 981 -MX6Q_PAD_GPIO_3__MLB_MLBCLK 982 -MX6Q_PAD_GPIO_6__ESAI1_SCKT 983 -MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 984 -MX6Q_PAD_GPIO_6__I2C3_SDA 985 -MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 986 -MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB 987 -MX6Q_PAD_GPIO_6__GPIO_1_6 988 -MX6Q_PAD_GPIO_6__USDHC2_LCTL 989 -MX6Q_PAD_GPIO_6__MLB_MLBSIG 990 -MX6Q_PAD_GPIO_2__ESAI1_FST 991 -MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 992 -MX6Q_PAD_GPIO_2__KPP_ROW_6 993 -MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 994 -MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 995 -MX6Q_PAD_GPIO_2__GPIO_1_2 996 -MX6Q_PAD_GPIO_2__USDHC2_WP 997 -MX6Q_PAD_GPIO_2__MLB_MLBDAT 998 -MX6Q_PAD_GPIO_4__ESAI1_HCKT 999 -MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 1000 -MX6Q_PAD_GPIO_4__KPP_COL_7 1001 -MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 1002 -MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1003 -MX6Q_PAD_GPIO_4__GPIO_1_4 1004 -MX6Q_PAD_GPIO_4__USDHC2_CD 1005 -MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA 1006 -MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 1007 -MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 1008 -MX6Q_PAD_GPIO_5__KPP_ROW_7 1009 -MX6Q_PAD_GPIO_5__CCM_CLKO 1010 -MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1011 -MX6Q_PAD_GPIO_5__GPIO_1_5 1012 -MX6Q_PAD_GPIO_5__I2C3_SCL 1013 -MX6Q_PAD_GPIO_5__CHEETAH_EVENTI 1014 -MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 1015 -MX6Q_PAD_GPIO_7__ECSPI5_RDY 1016 -MX6Q_PAD_GPIO_7__EPIT1_EPITO 1017 -MX6Q_PAD_GPIO_7__CAN1_TXCAN 1018 -MX6Q_PAD_GPIO_7__UART2_TXD 1019 -MX6Q_PAD_GPIO_7__GPIO_1_7 1020 -MX6Q_PAD_GPIO_7__SPDIF_PLOCK 1021 -MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE 1022 -MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 1023 -MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT 1024 -MX6Q_PAD_GPIO_8__EPIT2_EPITO 1025 -MX6Q_PAD_GPIO_8__CAN1_RXCAN 1026 -MX6Q_PAD_GPIO_8__UART2_RXD 1027 -MX6Q_PAD_GPIO_8__GPIO_1_8 1028 -MX6Q_PAD_GPIO_8__SPDIF_SRCLK 1029 -MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK 1030 -MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 1031 -MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 1032 -MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT 1033 -MX6Q_PAD_GPIO_16__USDHC1_LCTL 1034 -MX6Q_PAD_GPIO_16__SPDIF_IN1 1035 -MX6Q_PAD_GPIO_16__GPIO_7_11 1036 -MX6Q_PAD_GPIO_16__I2C3_SDA 1037 -MX6Q_PAD_GPIO_16__SJC_DE_B 1038 -MX6Q_PAD_GPIO_17__ESAI1_TX0 1039 -MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 1040 -MX6Q_PAD_GPIO_17__CCM_PMIC_RDY 1041 -MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 1042 -MX6Q_PAD_GPIO_17__SPDIF_OUT1 1043 -MX6Q_PAD_GPIO_17__GPIO_7_12 1044 -MX6Q_PAD_GPIO_17__SJC_JTAG_ACT 1045 -MX6Q_PAD_GPIO_18__ESAI1_TX1 1046 -MX6Q_PAD_GPIO_18__ENET_RX_CLK 1047 -MX6Q_PAD_GPIO_18__USDHC3_VSELECT 1048 -MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 1049 -MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK 1050 -MX6Q_PAD_GPIO_18__GPIO_7_13 1051 -MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 1052 -MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST 1053 -MX6Q_PAD_GPIO_19__KPP_COL_5 1054 -MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 1055 -MX6Q_PAD_GPIO_19__SPDIF_OUT1 1056 -MX6Q_PAD_GPIO_19__CCM_CLKO 1057 -MX6Q_PAD_GPIO_19__ECSPI1_RDY 1058 -MX6Q_PAD_GPIO_19__GPIO_4_5 1059 -MX6Q_PAD_GPIO_19__ENET_TX_ER 1060 -MX6Q_PAD_GPIO_19__SRC_INT_BOOT 1061 -MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 1062 -MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 1063 -MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 1064 -MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 1065 -MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 1066 -MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO 1067 -MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 1068 -MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 1069 -MX6Q_PAD_CSI0_MCLK__CCM_CLKO 1070 -MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 1071 -MX6Q_PAD_CSI0_MCLK__GPIO_5_19 1072 -MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 1073 -MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL 1074 -MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN 1075 -MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 1076 -MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 1077 -MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 1078 -MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 1079 -MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 1080 -MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK 1081 -MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 1082 -MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 1083 -MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 1084 -MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 1085 -MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 1086 -MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 1087 -MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 1088 -MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 1089 -MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 1090 -MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 1091 -MX6Q_PAD_CSI0_DAT4__KPP_COL_5 1092 -MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 1093 -MX6Q_PAD_CSI0_DAT4__GPIO_5_22 1094 -MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 1095 -MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 1096 -MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 1097 -MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 1098 -MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 1099 -MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 1100 -MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 1101 -MX6Q_PAD_CSI0_DAT5__GPIO_5_23 1102 -MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 1103 -MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 1104 -MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 1105 -MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 1106 -MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 1107 -MX6Q_PAD_CSI0_DAT6__KPP_COL_6 1108 -MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 1109 -MX6Q_PAD_CSI0_DAT6__GPIO_5_24 1110 -MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 1111 -MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 1112 -MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 1113 -MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 1114 -MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 1115 -MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 1116 -MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 1117 -MX6Q_PAD_CSI0_DAT7__GPIO_5_25 1118 -MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 1119 -MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 1120 -MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 1121 -MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 1122 -MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 1123 -MX6Q_PAD_CSI0_DAT8__KPP_COL_7 1124 -MX6Q_PAD_CSI0_DAT8__I2C1_SDA 1125 -MX6Q_PAD_CSI0_DAT8__GPIO_5_26 1126 -MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 1127 -MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 1128 -MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 1129 -MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 1130 -MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 1131 -MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 1132 -MX6Q_PAD_CSI0_DAT9__I2C1_SCL 1133 -MX6Q_PAD_CSI0_DAT9__GPIO_5_27 1134 -MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 1135 -MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 1136 -MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 1137 -MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 1138 -MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 1139 -MX6Q_PAD_CSI0_DAT10__UART1_TXD 1140 -MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 1141 -MX6Q_PAD_CSI0_DAT10__GPIO_5_28 1142 -MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 1143 -MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 1144 -MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 1145 -MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 1146 -MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 1147 -MX6Q_PAD_CSI0_DAT11__UART1_RXD 1148 -MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 1149 -MX6Q_PAD_CSI0_DAT11__GPIO_5_29 1150 -MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 1151 -MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 1152 -MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 1153 -MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 1154 -MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 1155 -MX6Q_PAD_CSI0_DAT12__UART4_TXD 1156 -MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 1157 -MX6Q_PAD_CSI0_DAT12__GPIO_5_30 1158 -MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 1159 -MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 1160 -MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 1161 -MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 1162 -MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 1163 -MX6Q_PAD_CSI0_DAT13__UART4_RXD 1164 -MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 1165 -MX6Q_PAD_CSI0_DAT13__GPIO_5_31 1166 -MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 1167 -MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 1168 -MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 1169 -MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 1170 -MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 1171 -MX6Q_PAD_CSI0_DAT14__UART5_TXD 1172 -MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 1173 -MX6Q_PAD_CSI0_DAT14__GPIO_6_0 1174 -MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 1175 -MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 1176 -MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 1177 -MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 1178 -MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 1179 -MX6Q_PAD_CSI0_DAT15__UART5_RXD 1180 -MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 1181 -MX6Q_PAD_CSI0_DAT15__GPIO_6_1 1182 -MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 1183 -MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 1184 -MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 1185 -MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 1186 -MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 1187 -MX6Q_PAD_CSI0_DAT16__UART4_RTS 1188 -MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 1189 -MX6Q_PAD_CSI0_DAT16__GPIO_6_2 1190 -MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 1191 -MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 1192 -MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 1193 -MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 1194 -MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 1195 -MX6Q_PAD_CSI0_DAT17__UART4_CTS 1196 -MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 1197 -MX6Q_PAD_CSI0_DAT17__GPIO_6_3 1198 -MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 1199 -MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 1200 -MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 1201 -MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 1202 -MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 1203 -MX6Q_PAD_CSI0_DAT18__UART5_RTS 1204 -MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 1205 -MX6Q_PAD_CSI0_DAT18__GPIO_6_4 1206 -MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 1207 -MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 1208 -MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 1209 -MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 1210 -MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 1211 -MX6Q_PAD_CSI0_DAT19__UART5_CTS 1212 -MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 1213 -MX6Q_PAD_CSI0_DAT19__GPIO_6_5 1214 -MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 1215 -MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 1216 -MX6Q_PAD_JTAG_TMS__SJC_TMS 1217 -MX6Q_PAD_JTAG_MOD__SJC_MOD 1218 -MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB 1219 -MX6Q_PAD_JTAG_TDI__SJC_TDI 1220 -MX6Q_PAD_JTAG_TCK__SJC_TCK 1221 -MX6Q_PAD_JTAG_TDO__SJC_TDO 1222 -MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 1223 -MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 1224 -MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 1225 -MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 1226 -MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 1227 -MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 1228 -MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 1229 -MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 1230 -MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 1231 -MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 1232 -MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 1233 -MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM 1234 -MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ 1235 -MX6Q_PAD_POR_B__SRC_POR_B 1236 -MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 1237 -MX6Q_PAD_RESET_IN_B__SRC_RESET_B 1238 -MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 1239 -MX6Q_PAD_TEST_MODE__TCU_TEST_MODE 1240 -MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 1241 -MX6Q_PAD_SD3_DAT7__UART1_TXD 1242 -MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 1243 -MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 1244 -MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 1245 -MX6Q_PAD_SD3_DAT7__GPIO_6_17 1246 -MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 1247 -MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV 1248 -MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 1249 -MX6Q_PAD_SD3_DAT6__UART1_RXD 1250 -MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 1251 -MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 1252 -MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 1253 -MX6Q_PAD_SD3_DAT6__GPIO_6_18 1254 -MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 1255 -MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 1256 -MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 1257 -MX6Q_PAD_SD3_DAT5__UART2_TXD 1258 -MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 1259 -MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 1260 -MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 1261 -MX6Q_PAD_SD3_DAT5__GPIO_7_0 1262 -MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 1263 -MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 1264 -MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 1265 -MX6Q_PAD_SD3_DAT4__UART2_RXD 1266 -MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 1267 -MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 1268 -MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 1269 -MX6Q_PAD_SD3_DAT4__GPIO_7_1 1270 -MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 1271 -MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 1272 -MX6Q_PAD_SD3_CMD__USDHC3_CMD 1273 -MX6Q_PAD_SD3_CMD__UART2_CTS 1274 -MX6Q_PAD_SD3_CMD__CAN1_TXCAN 1275 -MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 1276 -MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 1277 -MX6Q_PAD_SD3_CMD__GPIO_7_2 1278 -MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 1279 -MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 1280 -MX6Q_PAD_SD3_CLK__USDHC3_CLK 1281 -MX6Q_PAD_SD3_CLK__UART2_RTS 1282 -MX6Q_PAD_SD3_CLK__CAN1_RXCAN 1283 -MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 1284 -MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 1285 -MX6Q_PAD_SD3_CLK__GPIO_7_3 1286 -MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 1287 -MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 1288 -MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 1289 -MX6Q_PAD_SD3_DAT0__UART1_CTS 1290 -MX6Q_PAD_SD3_DAT0__CAN2_TXCAN 1291 -MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 1292 -MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 1293 -MX6Q_PAD_SD3_DAT0__GPIO_7_4 1294 -MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 1295 -MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 1296 -MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 1297 -MX6Q_PAD_SD3_DAT1__UART1_RTS 1298 -MX6Q_PAD_SD3_DAT1__CAN2_RXCAN 1299 -MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 1300 -MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 1301 -MX6Q_PAD_SD3_DAT1__GPIO_7_5 1302 -MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 1303 -MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 1304 -MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 1305 -MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 1306 -MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 1307 -MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 1308 -MX6Q_PAD_SD3_DAT2__GPIO_7_6 1309 -MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 1310 -MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 1311 -MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 1312 -MX6Q_PAD_SD3_DAT3__UART3_CTS 1313 -MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 1314 -MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 1315 -MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 1316 -MX6Q_PAD_SD3_DAT3__GPIO_7_7 1317 -MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 1318 -MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 1319 -MX6Q_PAD_SD3_RST__USDHC3_RST 1320 -MX6Q_PAD_SD3_RST__UART3_RTS 1321 -MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 1322 -MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 1323 -MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 1324 -MX6Q_PAD_SD3_RST__GPIO_7_8 1325 -MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 1326 -MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 1327 -MX6Q_PAD_NANDF_CLE__RAWNAND_CLE 1328 -MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 1329 -MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 1330 -MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 1331 -MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 1332 -MX6Q_PAD_NANDF_CLE__GPIO_6_7 1333 -MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 1334 -MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 1335 -MX6Q_PAD_NANDF_ALE__RAWNAND_ALE 1336 -MX6Q_PAD_NANDF_ALE__USDHC4_RST 1337 -MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 1338 -MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 1339 -MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 1340 -MX6Q_PAD_NANDF_ALE__GPIO_6_8 1341 -MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 1342 -MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 1343 -MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN 1344 -MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 1345 -MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 1346 -MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 1347 -MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 1348 -MX6Q_PAD_NANDF_WP_B__GPIO_6_9 1349 -MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 1350 -MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 1351 -MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 1352 -MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 1353 -MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 1354 -MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 1355 -MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 1356 -MX6Q_PAD_NANDF_RB0__GPIO_6_10 1357 -MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 1358 -MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 1359 -MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N 1360 -MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 1361 -MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 1362 -MX6Q_PAD_NANDF_CS0__GPIO_6_11 1363 -MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 1364 -MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N 1365 -MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT 1366 -MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT 1367 -MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 1368 -MX6Q_PAD_NANDF_CS1__GPIO_6_14 1369 -MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT 1370 -MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N 1371 -MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 1372 -MX6Q_PAD_NANDF_CS2__ESAI1_TX0 1373 -MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE 1374 -MX6Q_PAD_NANDF_CS2__CCM_CLKO2 1375 -MX6Q_PAD_NANDF_CS2__GPIO_6_15 1376 -MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 1377 -MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N 1378 -MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 1379 -MX6Q_PAD_NANDF_CS3__ESAI1_TX1 1380 -MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 1381 -MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 1382 -MX6Q_PAD_NANDF_CS3__GPIO_6_16 1383 -MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 1384 -MX6Q_PAD_NANDF_CS3__TPSMP_CLK 1385 -MX6Q_PAD_SD4_CMD__USDHC4_CMD 1386 -MX6Q_PAD_SD4_CMD__RAWNAND_RDN 1387 -MX6Q_PAD_SD4_CMD__UART3_TXD 1388 -MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 1389 -MX6Q_PAD_SD4_CMD__GPIO_7_9 1390 -MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR 1391 -MX6Q_PAD_SD4_CLK__USDHC4_CLK 1392 -MX6Q_PAD_SD4_CLK__RAWNAND_WRN 1393 -MX6Q_PAD_SD4_CLK__UART3_RXD 1394 -MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 1395 -MX6Q_PAD_SD4_CLK__GPIO_7_10 1396 -MX6Q_PAD_NANDF_D0__RAWNAND_D0 1397 -MX6Q_PAD_NANDF_D0__USDHC1_DAT4 1398 -MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 1399 -MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 1400 -MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 1401 -MX6Q_PAD_NANDF_D0__GPIO_2_0 1402 -MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 1403 -MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 1404 -MX6Q_PAD_NANDF_D1__RAWNAND_D1 1405 -MX6Q_PAD_NANDF_D1__USDHC1_DAT5 1406 -MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 1407 -MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 1408 -MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 1409 -MX6Q_PAD_NANDF_D1__GPIO_2_1 1410 -MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 1411 -MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 1412 -MX6Q_PAD_NANDF_D2__RAWNAND_D2 1413 -MX6Q_PAD_NANDF_D2__USDHC1_DAT6 1414 -MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 1415 -MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 1416 -MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 1417 -MX6Q_PAD_NANDF_D2__GPIO_2_2 1418 -MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 1419 -MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 1420 -MX6Q_PAD_NANDF_D3__RAWNAND_D3 1421 -MX6Q_PAD_NANDF_D3__USDHC1_DAT7 1422 -MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 1423 -MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 1424 -MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 1425 -MX6Q_PAD_NANDF_D3__GPIO_2_3 1426 -MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 1427 -MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 1428 -MX6Q_PAD_NANDF_D4__RAWNAND_D4 1429 -MX6Q_PAD_NANDF_D4__USDHC2_DAT4 1430 -MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 1431 -MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 1432 -MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 1433 -MX6Q_PAD_NANDF_D4__GPIO_2_4 1434 -MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 1435 -MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 1436 -MX6Q_PAD_NANDF_D5__RAWNAND_D5 1437 -MX6Q_PAD_NANDF_D5__USDHC2_DAT5 1438 -MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 1439 -MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 1440 -MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 1441 -MX6Q_PAD_NANDF_D5__GPIO_2_5 1442 -MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 1443 -MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 1444 -MX6Q_PAD_NANDF_D6__RAWNAND_D6 1445 -MX6Q_PAD_NANDF_D6__USDHC2_DAT6 1446 -MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 1447 -MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 1448 -MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 1449 -MX6Q_PAD_NANDF_D6__GPIO_2_6 1450 -MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 1451 -MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 1452 -MX6Q_PAD_NANDF_D7__RAWNAND_D7 1453 -MX6Q_PAD_NANDF_D7__USDHC2_DAT7 1454 -MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 1455 -MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 1456 -MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 1457 -MX6Q_PAD_NANDF_D7__GPIO_2_7 1458 -MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 1459 -MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 1460 -MX6Q_PAD_SD4_DAT0__RAWNAND_D8 1461 -MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 1462 -MX6Q_PAD_SD4_DAT0__RAWNAND_DQS 1463 -MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 1464 -MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 1465 -MX6Q_PAD_SD4_DAT0__GPIO_2_8 1466 -MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 1467 -MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 1468 -MX6Q_PAD_SD4_DAT1__RAWNAND_D9 1469 -MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 1470 -MX6Q_PAD_SD4_DAT1__PWM3_PWMO 1471 -MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 1472 -MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 1473 -MX6Q_PAD_SD4_DAT1__GPIO_2_9 1474 -MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 1475 -MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 1476 -MX6Q_PAD_SD4_DAT2__RAWNAND_D10 1477 -MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 1478 -MX6Q_PAD_SD4_DAT2__PWM4_PWMO 1479 -MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 1480 -MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 1481 -MX6Q_PAD_SD4_DAT2__GPIO_2_10 1482 -MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 1483 -MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 1484 -MX6Q_PAD_SD4_DAT3__RAWNAND_D11 1485 -MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 1486 -MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 1487 -MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 1488 -MX6Q_PAD_SD4_DAT3__GPIO_2_11 1489 -MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 1490 -MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 1491 -MX6Q_PAD_SD4_DAT4__RAWNAND_D12 1492 -MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 1493 -MX6Q_PAD_SD4_DAT4__UART2_RXD 1494 -MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 1495 -MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 1496 -MX6Q_PAD_SD4_DAT4__GPIO_2_12 1497 -MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 1498 -MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 1499 -MX6Q_PAD_SD4_DAT5__RAWNAND_D13 1500 -MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 1501 -MX6Q_PAD_SD4_DAT5__UART2_RTS 1502 -MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 1503 -MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 1504 -MX6Q_PAD_SD4_DAT5__GPIO_2_13 1505 -MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 1506 -MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 1507 -MX6Q_PAD_SD4_DAT6__RAWNAND_D14 1508 -MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 1509 -MX6Q_PAD_SD4_DAT6__UART2_CTS 1510 -MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 1511 -MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 1512 -MX6Q_PAD_SD4_DAT6__GPIO_2_14 1513 -MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 1514 -MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 1515 -MX6Q_PAD_SD4_DAT7__RAWNAND_D15 1516 -MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 1517 -MX6Q_PAD_SD4_DAT7__UART2_TXD 1518 -MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 1519 -MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 1520 -MX6Q_PAD_SD4_DAT7__GPIO_2_15 1521 -MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 1522 -MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 1523 -MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 1524 -MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 1525 -MX6Q_PAD_SD1_DAT1__PWM3_PWMO 1526 -MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 1527 -MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 1528 -MX6Q_PAD_SD1_DAT1__GPIO_1_17 1529 -MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 1530 -MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 1531 -MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 1532 -MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 1533 -MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS 1534 -MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 1535 -MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 1536 -MX6Q_PAD_SD1_DAT0__GPIO_1_16 1537 -MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 1538 -MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 1539 -MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 1540 -MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 1541 -MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 1542 -MX6Q_PAD_SD1_DAT3__PWM1_PWMO 1543 -MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B 1544 -MX6Q_PAD_SD1_DAT3__GPIO_1_21 1545 -MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB 1546 -MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 1547 -MX6Q_PAD_SD1_CMD__USDHC1_CMD 1548 -MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 1549 -MX6Q_PAD_SD1_CMD__PWM4_PWMO 1550 -MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 1551 -MX6Q_PAD_SD1_CMD__GPIO_1_18 1552 -MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 1553 -MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 1554 -MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 1555 -MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 1556 -MX6Q_PAD_SD1_DAT2__PWM2_PWMO 1557 -MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B 1558 -MX6Q_PAD_SD1_DAT2__GPIO_1_19 1559 -MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB 1560 -MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 1561 -MX6Q_PAD_SD1_CLK__USDHC1_CLK 1562 -MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 1563 -MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT 1564 -MX6Q_PAD_SD1_CLK__GPT_CLKIN 1565 -MX6Q_PAD_SD1_CLK__GPIO_1_20 1566 -MX6Q_PAD_SD1_CLK__PHY_DTB_0 1567 -MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 1568 -MX6Q_PAD_SD2_CLK__USDHC2_CLK 1569 -MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 1570 -MX6Q_PAD_SD2_CLK__KPP_COL_5 1571 -MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1572 -MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 1573 -MX6Q_PAD_SD2_CLK__GPIO_1_10 1574 -MX6Q_PAD_SD2_CLK__PHY_DTB_1 1575 -MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 1576 -MX6Q_PAD_SD2_CMD__USDHC2_CMD 1577 -MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 1578 -MX6Q_PAD_SD2_CMD__KPP_ROW_5 1579 -MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1580 -MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 1581 -MX6Q_PAD_SD2_CMD__GPIO_1_11 1582 -MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 1583 -MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 1584 -MX6Q_PAD_SD2_DAT3__KPP_COL_6 1585 -MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC 1586 -MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587 -MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588 -MX6Q_PAD_SD2_DAT3__SJC_DONE 1589 -MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590 -MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID 1591 -MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID 1592 +Refer to imx6q-pinfunc.h in device tree source folder for all available +imx6q PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt new file mode 100644 index 00000000000..e5f6d1f065a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt @@ -0,0 +1,39 @@ +* Freescale IMX6 SoloLite IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx6sl-iomuxc" +- fsl,pins: two integers array, represents a group of pins mux and config + setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a + pin working on a specific function, CONFIG is the pad setting value like + pull-up for this pin. Please refer to imx6sl datasheet for the valid pad + config settings. + +CONFIG bits definition: +PAD_CTL_LVE (1 << 22) +PAD_CTL_HYS (1 << 16) +PAD_CTL_PUS_100K_DOWN (0 << 14) +PAD_CTL_PUS_47K_UP (1 << 14) +PAD_CTL_PUS_100K_UP (2 << 14) +PAD_CTL_PUS_22K_UP (3 << 14) +PAD_CTL_PUE (1 << 13) +PAD_CTL_PKE (1 << 12) +PAD_CTL_ODE (1 << 11) +PAD_CTL_SPEED_LOW (1 << 6) +PAD_CTL_SPEED_MED (2 << 6) +PAD_CTL_SPEED_HIGH (3 << 6) +PAD_CTL_DSE_DISABLE (0 << 3) +PAD_CTL_DSE_240ohm (1 << 3) +PAD_CTL_DSE_120ohm (2 << 3) +PAD_CTL_DSE_80ohm (3 << 3) +PAD_CTL_DSE_60ohm (4 << 3) +PAD_CTL_DSE_48ohm (5 << 3) +PAD_CTL_DSE_40ohm (6 << 3) +PAD_CTL_DSE_34ohm (7 << 3) +PAD_CTL_SRE_FAST (1 << 0) +PAD_CTL_SRE_SLOW (0 << 0) + +Refer to imx6sl-pinfunc.h in device tree source folder for all available +imx6sl PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt index f7e8e8f4d9a..3077370c89a 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt @@ -70,6 +70,10 @@ Optional subnode-properties: 0: Disable the internal pull-up 1: Enable the internal pull-up +Note that when enabling the pull-up, the internal pad keeper gets disabled. +Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up +will only disable the internal pad keeper. + Examples: pinctrl@80018000 { diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 2c81e45f137..08f0c3d0157 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -1,7 +1,9 @@ One-register-per-pin type device tree based pinctrl driver Required properties: -- compatible : "pinctrl-single" +- compatible : "pinctrl-single" or "pinconf-single". + "pinctrl-single" means that pinconf isn't supported. + "pinconf-single" means that generic pinconf is supported. - reg : offset and length of the register set for the mux registers @@ -14,9 +16,61 @@ Optional properties: - pinctrl-single,function-off : function off mode for disabled state if available and same for all registers; if not specified, disabling of pin functions is ignored + - pinctrl-single,bit-per-mux : boolean to indicate that one register controls more than one pin +- pinctrl-single,drive-strength : array of value that are used to configure + drive strength in the pinmux register. They're value of drive strength + current and drive strength mask. + + /* drive strength current, mask */ + pinctrl-single,power-source = <0x30 0xf0>; + +- pinctrl-single,bias-pullup : array of value that are used to configure the + input bias pullup in the pinmux register. + + /* input, enabled pullup bits, disabled pullup bits, mask */ + pinctrl-single,bias-pullup = <0 1 0 1>; + +- pinctrl-single,bias-pulldown : array of value that are used to configure the + input bias pulldown in the pinmux register. + + /* input, enabled pulldown bits, disabled pulldown bits, mask */ + pinctrl-single,bias-pulldown = <2 2 0 2>; + + * Two bits to control input bias pullup and pulldown: User should use + pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means + pullup, and the other one bit means pulldown. + * Three bits to control input bias enable, pullup and pulldown. User should + use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias + enable bit should be included in pullup or pulldown bits. + * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as + pinctrl-single,bias-disable. Because pinctrl single driver could implement + it by calling pulldown, pullup disabled. + +- pinctrl-single,input-schmitt : array of value that are used to configure + input schmitt in the pinmux register. In some silicons, there're two input + schmitt value (rising-edge & falling-edge) in the pinmux register. + + /* input schmitt value, mask */ + pinctrl-single,input-schmitt = <0x30 0x70>; + +- pinctrl-single,input-schmitt-enable : array of value that are used to + configure input schmitt enable or disable in the pinmux register. + + /* input, enable bits, disable bits, mask */ + pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>; + +- pinctrl-single,gpio-range : list of value that are used to configure a GPIO + range. They're value of subnode phandle, pin base in pinctrl device, pin + number in this range, GPIO function value of this GPIO range. + The number of parameters is depend on #pinctrl-single,gpio-range-cells + property. + + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>; + This driver assumes that there is only one register for each pin (unless the pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt document in this directory. @@ -42,6 +96,20 @@ Where 0xdc is the offset from the pinctrl register base address for the device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to be used when applying this change to the register. + +Optional sub-node: In case some pins could be configured as GPIO in the pinmux +register, those pins could be defined as a GPIO range. This sub-node is required +by pinctrl-single,gpio-range property. + +Required properties in sub-node: +- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in + pinctrl-single,gpio-range property. + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + + Example: /* SoC common file */ @@ -58,7 +126,7 @@ pmx_core: pinmux@4a100040 { /* second controller instance for pins in wkup domain */ pmx_wkup: pinmux@4a31e040 { - compatible = "pinctrl-single; + compatible = "pinctrl-single"; reg = <0x4a31e040 0x0038>; #address-cells = <1>; #size-cells = <0>; @@ -76,6 +144,29 @@ control_devconf0: pinmux@48002274 { pinctrl-single,function-mask = <0x5F>; }; +/* third controller instance for pins in gpio domain */ +pmx_gpio: pinmux@d401e000 { + compatible = "pinconf-single"; + reg = <0xd401e000 0x0330>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + + /* sparse GPIO range could be supported */ + pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 + &range 12 1 0 &range 13 29 1 + &range 43 1 0 &range 44 49 1 + &range 94 1 1 &range 96 2 1>; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; +}; + + /* board specific .dts file */ &pmx_core { @@ -96,6 +187,15 @@ control_devconf0: pinmux@48002274 { >; }; + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x208 0 /* UART0_RXD (IOCFG138) */ + 0x20c 0 /* UART0_TXD (IOCFG139) */ + >; + pinctrl-single,bias-pulldown = <0 2 2>; + pinctrl-single,bias-pullup = <0 1 1>; + }; + /* map uart2 pins */ uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < @@ -122,6 +222,11 @@ control_devconf0: pinmux@48002274 { }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt new file mode 100644 index 00000000000..b3aa90f0ce4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt @@ -0,0 +1,57 @@ +VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller + +These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as +either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc). + +Required properties: +- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl", + "wm8750-pinctrl" or "wm,wm8850-pinctrl" +- reg: Should contain the physical address of the module's registers. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be two. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional parameters. + bit 0 - active low + +Please refer to ../gpio/gpio.txt for a general description of GPIO bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Each pin configuration node lists the pin(s) to which it applies, and one or +more of the mux functions to select on those pin(s), and pull-up/down +configuration. Each subnode only affects those parameters that are explicitly +listed. In other words, a subnode that lists only a mux function implies no +information about any pull configuration. Similarly, a subnode that lists only +a pull parameter implies no information about the mux function. + +Required subnode-properties: +- wm,pins: An array of cells. Each cell contains the ID of a pin. + +Optional subnode-properties: +- wm,function: Integer, containing the function to mux to the pin(s): + 0: GPIO in + 1: GPIO out + 2: alternate + +- wm,pull: Integer, representing the pull-down/up to apply to the pin(s): + 0: none + 1: down + 2: up + +Each of wm,function and wm,pull may contain either a single value which +will be applied to all pins in wm,pins, or one value for each entry in +wm,pins. + +Example: + + pinctrl: pinctrl { + compatible = "wm,wm8505-pinctrl"; + reg = <0xD8110000 0x10000>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 4598a47aa0c..c70fca146e9 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -7,6 +7,7 @@ on-chip controllers onto these pads. Required Properties: - compatible: should be one of the following. + - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. @@ -105,6 +106,8 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a - compatible: identifies the type of the external wakeup interrupt controller The possible values are: + - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller + found on Samsung S3C64xx SoCs, - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller found on Samsung Exynos4210 SoC. - interrupt-parent: phandle of the interrupt parent to which the external diff --git a/Documentation/devicetree/bindings/power_supply/power_supply.txt b/Documentation/devicetree/bindings/power_supply/power_supply.txt new file mode 100644 index 00000000000..8391bfa0eda --- /dev/null +++ b/Documentation/devicetree/bindings/power_supply/power_supply.txt @@ -0,0 +1,23 @@ +Power Supply Core Support + +Optional Properties: + - power-supplies : This property is added to a supply in order to list the + devices which supply it power, referenced by their phandles. + +Example: + + usb-charger: power@e { + compatible = "some,usb-charger"; + ... + }; + + ac-charger: power@c { + compatible = "some,ac-charger"; + ... + }; + + battery@b { + compatible = "some,battery"; + ... + power-supplies = <&usb-charger>, <&ac-charger>; + }; diff --git a/Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt b/Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt index 9a599d27bd7..0347d8350d9 100644 --- a/Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt +++ b/Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt @@ -2,7 +2,7 @@ QNAP NAS devices have a microcontroller controlling the main power supply. This microcontroller is connected to UART1 of the Kirkwood and -Orion5x SoCs. Sending the charactor 'A', at 19200 baud, tells the +Orion5x SoCs. Sending the character 'A', at 19200 baud, tells the microcontroller to turn the power off. This driver adds a handler to pm_power_off which is called to turn the power off. diff --git a/Documentation/devicetree/bindings/power_supply/tps65090.txt b/Documentation/devicetree/bindings/power_supply/tps65090.txt new file mode 100644 index 00000000000..8e5e0d3910d --- /dev/null +++ b/Documentation/devicetree/bindings/power_supply/tps65090.txt @@ -0,0 +1,17 @@ +TPS65090 Frontend PMU with Switchmode Charger + +Required Properties: +-compatible: "ti,tps65090-charger" + +Optional Properties: +-ti,enable-low-current-chrg: Enables charging when a low current is detected + while the default logic is to stop charging. + +This node is a subnode of the tps65090 PMIC. + +Example: + + tps65090-charger { + compatible = "ti,tps65090-charger"; + ti,enable-low-current-chrg; + }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt new file mode 100644 index 00000000000..922c30ad90d --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt @@ -0,0 +1,22 @@ +=================================================================== +Power Architecture CPU Binding +Copyright 2013 Freescale Semiconductor Inc. + +Power Architecture CPUs in Freescale SOCs are represented in device trees as +per the definition in ePAPR. + +In addition to the ePAPR definitions, the properties defined below may be +present on CPU nodes. + +PROPERTIES + + - fsl,eref-* + Usage: optional + Value type: <empty> + Definition: The EREF (EREF: A Programmer.s Reference Manual for + Freescale Power Architecture) defines the architecture for Freescale + Power CPUs. The EREF defines some architecture categories not defined + by the Power ISA. For these EREF-specific categories, the existence of + a property named fsl,eref-[CAT], where [CAT] is the abbreviated category + name with all uppercase letters converted to lowercase, indicates that + the category is supported by the implementation. diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt new file mode 100644 index 00000000000..ac67c687a32 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt @@ -0,0 +1,43 @@ +* Samsung PWM timers + +Samsung SoCs contain PWM timer blocks which can be used for system clock source +and clock event timers, as well as to drive SoC outputs with PWM signal. Each +PWM timer block provides 5 PWM channels (not all of them can drive physical +outputs - see SoC and board manual). + +Be aware that the clocksource driver supports only uniprocessor systems. + +Required properties: +- compatible : should be one of following: + samsung,s3c2410-pwm - for 16-bit timers present on S3C24xx SoCs + samsung,s3c6400-pwm - for 32-bit timers present on S3C64xx SoCs + samsung,s5p6440-pwm - for 32-bit timers present on S5P64x0 SoCs + samsung,s5pc100-pwm - for 32-bit timers present on S5PC100, S5PV210, + Exynos4210 rev0 SoCs + samsung,exynos4210-pwm - for 32-bit timers present on Exynos4210, + Exynos4x12 and Exynos5250 SoCs +- reg: base address and size of register area +- interrupts: list of timer interrupts (one interrupt per timer, starting at + timer 0) +- #pwm-cells: number of cells used for PWM specifier - must be 3 + the specifier format is as follows: + - phandle to PWM controller node + - index of PWM channel (from 0 to 4) + - PWM signal period in nanoseconds + - bitmask of optional PWM flags: + 0x1 - invert PWM signal + +Optional properties: +- samsung,pwm-outputs: list of PWM channels used as PWM outputs on particular + platform - an array of up to 5 elements being indices of PWM channels + (from 0 to 4), the order does not matter. + +Example: + pwm@7f006000 { + compatible = "samsung,s3c6400-pwm"; + reg = <0x7f006000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <23>, <24>, <25>, <27>, <28>; + samsung,pwm-outputs = <0>, <1>; + #pwm-cells = <3>; + } diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index 131e8c11d26..681afad7377 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -1,7 +1,9 @@ TI SOC ECAP based APWM controller Required properties: -- compatible: Must be "ti,am33xx-ecap" +- compatible: Must be "ti,<soc>-ecap". + for am33xx - compatible = "ti,am33xx-ecap"; + for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; - #pwm-cells: Should be 3. Number of cells being used to specify PWM property. First cell specifies the per-chip index of the PWM to use, the second cell is the period in nanoseconds and bit 0 in the third cell is used to @@ -15,9 +17,15 @@ Optional properties: Example: -ecap0: ecap@0 { +ecap0: ecap@0 { /* ECAP on am33xx */ compatible = "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; }; + +ecap0: ecap@0 { /* ECAP on da850 */ + compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x306000 0x80>; +}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index 4fc7079d822..337c6fc65d3 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -1,7 +1,9 @@ TI SOC EHRPWM based PWM controller Required properties: -- compatible : Must be "ti,am33xx-ehrpwm" +- compatible: Must be "ti,<soc>-ehrpwm". + for am33xx - compatible = "ti,am33xx-ehrpwm"; + for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells: Should be 3. Number of cells being used to specify PWM property. First cell specifies the per-chip index of the PWM to use, the second cell is the period in nanoseconds and bit 0 in the third cell is used to @@ -15,9 +17,15 @@ Optional properties: Example: -ehrpwm0: ehrpwm@0 { +ehrpwm0: ehrpwm@0 { /* EHRPWM on am33xx */ compatible = "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x100>; ti,hwmods = "ehrpwm0"; }; + +ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */ + compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x300000 0x2000>; +}; diff --git a/Documentation/devicetree/bindings/regulator/max8952.txt b/Documentation/devicetree/bindings/regulator/max8952.txt new file mode 100644 index 00000000000..866fcdd0f4e --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/max8952.txt @@ -0,0 +1,52 @@ +Maxim MAX8952 voltage regulator + +Required properties: +- compatible: must be equal to "maxim,max8952" +- reg: I2C slave address, usually 0x60 +- max8952,dvs-mode-microvolt: array of 4 integer values defining DVS voltages + in microvolts. All values must be from range <770000, 1400000> +- any required generic properties defined in regulator.txt + +Optional properties: +- max8952,vid-gpios: array of two GPIO pins used for DVS voltage selection +- max8952,en-gpio: GPIO used to control enable status of regulator +- max8952,default-mode: index of default DVS voltage, from <0, 3> range +- max8952,sync-freq: sync frequency, must be one of following values: + - 0: 26 MHz + - 1: 13 MHz + - 2: 19.2 MHz + Defaults to 26 MHz if not specified. +- max8952,ramp-speed: voltage ramp speed, must be one of following values: + - 0: 32mV/us + - 1: 16mV/us + - 2: 8mV/us + - 3: 4mV/us + - 4: 2mV/us + - 5: 1mV/us + - 6: 0.5mV/us + - 7: 0.25mV/us + Defaults to 32mV/us if not specified. +- any available generic properties defined in regulator.txt + +Example: + + vdd_arm_reg: pmic@60 { + compatible = "maxim,max8952"; + reg = <0x60>; + + /* max8952-specific properties */ + max8952,vid-gpios = <&gpx0 3 0>, <&gpx0 4 0>; + max8952,en-gpio = <&gpx0 1 0>; + max8952,default-mode = <0>; + max8952,dvs-mode-microvolt = <1250000>, <1200000>, + <1050000>, <950000>; + max8952,sync-freq = <0>; + max8952,ramp-speed = <0>; + + /* generic regulator properties */ + regulator-name = "vdd_arm"; + regulator-min-microvolt = <770000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; diff --git a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt index 9fd69a18b0b..9e5e51d7886 100644 --- a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt @@ -28,7 +28,7 @@ Required properties: safe operating voltage). If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional - property is specified, then all the eigth voltage values for the + property is specified, then all the eight voltage values for the 'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified. Optional properties: diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt new file mode 100644 index 00000000000..13301777e11 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt @@ -0,0 +1,49 @@ +Freescale i.MX System Reset Controller +====================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "fsl,<chip>-src" +- reg: should be register base and length as documented in the + datasheet +- interrupts: Should contain SRC interrupt and CPU WDOG interrupt, + in this order. +- #reset-cells: 1, see below + +example: + +src: src@020d8000 { + compatible = "fsl,imx6q-src"; + reg = <0x020d8000 0x4000>; + interrupts = <0 91 0x04 0 96 0x04>; + #reset-cells = <1>; +}; + +Specifying reset lines connected to IP modules +============================================== + +The system reset controller can be used to reset the GPU, VPU, +IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device +nodes should specify the reset line on the SRC in their resets +property, containing a phandle to the SRC device node and a +RESET_INDEX specifying which module to reset, as described in +reset.txt + +example: + + ipu1: ipu@02400000 { + resets = <&src 2>; + }; + ipu2: ipu@02800000 { + resets = <&src 4>; + }; + +The following RESET_INDEX values are valid for i.MX5: +GPU_RESET 0 +VPU_RESET 1 +IPU1_RESET 2 +OPEN_VG_RESET 3 +The following additional RESET_INDEX value is valid for i.MX6: +IPU2_RESET 4 diff --git a/Documentation/devicetree/bindings/reset/reset.txt b/Documentation/devicetree/bindings/reset/reset.txt new file mode 100644 index 00000000000..31db6ff8490 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/reset.txt @@ -0,0 +1,75 @@ += Reset Signal Device Tree Bindings = + +This binding is intended to represent the hardware reset signals present +internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole +standalone chips are most likely better represented as GPIOs, although there +are likely to be exceptions to this rule. + +Hardware blocks typically receive a reset signal. This signal is generated by +a reset provider (e.g. power management or clock module) and received by a +reset consumer (the module being reset, or a module managing when a sub- +ordinate module is reset). This binding exists to represent the provider and +consumer, and provide a way to couple the two together. + +A reset signal is represented by the phandle of the provider, plus a reset +specifier - a list of DT cells that represents the reset signal within the +provider. The length (number of cells) and semantics of the reset specifier +are dictated by the binding of the reset provider, although common schemes +are described below. + +A word on where to place reset signal consumers in device tree: It is possible +in hardware for a reset signal to affect multiple logically separate HW blocks +at once. In this case, it would be unwise to represent this reset signal in +the DT node of each affected HW block, since if activated, an unrelated block +may be reset. Instead, reset signals should be represented in the DT node +where it makes most sense to control it; this may be a bus node if all +children of the bus are affected by the reset signal, or an individual HW +block node for dedicated reset signals. The intent of this binding is to give +appropriate software access to the reset signals in order to manage the HW, +rather than to slavishly enumerate the reset signal that affects each HW +block. + += Reset providers = + +Required properties: +#reset-cells: Number of cells in a reset specifier; Typically 0 for nodes + with a single reset output and 1 for nodes with multiple + reset outputs. + +For example: + + rst: reset-controller { + #reset-cells = <1>; + }; + += Reset consumers = + +Required properties: +resets: List of phandle and reset specifier pairs, one pair + for each reset signal that affects the device, or that the + device manages. Note: if the reset provider specifies '0' for + #reset-cells, then only the phandle portion of the pair will + appear. + +Optional properties: +reset-names: List of reset signal name strings sorted in the same order as + the resets property. Consumers drivers will use reset-names to + match reset signal names with reset specifiers. + +For example: + + device { + resets = <&rst 20>; + reset-names = "reset"; + }; + +This represents a device with a single reset signal named "reset". + + bus { + resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>; + reset-names = "i2s1", "i2s2", "dma", "mixer"; + }; + +This represents a bus that controls the reset signal of each of four sub- +ordinate devices. Consider for example a bus that fails to operate unless no +child device has reset asserted. diff --git a/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt b/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt new file mode 100644 index 00000000000..07ccdaa6832 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt @@ -0,0 +1,13 @@ +BCM2835 Random number generator + +Required properties: + +- compatible : should be "brcm,bcm2835-rng" +- reg : Specifies base physical address and size of the registers. + +Example: + +rng { + compatible = "brcm,bcm2835-rng"; + reg = <0x7e104000 0x10>; +}; diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt new file mode 100644 index 00000000000..2a3feabd3b2 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt @@ -0,0 +1,15 @@ +Atmel AT91RM9200 Real Time Clock + +Required properties: +- compatible: should be: "atmel,at91rm9200-rtc" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: rtc alarm/event interrupt + +Example: + +rtc@fffffe00 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffe00 0x100>; + interrupts = <1 4 7>; +}; diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt new file mode 100644 index 00000000000..5d2e840ae65 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/pl011.txt @@ -0,0 +1,17 @@ +* ARM AMBA Primecell PL011 serial UART + +Required properties: +- compatible: must be "arm,primecell", "arm,pl011" +- reg: exactly one register range with length 0x1000 +- interrupts: exactly one interrupt specifier + +Optional properties: +- pinctrl: When present, must have one state named "sleep" + and one state named "default" +- clocks: When present, must refer to exactly one clock named + "apb_pclk" +- dmas: When present, may have one or two dma channels. + The first one must be named "rx", the second one + must be named "tx". + +See also bindings/arm/primecell.txt diff --git a/Documentation/devicetree/bindings/serio/snps-arc_ps2.txt b/Documentation/devicetree/bindings/serio/snps-arc_ps2.txt new file mode 100644 index 00000000000..38c2f21e804 --- /dev/null +++ b/Documentation/devicetree/bindings/serio/snps-arc_ps2.txt @@ -0,0 +1,16 @@ +* ARC PS/2 driver: PS/2 block used in some ARC FPGA's & nSIM OSCI model + +Required properties: +- compatible : "snps,arc_ps2" +- reg : offset and length (always 0x14) of registers +- interrupts : interrupt +- interrupt-names : name of interrupt, must be "arc_ps2_irq" + +Example: + +serio@c9000400 { + compatible = "snps,arc_ps2"; + reg = <0xc9000400 0x14>; + interrupts = <13>; + interrupt-names = "arc_ps2_irq"; +} diff --git a/Documentation/devicetree/bindings/sound/ak5386.txt b/Documentation/devicetree/bindings/sound/ak5386.txt new file mode 100644 index 00000000000..dc3914fe6ce --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ak5386.txt @@ -0,0 +1,19 @@ +AK5386 Single-ended 24-Bit 192kHz delta-sigma ADC + +This device has no control interface. + +Required properties: + + - compatible : "asahi-kasei,ak5386" + +Optional properties: + + - reset-gpio : a GPIO spec for the reset/power down pin. + If specified, it will be deasserted at probe time. + +Example: + +spdif: ak5386@0 { + compatible = "asahi-kasei,ak5386"; + reset-gpio = <&gpio0 23>; +}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt index b77a97c9101..05ffecb5710 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt @@ -2,6 +2,11 @@ NVIDIA Tegra audio complex Required properties: - compatible : "nvidia,tegra-audio-alc5632" +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Must include the following entries: + "pll_a" (The Tegra clock of that name), + "pll_a_out0" (The Tegra clock of that name), + "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) - nvidia,model : The user-visible name of this sound complex. - nvidia,audio-routing : A list of the connections between audio components. Each entry is a pair of strings, the first being the connection's sink, @@ -56,4 +61,7 @@ sound { nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&alc5632>; + + clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; + clock-names = "pll_a", "pll_a_out0", "mclk"; }; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt index 04b14cfb1f1..ef1fe735827 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt @@ -2,6 +2,11 @@ NVIDIA Tegra audio complex for TrimSlice Required properties: - compatible : "nvidia,tegra-audio-trimslice" +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Must include the following entries: + "pll_a" (The Tegra clock of that name), + "pll_a_out0" (The Tegra clock of that name), + "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller - nvidia,audio-codec : The phandle of the WM8903 audio codec @@ -11,4 +16,6 @@ sound { compatible = "nvidia,tegra-audio-trimslice"; nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&codec>; + clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; + clock-names = "pll_a", "pll_a_out0", "mclk"; }; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt index c4dd39ce616..d14510613a7 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt @@ -2,6 +2,11 @@ NVIDIA Tegra audio complex Required properties: - compatible : "nvidia,tegra-audio-wm8753" +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Must include the following entries: + "pll_a" (The Tegra clock of that name), + "pll_a_out0" (The Tegra clock of that name), + "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) - nvidia,model : The user-visible name of this sound complex. - nvidia,audio-routing : A list of the connections between audio components. Each entry is a pair of strings, the first being the connection's sink, @@ -50,5 +55,8 @@ sound { nvidia,i2s-controller = <&i2s1>; nvidia,audio-codec = <&wm8753>; + + clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; + clock-names = "pll_a", "pll_a_out0", "mclk"; }; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt index d5b0da8bf1d..3bf722deb72 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt @@ -2,6 +2,11 @@ NVIDIA Tegra audio complex Required properties: - compatible : "nvidia,tegra-audio-wm8903" +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Must include the following entries: + "pll_a" (The Tegra clock of that name), + "pll_a_out0" (The Tegra clock of that name), + "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) - nvidia,model : The user-visible name of this sound complex. - nvidia,audio-routing : A list of the connections between audio components. Each entry is a pair of strings, the first being the connection's sink, @@ -67,5 +72,8 @@ sound { nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ + + clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; + clock-names = "pll_a", "pll_a_out0", "mclk"; }; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt index be35d34e8b2..ad589b16363 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt @@ -2,6 +2,11 @@ NVIDIA Tegra audio complex Required properties: - compatible : "nvidia,tegra-audio-wm9712" +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Must include the following entries: + "pll_a" (The Tegra clock of that name), + "pll_a_out0" (The Tegra clock of that name), + "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) - nvidia,model : The user-visible name of this sound complex. - nvidia,audio-routing : A list of the connections between audio components. Each entry is a pair of strings, the first being the connection's sink, @@ -48,4 +53,7 @@ sound { "Mic", "MIC1"; nvidia,ac97-controller = <&ac97>; + + clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; + clock-names = "pll_a", "pll_a_out0", "mclk"; }; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt index 1ac7b164218..0e5c12c6652 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt @@ -1,12 +1,22 @@ NVIDIA Tegra30 AHUB (Audio Hub) Required properties: -- compatible : "nvidia,tegra30-ahub" +- compatible : "nvidia,tegra30-ahub", "nvidia,tegra114-ahub", etc. - reg : Should contain the register physical address and length for each of - the AHUB's APBIF registers and the AHUB's own registers. + the AHUB's register blocks. + - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks. + - Tegra114 requires an additional entry, for the APBIF2 register block. - interrupts : Should contain AHUB interrupt -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and - request selector for the first APBIF channel. +- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each + entry contains the Tegra DMA controller's phandle and request selector. + If a single entry is present, the request selectors for the channels are + assumed to be contiguous, and increment from this value. + If multiple values are given, one value must be given per channel. +- clocks : Must contain an entry for each required entry in clock-names. +- clock-names : Must include the following entries: + - Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0, + dam1, dam2, spdif_in. + - Tegra114: Additionally requires amx, adx. - ranges : The bus address mapping for the configlink register bus. Can be empty since the mapping is 1:1. - #address-cells : For the configlink bus. Should be <1>; @@ -25,7 +35,13 @@ ahub@70080000 { reg = <0x70080000 0x200 0x70080200 0x100>; interrupts = < 0 103 0x04 >; nvidia,dma-request-selector = <&apbdma 1>; - + clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, + <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, + <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, + <&tegra_car 110>, <&tegra_car 162>; + clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif_in"; ranges; #address-cells = <1>; #size-cells = <1>; diff --git a/Documentation/devicetree/bindings/sound/ti,tas5086.txt b/Documentation/devicetree/bindings/sound/ti,tas5086.txt new file mode 100644 index 00000000000..8ea4f5b4818 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti,tas5086.txt @@ -0,0 +1,32 @@ +Texas Instruments TAS5086 6-channel PWM Processor + +Required properties: + + - compatible: Should contain "ti,tas5086". + - reg: The i2c address. Should contain <0x1b>. + +Optional properties: + + - reset-gpio: A GPIO spec to define which pin is connected to the + chip's !RESET pin. If specified, the driver will + assert a hardware reset at probe time. + + - ti,charge-period: This property should contain the time in microseconds + that closely matches the external single-ended + split-capacitor charge period. The hardware chip + waits for this period of time before starting the + PWM signals. This helps reduce pops and clicks. + + When not specified, the hardware default of 1300ms + is retained. + +Examples: + + i2c_bus { + tas5086@1b { + compatible = "ti,tas5086"; + reg = <0x1b>; + reset-gpio = <&gpio 23 0>; + ti,charge-period = <156000>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/wm8994.txt b/Documentation/devicetree/bindings/sound/wm8994.txt index 7a7eb1e7bda..f2f3e80934d 100644 --- a/Documentation/devicetree/bindings/sound/wm8994.txt +++ b/Documentation/devicetree/bindings/sound/wm8994.txt @@ -5,14 +5,70 @@ on the board). Required properties: - - compatible : "wlf,wm1811", "wlf,wm8994", "wlf,wm8958" + - compatible : One of "wlf,wm1811", "wlf,wm8994" or "wlf,wm8958". - reg : the I2C address of the device for I2C, the chip select number for SPI. + - gpio-controller : Indicates this device is a GPIO controller. + - #gpio-cells : Must be 2. The first cell is the pin number and the + second cell is used to specify optional parameters (currently unused). + + - AVDD2-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply, CPVDD-supply, + SPKVDD1-supply, SPKVDD2-supply : power supplies for the device, as covered + in Documentation/devicetree/bindings/regulator/regulator.txt + +Optional properties: + + - interrupts : The interrupt line the IRQ signal for the device is + connected to. This is optional, if it is not connected then none + of the interrupt related properties should be specified. + - interrupt-controller : These devices contain interrupt controllers + and may provide interrupt services to other devices if they have an + interrupt line connected. + - interrupt-parent : The parent interrupt controller. + - #interrupt-cells: the number of cells to describe an IRQ, this should be 2. + The first cell is the IRQ number. + The second cell is the flags, encoded as the trigger masks from + Documentation/devicetree/bindings/interrupts.txt + + - wlf,gpio-cfg : A list of GPIO configuration register values. If absent, + no configuration of these registers is performed. If any value is + over 0xffff then the register will be left as default. If present 11 + values must be supplied. + + - wlf,micbias-cfg : Two MICBIAS register values for WM1811 or + WM8958. If absent the register defaults will be used. + + - wlf,ldo1ena : GPIO specifier for control of LDO1ENA input to device. + - wlf,ldo2ena : GPIO specifier for control of LDO2ENA input to device. + + - wlf,lineout1-se : If present LINEOUT1 is in single ended mode. + - wlf,lineout2-se : If present LINEOUT2 is in single ended mode. + + - wlf,lineout1-feedback : If present LINEOUT1 has common mode feedback + connected. + - wlf,lineout2-feedback : If present LINEOUT2 has common mode feedback + connected. + + - wlf,ldoena-always-driven : If present LDOENA is always driven. + Example: codec: wm8994@1a { compatible = "wlf,wm8994"; reg = <0x1a>; + + gpio-controller; + #gpio-cells = <2>; + + lineout1-se; + + AVDD2-supply = <®ulator>; + CPVDD-supply = <®ulator>; + DBVDD1-supply = <®ulator>; + DBVDD2-supply = <®ulator>; + DBVDD3-supply = <®ulator>; + SPKVDD1-supply = <®ulator>; + SPKVDD2-supply = <®ulator>; }; diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt new file mode 100644 index 00000000000..8bf89c64364 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt @@ -0,0 +1,22 @@ +Broadcom BCM2835 SPI0 controller + +The BCM2835 contains two forms of SPI master controller, one known simply as +SPI0, and the other known as the "Universal SPI Master"; part of the +auxilliary block. This binding applies to the SPI0 controller. + +Required properties: +- compatible: Should be "brcm,bcm2835-spi". +- reg: Should contain register location and length. +- interrupts: Should contain interrupt. +- clocks: The clock feeding the SPI controller. + +Example: + +spi@20204000 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204000 0x1000>; + interrupts = <2 22>; + clocks = <&clk_spi>; + #address-cells = <1>; + #size-cells = <0>; +}; diff --git a/Documentation/devicetree/bindings/spi/fsl-spi.txt b/Documentation/devicetree/bindings/spi/fsl-spi.txt index 777abd7399d..b032dd76e9d 100644 --- a/Documentation/devicetree/bindings/spi/fsl-spi.txt +++ b/Documentation/devicetree/bindings/spi/fsl-spi.txt @@ -4,7 +4,7 @@ Required properties: - cell-index : QE SPI subblock index. 0: QE subblock SPI1 1: QE subblock SPI2 -- compatible : should be "fsl,spi". +- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl". - mode : the SPI operation mode, it can be "cpu" or "cpu-qe". - reg : Offset and length of the register set for the device - interrupts : <a b> where a is the interrupt number and b is a @@ -14,6 +14,7 @@ Required properties: controller you have. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. +- clock-frequency : input clock frequency to non FSL_SOC cores Optional properties: - gpios : specifies the gpio pins to be used for chipselects. diff --git a/Documentation/devicetree/bindings/spi/mxs-spi.txt b/Documentation/devicetree/bindings/spi/mxs-spi.txt index e2e13957c2a..3499b73293c 100644 --- a/Documentation/devicetree/bindings/spi/mxs-spi.txt +++ b/Documentation/devicetree/bindings/spi/mxs-spi.txt @@ -3,8 +3,11 @@ Required properties: - compatible: Should be "fsl,<soc>-spi", where soc is "imx23" or "imx28" - reg: Offset and length of the register set for the device -- interrupts: Should contain SSP interrupts (error irq first, dma irq second) -- fsl,ssp-dma-channel: APBX DMA channel for the SSP +- interrupts: Should contain SSP ERROR interrupt +- dmas: DMA specifier, consisting of a phandle to DMA controller node + and SSP DMA channel ID. + Refer to dma.txt and fsl-mxs-dma.txt for details. +- dma-names: Must be "rx-tx". Optional properties: - clock-frequency : Input clock frequency to the SPI block in Hz. @@ -17,6 +20,7 @@ ssp0: ssp@80010000 { #size-cells = <0>; compatible = "fsl,imx28-spi"; reg = <0x80010000 0x2000>; - interrupts = <96 82>; - fsl,ssp-dma-channel = <0>; + interrupts = <96>; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; }; diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt new file mode 100644 index 00000000000..91ff771c7e7 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt @@ -0,0 +1,26 @@ +NVIDIA Tegra114 SPI controller. + +Required properties: +- compatible : should be "nvidia,tegra114-spi". +- reg: Should contain SPI registers location and length. +- interrupts: Should contain SPI interrupts. +- nvidia,dma-request-selector : The Tegra DMA controller's phandle and + request selector for this SPI controller. +- This is also require clock named "spi" as per binding document + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Recommended properties: +- spi-max-frequency: Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt +Example: + +spi@7000d600 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + spi-max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt new file mode 100644 index 00000000000..6d0ac8d0ad9 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt @@ -0,0 +1,51 @@ +Davinci SPI controller device bindings + +Required properties: +- #address-cells: number of cells required to define a chip select + address on the SPI bus. Should be set to 1. +- #size-cells: should be zero. +- compatible: + - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family + - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family +- reg: Offset and length of SPI controller register space +- num-cs: Number of chip selects +- ti,davinci-spi-intr-line: interrupt line used to connect the SPI + IP to the interrupt controller within the SoC. Possible values + are 0 and 1. Manual says one of the two possible interrupt + lines can be tied to the interrupt controller. Set this + based on a specifc SoC configuration. +- interrupts: interrupt number mapped to CPU. +- clocks: spi clk phandle + +Example of a NOR flash slave device (n25q032) connected to DaVinci +SPI controller device over the SPI bus. + +spi0:spi@20BF0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,dm6446-spi"; + reg = <0x20BF0000 0x1000>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <338>; + clocks = <&clkspi>; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <25000000>; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "test"; + reg = <0x80000 0x380000>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt index a15ffeddfba..86aa061f069 100644 --- a/Documentation/devicetree/bindings/spi/spi-samsung.txt +++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt @@ -31,9 +31,6 @@ Required Board Specific Properties: - #address-cells: should be 1. - #size-cells: should be 0. -- gpios: The gpio specifier for clock, mosi and miso interface lines (in the - order specified). The format of the gpio specifier depends on the gpio - controller. Optional Board Specific Properties: @@ -86,9 +83,8 @@ Example: spi_0: spi@12d20000 { #address-cells = <1>; #size-cells = <0>; - gpios = <&gpa2 4 2 3 0>, - <&gpa2 6 2 3 0>, - <&gpa2 7 2 3 0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; w25q80bw@0 { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt index f158fd31cfd..22ed6797216 100644 --- a/Documentation/devicetree/bindings/spi/spi_pl022.txt +++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt @@ -16,6 +16,11 @@ Optional properties: device will be suspended immediately - pl022,rt : indicates the controller should run the message pump with realtime priority to minimise the transfer latency on the bus (boolean) +- dmas : Two or more DMA channel specifiers following the convention outlined + in bindings/dma/dma.txt +- dma-names: Names for the dma channels, if present. There must be at + least one channel named "tx" for transmit and named "rx" for + receive. SPI slave nodes must be children of the SPI master node and can @@ -32,3 +37,34 @@ contain the following properties. - pl022,wait-state : Microwire interface: Wait state - pl022,duplex : Microwire interface: Full/Half duplex + +Example: + + spi@e0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xe0100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 31 0x4>; + dmas = <&dma-controller 23 1>, + <&dma-controller 24 0>; + dma-names = "rx", "tx"; + + m25p80@1 { + compatible = "st,m25p80"; + reg = <1>; + spi-max-frequency = <12000000>; + spi-cpol; + spi-cpha; + pl022,hierarchy = <0>; + pl022,interface = <0>; + pl022,slave-tx-disable; + pl022,com-mode = <0x2>; + pl022,rx-level-trig = <0>; + pl022,tx-level-trig = <0>; + pl022,ctrl-len = <0x11>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + }; + }; + diff --git a/Documentation/devicetree/bindings/staging/dwc2.txt b/Documentation/devicetree/bindings/staging/dwc2.txt new file mode 100644 index 00000000000..1a1b7cfa484 --- /dev/null +++ b/Documentation/devicetree/bindings/staging/dwc2.txt @@ -0,0 +1,15 @@ +Platform DesignWare HS OTG USB 2.0 controller +----------------------------------------------------- + +Required properties: +- compatible : "snps,dwc2" +- reg : Should contain 1 register range (address and length) +- interrupts : Should contain 1 interrupt + +Example: + + usb@101c0000 { + compatible = "ralink,rt3050-usb, snps,dwc2"; + reg = <0x101c0000 40000>; + interrupts = <18>; + }; diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt index 07654f0338b..b876d4925a5 100644 --- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt @@ -8,6 +8,8 @@ Required properties: - interrupts: Should contain sync interrupt and error interrupt, in this order. - #crtc-cells: 1, See below +- resets: phandle pointing to the system reset controller and + reset line index, see reset/fsl,imx-src.txt for details example: @@ -16,6 +18,7 @@ ipu: ipu@18000000 { compatible = "fsl,imx53-ipu"; reg = <0x18000000 0x080000000>; interrupts = <11 10>; + resets = <&src 2>; }; Parallel display support @@ -26,7 +29,7 @@ Required properties: - crtc: the crtc this display is connected to, see below Optional properties: - interface_pix_fmt: How this display is connected to the - crtc. Currently supported types: "rgb24", "rgb565" + crtc. Currently supported types: "rgb24", "rgb565", "bgr666" - edid: verbatim EDID data block describing attached display. - ddc: phandle describing the i2c bus handling the display data channel diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt new file mode 100644 index 00000000000..fff93d5f92d --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/armada-thermal.txt @@ -0,0 +1,22 @@ +* Marvell Armada 370/XP thermal management + +Required properties: + +- compatible: Should be set to one of the following: + marvell,armada370-thermal + marvell,armadaxp-thermal + +- reg: Device's register space. + Two entries are expected, see the examples below. + The first one is required for the sensor register; + the second one is required for the control register + to be used for sensor initialization (a.k.a. calibration). + +Example: + + thermal@d0018300 { + compatible = "marvell,armada370-thermal"; + reg = <0xd0018300 0x4 + 0xd0018304 0x4>; + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt index 0c7b64e95a6..48aeb7884ed 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt @@ -2,7 +2,7 @@ Allwinner A1X SoCs Timer Controller Required properties: -- compatible : should be "allwinner,sunxi-timer" +- compatible : should be "allwinner,sun4i-timer" - reg : Specifies base physical address and size of the registers. - interrupts : The interrupt of the first timer - clocks: phandle to the source clock (usually a 24 MHz fixed clock) @@ -10,7 +10,7 @@ Required properties: Example: timer { - compatible = "allwinner,sunxi-timer"; + compatible = "allwinner,sun4i-timer"; reg = <0x01c20c00 0x400>; interrupts = <22>; clocks = <&osc>; diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.txt b/Documentation/devicetree/bindings/timer/arm,sp804.txt new file mode 100644 index 00000000000..5cd8eee74af --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,sp804.txt @@ -0,0 +1,29 @@ +ARM sp804 Dual Timers +--------------------------------------- + +Required properties: +- compatible: Should be "arm,sp804" & "arm,primecell" +- interrupts: Should contain the list of Dual Timer interrupts. This is the + interrupt for timer 1 and timer 2. In the case of a single entry, it is + the combined interrupt or if "arm,sp804-has-irq" is present that + specifies which timer interrupt is connected. +- reg: Should contain location and length for dual timer register. +- clocks: clocks driving the dual timer hardware. This list should be 1 or 3 + clocks. With 3 clocks, the order is timer0 clock, timer1 clock, + apb_pclk. A single clock can also be specified if the same clock is + used for all clock inputs. + +Optional properties: +- arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this + specifies if the irq connection is for timer 1 or timer 2. A value of 1 + or 2 should be used. + +Example: + + timer0: timer@fc800000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xfc800000 0x1000>; + interrupts = <0 0 4>, <0 1 4>; + clocks = <&timclk1 &timclk2 &pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; diff --git a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt new file mode 100644 index 00000000000..993695c659e --- /dev/null +++ b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt @@ -0,0 +1,17 @@ +Cadence TTC - Triple Timer Counter + +Required properties: +- compatible : Should be "cdns,ttc". +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 3 interrupts; one per timer channel. +- clocks: phandle to the source clock + +Example: + +ttc0: ttc0@f8001000 { + interrupt-parent = <&intc>; + interrupts = < 0 10 4 0 11 4 0 12 4 >; + compatible = "cdns,ttc"; + reg = <0xF8001000 0x1000>; + clocks = <&cpu_clk 3>; +}; diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt new file mode 100644 index 00000000000..9809b11f718 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt @@ -0,0 +1,18 @@ +Freescale i.MX General Purpose Timer (GPT) + +Required properties: + +- compatible : should be "fsl,<soc>-gpt" +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 4 interrupts; one per timer channel. +- clocks : The clocks provided by the SoC to drive the timer. + +Example: + +gpt1: timer@10003000 { + compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; + reg = <0x10003000 0x1000>; + interrupts = <26>; + clocks = <&clks 46>, <&clks 61>; + clock-names = "ipg", "per"; +}; diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt new file mode 100644 index 00000000000..cb47bfbcaee --- /dev/null +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt @@ -0,0 +1,68 @@ +Samsung's Multi Core Timer (MCT) + +The Samsung's Multi Core Timer (MCT) module includes two main blocks, the +global timer and CPU local timers. The global timer is a 64-bit free running +up-counter and can generate 4 interrupts when the counter reaches one of the +four preset counter values. The CPU local timers are 32-bit free running +down-counters and generate an interrupt when the counter expires. There is +one CPU local timer instantiated in MCT for every CPU in the system. + +Required properties: + +- compatible: should be "samsung,exynos4210-mct". + (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct. + (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct. + +- reg: base address of the mct controller and length of the address space + it occupies. + +- interrupts: the list of interrupts generated by the controller. The following + should be the order of the interrupts specified. The local timer interrupts + should be specified after the four global timer interrupts have been + specified. + + 0: Global Timer Interrupt 0 + 1: Global Timer Interrupt 1 + 2: Global Timer Interrupt 2 + 3: Global Timer Interrupt 3 + 4: Local Timer Interrupt 0 + 5: Local Timer Interrupt 1 + 6: .. + 7: .. + i: Local Timer Interrupt n + +Example 1: In this example, the system uses only the first global timer + interrupt generated by MCT and the remaining three global timer + interrupts are unused. Two local timer interrupts have been + specified. + + mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>, + <0 42 0>, <0 48 0>; + }; + +Example 2: In this example, the MCT global and local timer interrupts are + connected to two seperate interrupt controllers. Hence, an + interrupt-map is created to map the interrupts to the respective + interrupt controllers. + + mct@101C0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101C0000 0x800>; + interrupt-controller; + #interrups-cells = <2>; + interrupt-parent = <&mct_map>; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>; + + mct_map: mct-map { + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0x0 0 &combiner 23 3>, + <0x4 0 &gic 0 120 0>, + <0x5 0 &gic 0 121 0>; + }; + }; diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt index 273a8d5b330..2c00ec64628 100644 --- a/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt +++ b/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt @@ -5,20 +5,18 @@ Required properties: imx23 and imx28. - reg : Address and length of the register set for the device - interrupts : Should contain the auart interrupt numbers - -Optional properties: -- fsl,auart-dma-channel : The DMA channels, the first is for RX, the other - is for TX. If you add this property, it also means that you - will enable the DMA support for the auart. - Note: due to the hardware bug in imx23(see errata : 2836), - only the imx28 can enable the DMA support for the auart. +- dmas: DMA specifier, consisting of a phandle to DMA controller node + and AUART DMA channel ID. + Refer to dma.txt and fsl-mxs-dma.txt for details. +- dma-names: "rx" for RX channel, "tx" for TX channel. Example: auart0: serial@8006a000 { compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006a000 0x2000>; - interrupts = <112 70 71>; - fsl,auart-dma-channel = <8 9>; + interrupts = <112>; + dmas = <&dma_apbx 8>, <&dma_apbx 9>; + dma-names = "rx", "tx"; }; Note: Each auart port should have an alias correctly numbered in "aliases" diff --git a/Documentation/devicetree/bindings/tty/serial/of-serial.txt b/Documentation/devicetree/bindings/tty/serial/of-serial.txt index 8f01cb190f2..1928a3e83cd 100644 --- a/Documentation/devicetree/bindings/tty/serial/of-serial.txt +++ b/Documentation/devicetree/bindings/tty/serial/of-serial.txt @@ -33,6 +33,10 @@ Optional properties: RTAS and should not be registered. - no-loopback-test: set to indicate that the port does not implements loopback test mode +- fifo-size: the fifo size of the UART. +- auto-flow-control: one way to enable automatic flow control support. The + driver is allowed to detect support for the capability even without this + property. Example: diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt index 5778b9c83bd..1c04a4c9515 100644 --- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt +++ b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt @@ -11,6 +11,7 @@ Optional properties: that indicate usb controller index - vbus-supply: regulator for vbus - disable-over-current: disable over current detect +- external-vbus-divider: enables off-chip resistor divider for Vbus Examples: usb@02184000 { /* USB OTG */ @@ -20,4 +21,5 @@ usb@02184000 { /* USB OTG */ fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; disable-over-current; + external-vbus-divider; }; diff --git a/Documentation/devicetree/bindings/usb/ehci-omap.txt b/Documentation/devicetree/bindings/usb/ehci-omap.txt new file mode 100644 index 00000000000..485a9a1efa7 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ehci-omap.txt @@ -0,0 +1,32 @@ +OMAP HS USB EHCI controller + +This device is usually the child of the omap-usb-host +Documentation/devicetree/bindings/mfd/omap-usb-host.txt + +Required properties: + +- compatible: should be "ti,ehci-omap" +- reg: should contain one register range i.e. start and length +- interrupts: description of the interrupt line + +Optional properties: + +- phys: list of phandles to PHY nodes. + This property is required if at least one of the ports are in + PHY mode i.e. OMAP_EHCI_PORT_MODE_PHY + +To specify the port mode, see +Documentation/devicetree/bindings/mfd/omap-usb-host.txt + +Example for OMAP4: + +usbhsehci: ehci@4a064c00 { + compatible = "ti,ehci-omap", "usb-ehci"; + reg = <0x4a064c00 0x400>; + interrupts = <0 77 0x4>; +}; + +&usbhsehci { + phys = <&hsusb1_phy 0 &hsusb3_phy>; +}; + diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt new file mode 100644 index 00000000000..b3abde73601 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt @@ -0,0 +1,50 @@ +Samsung Exynos SoC USB controller + +The USB devices interface with USB controllers on Exynos SOCs. +The device node has following properties. + +EHCI +Required properties: + - compatible: should be "samsung,exynos4210-ehci" for USB 2.0 + EHCI controller in host mode. + - reg: physical base address of the controller and length of memory mapped + region. + - interrupts: interrupt number to the cpu. + - clocks: from common clock binding: handle to usb clock. + - clock-names: from common clock binding: Shall be "usbhost". + +Optional properties: + - samsung,vbus-gpio: if present, specifies the GPIO that + needs to be pulled up for the bus to be powered. + +Example: + + usb@12110000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12110000 0x100>; + interrupts = <0 71 0>; + samsung,vbus-gpio = <&gpx2 6 1 3 3>; + + clocks = <&clock 285>; + clock-names = "usbhost"; + }; + +OHCI +Required properties: + - compatible: should be "samsung,exynos4210-ohci" for USB 2.0 + OHCI companion controller in host mode. + - reg: physical base address of the controller and length of memory mapped + region. + - interrupts: interrupt number to the cpu. + - clocks: from common clock binding: handle to usb clock. + - clock-names: from common clock binding: Shall be "usbhost". + +Example: + usb@12120000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12120000 0x100>; + interrupts = <0 71 0>; + + clocks = <&clock 285>; + clock-names = "usbhost"; + }; diff --git a/Documentation/devicetree/bindings/usb/ohci-omap3.txt b/Documentation/devicetree/bindings/usb/ohci-omap3.txt new file mode 100644 index 00000000000..14ab42812a8 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ohci-omap3.txt @@ -0,0 +1,15 @@ +OMAP HS USB OHCI controller (OMAP3 and later) + +Required properties: + +- compatible: should be "ti,ohci-omap3" +- reg: should contain one register range i.e. start and length +- interrupts: description of the interrupt line + +Example for OMAP4: + +usbhsohci: ohci@4a064800 { + compatible = "ti,ohci-omap3", "usb-ohci"; + reg = <0x4a064800 0x400>; + interrupts = <0 76 0x4>; +}; diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt index 1ef0ce71f8f..d4769f343d6 100644 --- a/Documentation/devicetree/bindings/usb/omap-usb.txt +++ b/Documentation/devicetree/bindings/usb/omap-usb.txt @@ -8,16 +8,17 @@ OMAP MUSB GLUE and disconnect. - multipoint : Should be "1" indicating the musb controller supports multipoint. This is a MUSB configuration-specific setting. - - num_eps : Specifies the number of endpoints. This is also a + - num-eps : Specifies the number of endpoints. This is also a MUSB configuration-specific setting. Should be set to "16" - - ram_bits : Specifies the ram address size. Should be set to "12" - - interface_type : This is a board specific setting to describe the type of + - ram-bits : Specifies the ram address size. Should be set to "12" + - interface-type : This is a board specific setting to describe the type of interface between the controller and the phy. It should be "0" or "1" specifying ULPI and UTMI respectively. - mode : Should be "3" to represent OTG. "1" signifies HOST and "2" represents PERIPHERAL. - power : Should be "50". This signifies the controller can supply upto 100mA when operating in host mode. + - usb-phy : the phandle for the PHY device Optional properties: - ctrl-module : phandle of the control module this glue uses to write to @@ -29,18 +30,46 @@ usb_otg_hs: usb_otg_hs@4a0ab000 { ti,hwmods = "usb_otg_hs"; ti,has-mailbox; multipoint = <1>; - num_eps = <16>; - ram_bits = <12>; + num-eps = <16>; + ram-bits = <12>; ctrl-module = <&omap_control_usb>; }; Board specific device node entry &usb_otg_hs { - interface_type = <1>; + interface-type = <1>; mode = <3>; power = <50>; }; +OMAP DWC3 GLUE + - compatible : Should be "ti,dwc3" + - ti,hwmods : Should be "usb_otg_ss" + - reg : Address and length of the register set for the device. + - interrupts : The irq number of this device that is used to interrupt the + MPU + - #address-cells, #size-cells : Must be present if the device has sub-nodes + - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID. + It should be set to "1" for HW mode and "2" for SW mode. + - ranges: the child address space are mapped 1:1 onto the parent address space + +Sub-nodes: +The dwc3 core should be added as subnode to omap dwc3 glue. +- dwc3 : + The binding details of dwc3 can be found in: + Documentation/devicetree/bindings/usb/dwc3.txt + +omap_dwc3 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss"; + reg = <0x4a020000 0x1ff>; + interrupts = <0 93 4>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; +}; + OMAP CONTROL USB Required properties: diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt index 033194934f6..33fd3543f3f 100644 --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt @@ -1,20 +1,25 @@ -* Samsung's usb phy transceiver +SAMSUNG USB-PHY controllers -The Samsung's phy transceiver is used for controlling usb phy for -s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers -across Samsung SOCs. +** Samsung's usb 2.0 phy transceiver + +The Samsung's usb 2.0 phy transceiver is used for controlling +usb 2.0 phy for s3c-hsotg as well as ehci-s5p and ohci-exynos +usb controllers across Samsung SOCs. TODO: Adding the PHY binding with controller(s) according to the under -developement generic PHY driver. +development generic PHY driver. Required properties: Exynos4210: -- compatible : should be "samsung,exynos4210-usbphy" +- compatible : should be "samsung,exynos4210-usb2phy" - reg : base physical address of the phy registers and length of memory mapped region. +- clocks: Clock IDs array as required by the controller. +- clock-names: names of clock correseponding IDs clock property as requested + by the controller driver. Exynos5250: -- compatible : should be "samsung,exynos5250-usbphy" +- compatible : should be "samsung,exynos5250-usb2phy" - reg : base physical address of the phy registers and length of memory mapped region. @@ -44,12 +49,69 @@ Example: usbphy@125B0000 { #address-cells = <1>; #size-cells = <1>; - compatible = "samsung,exynos4210-usbphy"; + compatible = "samsung,exynos4210-usb2phy"; reg = <0x125B0000 0x100>; ranges; + clocks = <&clock 2>, <&clock 305>; + clock-names = "xusbxti", "otg"; + usbphy-sys { /* USB device and host PHY_CONTROL registers */ reg = <0x10020704 0x8>; }; }; + + +** Samsung's usb 3.0 phy transceiver + +Starting exynso5250, Samsung's SoC have usb 3.0 phy transceiver +which is used for controlling usb 3.0 phy for dwc3-exynos usb 3.0 +controllers across Samsung SOCs. + +Required properties: + +Exynos5250: +- compatible : should be "samsung,exynos5250-usb3phy" +- reg : base physical address of the phy registers and length of memory mapped + region. +- clocks: Clock IDs array as required by the controller. +- clock-names: names of clocks correseponding to IDs in the clock property + as requested by the controller driver. + +Optional properties: +- #address-cells: should be '1' when usbphy node has a child node with 'reg' + property. +- #size-cells: should be '1' when usbphy node has a child node with 'reg' + property. +- ranges: allows valid translation between child's address space and parent's + address space. + +- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller + interface for usb-phy. It should provide the following information required by + usb-phy controller to control phy. + - reg : base physical address of PHY_CONTROL registers. + The size of this register is the total sum of size of all PHY_CONTROL + registers that the SoC has. For example, the size will be + '0x4' in case we have only one PHY_CONTROL register (e.g. + OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210) + and, '0x8' in case we have two PHY_CONTROL registers (e.g. + USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x). + and so on. + +Example: + usbphy@12100000 { + compatible = "samsung,exynos5250-usb3phy"; + reg = <0x12100000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&clock 1>, <&clock 286>; + clock-names = "ext_xtal", "usbdrd30"; + + usbphy-sys { + /* USB device and host PHY_CONTROL registers */ + reg = <0x10040704 0x8>; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt b/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt new file mode 100644 index 00000000000..d7e272671c7 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt @@ -0,0 +1,34 @@ +USB NOP PHY + +Required properties: +- compatible: should be usb-nop-xceiv + +Optional properties: +- clocks: phandle to the PHY clock. Use as per Documentation/devicetree + /bindings/clock/clock-bindings.txt + This property is required if clock-frequency is specified. + +- clock-names: Should be "main_clk" + +- clock-frequency: the clock frequency (in Hz) that the PHY clock must + be configured to. + +- vcc-supply: phandle to the regulator that provides RESET to the PHY. + +- reset-supply: phandle to the regulator that provides power to the PHY. + +Example: + + hsusb1_phy { + compatible = "usb-nop-xceiv"; + clock-frequency = <19200000>; + clocks = <&osc 0>; + clock-names = "main_clk"; + vcc-supply = <&hsusb1_vcc_regulator>; + reset-supply = <&hsusb1_reset_regulator>; + }; + +hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator +and expects that clock to be configured to 19.2MHz by the NOP PHY driver. +hsusb1_vcc_regulator provides power to the PHY and hsusb1_reset_regulator +controls RESET. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 19e1ef73ab0..4d1919bf233 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -5,6 +5,7 @@ using them to avoid name-space collisions. ad Avionic Design GmbH adi Analog Devices, Inc. +aeroflexgaisler Aeroflex Gaisler AB ak Asahi Kasei Corp. amcc Applied Micro Circuits Corporation (APM, formally AMCC) apm Applied Micro Circuits Corporation (APM) @@ -48,6 +49,7 @@ samsung Samsung Semiconductor sbs Smart Battery System schindler Schindler sil Silicon Image +silabs Silicon Laboratories simtek sirf SiRF Technology, Inc. snps Synopsys, Inc. diff --git a/Documentation/devicetree/bindings/video/backlight/lp855x.txt b/Documentation/devicetree/bindings/video/backlight/lp855x.txt new file mode 100644 index 00000000000..1482103d288 --- /dev/null +++ b/Documentation/devicetree/bindings/video/backlight/lp855x.txt @@ -0,0 +1,41 @@ +lp855x bindings + +Required properties: + - compatible: "ti,lp8550", "ti,lp8551", "ti,lp8552", "ti,lp8553", + "ti,lp8556", "ti,lp8557" + - reg: I2C slave address (u8) + - dev-ctrl: Value of DEVICE CONTROL register (u8). It depends on the device. + +Optional properties: + - bl-name: Backlight device name (string) + - init-brt: Initial value of backlight brightness (u8) + - pwm-period: PWM period value. Set only PWM input mode used (u32) + - rom-addr: Register address of ROM area to be updated (u8) + - rom-val: Register value to be updated (u8) + +Example: + + /* LP8556 */ + backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + + bl-name = "lcd-bl"; + dev-ctrl = /bits/ 8 <0x85>; + init-brt = /bits/ 8 <0x10>; + }; + + /* LP8557 */ + backlight@2c { + compatible = "ti,lp8557"; + reg = <0x2c>; + + dev-ctrl = /bits/ 8 <0x41>; + init-brt = /bits/ 8 <0x0a>; + + /* 4V OV, 4 output LED string enabled */ + rom_14h { + rom-addr = /bits/ 8 <0x14>; + rom-val = /bits/ 8 <0xcf>; + }; + }; diff --git a/Documentation/devicetree/bindings/video/backlight/tps65217-backlight.txt b/Documentation/devicetree/bindings/video/backlight/tps65217-backlight.txt new file mode 100644 index 00000000000..5fb9279ac28 --- /dev/null +++ b/Documentation/devicetree/bindings/video/backlight/tps65217-backlight.txt @@ -0,0 +1,27 @@ +TPS65217 family of regulators + +The TPS65217 chip contains a boost converter and current sinks which can be +used to drive LEDs for use as backlights. + +Required properties: +- compatible: "ti,tps65217" +- reg: I2C slave address +- backlight: node for specifying WLED1 and WLED2 lines in TPS65217 +- isel: selection bit, valid values: 1 for ISEL1 (low-level) and 2 for ISEL2 (high-level) +- fdim: PWM dimming frequency, valid values: 100, 200, 500, 1000 +- default-brightness: valid values: 0-100 + +Each regulator is defined using the standard binding for regulators. + +Example: + + tps: tps@24 { + reg = <0x24>; + compatible = "ti,tps65217"; + backlight { + isel = <1>; /* 1 - ISET1, 2 ISET2 */ + fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ + default-brightness = <50>; + }; + }; + diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt new file mode 100644 index 00000000000..778838a0336 --- /dev/null +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt @@ -0,0 +1,65 @@ +Device-Tree bindings for Samsung SoC display controller (FIMD) + +FIMD (Fully Interactive Mobile Display) is the Display Controller for the +Samsung series of SoCs which transfers the image data from a video memory +buffer to an external LCD interface. + +Required properties: +- compatible: value should be one of the following + "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */ + "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */ + "samsung,s5p6440-fimd"; /* for S5P64X0 SoCs */ + "samsung,s5pc100-fimd"; /* for S5PC100 SoC */ + "samsung,s5pv210-fimd"; /* for S5PV210 SoC */ + "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */ + "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */ + +- reg: physical base address and length of the FIMD registers set. + +- interrupt-parent: should be the phandle of the fimd controller's + parent interrupt controller. + +- interrupts: should contain a list of all FIMD IP block interrupts in the + order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier + format depends on the interrupt controller used. + +- interrupt-names: should contain the interrupt names: "fifo", "vsync", + "lcd_sys", in the same order as they were listed in the interrupts + property. + +- pinctrl-0: pin control group to be used for this controller. + +- pinctrl-names: must contain a "default" entry. + +- clocks: must include clock specifiers corresponding to entries in the + clock-names property. + +- clock-names: list of clock names sorted in the same order as the clocks + property. Must contain "sclk_fimd" and "fimd". + +Optional Properties: +- samsung,power-domain: a phandle to FIMD power domain node. + +Example: + +SoC specific DT entry: + + fimd@11c00000 { + compatible = "samsung,exynos4210-fimd"; + interrupt-parent = <&combiner>; + reg = <0x11c00000 0x20000>; + interrupt-names = "fifo", "vsync", "lcd_sys"; + interrupts = <11 0>, <11 1>, <11 2>; + clocks = <&clock 140>, <&clock 283>; + clock-names = "sclk_fimd", "fimd"; + samsung,power-domain = <&pd_lcd0>; + status = "disabled"; + }; + +Board specific DT entry: + + fimd@11c00000 { + pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; + pinctrl-names = "default"; + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt index c870b6478ec..2871e218a0f 100644 --- a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt +++ b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt @@ -5,58 +5,32 @@ Required properties: - compatible : "via,vt8500-fb" - reg : Should contain 1 register ranges(address and length) - interrupts : framebuffer controller interrupt -- display: a phandle pointing to the display node +- bits-per-pixel : bit depth of framebuffer (16 or 32) -Required nodes: -- display: a display node is required to initialize the lcd panel - This should be in the board dts. -- default-mode: a videomode within the display with timing parameters - as specified below. +Required subnodes: +- display-timings: see display-timing.txt for information Example: - fb@d800e400 { + fb@d8050800 { compatible = "via,vt8500-fb"; reg = <0xd800e400 0x400>; interrupts = <12>; - display = <&display>; - default-mode = <&mode0>; - }; - -VIA VT8500 Display ------------------------------------------------------ -Required properties (as per of_videomode_helper): - - - hactive, vactive: Display resolution - - hfront-porch, hback-porch, hsync-len: Horizontal Display timing parameters - in pixels - vfront-porch, vback-porch, vsync-len: Vertical display timing parameters in - lines - - clock: displayclock in Hz - - bpp: lcd panel bit-depth. - <16> for RGB565, <32> for RGB888 - -Optional properties (as per of_videomode_helper): - - width-mm, height-mm: Display dimensions in mm - - hsync-active-high (bool): Hsync pulse is active high - - vsync-active-high (bool): Vsync pulse is active high - - interlaced (bool): This is an interlaced mode - - doublescan (bool): This is a doublescan mode + bits-per-pixel = <16>; -Example: - display: display@0 { - modes { - mode0: mode@0 { + display-timings { + native-mode = <&timing0>; + timing0: 800x480 { + clock-frequency = <0>; /* unused but required */ hactive = <800>; vactive = <480>; - hback-porch = <88>; hfront-porch = <40>; + hback-porch = <88>; hsync-len = <0>; vback-porch = <32>; vfront-porch = <11>; vsync-len = <1>; - clock = <0>; /* unused but required */ - bpp = <16>; /* non-standard but required */ }; }; }; + diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt index 3d325e1d11e..0bcadb2840a 100644 --- a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt +++ b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt @@ -4,20 +4,30 @@ Wondermedia WM8505 Framebuffer Required properties: - compatible : "wm,wm8505-fb" - reg : Should contain 1 register ranges(address and length) -- via,display: a phandle pointing to the display node +- bits-per-pixel : bit depth of framebuffer (16 or 32) -Required nodes: -- display: a display node is required to initialize the lcd panel - This should be in the board dts. See definition in - Documentation/devicetree/bindings/video/via,vt8500-fb.txt -- default-mode: a videomode node as specified in - Documentation/devicetree/bindings/video/via,vt8500-fb.txt +Required subnodes: +- display-timings: see display-timing.txt for information Example: - fb@d8050800 { + fb@d8051700 { compatible = "wm,wm8505-fb"; - reg = <0xd8050800 0x200>; - display = <&display>; - default-mode = <&mode0>; + reg = <0xd8051700 0x200>; + bits-per-pixel = <16>; + + display-timings { + native-mode = <&timing0>; + timing0: 800x480 { + clock-frequency = <0>; /* unused but required */ + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <88>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt index 0b271777560..ecd650adff3 100644 --- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt @@ -1,13 +1,13 @@ -Allwinner sunXi Watchdog timer +Allwinner sun4i Watchdog timer Required properties: -- compatible : should be "allwinner,sunxi-wdt" +- compatible : should be "allwinner,sun4i-wdt" - reg : Specifies base physical address and size of the registers. Example: wdt: watchdog@01c20c90 { - compatible = "allwinner,sunxi-wdt"; + compatible = "allwinner,sun4i-wdt"; reg = <0x01c20c90 0x10>; }; |