diff options
55 files changed, 419 insertions, 388 deletions
diff --git a/Documentation/networking/phy.txt b/Documentation/networking/phy.txt index 8df6a7b0e66..88bb71b46da 100644 --- a/Documentation/networking/phy.txt +++ b/Documentation/networking/phy.txt @@ -96,7 +96,7 @@ Letting the PHY Abstraction Layer do Everything static void adjust_link(struct net_device *dev); Next, you need to know the device name of the PHY connected to this device. - The name will look something like, "phy0:0", where the first number is the + The name will look something like, "0:00", where the first number is the bus id, and the second is the PHY's address on that bus. Typically, the bus is responsible for making its ID unique. diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h index c8e554eafce..b5cf6457305 100644 --- a/arch/mips/include/asm/mach-rc32434/gpio.h +++ b/arch/mips/include/asm/mach-rc32434/gpio.h @@ -84,5 +84,7 @@ extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned extern unsigned get_434_reg(unsigned reg_offs); extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); extern unsigned char get_latch_u5(void); +extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); +extern void rb532_gpio_set_istat(int bit, unsigned gpio); #endif /* _RC32434_GPIO_H_ */ diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h index 79e8ef67d0d..f25a8491670 100644 --- a/arch/mips/include/asm/mach-rc32434/rb.h +++ b/arch/mips/include/asm/mach-rc32434/rb.h @@ -40,12 +40,14 @@ #define BTCS 0x010040 #define BTCOMPARE 0x010044 #define GPIOBASE 0x050000 -#define GPIOCFG 0x050004 -#define GPIOD 0x050008 -#define GPIOILEVEL 0x05000C -#define GPIOISTAT 0x050010 -#define GPIONMIEN 0x050014 -#define IMASK6 0x038038 +/* Offsets relative to GPIOBASE */ +#define GPIOFUNC 0x00 +#define GPIOCFG 0x04 +#define GPIOD 0x08 +#define GPIOILEVEL 0x0C +#define GPIOISTAT 0x10 +#define GPIONMIEN 0x14 +#define IMASK6 0x38 #define LO_WPX (1 << 0) #define LO_ALE (1 << 1) #define LO_CLE (1 << 2) diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index d3bd5c5aa2e..9601ea95054 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -63,7 +63,7 @@ static inline int mips_clockevent_init(void) /* * Initialize the count register as a clocksource */ -#ifdef CONFIG_CEVT_R4K +#ifdef CONFIG_CSRC_R4K extern int init_mips_clocksource(void); #else static inline int init_mips_clocksource(void) diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index 86e026f067b..74fb74583b4 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -27,7 +27,7 @@ int __init init_mips_clocksource(void) if (!cpu_has_counter || !mips_hpt_frequency) return -ENXIO; - /* Calclate a somewhat reasonable rating value */ + /* Calculate a somewhat reasonable rating value */ clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c index 1f602a110e1..13adb578211 100644 --- a/arch/mips/mm/sc-ip22.c +++ b/arch/mips/mm/sc-ip22.c @@ -161,7 +161,7 @@ static inline int __init indy_sc_probe(void) /* XXX Check with wje if the Indy caches can differenciate between writeback + invalidate and just invalidate. */ -struct bcache_ops indy_sc_ops = { +static struct bcache_ops indy_sc_ops = { .bc_enable = indy_sc_enable, .bc_disable = indy_sc_disable, .bc_wback_inv = indy_sc_wback_invalidate, diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c index 96236bf3383..df9e526312a 100644 --- a/arch/mips/mti-malta/malta-amon.c +++ b/arch/mips/mti-malta/malta-amon.c @@ -22,9 +22,9 @@ #include <linux/init.h> #include <linux/smp.h> -#include <asm-mips/addrspace.h> -#include <asm-mips/mips-boards/launch.h> -#include <asm-mips/mipsmtregs.h> +#include <asm/addrspace.h> +#include <asm/mips-boards/launch.h> +#include <asm/mipsmtregs.h> int amon_cpu_avail(int cpu) { diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 2f22d714d5b..c1c29181bd4 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -118,7 +118,7 @@ static struct platform_device cf_slot0 = { /* Resources and device for NAND */ static int rb532_dev_ready(struct mtd_info *mtd) { - return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY; + return gpio_get_value(GPIO_RDY); } static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index 70c4a672637..0e84c8ab6a3 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -39,10 +39,6 @@ struct rb532_gpio_chip { struct gpio_chip chip; void __iomem *regbase; - void (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value); - int (*get_int_level)(struct gpio_chip *chip, unsigned offset); - void (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value); - int (*get_int_status)(struct gpio_chip *chip, unsigned offset); }; struct mpmc_device dev3; @@ -111,15 +107,47 @@ unsigned char get_latch_u5(void) } EXPORT_SYMBOL(get_latch_u5); +/* rb532_set_bit - sanely set a bit + * + * bitval: new value for the bit + * offset: bit index in the 4 byte address range + * ioaddr: 4 byte aligned address being altered + */ +static inline void rb532_set_bit(unsigned bitval, + unsigned offset, void __iomem *ioaddr) +{ + unsigned long flags; + u32 val; + + bitval = !!bitval; /* map parameter to {0,1} */ + + local_irq_save(flags); + + val = readl(ioaddr); + val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */ + val |= ( bitval << offset ); /* set bit if bitval == 1 */ + writel(val, ioaddr); + + local_irq_restore(flags); +} + +/* rb532_get_bit - read a bit + * + * returns the boolean state of the bit, which may be > 1 + */ +static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr) +{ + return (readl(ioaddr) & (1 << offset)); +} + /* * Return GPIO level */ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) { - u32 mask = 1 << offset; struct rb532_gpio_chip *gpch; gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOD) & mask; + return rb532_get_bit(offset, gpch->regbase + GPIOD); } /* @@ -128,23 +156,10 @@ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) static void rb532_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; struct rb532_gpio_chip *gpch; - void __iomem *gpvr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpvr = gpch->regbase + GPIOD; - - local_irq_save(flags); - tmp = readl(gpvr); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpvr); - local_irq_restore(flags); + rb532_set_bit(value, offset, gpch->regbase + GPIOD); } /* @@ -152,21 +167,14 @@ static void rb532_gpio_set(struct gpio_chip *chip, */ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { - unsigned long flags; - u32 mask = 1 << offset; - u32 value; struct rb532_gpio_chip *gpch; - void __iomem *gpdr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpdr = gpch->regbase + GPIOCFG; - local_irq_save(flags); - value = readl(gpdr); - value &= ~mask; - writel(value, gpdr); - local_irq_restore(flags); + if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) + return 1; /* alternate function, GPIOCFG is ignored */ + rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); return 0; } @@ -176,117 +184,60 @@ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) static int rb532_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; struct rb532_gpio_chip *gpch; - void __iomem *gpdr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - writel(mask, gpch->regbase + GPIOD); - gpdr = gpch->regbase + GPIOCFG; - local_irq_save(flags); - tmp = readl(gpdr); - tmp |= mask; - writel(tmp, gpdr); - local_irq_restore(flags); + if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) + return 1; /* alternate function, GPIOCFG is ignored */ + /* set the initial output value */ + rb532_set_bit(value, offset, gpch->regbase + GPIOD); + + rb532_set_bit(1, offset, gpch->regbase + GPIOCFG); return 0; } -/* - * Set the GPIO interrupt level - */ -static void rb532_gpio_set_int_level(struct gpio_chip *chip, - unsigned offset, int value) -{ - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; - struct rb532_gpio_chip *gpch; - void __iomem *gpil; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpil = gpch->regbase + GPIOILEVEL; - - local_irq_save(flags); - tmp = readl(gpil); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpil); - local_irq_restore(flags); -} +static struct rb532_gpio_chip rb532_gpio_chip[] = { + [0] = { + .chip = { + .label = "gpio0", + .direction_input = rb532_gpio_direction_input, + .direction_output = rb532_gpio_direction_output, + .get = rb532_gpio_get, + .set = rb532_gpio_set, + .base = 0, + .ngpio = 32, + }, + }, +}; /* - * Get the GPIO interrupt level + * Set GPIO interrupt level */ -static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset) +void rb532_gpio_set_ilevel(int bit, unsigned gpio) { - u32 mask = 1 << offset; - struct rb532_gpio_chip *gpch; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOILEVEL) & mask; + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL); } +EXPORT_SYMBOL(rb532_gpio_set_ilevel); /* - * Set the GPIO interrupt status + * Set GPIO interrupt status */ -static void rb532_gpio_set_int_status(struct gpio_chip *chip, - unsigned offset, int value) +void rb532_gpio_set_istat(int bit, unsigned gpio) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; - struct rb532_gpio_chip *gpch; - void __iomem *gpis; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpis = gpch->regbase + GPIOISTAT; - - local_irq_save(flags); - tmp = readl(gpis); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpis); - local_irq_restore(flags); + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT); } +EXPORT_SYMBOL(rb532_gpio_set_istat); /* - * Get the GPIO interrupt status + * Configure GPIO alternate function */ -static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset) +static void rb532_gpio_set_func(int bit, unsigned gpio) { - u32 mask = 1 << offset; - struct rb532_gpio_chip *gpch; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOISTAT) & mask; + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC); } -static struct rb532_gpio_chip rb532_gpio_chip[] = { - [0] = { - .chip = { - .label = "gpio0", - .direction_input = rb532_gpio_direction_input, - .direction_output = rb532_gpio_direction_output, - .get = rb532_gpio_get, - .set = rb532_gpio_set, - .base = 0, - .ngpio = 32, - }, - .get_int_level = rb532_gpio_get_int_level, - .set_int_level = rb532_gpio_set_int_level, - .get_int_status = rb532_gpio_get_int_status, - .set_int_status = rb532_gpio_set_int_status, - }, -}; - int __init rb532_gpio_init(void) { struct resource *r; @@ -310,9 +261,11 @@ int __init rb532_gpio_init(void) return -ENXIO; } - /* Set the interrupt status and level for the CF pin */ - rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1); - rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0); + /* configure CF_GPIO_NUM as CFRDY IRQ source */ + rb532_gpio_set_func(0, CF_GPIO_NUM); + rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM); + rb532_gpio_set_ilevel(1, CF_GPIO_NUM); + rb532_gpio_set_istat(0, CF_GPIO_NUM); return 0; } diff --git a/arch/parisc/kernel/ptrace.c b/arch/parisc/kernel/ptrace.c index 90904f9dfc5..927db3668b6 100644 --- a/arch/parisc/kernel/ptrace.c +++ b/arch/parisc/kernel/ptrace.c @@ -183,10 +183,10 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) * being 64 bit in both cases. */ -static long translate_usr_offset(long offset) +static compat_ulong_t translate_usr_offset(compat_ulong_t offset) { if (offset < 0) - return -1; + return sizeof(struct pt_regs); else if (offset <= 32*4) /* gr[0..31] */ return offset * 2 + 4; else if (offset <= 32*4+32*8) /* gr[0..31] + fr[0..31] */ @@ -194,7 +194,7 @@ static long translate_usr_offset(long offset) else if (offset < sizeof(struct pt_regs)/2 + 32*4) return offset * 2 + 4 - 32*8; else - return -1; + return sizeof(struct pt_regs); } long compat_arch_ptrace(struct task_struct *child, compat_long_t request, @@ -209,7 +209,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, if (addr & (sizeof(compat_uint_t)-1)) break; addr = translate_usr_offset(addr); - if (addr < 0) + if (addr >= sizeof(struct pt_regs)) break; tmp = *(compat_uint_t *) ((char *) task_regs(child) + addr); @@ -236,7 +236,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, if (addr & (sizeof(compat_uint_t)-1)) break; addr = translate_usr_offset(addr); - if (addr < 0) + if (addr >= sizeof(struct pt_regs)) break; if (addr >= PT_FR0 && addr <= PT_FR31 + 4) { /* Special case, fp regs are 64 bits anyway */ diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h index 664f15280f1..f8cfd00db45 100644 --- a/arch/x86/include/asm/uaccess_64.h +++ b/arch/x86/include/asm/uaccess_64.h @@ -46,7 +46,7 @@ int __copy_from_user(void *dst, const void __user *src, unsigned size) return ret; case 10: __get_user_asm(*(u64 *)dst, (u64 __user *)src, - ret, "q", "", "=r", 16); + ret, "q", "", "=r", 10); if (unlikely(ret)) return ret; __get_user_asm(*(u16 *)(8 + (char *)dst), diff --git a/arch/x86/kernel/io_apic.c b/arch/x86/kernel/io_apic.c index 7a3f2028e2e..c9513e1ff28 100644 --- a/arch/x86/kernel/io_apic.c +++ b/arch/x86/kernel/io_apic.c @@ -1140,6 +1140,20 @@ static void __clear_irq_vector(int irq) cfg->vector = 0; cpus_clear(cfg->domain); + + if (likely(!cfg->move_in_progress)) + return; + cpus_and(mask, cfg->old_domain, cpu_online_map); + for_each_cpu_mask_nr(cpu, mask) { + for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; + vector++) { + if (per_cpu(vector_irq, cpu)[vector] != irq) + continue; + per_cpu(vector_irq, cpu)[vector] = -1; + break; + } + } + cfg->move_in_progress = 0; } void __setup_vector_irq(int cpu) diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 724adfc63cb..cc5a2545dd4 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -169,6 +169,15 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = { DMI_MATCH(DMI_BOARD_NAME, "0KW626"), }, }, + { /* Handle problems with rebooting on Dell Optiplex 330 with 0KP561 */ + .callback = set_bios_reboot, + .ident = "Dell OptiPlex 330", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 330"), + DMI_MATCH(DMI_BOARD_NAME, "0KP561"), + }, + }, { /* Handle problems with rebooting on Dell 2400's */ .callback = set_bios_reboot, .ident = "Dell PowerEdge 2400", diff --git a/drivers/net/atlx/atl2.c b/drivers/net/atlx/atl2.c index f5bdc92c1a6..8571e8c0bc6 100644 --- a/drivers/net/atlx/atl2.c +++ b/drivers/net/atlx/atl2.c @@ -1690,9 +1690,11 @@ static int atl2_resume(struct pci_dev *pdev) ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); - err = atl2_request_irq(adapter); - if (netif_running(netdev) && err) - return err; + if (netif_running(netdev)) { + err = atl2_request_irq(adapter); + if (err) + return err; + } atl2_reset_hw(&adapter->hw); diff --git a/drivers/net/ipg.c b/drivers/net/ipg.c index 7373dafbb3f..059369885be 100644 --- a/drivers/net/ipg.c +++ b/drivers/net/ipg.c @@ -1112,7 +1112,7 @@ static void ipg_nic_rx_free_skb(struct net_device *dev) struct ipg_rx *rxfd = sp->rxd + entry; pci_unmap_single(sp->pdev, - le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN), + le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN, sp->rx_buf_sz, PCI_DMA_FROMDEVICE); dev_kfree_skb_irq(sp->rx_buff[entry]); sp->rx_buff[entry] = NULL; @@ -1179,7 +1179,7 @@ static int ipg_nic_rx_check_error(struct net_device *dev) */ if (sp->rx_buff[entry]) { pci_unmap_single(sp->pdev, - le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN), + le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN, sp->rx_buf_sz, PCI_DMA_FROMDEVICE); dev_kfree_skb_irq(sp->rx_buff[entry]); @@ -1246,7 +1246,7 @@ static void ipg_nic_rx_with_start(struct net_device *dev, if (jumbo->found_start) dev_kfree_skb_irq(jumbo->skb); - pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN), + pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN, sp->rx_buf_sz, PCI_DMA_FROMDEVICE); skb_put(skb, sp->rxfrag_size); @@ -1349,7 +1349,7 @@ static int ipg_nic_rx_jumbo(struct net_device *dev) unsigned int entry = curr % IPG_RFDLIST_LENGTH; struct ipg_rx *rxfd = sp->rxd + entry; - if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE))) + if (!(rxfd->rfs & cpu_to_le64(IPG_RFS_RFDDONE))) break; switch (ipg_nic_rx_check_frame_type(dev)) { diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index 7548fb7360d..36f2bb666bf 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c @@ -1287,7 +1287,34 @@ static void ixgbe_set_itr(struct ixgbe_adapter *adapter) return; } -static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter); +/** + * ixgbe_irq_disable - Mask off interrupt generation on the NIC + * @adapter: board private structure + **/ +static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) +{ + IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); + IXGBE_WRITE_FLUSH(&adapter->hw); + if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { + int i; + for (i = 0; i < adapter->num_msix_vectors; i++) + synchronize_irq(adapter->msix_entries[i].vector); + } else { + synchronize_irq(adapter->pdev->irq); + } +} + +/** + * ixgbe_irq_enable - Enable default interrupt generation settings + * @adapter: board private structure + **/ +static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) +{ + u32 mask; + mask = IXGBE_EIMS_ENABLE_MASK; + IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); + IXGBE_WRITE_FLUSH(&adapter->hw); +} /** * ixgbe_intr - legacy mode Interrupt Handler @@ -1394,35 +1421,6 @@ static void ixgbe_free_irq(struct ixgbe_adapter *adapter) } /** - * ixgbe_irq_disable - Mask off interrupt generation on the NIC - * @adapter: board private structure - **/ -static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) -{ - IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); - IXGBE_WRITE_FLUSH(&adapter->hw); - if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { - int i; - for (i = 0; i < adapter->num_msix_vectors; i++) - synchronize_irq(adapter->msix_entries[i].vector); - } else { - synchronize_irq(adapter->pdev->irq); - } -} - -/** - * ixgbe_irq_enable - Enable defa |