diff options
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91rm9200_emac.h | 138 | ||||
| -rw-r--r-- | drivers/net/ethernet/cadence/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/net/ethernet/cadence/Makefile | 2 | ||||
| -rw-r--r-- | drivers/net/ethernet/cadence/at91_ether.c | 1024 | ||||
| -rw-r--r-- | drivers/net/ethernet/cadence/at91_ether.h | 112 | ||||
| -rw-r--r-- | drivers/net/ethernet/cadence/macb.c | 12 | ||||
| -rw-r--r-- | drivers/net/ethernet/cadence/macb.h | 22 |
7 files changed, 207 insertions, 1105 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h deleted file mode 100644 index b8260cd8041..00000000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91rm9200_emac.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Ethernet MAC registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91RM9200_EMAC_H -#define AT91RM9200_EMAC_H - -#define AT91_EMAC_CTL 0x00 /* Control Register */ -#define AT91_EMAC_LB (1 << 0) /* Loopback */ -#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */ -#define AT91_EMAC_RE (1 << 2) /* Receive Enable */ -#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */ -#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */ -#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */ -#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */ -#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */ -#define AT91_EMAC_BP (1 << 8) /* Back Pressure */ - -#define AT91_EMAC_CFG 0x04 /* Configuration Register */ -#define AT91_EMAC_SPD (1 << 0) /* Speed */ -#define AT91_EMAC_FD (1 << 1) /* Full Duplex */ -#define AT91_EMAC_BR (1 << 2) /* Bit Rate */ -#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */ -#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */ -#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */ -#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */ -#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */ -#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */ -#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */ -#define AT91_EMAC_CLK_DIV8 (0 << 10) -#define AT91_EMAC_CLK_DIV16 (1 << 10) -#define AT91_EMAC_CLK_DIV32 (2 << 10) -#define AT91_EMAC_CLK_DIV64 (3 << 10) -#define AT91_EMAC_RTY (1 << 12) /* Retry Test */ -#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */ - -#define AT91_EMAC_SR 0x08 /* Status Register */ -#define AT91_EMAC_SR_LINK (1 << 0) /* Link */ -#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */ -#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */ - -#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */ - -#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */ -#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */ -#define AT91_EMAC_NCRC (1 << 15) /* No CRC */ - -#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */ -#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */ -#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */ -#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */ -#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */ -#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */ -#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */ -#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */ - -#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ - -#define AT91_EMAC_RSR 0x20 /* Receive Status Register */ -#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */ -#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */ -#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */ - -#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */ -#define AT91_EMAC_DONE (1 << 0) /* Management Done */ -#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */ -#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */ -#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */ -#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */ -#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */ -#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */ -#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */ -#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */ -#define AT91_EMAC_LINK (1 << 9) /* Link */ -#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */ -#define AT91_EMAC_ABT (1 << 11) /* Abort */ - -#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */ -#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */ -#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */ - -#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */ -#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */ -#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */ -#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */ -#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */ -#define AT91_EMAC_RW_W (1 << 28) -#define AT91_EMAC_RW_R (2 << 28) -#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */ - -/* - * Statistics Registers. - */ -#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */ -#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */ -#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */ -#define AT91_EMAC_OK 0x4c /* Frames Received OK */ -#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */ -#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */ -#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */ -#define AT91_EMAC_LCOL 0x5c /* Late Collision */ -#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */ -#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */ -#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */ -#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */ -#define AT91_EMAC_ROV 0x70 /* Receive Overrun */ -#define AT91_EMAC_CDE 0x74 /* Code Error */ -#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */ -#define AT91_EMAC_RJB 0x7c /* Receive Jabber */ -#define AT91_EMAC_USF 0x80 /* Undersize Frame */ -#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */ - -/* - * Address Registers. - */ -#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */ -#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */ -#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */ -#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */ -#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */ -#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */ -#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */ -#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */ -#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */ -#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */ - -#endif diff --git a/drivers/net/ethernet/cadence/Kconfig b/drivers/net/ethernet/cadence/Kconfig index db931916da0..57f78abe11d 100644 --- a/drivers/net/ethernet/cadence/Kconfig +++ b/drivers/net/ethernet/cadence/Kconfig @@ -27,7 +27,7 @@ config ARM_AT91_ETHER tristate "AT91RM9200 Ethernet support" depends on ARM && ARCH_AT91RM9200 select NET_CORE - select MII + select PHYLIB ---help--- If you wish to compile a kernel for the AT91RM9200 and enable ethernet support, then you should always answer Y to this. diff --git a/drivers/net/ethernet/cadence/Makefile b/drivers/net/ethernet/cadence/Makefile index 9068b8331ed..798b1e0fd22 100644 --- a/drivers/net/ethernet/cadence/Makefile +++ b/drivers/net/ethernet/cadence/Makefile @@ -2,5 +2,5 @@ # Makefile for the Atmel network device drivers. # -obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o +obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o macb.o obj-$(CONFIG_MACB) += macb.o diff --git a/drivers/net/ethernet/cadence/at91_ether.c b/drivers/net/ethernet/cadence/at91_ether.c index 4e980a7886f..375d272d1a5 100644 --- a/drivers/net/ethernet/cadence/at91_ether.c +++ b/drivers/net/ethernet/cadence/at91_ether.c @@ -20,7 +20,6 @@ #include <linux/module.h> #include <linux/init.h> #include <linux/interrupt.h> -#include <linux/mii.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> @@ -31,402 +30,19 @@ #include <linux/clk.h> #include <linux/gfp.h> #include <linux/phy.h> +#include <linux/io.h> -#include <asm/io.h> -#include <asm/uaccess.h> #include <asm/mach-types.h> -#include <mach/at91rm9200_emac.h> -#include <asm/gpio.h> -#include <mach/board.h> - -#include "at91_ether.h" +#include "macb.h" #define DRV_NAME "at91_ether" #define DRV_VERSION "1.0" -#define LINK_POLL_INTERVAL (HZ) - -/* ..................................................................... */ - -/* - * Read from a EMAC register. - */ -static inline unsigned long at91_emac_read(struct at91_private *lp, unsigned int reg) -{ - return __raw_readl(lp->emac_base + reg); -} - -/* - * Write to a EMAC register. - */ -static inline void at91_emac_write(struct at91_private *lp, unsigned int reg, unsigned long value) -{ - __raw_writel(value, lp->emac_base + reg); -} - -/* ........................... PHY INTERFACE ........................... */ - -/* - * Enable the MDIO bit in MAC control register - * When not called from an interrupt-handler, access to the PHY must be - * protected by a spinlock. - */ -static void enable_mdi(struct at91_private *lp) -{ - unsigned long ctl; - - ctl = at91_emac_read(lp, AT91_EMAC_CTL); - at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */ -} - -/* - * Disable the MDIO bit in the MAC control register - */ -static void disable_mdi(struct at91_private *lp) -{ - unsigned long ctl; - - ctl = at91_emac_read(lp, AT91_EMAC_CTL); - at91_emac_write(lp, AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */ -} - -/* - * Wait until the PHY operation is complete. - */ -static inline void at91_phy_wait(struct at91_private *lp) -{ - unsigned long timeout = jiffies + 2; - - while (!(at91_emac_read(lp, AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) { - if (time_after(jiffies, timeout)) { - printk("at91_ether: MIO timeout\n"); - break; - } - cpu_relax(); - } -} - -/* - * Write value to the a PHY register - * Note: MDI interface is assumed to already have been enabled. - */ -static void write_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int value) -{ - at91_emac_write(lp, AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W - | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA)); - - /* Wait until IDLE bit in Network Status register is cleared */ - at91_phy_wait(lp); -} - -/* - * Read value stored in a PHY register. - * Note: MDI interface is assumed to already have been enabled. - */ -static void read_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int *value) -{ - at91_emac_write(lp, AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R - | ((phy_addr & 0x1f) << 23) | (address << 18)); - - /* Wait until IDLE bit in Network Status register is cleared */ - at91_phy_wait(lp); - - *value = at91_emac_read(lp, AT91_EMAC_MAN) & AT91_EMAC_DATA; -} - -/* ........................... PHY MANAGEMENT .......................... */ - -/* - * Access the PHY to determine the current link speed and mode, and update the - * MAC accordingly. - * If no link or auto-negotiation is busy, then no changes are made. - */ -static void update_linkspeed(struct net_device *dev, int silent) -{ - struct at91_private *lp = netdev_priv(dev); - unsigned int bmsr, bmcr, lpa, mac_cfg; - unsigned int speed, duplex; - - if (!mii_link_ok(&lp->mii)) { /* no link */ - netif_carrier_off(dev); - if (!silent) - printk(KERN_INFO "%s: Link down.\n", dev->name); - return; - } - - /* Link up, or auto-negotiation still in progress */ - read_phy(lp, lp->phy_address, MII_BMSR, &bmsr); - read_phy(lp, lp->phy_address, MII_BMCR, &bmcr); - if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */ - if (!(bmsr & BMSR_ANEGCOMPLETE)) - return; /* Do nothing - another interrupt generated when negotiation complete */ - - read_phy(lp, lp->phy_address, MII_LPA, &lpa); - if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100; - else speed = SPEED_10; - if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL; - else duplex = DUPLEX_HALF; - } else { - speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; - duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; - } - - /* Update the MAC */ - mac_cfg = at91_emac_read(lp, AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD); - if (speed == SPEED_100) { - if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ - mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD; - else /* 100 Half Duplex */ - mac_cfg |= AT91_EMAC_SPD; - } else { - if (duplex == DUPLEX_FULL) /* 10 Full Duplex */ - mac_cfg |= AT91_EMAC_FD; - else {} /* 10 Half Duplex */ - } - at91_emac_write(lp, AT91_EMAC_CFG, mac_cfg); - - if (!silent) - printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); - netif_carrier_on(dev); -} - -/* - * Handle interrupts from the PHY - */ -static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *) dev_id; - struct at91_private *lp = netdev_priv(dev); - unsigned int phy; - - /* - * This hander is triggered on both edges, but the PHY chips expect - * level-triggering. We therefore have to check if the PHY actually has - * an IRQ pending. - */ - enable_mdi(lp); - if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { - read_phy(lp, lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */ - if (!(phy & (1 << 0))) - goto done; - } - else if (lp->phy_type == MII_LXT971A_ID) { - read_phy(lp, lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */ - if (!(phy & (1 << 2))) - goto done; - } - else if (lp->phy_type == MII_BCM5221_ID) { - read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */ - if (!(phy & (1 << 0))) - goto done; - } - else if (lp->phy_type == MII_KS8721_ID) { - read_phy(lp, lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */ - if (!(phy & ((1 << 2) | 1))) - goto done; - } - else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */ - read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &phy); - if (!(phy & ((1 << 2) | 1))) - goto done; - } - else if (lp->phy_type == MII_DP83848_ID) { - read_phy(lp, lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */ - if (!(phy & (1 << 7))) - goto done; - } - - update_linkspeed(dev, 0); - -done: - disable_mdi(lp); - - return IRQ_HANDLED; -} - -/* - * Initialize and enable the PHY interrupt for link-state changes - */ -static void enable_phyirq(struct net_device *dev) -{ - struct at91_private *lp = netdev_priv(dev); - unsigned int dsintr, irq_number; - int status; - - if (!gpio_is_valid(lp->board_data.phy_irq_pin)) { - /* - * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L), - * or board does not have it connected. - */ - mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); - return; - } - - irq_number = gpio_to_irq(lp->board_data.phy_irq_pin); - status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); - if (status) { - printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status); - return; - } - - spin_lock_irq(&lp->lock); - enable_mdi(lp); - - if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ - read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr); - dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ - write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr); - } - else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ - read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr); - dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ - write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr); - } - else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ - dsintr = (1 << 15) | ( 1 << 14); - write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr); - } - else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ - dsintr = (1 << 10) | ( 1 << 8); - write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr); - } - else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ - read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr); - dsintr = dsintr | 0x500; /* set bits 8, 10 */ - write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr); - } - else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ - read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr); - dsintr = dsintr | 0x3c; /* set bits 2..5 */ - write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr); - read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr); - dsintr = dsintr | 0x3; /* set bits 0,1 */ - write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr); - } - - disable_mdi(lp); - spin_unlock_irq(&lp->lock); -} - -/* - * Disable the PHY interrupt - */ -static void disable_phyirq(struct net_device *dev) -{ - struct at91_private *lp = netdev_priv(dev); - unsigned int dsintr; - unsigned int irq_number; - - if (!gpio_is_valid(lp->board_data.phy_irq_pin)) { - del_timer_sync(&lp->check_timer); - return; - } - - spin_lock_irq(&lp->lock); - enable_mdi(lp); - - if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ - read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr); - dsintr = dsintr | 0xf00; /* set bits 8..11 */ - write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr); - } - else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ - read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr); - dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */ - write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr); - } - else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ - read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &dsintr); - dsintr = ~(1 << 14); - write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr); - } - else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ - read_phy(lp, lp->phy_address, MII_TPISTATUS, &dsintr); - dsintr = ~((1 << 10) | (1 << 8)); - write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr); - } - else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ - read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr); - dsintr = dsintr & ~0x500; /* clear bits 8, 10 */ - write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr); - } - else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ - read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr); - dsintr = dsintr & ~0x3; /* clear bits 0, 1 */ - write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr); - read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr); - dsintr = dsintr & ~0x3c; /* clear bits 2..5 */ - write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr); - } - - disable_mdi(lp); - spin_unlock_irq(&lp->lock); - - irq_number = gpio_to_irq(lp->board_data.phy_irq_pin); - free_irq(irq_number, dev); /* Free interrupt handler */ -} - -/* - * Perform a software reset of the PHY. - */ -#if 0 -static void reset_phy(struct net_device *dev) -{ - struct at91_private *lp = netdev_priv(dev); - unsigned int bmcr; - - spin_lock_irq(&lp->lock); - enable_mdi(lp); - - /* Perform PHY reset */ - write_phy(lp, lp->phy_address, MII_BMCR, BMCR_RESET); - - /* Wait until PHY reset is complete */ - do { - read_phy(lp, lp->phy_address, MII_BMCR, &bmcr); - } while (!(bmcr & BMCR_RESET)); - - disable_mdi(lp); - spin_unlock_irq(&lp->lock); -} -#endif - -static void at91ether_check_link(unsigned long dev_id) -{ - struct net_device *dev = (struct net_device *) dev_id; - struct at91_private *lp = netdev_priv(dev); - - enable_mdi(lp); - update_linkspeed(dev, 1); - disable_mdi(lp); - - mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); -} - -/* - * Perform any PHY-specific initialization. - */ -static void __init initialize_phy(struct at91_private *lp) -{ - unsigned int val; - - spin_lock_irq(&lp->lock); - enable_mdi(lp); - - if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { - read_phy(lp, lp->phy_address, MII_DSCR_REG, &val); - if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */ - lp->phy_media = PORT_FIBRE; - } else if (machine_is_csb337()) { - /* mix link activity status into LED2 link state */ - write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x0d22); - } else if (machine_is_ecbat91()) - write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x156A); - - disable_mdi(lp); - spin_unlock_irq(&lp->lock); -} +/* 1518 rounded up */ +#define MAX_RBUFF_SZ 0x600 +/* max number of receive buffers */ +#define MAX_RX_DESCR 9 /* ......................... ADDRESS MANAGEMENT ........................ */ @@ -476,19 +92,19 @@ static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, */ static void __init get_mac_address(struct net_device *dev) { - struct at91_private *lp = netdev_priv(dev); + struct macb *lp = netdev_priv(dev); /* Check Specific-Address 1 */ - if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA1H), at91_emac_read(lp, AT91_EMAC_SA1L))) + if (unpack_mac_address(dev, macb_readl(lp, SA1T), macb_readl(lp, SA1B))) return; /* Check Specific-Address 2 */ - if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA2H), at91_emac_read(lp, AT91_EMAC_SA2L))) + if (unpack_mac_address(dev, macb_readl(lp, SA2T), macb_readl(lp, SA2B))) return; /* Check Specific-Address 3 */ - if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA3H), at91_emac_read(lp, AT91_EMAC_SA3L))) + if (unpack_mac_address(dev, macb_readl(lp, SA3T), macb_readl(lp, SA3B))) return; /* Check Specific-Address 4 */ - if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA4H), at91_emac_read(lp, AT91_EMAC_SA4L))) + if (unpack_mac_address(dev, macb_readl(lp, SA4T), macb_readl(lp, SA4B))) return; printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n"); @@ -499,13 +115,14 @@ static void __init get_mac_address(struct net_device *dev) */ static void update_mac_address(struct net_device *dev) { - struct at91_private *lp = netdev_priv(dev); + struct macb *lp = netdev_priv(dev); - at91_emac_write(lp, AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0])); - at91_emac_write(lp, AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4])); + macb_writel(lp, SA1B, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) + | (dev->dev_addr[1] << 8) | (dev->dev_addr[0])); + macb_writel(lp, SA1T, (dev->dev_addr[5] << 8) | (dev->dev_addr[4])); - at91_emac_write(lp, AT91_EMAC_SA2L, 0); - at91_emac_write(lp, AT91_EMAC_SA2H, 0); + macb_writel(lp, SA2B, 0); + macb_writel(lp, SA2T, 0); } /* @@ -527,246 +144,60 @@ static int set_mac_address(struct net_device *dev, void* addr) return 0; } -static int inline hash_bit_value(int bitnr, __u8 *addr) -{ - if (addr[bitnr / 8] & (1 << (bitnr % 8))) - return 1; - return 0; -} - -/* - * The hash address register is 64 bits long and takes up two locations in the memory map. - * The least significant bits are stored in EMAC_HSL and the most significant - * bits in EMAC_HSH. - * - * The unicast hash enable and the multicast hash enable bits in the network configuration - * register enable the reception of hash matched frames. The destination address is - * reduced to a 6 bit index into the 64 bit hash register using the following hash function. - * The hash function is an exclusive or of every sixth bit of the destination address. - * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] - * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] - * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] - * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] - * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] - * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] - * da[0] represents the least significant bit of the first byte received, that is, the multicast/ - * unicast indicator, and da[47] represents the most significant bit of the last byte - * received. - * If the hash index points to a bit that is set in the hash register then the frame will be - * matched according to whether the frame is multicast or unicast. - * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and - * the hash index points to a bit set in the hash register. - * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the - * hash index points to a bit set in the hash register. - * To receive all multicast frames, the hash register should be set with all ones and the - * multicast hash enable bit should be set in the network configuration register. - */ - -/* - * Return the hash index value for the specified address. - */ -static int hash_get_index(__u8 *addr) -{ - int i, j, bitval; - int hash_index = 0; - - for (j = 0; j < 6; j++) { - for (i = 0, bitval = 0; i < 8; i++) - bitval ^= hash_bit_value(i*6 + j, addr); - - hash_index |= (bitval << j); - } - - return hash_index; -} +/* ................................ MAC ................................ */ /* - * Add multicast addresses to the internal multicast-hash table. + * Initialize and start the Receiver and Transmit subsystems */ -static void at91ether_sethashtable(struct net_device *dev) +static int at91ether_start(struct net_device *dev) { - struct at91_private *lp = netdev_priv(dev); - struct netdev_hw_addr *ha; - unsigned long mc_filter[2]; - unsigned int bitnr; - - mc_filter[0] = mc_filter[1] = 0; - - netdev_for_each_mc_addr(ha, dev) { - bitnr = hash_get_index(ha->addr); - mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); - } - - at91_emac_write(lp, AT91_EMAC_HSL, mc_filter[0]); - at91_emac_write(lp, AT91_EMAC_HSH, mc_filter[1]); -} + struct macb *lp = netdev_priv(dev); + unsigned long ctl; + dma_addr_t addr; + int i; -/* - * Enable/Disable promiscuous and multicast modes. - */ -static void at91ether_set_multicast_list(struct net_device *dev) -{ - struct at91_private *lp = netdev_priv(dev); - unsigned long cfg; - - cfg = at91_emac_read(lp, AT91_EMAC_CFG); - - if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */ - cfg |= AT91_EMAC_CAF; - else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */ - cfg &= ~AT91_EMAC_CAF; - - if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */ - at91_emac_write(lp, AT91_EMAC_HSH, -1); - at91_emac_write(lp, AT91_EMAC_HSL, -1); - cfg |= AT91_EMAC_MTI; - } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */ - at91ether_sethashtable(dev); - cfg |= AT91_EMAC_MTI; - } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */ - at91_emac_write(lp, AT91_EMAC_HSH, 0); - at91_emac_write(lp, AT91_EMAC_HSL, 0); - cfg &= ~AT91_EMAC_MTI; + lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev, + MAX_RX_DESCR * sizeof(struct dma_desc), + &lp->rx_ring_dma, GFP_KERNEL); + if (!lp->rx_ring) { + netdev_err(lp->dev, "unable to alloc rx ring DMA buffer\n"); + return -ENOMEM; } - at91_emac_write(lp, AT91_EMAC_CFG, cfg); -} - -/* ......................... ETHTOOL SUPPORT ........................... */ - -static int mdio_read(struct net_device *dev, int phy_id, int location) -{ - struct at91_private *lp = netdev_priv(dev); - unsigned int value; - - read_phy(lp, phy_id, location, &value); - return value; -} - -static void mdio_write(struct net_device *dev, int phy_id, int location, int value) -{ - struct at91_private *lp = netdev_priv(dev); + lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev, + MAX_RX_DESCR * MAX_RBUFF_SZ, + &lp->rx_buffers_dma, GFP_KERNEL); + if (!lp->rx_buffers) { + netdev_err(lp->dev, "unable to alloc rx data DMA buffer\n"); - write_phy(lp, phy_id, location, value); -} - -static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) -{ - struct at91_private *lp = netdev_priv(dev); - int ret; - - spin_lock_irq(&lp->lock); - enable_mdi(lp); - - ret = mii_ethtool_gset(&lp->mii, cmd); - - disable_mdi(lp); - spin_unlock_irq(&lp->lock); - - if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */ - cmd->supported = SUPPORTED_FIBRE; - cmd->port = PORT_FIBRE; + dma_free_coherent(&lp->pdev->dev, + MAX_RX_DESCR * sizeof(struct dma_desc), + lp->rx_ring, lp->rx_ring_dma); + lp->rx_ring = NULL; + return -ENOMEM; } - return ret; -} - -static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) -{ - struct at91_private *lp = netdev_priv(dev); - int ret; - - spin_lock_irq(&lp->lock); - enable_mdi(lp); - - ret = mii_ethtool_sset(&lp->mii, cmd); - - disable_mdi(lp); - spin_unlock_irq(&lp->lock); - - return ret; -} - -static int at91ether_nwayreset(struct net_device *dev) -{ - struct at91_private *lp = netdev_priv(dev); - int ret; - - spin_lock_irq(&lp->lock); - enable_mdi(lp); - - ret = mii_nway_restart(&lp->mii); - - disable_mdi(lp); - spin_unlock_irq(&lp->lock); - - return ret; -} - -static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) -{ - strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); - strlcpy(info->version, DRV_VERSION, sizeof(info->version)); - strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info)); -} - -static const struct ethtool_ops at91ether_ethtool_ops = { - .get_settings = at91ether_get_settings, - .set_settings = at91ether_set_settings, - .get_drvinfo = at91ether_get_drvinfo, - .nway_reset = at91ether_nwayreset, - .get_link = ethtool_op_get_link, -}; - -static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -{ - struct at91_private *lp = netdev_priv(dev); - int res; - - if (!netif_running(dev)) - return -EINVAL; - - spin_lock_irq(&lp->lock); - enable_mdi(lp); - res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL); - disable_mdi(lp); - spin_unlock_irq(&lp->lock); - - return res; -} - -/* ................................ MAC ................................ */ - -/* - * Initialize and start the Receiver and Transmit subsystems - */ -static void at91ether_start(struct net_device *dev) -{ - struct at91_private *lp = netdev_priv(dev); - struct recv_desc_bufs *dlist, *dlist_phys; - int i; - unsigned long ctl; - - dlist = lp->dlist; - dlist_phys = lp->dlist_phys; - + addr = lp->rx_buffers_dma; for (i = 0; i < MAX_RX_DESCR; i++) { - dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0]; - dlist->descriptors[i].size = 0; + lp->rx_ring[i].addr = addr; + lp->rx_ring[i].ctrl = 0; + addr += MAX_RBUFF_SZ; } /* Set the Wrap bit on the last descriptor */ - dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP; + lp->rx_ring[MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP); /* Reset buffer index */ - lp->rxBuffIndex = 0; + lp->rx_tail = 0; /* Program address of descriptor list in Rx Buffer Queue register */ - at91_emac_write(lp, AT91_EMAC_RBQP, (unsigned long) dlist_phys); + macb_writel(lp, RBQP, lp->rx_ring_dma); /* Enable Receive and Transmit */ - ctl = at91_emac_read(lp, AT91_EMAC_CTL); - at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE); + ctl = macb_readl(lp, NCR); + macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE)); + + return 0; } /* @@ -774,38 +205,34 @@ static void at91ether_start(struct net_device *dev) */ static int at91ether_open(struct net_device *dev) { - struct at91_private *lp = netdev_priv(dev); + struct macb *lp = netdev_priv(dev); unsigned long ctl; + int ret; if (!is_valid_ether_addr(dev->dev_addr)) return -EADDRNOTAVAIL; - clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */ - /* Clear internal statistics */ - ctl = at91_emac_read(lp, AT91_EMAC_CTL); - at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_CSR); + ctl = macb_readl(lp, NCR); + macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT)); /* Update the MAC address (incase user has changed it) */ update_mac_address(dev); - /* Enable PHY interrupt */ - enable_phyirq(dev); + ret = at91ether_start(dev); + if (ret) + return ret; /* Enable MAC interrupts */ - at91_emac_write(lp, AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA - | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM - | AT91_EMAC_ROVR | AT91_EMAC_ABT); - - /* Determine current link speed */ - spin_lock_irq(&lp->lock); - enable_mdi(lp); - update_linkspeed(dev, 0); - disable_mdi(lp); - spin_unlock_irq(&lp->lock); - - at91ether_start(dev); + macb_writel(lp, IER, MACB_BIT(RCOMP) | MACB_BIT(RXUBR) + | MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE) | MACB_BIT(TCOMP) + | MACB_BIT(ISR_ROVR) | MACB_BIT(HRESP)); + + /* schedule a link state check */ + phy_start(lp->phy_dev); + netif_start_queue(dev); + return 0; } @@ -814,24 +241,30 @@ static int at91ether_open(struct net_device *dev) */ static int at91ether_close(struct net_device *dev) { - struct at91_private *lp = netdev_priv(dev); + struct macb *lp = netdev_priv(dev); unsigned long ctl; /* Disable Receiver and Transmitter */ - ctl = at91_emac_read(lp, AT91_EMAC_CTL); - at91_emac_write(lp, AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE)); - - /* Disable PHY interrupt */ - disable_phyirq(dev); + ctl = macb_readl(lp, NCR); + macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE))); /* Disable MAC interrupts */ - at91_emac_write(lp, AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA - | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM - | AT91_EMAC_ROVR | AT91_EMAC_ABT); + macb_writel(lp, IDR, MACB_BIT(RCOMP) | MACB_BIT(RXUBR) |