diff options
81 files changed, 237 insertions, 444 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e55bbd32dca..50d9f3e4e0f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -287,6 +287,7 @@ config ARCH_IXP2000 config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU + select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS help diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index 6fbe7722aa4..b36b1e8a105 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c @@ -6,7 +6,7 @@ * copy data to/from buffers located outside the DMA region. This * only works for systems in which DMA memory is at the bottom of * RAM, the remainder of memory is at the top and the DMA memory - * can be marked as ZONE_DMA. Anything beyond that such as discontigous + * can be marked as ZONE_DMA. Anything beyond that such as discontiguous * DMA windows will require custom implementations that reserve memory * areas at early bootup. * diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 4deece5fbdf..0c89bd35e06 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -72,7 +72,7 @@ static inline unsigned int gic_irq(unsigned int irq) * unmask it, in the same way we need to unmask an interrupt when * we first enable it. * - * The GIC has a seperate notion of "end of interrupt" to re-enable + * The GIC has a separate notion of "end of interrupt" to re-enable * an interrupt after handling, in order to support hardware * prioritisation. * @@ -125,12 +125,11 @@ static void gic_set_cpu(unsigned int irq, cpumask_t mask_val) } #endif -static void fastcall gic_handle_cascade_irq(unsigned int irq, - struct irq_desc *desc) +static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { struct gic_chip_data *chip_data = get_irq_data(irq); struct irq_chip *chip = get_irq_chip(irq); - unsigned int cascade_irq; + unsigned int cascade_irq, gic_irq; unsigned long status; /* primary controller ack'ing */ @@ -140,16 +139,15 @@ static void fastcall gic_handle_cascade_irq(unsigned int irq, status = readl(chip_data->cpu_base + GIC_CPU_INTACK); spin_unlock(&irq_controller_lock); - cascade_irq = (status & 0x3ff); - if (cascade_irq > 1020) + gic_irq = (status & 0x3ff); + if (gic_irq == 1023) goto out; - if (cascade_irq < 32 || cascade_irq >= NR_IRQS) { - do_bad_IRQ(cascade_irq, desc); - goto out; - } - cascade_irq += chip_data->irq_offset; - generic_handle_irq(cascade_irq); + cascade_irq = gic_irq + chip_data->irq_offset; + if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) + do_bad_IRQ(cascade_irq, desc); + else + generic_handle_irq(cascade_irq); out: /* primary controller unmasking */ diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c index c94864c5b1a..aad4d94ba8f 100644 --- a/arch/arm/common/sharpsl_param.c +++ b/arch/arm/common/sharpsl_param.c @@ -20,7 +20,7 @@ * typically including LCD parameters are loaded by the bootloader at the * address PARAM_BASE. As the kernel will overwrite them, we need to store * them early in the boot process, then pass them to the appropriate drivers. - * Not all devices use all paramaters but the format is common to all. + * Not all devices use all parameters but the format is common to all. */ #ifdef CONFIG_ARCH_SA1100 #define PARAM_BASE 0xe8ffc000 diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c index 5972df2b9af..3bf3a927ae2 100644 --- a/arch/arm/common/sharpsl_pm.c +++ b/arch/arm/common/sharpsl_pm.c @@ -153,7 +153,7 @@ static void sharpsl_battery_thread(struct work_struct *private_) sharpsl_pm.battstat.mainbat_percent = percent; } - dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %d\n", voltage, + dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage, sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies); /* If battery is low. limit backlight intensity to save power. */ @@ -291,7 +291,7 @@ static void sharpsl_chrg_full_timer(unsigned long data) } /* Charging Finished Interrupt (Not present on Corgi) */ -/* Can trigger at the same time as an AC staus change so +/* Can trigger at the same time as an AC status change so delay until after that has been processed */ irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id) { @@ -625,7 +625,7 @@ static int sharpsl_fatal_check(void) } temp = get_select_val(buff); - dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %d\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT)); + dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %ld\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT)); if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) || (!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt))) @@ -635,7 +635,7 @@ static int sharpsl_fatal_check(void) static int sharpsl_off_charge_error(void) { - dev_err(sharpsl_pm.dev, "Offline Charger: Error occured.\n"); + dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n"); sharpsl_pm.machinfo->charge(0); sharpsl_pm_led(SHARPSL_LED_ERROR); sharpsl_pm.charge_mode = CHRG_ERROR; @@ -691,14 +691,14 @@ static int sharpsl_off_charge_battery(void) time = RCNR; while(1) { - /* Check if any wakeup event had occured */ + /* Check if any wakeup event had occurred */ if (sharpsl_pm.machinfo->charger_wakeup() != 0) return 0; /* Check for timeout */ if ((RCNR - time) > SHARPSL_WAIT_CO_TIME) return 1; if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) { - dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occured. Retrying to check\n"); + dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occurred. Retrying to check\n"); sharpsl_pm.full_count++; sharpsl_pm.machinfo->charge(0); mdelay(SHARPSL_CHARGE_WAIT_TIME); @@ -714,7 +714,7 @@ static int sharpsl_off_charge_battery(void) time = RCNR; while(1) { - /* Check if any wakeup event had occured */ + /* Check if any wakeup event had occurred */ if (sharpsl_pm.machinfo->charger_wakeup() != 0) return 0; /* Check for timeout */ @@ -774,6 +774,8 @@ static struct pm_ops sharpsl_pm_ops = { static int __init sharpsl_pm_probe(struct platform_device *pdev) { + int ret; + if (!pdev->dev.platform_data) return -EINVAL; @@ -792,8 +794,10 @@ static int __init sharpsl_pm_probe(struct platform_device *pdev) sharpsl_pm.machinfo->init(); - device_create_file(&pdev->dev, &dev_attr_battery_percentage); - device_create_file(&pdev->dev, &dev_attr_battery_voltage); + ret = device_create_file(&pdev->dev, &dev_attr_battery_percentage); + ret |= device_create_file(&pdev->dev, &dev_attr_battery_voltage); + if (ret != 0) + dev_warn(&pdev->dev, "Failed to register attributes (%d)\n", ret); apm_get_power_status = sharpsl_apm_get_power_status; diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 3c078e34675..3278e713c32 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -85,7 +85,7 @@ int main(void) DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0)); DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); BLANK(); -#if __LINUX_ARM_ARCH__ >= 6 +#ifdef CONFIG_CPU_HAS_ASID DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); BLANK(); #endif diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index ae89cdd82b1..19326d7cdeb 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -357,6 +357,10 @@ /* 345 */ CALL(sys_getcpu) CALL(sys_ni_syscall) /* eventually epoll_pwait */ CALL(sys_kexec_load) + CALL(sys_utimensat) + CALL(sys_signalfd) +/* 350 */ CALL(sys_timerfd) + CALL(sys_eventfd) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 0453dcc757b..650eac1bc0a 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -918,7 +918,7 @@ static int c_show(struct seq_file *m, void *v) if ((processor_id & 0x0008f000) == 0x00000000) { /* pre-ARM7 */ - seq_printf(m, "CPU part\t\t: %07x\n", processor_id >> 4); + seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4); } else { if ((processor_id & 0x0008f000) == 0x00007000) { /* ARM7 */ diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index 3d4fcbc1627..1ca2d5174fc 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -320,7 +320,7 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[]) EXPORT_SYMBOL(kernel_execve); /* - * Since loff_t is a 64 bit type we avoid a lot of ABI hastle + * Since loff_t is a 64 bit type we avoid a lot of ABI hassle * with a different argument ordering. */ asmlinkage long sys_arm_fadvise64_64(int fd, int advice, diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h index 54225102174..2e787d40d59 100644 --- a/arch/arm/lib/bitops.h +++ b/arch/arm/lib/bitops.h @@ -47,7 +47,7 @@ * @store: store instruction * * Note: we can trivially conditionalise the store instruction - * to avoid dirting the data cache. + * to avoid dirtying the data cache. */ .macro testop, instr, store add r1, r1, r0, lsr #3 diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index b4518619063..76ec856cd4f 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c @@ -79,7 +79,7 @@ static struct at91_udc_data __initdata carmeva_udc_data = { .pullup_pin = AT91_PIN_PD9, }; -/* FIXME: user dependend */ +/* FIXME: user dependant */ // static struct at91_cf_data __initdata carmeva_cf_data = { // .det_pin = AT91_PIN_PB0, // .rst_pin = AT91_PIN_PC5, @@ -100,17 +100,17 @@ static struct spi_board_info carmeva_spi_devices[] = { .chip_select = 0, .max_speed_hz = 10 * 1000 * 1000, }, - { /* User accessable spi - cs1 (250KHz) */ + { /* User accessible spi - cs1 (250KHz) */ .modalias = "spi-cs1", .chip_select = 1, .max_speed_hz = 250 * 1000, }, - { /* User accessable spi - cs2 (1MHz) */ + { /* User accessible spi - cs2 (1MHz) */ .modalias = "spi-cs2", .chip_select = 2, .max_speed_hz = 1 * 1000 * 1000, }, - { /* User accessable spi - cs3 (10MHz) */ + { /* User accessible spi - cs3 (10MHz) */ .modalias = "spi-cs3", .chip_select = 3, .max_speed_hz = 10 * 1000 * 1000, diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c index 82e420d6fd1..0a1a25fb8ba 100644 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ b/arch/arm/mach-h720x/cpu-h7202.c @@ -143,7 +143,7 @@ h7202_timer_interrupt(int irq, void *dev_id) } /* - * mask multiplexed timer irq's + * mask multiplexed timer IRQs */ static void inline mask_timerx_irq (u32 irq) { @@ -153,7 +153,7 @@ static void inline mask_timerx_irq (u32 irq) } /* - * unmask multiplexed timer irq's + * unmask multiplexed timer IRQs */ static void inline unmask_timerx_irq (u32 irq) { diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c index 7e70e0b0b98..467d899fbe7 100644 --- a/arch/arm/mach-imx/cpufreq.c +++ b/arch/arm/mach-imx/cpufreq.c @@ -245,7 +245,7 @@ static int imx_set_target(struct cpufreq_policy *policy, if(mpctl0) { CSCR |= CSCR_MPLL_RESTART; - /* Wait until MPLL is stablized */ + /* Wait until MPLL is stabilized */ while( CSCR & CSCR_MPLL_RESTART ); imx_set_async_mode(); diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c index 6d50d85a618..bc6fb02d213 100644 --- a/arch/arm/mach-imx/dma.c +++ b/arch/arm/mach-imx/dma.c @@ -131,7 +131,7 @@ imx_dma_setup_sg_base(imx_dmach_t dma_ch, * The function setups DMA channel source and destination addresses for transfer * specified by provided parameters. The scatter-gather emulation is disabled, * because linear data block - * form the physical address range is transfered. + * form the physical address range is transferred. * Return value: if incorrect parameters are provided -%EINVAL. * Zero indicates success. */ @@ -192,7 +192,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory * or %DMA_MODE_WRITE from memory to the device * - * The function setups DMA channel state and registers to be ready for transfer + * The function sets up DMA channel state and registers to be ready for transfer * specified by provided parameters. The scatter-gather emulation is set up * according to the parameters. * @@ -212,7 +212,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, * * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x * - * Be carefull there and do not mistakenly mix source and target device + * Be careful here and do not mistakenly mix source and target device * port sizes constants, they are really different: * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 @@ -495,7 +495,7 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id) /* * The cleaning of @sg field would be questionable * there, because its value can help to compute - * remaining/transfered bytes count in the handler + * remaining/transferred bytes count in the handler */ /*imx_dma_channels[i].sg = NULL;*/ diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile index ebb255bdce8..158daaf9e3b 100644 --- a/arch/arm/mach-integrator/Makefile +++ b/arch/arm/mach-integrator/Makefile @@ -12,4 +12,3 @@ obj-$(CONFIG_LEDS) += leds.o obj-$(CONFIG_PCI) += pci_v3.o pci.o obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 897c21c2fb5..e9c82deb791 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -257,23 +257,7 @@ integrator_timer_interrupt(int irq, void *dev_id) */ writel(1, TIMER1_VA_BASE + TIMER_INTCLR); - /* - * the clock tick routines are only processed on the - * primary CPU - */ - if (hard_smp_processor_id() == 0) { - timer_tick(); -#ifdef CONFIG_SMP - smp_send_timer(); -#endif - } - -#ifdef CONFIG_SMP - /* - * this is the ARM equivalent of the APIC timer interrupt - */ - update_process_times(user_mode(get_irq_regs())); -#endif /* CONFIG_SMP */ + timer_tick(); write_sequnlock(&xtime_lock); diff --git a/arch/arm/mach-integrator/headsmp.S b/arch/arm/mach-integrator/headsmp.S deleted file mode 100644 index ceaa88e30d7..00000000000 --- a/arch/arm/mach-integrator/headsmp.S |