diff options
| -rw-r--r-- | drivers/usb/dwc3/ep0.c | 6 | ||||
| -rw-r--r-- | drivers/usb/dwc3/gadget.c | 40 | ||||
| -rw-r--r-- | drivers/usb/dwc3/gadget.h | 139 |
3 files changed, 48 insertions, 137 deletions
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 2def48ed30e..69a4e43ddf5 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -103,10 +103,8 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, dwc3_trb_to_hw(&trb, trb_hw); memset(¶ms, 0, sizeof(params)); - params.param0.depstrtxfer.transfer_desc_addr_high = - upper_32_bits(dwc->ep0_trb_addr); - params.param1.depstrtxfer.transfer_desc_addr_low = - lower_32_bits(dwc->ep0_trb_addr); + params.param0 = upper_32_bits(dwc->ep0_trb_addr); + params.param1 = lower_32_bits(dwc->ep0_trb_addr); ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, DWC3_DEPCMD_STARTTRANSFER, ¶ms); diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index fd1ac4dd560..fa824cfdd2e 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -158,12 +158,12 @@ int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", dep->name, - dwc3_gadget_ep_cmd_string(cmd), params->param0.raw, - params->param1.raw, params->param2.raw); + dwc3_gadget_ep_cmd_string(cmd), params->param0, + params->param1, params->param2); - dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0.raw); - dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1.raw); - dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2.raw); + dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); + dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); + dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); do { @@ -257,21 +257,21 @@ static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, memset(¶ms, 0x00, sizeof(params)); - params.param0.depcfg.ep_type = usb_endpoint_type(desc); - params.param0.depcfg.max_packet_size = usb_endpoint_maxp(desc); - params.param0.depcfg.burst_size = dep->endpoint.maxburst; + params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) + | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) + | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst); - params.param1.depcfg.xfer_complete_enable = true; - params.param1.depcfg.xfer_not_ready_enable = true; + params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN + | DWC3_DEPCFG_XFER_NOT_READY_EN; if (usb_endpoint_xfer_bulk(desc) && dep->endpoint.max_streams) { - params.param1.depcfg.stream_capable = true; - params.param1.depcfg.stream_event_enable = true; + params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE + | DWC3_DEPCFG_STREAM_EVENT_EN; dep->stream_capable = true; } if (usb_endpoint_xfer_isoc(desc)) - params.param1.depcfg.xfer_in_progress_enable = true; + params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; /* * We are doing 1:1 mapping for endpoints, meaning @@ -279,17 +279,17 @@ static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, * so on. We consider the direction bit as part of the physical * endpoint number. So USB endpoint 0x81 is 0x03. */ - params.param1.depcfg.ep_number = dep->number; + params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); /* * We must use the lower 16 TX FIFOs even though * HW might have more */ if (dep->direction) - params.param0.depcfg.fifo_number = dep->number >> 1; + params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); if (desc->bInterval) { - params.param1.depcfg.binterval_m1 = desc->bInterval - 1; + params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); dep->interval = 1 << (desc->bInterval - 1); } @@ -303,7 +303,7 @@ static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) memset(¶ms, 0x00, sizeof(params)); - params.param0.depxfercfg.number_xfer_resources = 1; + params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); return dwc3_send_gadget_ep_cmd(dwc, dep->number, DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); @@ -719,10 +719,8 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, } memset(¶ms, 0, sizeof(params)); - params.param0.depstrtxfer.transfer_desc_addr_high = - upper_32_bits(req->trb_dma); - params.param1.depstrtxfer.transfer_desc_addr_low = - lower_32_bits(req->trb_dma); + params.param0 = upper_32_bits(req->trb_dma); + params.param1 = lower_32_bits(req->trb_dma); if (start_new) cmd = DWC3_DEPCMD_STARTTRANSFER; diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h index b025651e013..71145a449d9 100644 --- a/drivers/usb/dwc3/gadget.h +++ b/drivers/usb/dwc3/gadget.h @@ -47,120 +47,35 @@ struct dwc3; #define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint)) #define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget)) -/** - * struct dwc3_gadget_ep_depcfg_param1 - DEPCMDPAR0 for DEPCFG command - * @interrupt_number: self-explanatory - * @reserved7_5: set to zero - * @xfer_complete_enable: event generated when transfer completed - * @xfer_in_progress_enable: event generated when transfer in progress - * @xfer_not_ready_enable: event generated when transfer not read - * @fifo_error_enable: generates events when FIFO Underrun (IN eps) - * or FIFO Overrun (OUT) eps - * @reserved_12: set to zero - * @stream_event_enable: event generated on stream - * @reserved14_15: set to zero - * @binterval_m1: bInterval minus 1 - * @stream_capable: this EP is capable of handling streams - * @ep_number: self-explanatory - * @bulk_based: Set to ‘1’ if this isochronous endpoint represents a bulk - * data stream that ignores the relationship of bus time to the - * intervals programmed in TRBs. - * @fifo_based: Set to ‘1’ if this isochronous endpoint represents a - * FIFO-based data stream where TRBs have fixed values and are never - * written back by the core. - */ -struct dwc3_gadget_ep_depcfg_param1 { - u32 interrupt_number:5; - u32 reserved7_5:3; /* set to zero */ - u32 xfer_complete_enable:1; - u32 xfer_in_progress_enable:1; - u32 xfer_not_ready_enable:1; - u32 fifo_error_enable:1; /* IN-underrun, OUT-overrun */ - u32 reserved12:1; /* set to zero */ - u32 stream_event_enable:1; - u32 reserved14_15:2; - u32 binterval_m1:8; /* bInterval minus 1 */ - u32 stream_capable:1; - u32 ep_number:5; - u32 bulk_based:1; - u32 fifo_based:1; -} __packed; - -/** - * struct dwc3_gadget_ep_depcfg_param0 - Parameter 0 for DEPCFG - * @reserved0: set to zero - * @ep_type: Endpoint Type (control, bulk, iso, interrupt) - * @max_packet_size: max packet size in bytes - * @reserved16_14: set to zero - * @fifo_number: self-explanatory - * @burst_size: burst size minus 1 - * @data_sequence_number: Must be 0 when an endpoint is initially configured - * May be non-zero when an endpoint is configured after a power transition - * that requires a save/restore. - * @ignore_sequence_number: Set to ‘1’ to avoid resetting the sequence - * number. This setting is used by software to modify the DEPEVTEN - * event enable bits without modifying other endpoint settings. - */ -struct dwc3_gadget_ep_depcfg_param0 { - u32 reserved0:1; - u32 ep_type:2; - u32 max_packet_size:11; - u32 reserved16_14:3; - u32 fifo_number:5; - u32 burst_size:4; - u32 data_sequence_number:5; - u32 ignore_sequence_number:1; -} __packed; - -/** - * struct dwc3_gadget_ep_depxfercfg_param0 - Parameter 0 of DEPXFERCFG - * @number_xfer_resources: Defines the number of Transfer Resources allocated - * to this endpoint. This field must be set to 1. - * @reserved16_31: set to zero; - */ -struct dwc3_gadget_ep_depxfercfg_param0 { - u32 number_xfer_resources:16; - u32 reserved16_31:16; -} __packed; - -/** - * struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER - * @transfer_desc_addr_low: Indicates the lower 32 bits of the external - * memory's start address for the transfer descriptor. Because TRBs - * must be aligned to a 16-byte boundary, the lower 4 bits of this - * address must be 0. - */ -struct dwc3_gadget_ep_depstrtxfer_param1 { - u32 transfer_desc_addr_low; -} __packed; - -/** - * struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER - * @transfer_desc_addr_high: Indicates the higher 32 bits of the external - * memory’s start address for the transfer descriptor. - */ -struct dwc3_gadget_ep_depstrtxfer_param0 { - u32 transfer_desc_addr_high; -} __packed; +/* DEPCFG parameter 1 */ +#define DWC3_DEPCFG_INT_NUM(n) ((n) << 0) +#define DWC3_DEPCFG_XFER_COMPLETE_EN (1 << 8) +#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9) +#define DWC3_DEPCFG_XFER_NOT_READY_EN (1 << 10) +#define DWC3_DEPCFG_FIFO_ERROR_EN (1 << 11) +#define DWC3_DEPCFG_STREAM_EVENT_EN (1 << 13) +#define DWC3_DEPCFG_BINTERVAL_M1(n) ((n) << 16) +#define DWC3_DEPCFG_STREAM_CAPABLE (1 << 24) +#define DWC3_DEPCFG_EP_NUMBER(n) ((n) << 25) +#define DWC3_DEPCFG_BULK_BASED (1 << 30) +#define DWC3_DEPCFG_FIFO_BASED (1 << 31) + +/* DEPCFG parameter 0 */ +#define DWC3_DEPCFG_EP_TYPE(n) ((n) << 1) +#define DWC3_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3) +#define DWC3_DEPCFG_FIFO_NUMBER(n) ((n) << 17) +#define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22) +#define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26) +#define DWC3_DEPCFG_IGN_SEQ_NUM (1 << 31) + +/* DEPXFERCFG parameter 0 */ +#define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff) struct dwc3_gadget_ep_cmd_params { - union { - u32 raw; - } param2; - - union { - u32 raw; - struct dwc3_gadget_ep_depcfg_param1 depcfg; - struct dwc3_gadget_ep_depstrtxfer_param1 depstrtxfer; - } param1; - - union { - u32 raw; - struct dwc3_gadget_ep_depcfg_param0 depcfg; - struct dwc3_gadget_ep_depxfercfg_param0 depxfercfg; - struct dwc3_gadget_ep_depstrtxfer_param0 depstrtxfer; - } param0; -} __packed; + u32 param2; + u32 param1; + u32 param0; +}; /* -------------------------------------------------------------------------- */ |