diff options
61 files changed, 1234 insertions, 883 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8d39c8ba969..fe31c8c6b3e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -562,6 +562,7 @@ config ARCH_DOVE select PINCTRL_DOVE select PLAT_ORION_LEGACY select USB_ARCH_HAS_EHCI + select MVEBU_MBUS help Support for the Marvell Dove SoC 88AP510 @@ -575,6 +576,7 @@ config ARCH_KIRKWOOD select PINCTRL select PINCTRL_KIRKWOOD select PLAT_ORION_LEGACY + select MVEBU_MBUS help Support for the following Marvell Kirkwood series SoCs: 88F6180, 88F6192 and 88F6281. @@ -586,6 +588,7 @@ config ARCH_MV78XX0 select GENERIC_CLOCKEVENTS select PCI select PLAT_ORION_LEGACY + select MVEBU_MBUS help Support for the following Marvell MV78xx0 series SoCs: MV781x0, MV782x0. @@ -598,6 +601,7 @@ config ARCH_ORION5X select GENERIC_CLOCKEVENTS select PCI select PLAT_ORION_LEGACY + select MVEBU_MBUS help Support for the following Marvell Orion 5x series SoCs: Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 5b708208b60..7704829a12c 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -73,11 +73,6 @@ clocks = <&coreclk 2>; }; - addr-decoding@d0020000 { - compatible = "marvell,armada-addr-decoding-controller"; - reg = <0xd0020000 0x258>; - }; - sata@d00a0000 { compatible = "marvell,orion-sata"; reg = <0xd00a0000 0x2400>; diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S index 865c6d02b33..df191afa3be 100644 --- a/arch/arm/include/debug/mvebu.S +++ b/arch/arm/include/debug/mvebu.S @@ -12,7 +12,7 @@ */ #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 -#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000 +#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000 .macro addruart, rp, rv, tmp ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index 3f0a858fb59..4d9d2ffc453 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o irq.o +obj-y += common.o irq.o obj-$(CONFIG_DOVE_LEGACY) += mpp.o obj-$(CONFIG_PCI) += pcie.o obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c deleted file mode 100644 index 2a06c016341..00000000000 --- a/arch/arm/mach-dove/addr-map.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * arch/arm/mach-dove/addr-map.c - * - * Address map functions for Marvell Dove 88AP510 SoC - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include <asm/mach/arch.h> -#include <asm/setup.h> -#include <mach/dove.h> -#include <plat/addr-map.h> -#include "common.h" - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DDR 0x0 -#define TARGET_BOOTROM 0x1 -#define TARGET_CESA 0x3 -#define TARGET_PCIE0 0x4 -#define TARGET_PCIE1 0x8 -#define TARGET_SCRATCHPAD 0xd - -#define ATTR_CESA 0x01 -#define ATTR_BOOTROM 0xfd -#define ATTR_DEV_SPI0_ROM 0xfe -#define ATTR_DEV_SPI1_ROM 0xfb -#define ATTR_PCIE_IO 0xe0 -#define ATTR_PCIE_MEM 0xe8 -#define ATTR_SCRATCHPAD 0x0 - -static inline void __iomem *ddr_map_sc(int i) -{ - return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); -} - -/* - * Description of the windows needed by the platform code - */ -static struct __initdata orion_addr_map_cfg addr_map_cfg = { - .num_wins = 8, - .remappable_wins = 4, - .bridge_virt_base = BRIDGE_VIRT_BASE, -}; - -static const struct __initdata orion_addr_map_info addr_map_info[] = { - /* - * Windows for PCIe IO+MEM space. - */ - { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, - TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE - }, - { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, - TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE - }, - { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, - TARGET_PCIE0, ATTR_PCIE_MEM, -1 - }, - { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, - TARGET_PCIE1, ATTR_PCIE_MEM, -1 - }, - /* - * Window for CESA engine. - */ - { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, - TARGET_CESA, ATTR_CESA, -1 - }, - /* - * Window to the BootROM for Standby and Sleep Resume - */ - { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, - TARGET_BOOTROM, ATTR_BOOTROM, -1 - }, - /* - * Window to the PMU Scratch Pad space - */ - { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, - TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1 - }, - /* End marker */ - { -1, 0, 0, 0, 0, 0 } -}; - -void __init dove_setup_cpu_mbus(void) -{ - int i; - int cs; - - /* - * Disable, clear and configure windows. - */ - orion_config_wins(&addr_map_cfg, addr_map_info); - - /* - * Setup MBUS dram target info. - */ - orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - for (i = 0, cs = 0; i < 2; i++) { - u32 map = readl(ddr_map_sc(i)); - - /* - * Chip select enabled? - */ - if (map & 1) { - struct mbus_dram_window *w; - - w = &orion_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0; /* CS address decoding done inside */ - /* the DDR controller, no need to */ - /* provide attributes */ - w->base = map & 0xff800000; - w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); - } - } - orion_mbus_dram_info.num_cs = cs; -} diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c index fbde1dd6711..0b142803b2e 100644 --- a/arch/arm/mach-dove/board-dt.c +++ b/arch/arm/mach-dove/board-dt.c @@ -64,7 +64,7 @@ static void __init dove_dt_init(void) #ifdef CONFIG_CACHE_TAUROS2 tauros2_init(0); #endif - dove_setup_cpu_mbus(); + dove_setup_cpu_wins(); /* Setup root of clk tree */ dove_of_clk_init(); diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index c6b3b2bb50e..e2b5da031f9 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -224,6 +224,9 @@ void __init dove_i2c_init(void) void __init dove_init_early(void) { orion_time_set_base(TIMER_VIRT_BASE); + mvebu_mbus_init("marvell,dove-mbus", + BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, + DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); } static int __init dove_find_tclk(void) @@ -326,6 +329,40 @@ void __init dove_sdio1_init(void) platform_device_register(&dove_sdio1); } +void __init dove_setup_cpu_wins(void) +{ + /* + * The PCIe windows will no longer be statically allocated + * here once Dove is migrated to the pci-mvebu driver. + */ + mvebu_mbus_add_window_remap_flags("pcie0.0", + DOVE_PCIE0_IO_PHYS_BASE, + DOVE_PCIE0_IO_SIZE, + DOVE_PCIE0_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie1.0", + DOVE_PCIE1_IO_PHYS_BASE, + DOVE_PCIE1_IO_SIZE, + DOVE_PCIE1_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie0.0", + DOVE_PCIE0_MEM_PHYS_BASE, + DOVE_PCIE0_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window_remap_flags("pcie1.0", + DOVE_PCIE1_MEM_PHYS_BASE, + DOVE_PCIE1_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE, + DOVE_CESA_SIZE); + mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE, + DOVE_BOOTROM_SIZE); + mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE, + DOVE_SCRATCHPAD_SIZE); +} + void __init dove_init(void) { pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", @@ -334,7 +371,7 @@ void __init dove_init(void) #ifdef CONFIG_CACHE_TAUROS2 tauros2_init(0); #endif - dove_setup_cpu_mbus(); + dove_setup_cpu_wins(); /* Setup root of clk tree */ dove_clk_init(); diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h index ee59fba4c6d..e86347928b6 100644 --- a/arch/arm/mach-dove/common.h +++ b/arch/arm/mach-dove/common.h @@ -23,7 +23,7 @@ void dove_map_io(void); void dove_init(void); void dove_init_early(void); void dove_init_irq(void); -void dove_setup_cpu_mbus(void); +void dove_setup_cpu_wins(void); void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); void dove_sata_init(struct mv_sata_platform_data *sata_data); #ifdef CONFIG_PCI diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index 661725e3115..0c4b35f4ee5 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -77,6 +77,8 @@ /* North-South Bridge */ #define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) #define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) +#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) +#define BRIDGE_WINS_SZ (0x80) /* Cryptographic Engine */ #define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) @@ -168,6 +170,9 @@ #define DOVE_SSP_CLOCK_ENABLE (1 << 1) #define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) /* Memory Controller */ +#define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000) +#define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100) +#define DOVE_MC_WINS_SZ (0x8) #define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) /* LCD Controller */ diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 4cc4bee4d0c..d805f8078fa 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o irq.o pcie.o mpp.o +obj-y += common.o irq.o pcie.o mpp.o obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c deleted file mode 100644 index 8f0d162a1e1..00000000000 --- a/arch/arm/mach-kirkwood/addr-map.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * arch/arm/mach-kirkwood/addr-map.c - * - * Address map functions for Marvell Kirkwood SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <plat/addr-map.h> -#include "common.h" - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DEV_BUS 1 -#define TARGET_SRAM 3 -#define TARGET_PCIE 4 -#define ATTR_DEV_SPI_ROM 0x1e -#define ATTR_DEV_BOOT 0x1d -#define ATTR_DEV_NAND 0x2f -#define ATTR_DEV_CS3 0x37 -#define ATTR_DEV_CS2 0x3b -#define ATTR_DEV_CS1 0x3d -#define ATTR_DEV_CS0 0x3e -#define ATTR_PCIE_IO 0xe0 -#define ATTR_PCIE_MEM 0xe8 -#define ATTR_PCIE1_IO 0xd0 -#define ATTR_PCIE1_MEM 0xd8 -#define ATTR_SRAM 0x01 - -/* - * Description of the windows needed by the platform code - */ -static struct __initdata orion_addr_map_cfg addr_map_cfg = { - .num_wins = 8, - .remappable_wins = 4, - .bridge_virt_base = BRIDGE_VIRT_BASE, -}; - -static const struct __initdata orion_addr_map_info addr_map_info[] = { - /* - * Windows for PCIe IO+MEM space. - */ - { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE - }, - { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE - }, - { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, - TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE - }, - { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE - }, - /* - * Window for NAND controller. - */ - { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, - TARGET_DEV_BUS, ATTR_DEV_NAND, -1 - }, - /* - * Window for SRAM. - */ - { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, - TARGET_SRAM, ATTR_SRAM, -1 - }, - /* End marker */ - { -1, 0, 0, 0, 0, 0 } -}; - -void __init kirkwood_setup_cpu_mbus(void) -{ - /* - * Disable, clear and configure windows. - */ - orion_config_wins(&addr_map_cfg, addr_map_info); - - /* - * Setup MBUS dram target info. - */ - orion_setup_cpu_mbus_target(&addr_map_cfg, - (void __iomem *) DDR_WINDOW_CPU_BASE); -} diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index d367aa6b47b..f5437c27dc2 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -93,7 +93,7 @@ static void __init kirkwood_dt_init(void) */ writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); - kirkwood_setup_cpu_mbus(); + kirkwood_setup_wins(); kirkwood_l2_init(); diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 49792a0cd2d..c2cae69e6d2 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -33,7 +33,6 @@ #include <linux/platform_data/usb-ehci-orion.h> #include <plat/common.h> #include <plat/time.h> -#include <plat/addr-map.h> #include <linux/platform_data/dma-mv_xor.h> #include "common.h" @@ -535,6 +534,9 @@ void __init kirkwood_init_early(void) * the allocations won't fail. */ init_dma_coherent_pool_size(SZ_1M); + mvebu_mbus_init("marvell,kirkwood-mbus", + BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, + DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ); } int kirkwood_tclk; @@ -650,6 +652,38 @@ char * __init kirkwood_id(void) } } +void __init kirkwood_setup_wins(void) +{ + /* + * The PCIe windows will no longer be statically allocated + * here once Kirkwood is migrated to the pci-mvebu driver. + */ + mvebu_mbus_add_window_remap_flags("pcie0.0", + KIRKWOOD_PCIE_IO_PHYS_BASE, + KIRKWOOD_PCIE_IO_SIZE, + KIRKWOOD_PCIE_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie0.0", + KIRKWOOD_PCIE_MEM_PHYS_BASE, + KIRKWOOD_PCIE_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE1_IO_PHYS_BASE, + KIRKWOOD_PCIE1_IO_SIZE, + KIRKWOOD_PCIE1_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE1_MEM_PHYS_BASE, + KIRKWOOD_PCIE1_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE, + KIRKWOOD_NAND_MEM_SIZE); + mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE, + KIRKWOOD_SRAM_SIZE); +} + void __init kirkwood_l2_init(void) { #ifdef CONFIG_CACHE_FEROCEON_L2 @@ -675,7 +709,7 @@ void __init kirkwood_init(void) */ writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); - kirkwood_setup_cpu_mbus(); + kirkwood_setup_wins(); kirkwood_l2_init(); diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 5ed70565c84..e24f74305b3 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -30,7 +30,7 @@ void kirkwood_init(void); void kirkwood_init_early(void); void kirkwood_init_irq(void); -void kirkwood_setup_cpu_mbus(void); +void kirkwood_setup_wins(void); void kirkwood_enable_pcie(void); void kirkwood_pcie_id(u32 *dev, u32 *rev); diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index a05563a31c9..92976cef391 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -60,8 +60,9 @@ * Register Map */ #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000) -#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) -#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500) +#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) +#define DDR_WINDOW_CPU_BASE (DDR_PHYS_BASE + 0x1500) +#define DDR_WINDOW_CPU_SZ (0x20) #define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418) #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000) @@ -80,6 +81,8 @@ #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000) #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) +#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) +#define BRIDGE_WINS_SZ (0x80) #define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000) diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index d96ad4c0997..7f43e6c2f8c 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -17,7 +17,6 @@ #include <asm/mach/pci.h> #include <plat/pcie.h> #include <mach/bridge-regs.h> -#include <plat/addr-map.h> #include "common.h" static void kirkwood_enable_pcie_clk(const char *port) diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index 67a13f9bfe6..7cd04634d30 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o mpp.o irq.o pcie.o +obj-y += common.o mpp.o irq.o pcie.o obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c deleted file mode 100644 index 26e9876b50e..00000000000 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/addr-map.c - * - * Address map functions for Marvell MV78xx0 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include <plat/addr-map.h> -#include <mach/mv78xx0.h> -#include "common.h" - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DEV_BUS 1 -#define TARGET_PCIE0 4 -#define TARGET_PCIE1 8 -#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0) -#define ATTR_DEV_SPI_ROM 0x1 |