diff options
54 files changed, 4618 insertions, 1737 deletions
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig index 3de640ac294..7ac3fbf0fe0 100644 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ b/arch/arm/configs/omap_4430sdp_defconfig @@ -199,7 +199,7 @@ CONFIG_ARCH_OMAP4=y # # CONFIG_OMAP_RESET_CLOCKS is not set # CONFIG_OMAP_MUX is not set -# CONFIG_OMAP_MCBSP is not set +CONFIG_OMAP_MCBSP=y # CONFIG_OMAP_MBOX_FWK is not set # CONFIG_OMAP_MPU_TIMER is not set CONFIG_OMAP_32K_TIMER=y @@ -304,7 +304,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600000,20M ramdisk_size=20480" +CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480" # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set @@ -488,7 +488,8 @@ CONFIG_GPIOLIB=y # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set -# CONFIG_WATCHDOG is not set +CONFIG_WATCHDOG=y +CONFIG_OMAP_WATCHDOG=y CONFIG_SSB_POSSIBLE=y # diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 3e052f6532b..e0aec1007a0 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -1,7 +1,7 @@ /* * linux/arch/arm/mach-omap1/clock.c * - * Copyright (C) 2004 - 2005, 2009 Nokia corporation + * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> * * Modified to use omap shared clock framework by @@ -38,20 +38,6 @@ struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; * Omap1 specific clock functions *-------------------------------------------------------------------------*/ -static int clk_omap1_dummy_enable(struct clk *clk) -{ - return 0; -} - -static void clk_omap1_dummy_disable(struct clk *clk) -{ -} - -const struct clkops clkops_dummy = { - .enable = clk_omap1_dummy_enable, - .disable = clk_omap1_dummy_disable, -}; - unsigned long omap1_uart_recalc(struct clk *clk) { unsigned int val = __raw_readl(clk->enable_reg); @@ -571,9 +557,6 @@ const struct clkops clkops_uart = { long omap1_clk_round_rate(struct clk *clk, unsigned long rate) { - if (clk->flags & RATE_FIXED) - return clk->rate; - if (clk->round_rate != NULL) return clk->round_rate(clk, rate); diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index edefb3440d3..aa8558adbf1 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -1,7 +1,7 @@ /* * linux/arch/arm/mach-omap1/clock_data.c * - * Copyright (C) 2004 - 2005, 2009 Nokia corporation + * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc * @@ -27,13 +27,6 @@ * Omap1 clocks *-------------------------------------------------------------------------*/ -/* XXX is this necessary? */ -static struct clk dummy_ck = { - .name = "dummy", - .ops = &clkops_dummy, - .flags = RATE_FIXED, -}; - static struct clk ck_ref = { .name = "ck_ref", .ops = &clkops_null, @@ -389,8 +382,7 @@ static struct uart_clk uart1_16xx = { /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 48000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT | - CLOCK_NO_IDLE_PARENT, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 29, }, @@ -430,8 +422,7 @@ static struct uart_clk uart3_16xx = { /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 48000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT | - CLOCK_NO_IDLE_PARENT, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 31, }, @@ -443,7 +434,7 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ .ops = &clkops_generic, /* Direct from ULPD, no parent */ .rate = 6000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT, + .flags = ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), .enable_bit = USB_MCLK_EN_BIT, }; @@ -453,7 +444,7 @@ static struct clk usb_hhc_ck1510 = { .ops = &clkops_generic, /* Direct from ULPD, no parent */ .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ - .flags = RATE_FIXED | ENABLE_REG_32BIT, + .flags = ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = USB_HOST_HHC_UHOST_EN, }; @@ -464,7 +455,7 @@ static struct clk usb_hhc_ck16xx = { /* Direct from ULPD, no parent */ .rate = 48000000, /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ - .flags = RATE_FIXED | ENABLE_REG_32BIT, + .flags = ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ .enable_bit = 8 /* UHOST_EN */, }; @@ -474,7 +465,6 @@ static struct clk usb_dc_ck = { .ops = &clkops_generic, /* Direct from ULPD, no parent */ .rate = 48000000, - .flags = RATE_FIXED, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = 4, }; @@ -484,7 +474,6 @@ static struct clk usb_dc_ck7xx = { .ops = &clkops_generic, /* Direct from ULPD, no parent */ .rate = 48000000, - .flags = RATE_FIXED, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = 8, }; @@ -494,7 +483,6 @@ static struct clk mclk_1510 = { .ops = &clkops_generic, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ .rate = 12000000, - .flags = RATE_FIXED, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = 6, }; @@ -515,7 +503,6 @@ static struct clk bclk_1510 = { .ops = &clkops_generic, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ .rate = 12000000, - .flags = RATE_FIXED, }; static struct clk bclk_16xx = { @@ -530,36 +517,34 @@ static struct clk bclk_16xx = { }; static struct clk mmc1_ck = { - .name = "mmc_ck", + .name = "mmc1_ck", .ops = &clkops_generic, /* Functional clock is direct from ULPD, interface clock is ARMPER */ .parent = &armper_ck.clk, .rate = 48000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 23, }; static struct clk mmc2_ck = { - .name = "mmc_ck", - .id = 1, + .name = "mmc2_ck", .ops = &clkops_generic, /* Functional clock is direct from ULPD, interface clock is ARMPER */ .parent = &armper_ck.clk, .rate = 48000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 20, }; static struct clk mmc3_ck = { - .name = "mmc_ck", - .id = 2, + .name = "mmc3_ck", .ops = &clkops_generic, /* Functional clock is direct from ULPD, interface clock is ARMPER */ .parent = &armper_ck.clk, .rate = 48000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = 12, }; @@ -577,7 +562,6 @@ static struct clk virtual_ck_mpu = { remains active during MPU idle whenever this is enabled */ static struct clk i2c_fck = { .name = "i2c_fck", - .id = 1, .ops = &clkops_null, .flags = CLOCK_NO_IDLE_PARENT, .parent = &armxor_ck.clk, @@ -586,7 +570,6 @@ static struct clk i2c_fck = { static struct clk i2c_ick = { .name = "i2c_ick", - .id = 1, .ops = &clkops_null, .flags = CLOCK_NO_IDLE_PARENT, .parent = &armper_ck.clk, diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d3e54da7e25..2069fb33baa 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -5,23 +5,17 @@ # Common support obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o -omap-2-3-common = irq.o sdrc.o omap_hwmod.o -omap-3-4-common = dpll3xxx.o +omap-2-3-common = irq.o sdrc.o +hwmod-common = omap_hwmod.o \ + omap_hwmod_common_data.o prcm-common = prcm.o powerdomain.o clock-common = clock.o clock_common_data.o \ clockdomain.o clkt_dpll.o \ clkt_clksel.o -clock-omap2xxx = clkt2xxx_dpllcore.o \ - clkt2xxx_virt_prcm_set.o \ - clkt2xxx_apll.o clkt2xxx_osc.o \ - clkt2xxx_sys.o -clock-omap3xxx = clkt34xx_dpll3m2.o - -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ - $(clock-omap2xxx) -obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ - $(omap-3-4-common) $(clock-omap3xxx) -obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) $(prcm-common) $(clock-common) + +obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o @@ -63,14 +57,31 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o # Clock framework -obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o +obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ + clkt2xxx_sys.o \ + clkt2xxx_dpllcore.o \ + clkt2xxx_virt_prcm_set.o \ + clkt2xxx_apll.o clkt2xxx_osc.o +obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o +obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o +obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ + clock34xx.o clkt34xx_dpll3m2.o \ + clock3517.o clock36xx.o \ + dpll3xxx.o clock3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \ + dpll3xxx.o + +# OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o -obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o -obj-$(CONFIG_ARCH_OMAP4) += clock44xx.o clock44xx_data.o + +# hwmod data +obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o +obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o +obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o # EMU peripherals -obj-$(CONFIG_OMAP3_EMU) += emu.o +obj-$(CONFIG_OMAP3_EMU) += emu.o obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o @@ -128,7 +139,7 @@ obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o -obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o +obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o # Platform specific device init code obj-y += usb-musb.o diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index fc32ff8e790..43d7246ce33 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -38,6 +38,8 @@ #define APLLS_CLKIN_13MHZ 2 #define APLLS_CLKIN_12MHZ 3 +void __iomem *cm_idlest_pll; + /* Private functions */ /* Enable an APLL if off */ @@ -56,8 +58,8 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) cval |= apll_mask; cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); - omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask, - clk->name); + omap2_cm_wait_idlest(cm_idlest_pll, status_mask, + OMAP24XX_CM_IDLEST_VAL, clk->name); /* * REVISIT: Should we return an error code if omap2_wait_clock_ready() diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index 8716a01d1f5..b2b1e37bb6b 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -26,6 +26,7 @@ #include <plat/sdrc.h> #include "clock.h" +#include "clock3xxx.h" #include "clock34xx.h" #include "sdrc.h" diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 25a2363106d..e50812dd03f 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -258,10 +258,6 @@ long omap2_clk_round_rate(struct clk *clk, unsigned long rate) if (clk->round_rate) return clk->round_rate(clk, rate); - if (clk->flags & RATE_FIXED) - printk(KERN_ERR "clock: generic omap2_clk_round_rate called " - "on fixed-rate clock %s\n", clk->name); - return clk->rate; } @@ -377,8 +373,6 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) clk->rate = clk->parent->rate / new_div; - omap2xxx_clk_commit(clk); - return 0; } @@ -400,8 +394,6 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) __raw_writel(v, clk->clksel_reg); v = __raw_readl(clk->clksel_reg); /* OCP barrier */ - omap2xxx_clk_commit(clk); - clk_reparent(clk, new_parent); /* CLKSEL clocks follow their parents' rates, divided by a divisor */ diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 9eee0e67d5d..6ce512e902c 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -29,7 +29,7 @@ #include "cm-regbits-34xx.h" /* DPLL rate rounding: minimum DPLL multiplier, divider values */ -#define DPLL_MIN_MULTIPLIER 1 +#define DPLL_MIN_MULTIPLIER 2 #define DPLL_MIN_DIVIDER 1 /* Possible error results from _dpll_test_mult */ diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 999b91e023b..a6d0b34b799 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -2,7 +2,7 @@ * linux/arch/arm/mach-omap2/clock.c * * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2008 Nokia Corporation + * Copyright (C) 2004-2010 Nokia Corporation * * Contacts: * Richard Woodruff <r-woodruff2@ti.com> @@ -14,11 +14,10 @@ */ #undef DEBUG -#include <linux/module.h> #include <linux/kernel.h> -#include <linux/device.h> #include <linux/list.h> #include <linux/errno.h> +#include <linux/err.h> #include <linux/delay.h> #include <linux/clk.h> #include <linux/io.h> @@ -38,9 +37,9 @@ u8 cpu_mask; -/*------------------------------------------------------------------------- - * OMAP2/3/4 specific clock functions - *-------------------------------------------------------------------------*/ +/* + * OMAP2+ specific clock functions + */ /* Private functions */ @@ -57,7 +56,7 @@ u8 cpu_mask; static void _omap2_module_wait_ready(struct clk *clk) { void __iomem *companion_reg, *idlest_reg; - u8 other_bit, idlest_bit; + u8 other_bit, idlest_bit, idlest_val; /* Not all modules have multiple clocks that their IDLEST depends on */ if (clk->ops->find_companion) { @@ -66,50 +65,15 @@ static void _omap2_module_wait_ready(struct clk *clk) return; } - clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); + clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); - omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); -} - -/* Enables clock without considering parent dependencies or use count - * REVISIT: Maybe change this to use clk->enable like on omap1? - */ -static int _omap2_clk_enable(struct clk *clk) -{ - return clk->ops->enable(clk); -} - -/* Disables clock without considering parent dependencies or use count */ -static void _omap2_clk_disable(struct clk *clk) -{ - clk->ops->disable(clk); + omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, + clk->name); } /* Public functions */ /** - * omap2xxx_clk_commit - commit clock parent/rate changes in hardware - * @clk: struct clk * - * - * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes - * don't take effect until the VALID_CONFIG bit is written, write the - * VALID_CONFIG bit and wait for the write to complete. No return value. - */ -void omap2xxx_clk_commit(struct clk *clk) -{ - if (!cpu_is_omap24xx()) - return; - - if (!(clk->flags & DELAYED_APP)) - return; - - prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, - OMAP2_PRCM_CLKCFG_CTRL_OFFSET); - /* OCP barrier */ - prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); -} - -/** * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk * @clk: OMAP clock struct ptr to use * @@ -175,7 +139,8 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk * @clk: struct clk * to find IDLEST info for * @idlest_reg: void __iomem ** to return the CM_IDLEST va in - * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in + * @idlest_bit: u8 * to return the CM_IDLEST bit shift in + * @idlest_val: u8 * to return the idle status indicator * * Return the CM_IDLEST register address and bit shift corresponding * to the module that "owns" this clock. This default code assumes @@ -185,13 +150,26 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, * CM_IDLEST2). This is not true for all modules. No return value. */ void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, - u8 *idlest_bit) + u8 *idlest_bit, u8 *idlest_val) { u32 r; r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); *idlest_reg = (__force void __iomem *)r; *idlest_bit = clk->enable_bit; + + /* + * 24xx uses 0 to indicate not ready, and 1 to indicate ready. + * 34xx reverses this, just to keep us on our toes + * AM35xx uses both, depending on the module. + */ + if (cpu_is_omap24xx()) + *idlest_val = OMAP24XX_CM_IDLEST_VAL; + else if (cpu_is_omap34xx()) + *idlest_val = OMAP34XX_CM_IDLEST_VAL; + else + BUG(); + } int omap2_dflt_clk_enable(struct clk *clk) @@ -253,46 +231,106 @@ const struct clkops clkops_omap2_dflt = { .disable = omap2_dflt_clk_disable, }; +/** + * omap2_clk_disable - disable a clock, if the system is not using it + * @clk: struct clk * to disable + * + * Decrements the usecount on struct clk @clk. If there are no users + * left, call the clkops-specific clock disable function to disable it + * in hardware. If the clock is part of a clockdomain (which they all + * should be), request that the clockdomain be disabled. (It too has + * a usecount, and so will not be disabled in the hardware until it no + * longer has any users.) If the clock has a parent clock (most of + * them do), then call ourselves, recursing on the parent clock. This + * can cause an entire branch of the clock tree to be powered off by + * simply disabling one clock. Intended to be called with the clockfw_lock + * spinlock held. No return value. + */ void omap2_clk_disable(struct clk *clk) { - if (clk->usecount > 0 && !(--clk->usecount)) { - _omap2_clk_disable(clk); - if (clk->parent) - omap2_clk_disable(clk->parent); - if (clk->clkdm) - omap2_clkdm_clk_disable(clk->clkdm, clk); - + if (clk->usecount == 0) { + WARN(1, "clock: %s: omap2_clk_disable() called, but usecount " + "already 0?", clk->name); + return; } + + pr_debug("clock: %s: decrementing usecount\n", clk->name); + + clk->usecount--; + + if (clk->usecount > 0) + return; + + pr_debug("clock: %s: disabling in hardware\n", clk->name); + + clk->ops->disable(clk); + + if (clk->clkdm) + omap2_clkdm_clk_disable(clk->clkdm, clk); + + if (clk->parent) + omap2_clk_disable(clk->parent); } +/** + * omap2_clk_enable - request that the system enable a clock + * @clk: struct clk * to enable + * + * Increments the usecount on struct clk @clk. If there were no users + * previously, then recurse up the clock tree, enabling all of the + * clock's parents and all of the parent clockdomains, and finally, + * enabling @clk's clockdomain, and @clk itself. Intended to be + * called with the clockfw_lock spinlock held. Returns 0 upon success + * or a negative error code upon failure. + */ int omap2_clk_enable(struct clk *clk) { - int ret = 0; + int ret; - if (clk->usecount++ == 0) { - if (clk->clkdm) - omap2_clkdm_clk_enable(clk->clkdm, clk); + pr_debug("clock: %s: incrementing usecount\n", clk->name); - if (clk->parent) { - ret = omap2_clk_enable(clk->parent); - if (ret) - goto err; - } + clk->usecount++; - ret = _omap2_clk_enable(clk); + if (clk->usecount > 1) + return 0; + + pr_debug("clock: %s: enabling in hardware\n", clk->name); + + if (clk->parent) { + ret = omap2_clk_enable(clk->parent); if (ret) { - if (clk->parent) - omap2_clk_disable(clk->parent); + WARN(1, "clock: %s: could not enable parent %s: %d\n", + clk->name, clk->parent->name, ret); + goto oce_err1; + } + } - goto err; + if (clk->clkdm) { + ret = omap2_clkdm_clk_enable(clk->clkdm, clk); + if (ret) { + WARN(1, "clock: %s: could not enable clockdomain %s: " + "%d\n", clk->name, clk->clkdm->name, ret); + goto oce_err2; } } - return ret; -err: + ret = clk->ops->enable(clk); + if (ret) { |