diff options
| -rw-r--r-- | drivers/net/bnx2x.h | 2 | ||||
| -rw-r--r-- | drivers/net/bnx2x_fw_defs.h | 70 | ||||
| -rw-r--r-- | drivers/net/bnx2x_hsi.h | 174 | ||||
| -rw-r--r-- | drivers/net/bnx2x_init_values.h | 26527 | ||||
| -rw-r--r-- | drivers/net/bnx2x_main.c | 89 | ||||
| -rw-r--r-- | drivers/net/bnx2x_reg.h | 147 |
6 files changed, 14374 insertions, 12635 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h index 15a5cf0f676..de094d4b68a 100644 --- a/drivers/net/bnx2x.h +++ b/drivers/net/bnx2x.h @@ -1125,7 +1125,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ - TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE) + TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE) #define MULTI_MASK 0x7f diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h index 192fa981b93..2fe14a25ea3 100644 --- a/drivers/net/bnx2x_fw_defs.h +++ b/drivers/net/bnx2x_fw_defs.h @@ -50,8 +50,10 @@ #define TSTORM_ASSERT_LIST_OFFSET(idx) \ (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ - (IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \ - : (0x9c8 + (port * 0x2f8) + (client_id * 0x28))) + (IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \ + : (0x9c0 + (port * 0x130) + (client_id * 0x10))) +#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \ + (IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff) #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \ ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ @@ -81,43 +83,43 @@ (function * 0x38))) #define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \ - 0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38))) -#define TSTORM_RX_PRODS_OFFSET(port, client_id) \ - (IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \ - : (0x9c0 + (port * 0x2f8) + (client_id * 0x28))) + 0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50))) #define TSTORM_STATS_FLAGS_OFFSET(function) \ (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \ (function * 0x8))) -#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3b30 : 0x1c20) +#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20) #define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10) #define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200) #define USTORM_ASSERT_LIST_INDEX_OFFSET \ - (IS_E1H_OFFSET ? 0x8000 : 0x1000) + (IS_E1H_OFFSET ? 0x8960 : 0x1000) #define USTORM_ASSERT_LIST_OFFSET(idx) \ - (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) + (IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ - (IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \ - (0x5450 + (port * 0x1c8) + (clientId * 0x18))) + (IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \ + (0x5330 + (port * 0x260) + (clientId * 0x20))) #define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ - (IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \ - ((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \ - 0x28) + (index * 0x4))) + (IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \ + ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \ + 0x40) + (index * 0x4))) #define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ - (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \ - ((function&1) * 0xa0)) : (0x1900 + (function * 0x28))) + (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \ + ((function&1) * 0x100)) : (0x1900 + (function * 0x40))) #define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ - (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \ - ((function&1) * 0xa0)) : (0x1908 + (function * 0x28))) + (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \ + ((function&1) * 0x100)) : (0x1908 + (function * 0x40))) #define USTORM_FUNCTION_MODE_OFFSET \ (IS_E1H_OFFSET ? 0x2448 : 0xffffffff) #define USTORM_HC_BTR_OFFSET(port) \ - (IS_E1H_OFFSET ? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8))) + (IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ - (IS_E1H_OFFSET ? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \ - (0x5448 + (port * 0x1c8) + (clientId * 0x18))) + (IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \ + (0x5328 + (port * 0x260) + (clientId * 0x20))) #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ - (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5408 + \ + (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \ (function * 0x8))) +#define USTORM_RX_PRODS_OFFSET(port, client_id) \ + (IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \ + : (0x5318 + (port * 0x260) + (client_id * 0x20))) #define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \ (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ @@ -137,7 +139,7 @@ #define XSTORM_ASSERT_LIST_OFFSET(idx) \ (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ - (IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40))) + (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50))) #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \ ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ @@ -149,23 +151,23 @@ (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \ ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) #define XSTORM_E1HOV_OFFSET(function) \ - (IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff) + (IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff) #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \ (function * 0x8))) #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ - (IS_E1H_OFFSET ? (0x2568 + (function * 0x70)) : (0x3c60 + \ - (function * 0x70))) + (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \ + (function * 0x90))) #define XSTORM_FUNCTION_MODE_OFFSET \ - (IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff) + (IS_E1H_OFFSET ? 0x2c20 : 0xffffffff) #define XSTORM_HC_BTR_OFFSET(port) \ (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \ 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38))) #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ - (IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \ - (function * 0x70))) + (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \ + (function * 0x90))) #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \ (function * 0x10))) @@ -278,9 +280,6 @@ #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) -#define ISCSI_STATE \ - (ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) -#define FCOE_STATE (FCOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) /* microcode fixed page page size 4K (chains and ring segments) */ #define MC_PAGE_SIZE (4096) @@ -289,7 +288,7 @@ /* Host coalescing constants */ /* index numbers */ -#define HC_USTORM_DEF_SB_NUM_INDICES 4 +#define HC_USTORM_DEF_SB_NUM_INDICES 8 #define HC_CSTORM_DEF_SB_NUM_INDICES 8 #define HC_XSTORM_DEF_SB_NUM_INDICES 4 #define HC_TSTORM_DEF_SB_NUM_INDICES 4 @@ -386,9 +385,12 @@ #define FW_LOG_LIST_SIZE (50) #define NUM_OF_PROTOCOLS 4 -#define MAX_COS_NUMBER 16 +#define NUM_OF_SAFC_BITS 16 +#define MAX_COS_NUMBER 4 #define MAX_T_STAT_COUNTER_ID 18 #define MAX_X_STAT_COUNTER_ID 18 +#define MAX_U_STAT_COUNTER_ID 18 + #define UNKNOWN_ADDRESS 0 #define UNICAST_ADDRESS 1 diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h index efd764427fa..c4168235305 100644 --- a/drivers/net/bnx2x_hsi.h +++ b/drivers/net/bnx2x_hsi.h @@ -1212,8 +1212,9 @@ struct host_func_stats { #define BCM_5710_FW_MAJOR_VERSION 4 -#define BCM_5710_FW_MINOR_VERSION 5 -#define BCM_5710_FW_REVISION_VERSION 1 +#define BCM_5710_FW_MINOR_VERSION 8 +#define BCM_5710_FW_REVISION_VERSION 53 +#define BCM_5710_FW_ENGINEERING_VERSION 0 #define BCM_5710_FW_COMPILE_FLAGS 1 @@ -1465,9 +1466,11 @@ struct ustorm_eth_st_context_config { #endif #if defined(__BIG_ENDIAN) u16 bd_buff_size; - u16 mc_alignment_size; + u8 statistics_counter_id; + u8 mc_alignment_log_size; #elif defined(__LITTLE_ENDIAN) - u16 mc_alignment_size; + u8 mc_alignment_log_size; + u8 statistics_counter_id; u16 bd_buff_size; #endif #if defined(__BIG_ENDIAN) @@ -1479,13 +1482,7 @@ struct ustorm_eth_st_context_config { u8 __local_bd_prod; u8 __local_sge_prod; #endif -#if defined(__BIG_ENDIAN) - u16 __bd_cons; - u16 __sge_cons; -#elif defined(__LITTLE_ENDIAN) - u16 __sge_cons; - u16 __bd_cons; -#endif + u32 reserved; u32 bd_page_base_lo; u32 bd_page_base_hi; u32 sge_page_base_lo; @@ -2162,9 +2159,9 @@ struct host_status_block { * The data for RSS setup ramrod */ struct eth_client_setup_ramrod_data { - u32 client_id_5b; - u8 is_rdma_1b; - u8 reserved0; + u32 client_id; + u8 is_rdma; + u8 is_fcoe; u16 reserved1; }; @@ -2225,7 +2222,7 @@ struct eth_fast_path_rx_cqe { * The data for RSS setup ramrod */ struct eth_halt_ramrod_data { - u32 client_id_5b; + u32 client_id; u32 reserved0; }; @@ -2236,11 +2233,11 @@ struct eth_halt_ramrod_data { struct eth_query_ramrod_data { #if defined(__BIG_ENDIAN) u8 reserved0; - u8 collect_port_1b; + u8 collect_port; u16 drv_counter; #elif defined(__LITTLE_ENDIAN) u16 drv_counter; - u8 collect_port_1b; + u8 collect_port; u8 reserved0; #endif u32 ctr_id_vector; @@ -2282,7 +2279,7 @@ struct common_ramrod_eth_rx_cqe { #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1) #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1 - u8 conn_type_3b; + u8 conn_type; u16 reserved1; u32 conn_and_cmd_data; #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) @@ -2377,14 +2374,16 @@ struct tstorm_eth_function_common_config { #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4) -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4 -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5) -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5 -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6) -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6 -#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7) -#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7) +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8) +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9) +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9 +#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10) +#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10 #elif defined(__LITTLE_ENDIAN) u16 config_flags; #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) @@ -2395,14 +2394,16 @@ struct tstorm_eth_function_common_config { #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4) -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4 -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5) -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5 -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6) -#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6 -#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7) -#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7) +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8) +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9) +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9 +#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10) +#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10 u8 rss_result_mask; u8 leading_client_id; #endif @@ -2422,7 +2423,7 @@ struct eth_update_ramrod_data { * MAC filtering configuration command header */ struct mac_configuration_hdr { - u8 length_6b; + u8 length; u8 offset; u16 client_id; u32 reserved1; @@ -2544,24 +2545,28 @@ struct tstorm_eth_client_config { #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4) #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4 u16 config_flags; -#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0) -#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0 -#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1) -#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1 -#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2) -#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2 -#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3) -#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3 +#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0) +#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0 +#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1) +#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1 +#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2) +#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2 +#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3) +#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3 +#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4) +#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4 #elif defined(__LITTLE_ENDIAN) u16 config_flags; -#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0) -#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0 -#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1) -#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1 -#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2) -#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2 -#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3) -#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3 +#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0) +#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0 +#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1) +#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1 +#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2) +#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2 +#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3) +#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3 +#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4) +#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4 u16 drop_flags; #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0) #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0 @@ -2594,9 +2599,26 @@ struct tstorm_eth_mac_filter_config { /* + * common flag to indicate existance of TPA. + */ +struct tstorm_eth_tpa_exist { +#if defined(__BIG_ENDIAN) + u16 reserved1; + u8 reserved0; + u8 tpa_exist; +#elif defined(__LITTLE_ENDIAN) + u8 tpa_exist; + u8 reserved0; + u16 reserved1; +#endif + u32 reserved2; +}; + + +/* * Three RX producers for ETH */ -struct tstorm_eth_rx_producers { +struct ustorm_eth_rx_producers { #if defined(__BIG_ENDIAN) u16 bd_prod; u16 cqe_prod; @@ -2615,23 +2637,6 @@ struct tstorm_eth_rx_producers { /* - * common flag to indicate existence of TPA. - */ -struct tstorm_eth_tpa_exist { -#if defined(__BIG_ENDIAN) - u16 reserved1; - u8 reserved0; - u8 tpa_exist; -#elif defined(__LITTLE_ENDIAN) - u8 tpa_exist; - u8 reserved0; - u16 reserved1; -#endif - u32 reserved2; -}; - - -/* * per-port SAFC demo variables */ struct cmng_flags_per_port { @@ -2674,15 +2679,15 @@ struct fairness_vars_per_port { */ struct safc_struct_per_port { #if defined(__BIG_ENDIAN) - u16 __reserved0; - u8 cur_cos_types; + u16 __reserved1; + u8 __reserved0; u8 safc_timeout_usec; #elif defined(__LITTLE_ENDIAN) u8 safc_timeout_usec; - u8 cur_cos_types; - u16 __reserved0; + u8 __reserved0; + u16 __reserved1; #endif - u8 cos_to_protocol[MAX_COS_NUMBER]; + u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; }; @@ -2788,13 +2793,15 @@ struct fairness_vars_per_vn { */ struct fw_version { #if defined(__BIG_ENDIAN) - u16 patch; - u8 primary; - u8 client; + u8 engineering; + u8 revision; + u8 minor; + u8 major; #elif defined(__LITTLE_ENDIAN) - u8 client; - u8 primary; - u16 patch; + u8 major; + u8 minor; + u8 revision; + u8 engineering; #endif u32 flags; #define FW_VERSION_OPTIMIZED (0x1<<0) @@ -2812,9 +2819,10 @@ struct fw_version { * FW version stored in first line of pram */ struct pram_fw_version { - u8 client; - u8 primary; - u16 patch; + u8 major; + u8 minor; + u8 revision; + u8 engineering; u8 flags; #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 diff --git a/drivers/net/bnx2x_init_values.h b/drivers/net/bnx2x_init_values.h index 9755bf6b08d..6e18a556fb5 100644 --- a/drivers/net/bnx2x_init_values.h +++ b/drivers/net/bnx2x_init_values.h @@ -47,12 +47,16 @@ static const struct raw_op init_ops[] = { {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000}, {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000}, {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000}, - {OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4}, + {OP_ZR_E1, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4}, + {OP_WR_E1H, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x40100000}, + {OP_ZR_E1H, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5, 0x3}, {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000}, {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000}, {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000}, {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000}, - {OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4}, + {OP_ZR_E1, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4}, + {OP_WR_E1H, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x42140000}, + {OP_ZR_E1H, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5, 0x3}, {OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0}, {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0}, {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0}, @@ -71,15 +75,16 @@ static const struct raw_op init_ops[] = { {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f}, {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f}, {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f}, - {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0}, + {OP_WR_E1, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0}, + {OP_WR_E1H, PRS_REG_PACKET_REGIONS_TYPE_4, 0x3f}, {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f}, {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f}, {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f}, -#define PRS_COMMON_END 47 -#define SRCH_COMMON_START 47 +#define PRS_COMMON_END 52 +#define SRCH_COMMON_START 52 {OP_WR_E1H, SRC_REG_E1HMF_ENABLE, 0x1}, -#define SRCH_COMMON_END 48 -#define TSDM_COMMON_START 48 +#define SRCH_COMMON_END 53 +#define TSDM_COMMON_START 53 {OP_WR_E1, TSDM_REG_CFC_RSP_START_ADDR, 0x411}, {OP_WR_E1H, TSDM_REG_CFC_RSP_START_ADDR, 0x211}, {OP_WR_E1, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400}, @@ -92,10 +97,15 @@ static const struct raw_op init_ops[] = { {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff}, {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff}, {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff}, - {OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x2}, + {OP_ZR_E1, TSDM_REG_AGG_INT_EVENT_0, 0x2}, + {OP_WR_E1H, TSDM_REG_AGG_INT_EVENT_0, 0x20}, + {OP_WR_E1H, TSDM_REG_AGG_INT_EVENT_1, 0x0}, {OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34}, {OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35}, - {OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x7c}, + {OP_ZR_E1, TSDM_REG_AGG_INT_EVENT_4, 0x7c}, + {OP_ZR_E1H, TSDM_REG_AGG_INT_EVENT_4, 0x1c}, + {OP_WR_E1H, TSDM_REG_AGG_INT_T_0, 0x1}, + {OP_ZR_E1H, TSDM_REG_AGG_INT_T_1, 0x5f}, {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff}, {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f}, {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff}, @@ -118,8 +128,8 @@ static const struct raw_op init_ops[] = { {OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8}, {OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1}, {OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa}, -#define TSDM_COMMON_END 86 -#define TCM_COMMON_START 86 +#define TSDM_COMMON_END 96 +#define TCM_COMMON_START 96 {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20}, {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32}, {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020}, @@ -129,10 +139,16 @@ static const struct raw_op init_ops[] = { {OP_WR, TCM_REG_ERR_EVNT_ID, 0x33}, {OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30}, {OP_WR, TCM_REG_STOP_EVNT_ID, 0x31}, - {OP_WR, TCM_REG_PRS_WEIGHT, 0x4}, - {OP_WR, TCM_REG_PBF_WEIGHT, 0x5}, + {OP_WR, TCM_REG_STORM_WEIGHT, 0x2}, + {OP_WR, TCM_REG_PRS_WEIGHT, 0x5}, + {OP_WR, TCM_REG_PBF_WEIGHT, 0x6}, + {OP_WR, TCM_REG_USEM_WEIGHT, 0x2}, + {OP_WR, TCM_REG_CSEM_WEIGHT, 0x2}, {OP_WR, TCM_REG_CP_WEIGHT, 0x0}, - {OP_WR, TCM_REG_TSDM_WEIGHT, 0x4}, + {OP_WR, TCM_REG_TSDM_WEIGHT, 0x5}, + {OP_WR, TCM_REG_TQM_P_WEIGHT, 0x2}, + {OP_WR, TCM_REG_TQM_S_WEIGHT, 0x2}, + {OP_WR, TCM_REG_TM_WEIGHT, 0x2}, {OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1}, {OP_WR, TCM_REG_GR_ARB_TYPE, 0x1}, {OP_WR, TCM_REG_GR_LD0_PR, 0x1}, @@ -149,7 +165,9 @@ static const struct raw_op init_ops[] = { {OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7}, {OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8}, {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8}, - {OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4}, + {OP_ZR_E1, TCM_REG_N_SM_CTX_LD_4, 0x4}, + {OP_WR_E1H, TCM_REG_N_SM_CTX_LD_4, 0x1}, + {OP_ZR_E1H, TCM_REG_N_SM_CTX_LD_5, 0x3}, {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6}, {OP_WR_E1, TCM_REG_PHYS_QNUM0_0, 0xd}, {OP_WR_E1, TCM_REG_PHYS_QNUM0_1, 0x2d}, @@ -175,75 +193,75 @@ static const struct raw_op init_ops[] = { {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1}, {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1}, {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1}, -#define TCM_COMMON_END 141 -#define TCM_FUNC0_START 141 +#define TCM_COMMON_END 159 +#define TCM_FUNC0_START 159 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0xd}, {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x7}, {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x7}, {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x7}, -#define TCM_FUNC0_END 145 -#define TCM_FUNC1_START 145 +#define TCM_FUNC0_END 163 +#define TCM_FUNC1_START 163 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x2d}, {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x27}, {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x27}, {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x27}, -#define TCM_FUNC1_END 149 -#define TCM_FUNC2_START 149 +#define TCM_FUNC1_END 167 +#define TCM_FUNC2_START 167 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x1d}, {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x17}, {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x17}, {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x17}, -#define TCM_FUNC2_END 153 -#define TCM_FUNC3_START 153 +#define TCM_FUNC2_END 171 +#define TCM_FUNC3_START 171 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x3d}, {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x37}, {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x37}, {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x37}, -#define TCM_FUNC3_END 157 -#define TCM_FUNC4_START 157 +#define TCM_FUNC3_END 175 +#define TCM_FUNC4_START 175 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x4d}, {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x47}, {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x47}, {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x47}, -#define TCM_FUNC4_END 161 -#define TCM_FUNC5_START 161 +#define TCM_FUNC4_END 179 +#define TCM_FUNC5_START 179 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x6d}, {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x67}, {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x67}, {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x67}, -#define TCM_FUNC5_END 165 -#define TCM_FUNC6_START 165 +#define TCM_FUNC5_END 183 +#define TCM_FUNC6_START 183 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x5d}, {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x57}, {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x57}, {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x57}, -#define TCM_FUNC6_END 169 -#define TCM_FUNC7_START 169 +#define TCM_FUNC6_END 187 +#define TCM_FUNC7_START 187 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x7d}, {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x77}, {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x77}, {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x77}, -#define TCM_FUNC7_END 173 -#define BRB1_COMMON_START 173 +#define TCM_FUNC7_END 191 +#define BRB1_COMMON_START 191 {OP_SW, BRB1_REG_LL_RAM, 0x2000020}, {OP_WR, BRB1_REG_SOFT_RESET, 0x1}, {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0}, {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220}, {OP_WR, BRB1_REG_SOFT_RESET, 0x0}, -#define BRB1_COMMON_END 178 -#define BRB1_PORT0_START 178 +#define BRB1_COMMON_END 196 +#define BRB1_PORT0_START 196 {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0xb8}, {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 0x114}, {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0}, {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0}, -#define BRB1_PORT0_END 182 -#define BRB1_PORT1_START 182 +#define BRB1_PORT0_END 200 +#define BRB1_PORT1_START 200 {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0xb8}, {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 0x114}, {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0}, {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0}, -#define BRB1_PORT1_END 186 -#define TSEM_COMMON_START 186 +#define BRB1_PORT1_END 204 +#define TSEM_COMMON_START 204 {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0}, {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0}, {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0}, @@ -303,143 +321,166 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c18, 0x4}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa000, 0x2}, - {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c10, 0x2}, {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad0, 0x0}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad8, 0x4}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3b28, 0x6}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3678, 0x6}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x810, 0x4}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3670, 0x2}, {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x40224}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5008, 0x4}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2}, {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x4cb0, 0x80228}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5008, 0x4}, + {OP_ZP_E1, TSEM_REG_INT_TABLE, 0x930000}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5018, 0x4}, - {OP_ZP_E1, TSEM_REG_INT_TABLE, 0x940000}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5028, 0x4}, {OP_WR_64_E1, TSEM_REG_INT_TABLE + 0x360, 0x140230}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5028, 0x4}, + {OP_ZP_E1, TSEM_REG_PRAM, 0x324f0000}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5038, 0x4}, - {OP_ZP_E1, TSEM_REG_PRAM, 0x30b10000}, + {OP_ZP_E1, TSEM_REG_PRAM + 0x8000, 0x33250c94}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5048, 0x4}, - {OP_ZP_E1, TSEM_REG_PRAM + 0x8000, 0x33c50c2d}, + {OP_ZP_E1, TSEM_REG_PRAM + 0x10000, 0xe4d195e}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5058, 0x4}, - {OP_ZP_E1, TSEM_REG_PRAM + 0x10000, 0xbc6191f}, + {OP_WR_64_E1, TSEM_REG_PRAM + 0x11e00, 0x5c400232}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5068, 0x4}, - {OP_WR_64_E1, TSEM_REG_PRAM + 0x117f0, 0x5d020232}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5078, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2}, - {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x6140, 0x200224}, - {OP_ZP_E1H, TSEM_REG_INT_TABLE, 0x960000}, - {OP_WR_64_E1H, TSEM_REG_INT_TABLE + 0x360, 0x140244}, - {OP_ZP_E1H, TSEM_REG_PRAM, 0x30cc0000}, - {OP_ZP_E1H, TSEM_REG_PRAM + 0x8000, 0x33df0c33}, - {OP_ZP_E1H, TSEM_REG_PRAM + 0x10000, 0xdce192b}, - {OP_WR_64_E1H, TSEM_REG_PRAM + 0x11c70, 0x5c720246}, -#define TSEM_COMMON_END 276 -#define TSEM_PORT0_START 276 + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x62c0, 0x200224}, + {OP_ZP_E1H, TSEM_REG_INT_TABLE, 0x9b0000}, + {OP_WR_64_E1H, TSEM_REG_INT_TABLE + 0x398, 0xd0244}, + {OP_ZP_E1H, TSEM_REG_PRAM, 0x325e0000}, + {OP_ZP_E1H, TSEM_REG_PRAM + 0x8000, 0x35960c98}, + {OP_ZP_E1H, TSEM_REG_PRAM + 0x10000, 0x1aea19fe}, + {OP_WR_64_E1H, TSEM_REG_PRAM + 0x143d0, 0x57860246}, +#define TSEM_COMMON_END 297 +#define TSEM_PORT0_START 297 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x2000, 0x16c}, - {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x4000, 0xfc}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x4000, 0x16c}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb000, 0x28}, {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b60, 0x0}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb140, 0xc}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1400, 0xa}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32c0, 0x12}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1450, 0x6}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3350, 0xfa}, - {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3350, 0x64}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8108, 0x2}, + {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1500 + 0x8, 0x50234}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500 + 0x1c, 0x7}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1570, 0x12}, - {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x9c0, 0xbe}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x9c0, 0x4c}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x820, 0xe}, - {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x20234}, + {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x20239}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2908, 0x2}, -#define TSEM_PORT0_END 294 -#define TSEM_PORT1_START 294 +#define TSEM_PORT0_END 317 +#define TSEM_PORT1_START 317 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2348, 0x20}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x25b0, 0x16c}, - {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x43f0, 0xfc}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x45b0, 0x16c}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28}, {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b64, 0x0}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb170, 0xc}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1428, 0xa}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3308, 0x12}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1468, 0x6}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3738, 0xfa}, - {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x34e0, 0x64}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8110, 0x2}, + {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1538 + 0x8, 0x5023b}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538 + 0x1c, 0x7}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x15b8, 0x12}, - {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0xcb8, 0xbe}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0xaf0, 0x4c}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x858, 0xe}, - {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20236}, + {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20240}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2910, 0x2}, -#define TSEM_PORT1_END 312 -#define TSEM_FUNC0_START 312 +#define TSEM_PORT1_END 337 +#define TSEM_FUNC0_START 337 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b60, 0x0}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000, 0x2}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x50248}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000 + 0x1c, 0x7}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31c0, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5080, 0x12}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2}, -#define TSEM_FUNC0_END 318 -#define TSEM_FUNC1_START 318 +#define TSEM_FUNC0_END 345 +#define TSEM_FUNC1_START 345 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b64, 0x0}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038, 0x2}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3038 + 0x8, 0x5024d}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038 + 0x1c, 0x7}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31e0, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5010, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2}, -#define TSEM_FUNC1_END 324 -#define TSEM_FUNC2_START 324 +#define TSEM_FUNC1_END 353 +#define TSEM_FUNC2_START 353 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b68, 0x0}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070, 0x2}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3070 + 0x8, 0x50252}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070 + 0x1c, 0x7}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3200, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5020, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5110, 0x12}, - {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4010, 0x20248}, -#define TSEM_FUNC2_END 330 -#define TSEM_FUNC3_START 330 + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4010, 0x20257}, +#define TSEM_FUNC2_END 361 +#define TSEM_FUNC3_START 361 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b6c, 0x0}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8, 0x2}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x30a8 + 0x8, 0x50259}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8 + 0x1c, 0x7}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3220, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5030, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5158, 0x12}, - {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4018, 0x2024a}, -#define TSEM_FUNC3_END 336 -#define TSEM_FUNC4_START 336 + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4018, 0x2025e}, +#define TSEM_FUNC3_END 369 +#define TSEM_FUNC4_START 369 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b70, 0x0}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0, 0x2}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x30e0 + 0x8, 0x50260}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0 + 0x1c, 0x7}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3240, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5040, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12}, - {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4020, 0x2024c}, -#define TSEM_FUNC4_END 342 -#define TSEM_FUNC5_START 342 + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4020, 0x20265}, +#define TSEM_FUNC4_END 377 +#define TSEM_FUNC5_START 377 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b74, 0x0}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118, 0x2}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3118 + 0x8, 0x50267}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118 + 0x1c, 0x7}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3260, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5050, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12}, - {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4028, 0x2024e}, -#define TSEM_FUNC5_END 348 -#define TSEM_FUNC6_START 348 + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4028, 0x2026c}, +#define TSEM_FUNC5_END 385 +#define TSEM_FUNC6_START 385 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b78, 0x0}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150, 0x2}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3150 + 0x8, 0x5026e}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150 + 0x1c, 0x7}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3280, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5060, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5230, 0x12}, - {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4030, 0x20250}, -#define TSEM_FUNC6_END 354 -#define TSEM_FUNC7_START 354 + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4030, 0x20273}, +#define TSEM_FUNC6_END 393 +#define TSEM_FUNC7_START 393 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b7c, 0x0}, - {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188, 0x2}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3188 + 0x8, 0x50275}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188 + 0x1c, 0x7}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5070, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5278, 0x12}, - {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4038, 0x20252}, -#define TSEM_FUNC7_END 360 -#define MISC_COMMON_START |