diff options
| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2013-08-19 17:05:59 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2013-08-22 11:09:52 +0100 |
| commit | f8fdf5375e2005f238ce9b430724752a6e3d55cc (patch) | |
| tree | d53268fb193d587e34f3d86b1b2f73f147c6e413 /sound/soc/fsl | |
| parent | cd7f0295aab102acb77c19d6d77eab5f5145364c (diff) | |
ASoC: fsl-ssi: add SSIEN errata work around
The chip errata for the i.MX35, Rev.2 has the following errata:
ENGcm06222: SSI:Transmission does not take place in bit length early frame sync
configuration
The workaround states, that TX_EN and SSI_EN bits should be set in the same
register write. As the next errata in the document (ENGcm06532) says to always
write RX_EN and TX_EN in the same register write in network mode.
Therefore include the whole write to
CCSR_SSI_SCR_TE and CCSR_SSI_SCR_RE
into the write to
CCSR_SSI_SCR_SSIEN
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound/soc/fsl')
| -rw-r--r-- | sound/soc/fsl/fsl_ssi.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index 9e410e1e49a..6daeb5fbdc9 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -424,15 +424,12 @@ static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private) write_ssi(0x300, &ssi->saccen); /* - * Enable SSI + * Enable SSI, Transmit and Receive */ - write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); - write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); + write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | + CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); - /* - * Enable Transmit and Receive - */ - write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); + write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); } return 0; |