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authorDavid Daney <ddaney@caviumnetworks.com>2008-12-11 15:33:19 -0800
committerRalf Baechle <ralf@linux-mips.org>2009-01-11 09:57:20 +0000
commit54293ec3074a5fe61abd297502f68b2529a3dab3 (patch)
tree740675a4e198c487225bd35fb5fe8b9951aab2f5 /lib/iommu-helper.c
parent2bd2dd059ca7406a030bace8dccdb25f635578c1 (diff)
MIPS: Add Cavium OCTEON processor CSR definitions
Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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