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| author | Will Deacon <will.deacon@arm.com> | 2014-02-06 14:59:05 +0000 |
|---|---|---|
| committer | Jiri Slaby <jslaby@suse.cz> | 2014-03-05 17:13:51 +0100 |
| commit | 01ffe6154b9939874fb5d7d4cc59d66bec9ebb68 (patch) | |
| tree | b224540f80d47f189cc0530819496e3ad7305481 /kernel | |
| parent | 011b7e12aeb92635e5ff3864f5ba6f388720f6ec (diff) | |
iommu/arm-smmu: set CBARn.BPSHCFG to NSH for s1-s2-bypass contexts
commit 57ca90f6800987ac274d7ba065ae6692cdf9bcd7 upstream.
Whilst trying to bring-up an SMMUv2 implementation with the table
walker plumbed into a coherent interconnect, I noticed that the memory
transactions targetting the CPU caches from the SMMU were marked as
outer-shareable instead of inner-shareable.
After a bunch of digging, it seems that we actually need to program
CBARn.BPSHCFG for s1-s2-bypass contexts to act as non-shareable in order
for the shareability configured in the corresponding TTBCR not to be
overridden with an outer-shareable attribute.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Diffstat (limited to 'kernel')
0 files changed, 0 insertions, 0 deletions