diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-02-04 07:58:52 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-02-04 07:58:52 -0800 |
| commit | f5bb3a5e9dcdb8435471562b6cada89525cf4df1 (patch) | |
| tree | 7b7cf9b90bacd0e2fe07cb3387516e9243f1ab66 /include | |
| parent | 9853832c49dc1685587abeb4e1decd4be690d256 (diff) | |
| parent | 1560a79a2c2ea0c3826150da8029991d685de990 (diff) | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial
* git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial: (79 commits)
Jesper Juhl is the new trivial patches maintainer
Documentation: mention email-clients.txt in SubmittingPatches
fs/binfmt_elf.c: spello fix
do_invalidatepage() comment typo fix
Documentation/filesystems/porting fixes
typo fixes in net/core/net_namespace.c
typo fix in net/rfkill/rfkill.c
typo fixes in net/sctp/sm_statefuns.c
lib/: Spelling fixes
kernel/: Spelling fixes
include/scsi/: Spelling fixes
include/linux/: Spelling fixes
include/asm-m68knommu/: Spelling fixes
include/asm-frv/: Spelling fixes
fs/: Spelling fixes
drivers/watchdog/: Spelling fixes
drivers/video/: Spelling fixes
drivers/ssb/: Spelling fixes
drivers/serial/: Spelling fixes
drivers/scsi/: Spelling fixes
...
Diffstat (limited to 'include')
56 files changed, 100 insertions, 102 deletions
diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index b729e64d0d4..d970f7f9954 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -85,7 +85,7 @@ acpi_install_initialization_handler(acpi_init_handler handler, u32 function); #endif /* - * ACPI Memory managment + * ACPI Memory management */ void *acpi_allocate(u32 size); diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 76411b1fc4f..6e253b5b0f3 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -182,7 +182,7 @@ struct acpi_processor_throttling { /* Limit Interface */ struct acpi_processor_lx { - int px; /* performace state */ + int px; /* performance state */ int tx; /* throttle level */ }; diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h index 5d949d763a9..1205c28a207 100644 --- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h +++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h @@ -587,23 +587,23 @@ #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ -#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ -#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */ -#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */ -#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ -#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ -#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ -#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ -#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ - -#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ -#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ -#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ -#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ -#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ -#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ -#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ -#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ +#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ +#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ +#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ +#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ +#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ +#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ +#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ +#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ + +#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ +#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ +#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ +#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ +#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ +#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ +#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ +#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 442494d71f1..16ed24dbda4 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -737,25 +737,25 @@ #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ -#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ -#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */ -#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */ -#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ -#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ -#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ -#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ -#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ +#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ +#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ +#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ +#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ +#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ +#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ +#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ +#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ -#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ -#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ -#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ -#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ -#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ -#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ -#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ -#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ +#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ +#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ +#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ +#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ +#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ +#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ +#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ +#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ #elif defined(CONFIG_PXA27x) @@ -1020,7 +1020,7 @@ #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ -#define ICCR0_AME (1 << 7) /* Adress match enable */ +#define ICCR0_AME (1 << 7) /* Address match enable */ #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ #define ICCR0_RXE (1 << 4) /* Receive enable */ diff --git a/include/asm-arm/arch-versatile/irqs.h b/include/asm-arm/arch-versatile/irqs.h index 745aa841b31..f7263b99403 100644 --- a/include/asm-arm/arch-versatile/irqs.h +++ b/include/asm-arm/arch-versatile/irqs.h @@ -22,7 +22,7 @@ #include <asm/arch/platform.h> /* - * IRQ interrupts definitions are the same the INT definitions + * IRQ interrupts definitions are the same as the INT definitions * held within platform.h */ #define IRQ_VIC_START 0 @@ -94,7 +94,7 @@ #define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31 /* - * FIQ interrupts definitions are the same the INT definitions. + * FIQ interrupts definitions are the same as the INT definitions. */ #define FIQ_WDOGINT INT_WDOGINT #define FIQ_SOFTINT INT_SOFTINT diff --git a/include/asm-arm/hardware/it8152.h b/include/asm-arm/hardware/it8152.h index aaebb61aca4..74b5fff7f57 100644 --- a/include/asm-arm/hardware/it8152.h +++ b/include/asm-arm/hardware/it8152.h @@ -42,7 +42,7 @@ extern unsigned long it8152_base_address; #define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500) /* - Interrup contoler per register summary: + Interrupt controller per register summary: --------------------------------------- LCDNIRR: IT8152_LD_IRQ(8) PCICLK stop diff --git a/include/asm-arm/mach/udc_pxa2xx.h b/include/asm-arm/mach/udc_pxa2xx.h index f191e147ea9..f9f3606986c 100644 --- a/include/asm-arm/mach/udc_pxa2xx.h +++ b/include/asm-arm/mach/udc_pxa2xx.h @@ -16,7 +16,7 @@ struct pxa2xx_udc_mach_info { #define PXA2XX_UDC_CMD_DISCONNECT 1 /* so host won't see us */ /* Boards following the design guidelines in the developer's manual, - * with on-chip GPIOs not Lubbock's wierd hardware, can have a sane + * with on-chip GPIOs not Lubbock's weird hardware, can have a sane * VBUS IRQ and omit the methods above. Store the GPIO number * here; for GPIO 0, also mask in one of the pxa_gpio_mode() bits. * Note that sometimes the signals go through inverters... diff --git a/include/asm-frv/atomic.h b/include/asm-frv/atomic.h index d425d8d0ad7..6ec494a5bc5 100644 --- a/include/asm-frv/atomic.h +++ b/include/asm-frv/atomic.h @@ -1,7 +1,7 @@ /* atomic.h: atomic operation emulation for FR-V * * For an explanation of how atomic ops work in this arch, see: - * Documentation/fujitsu/frv/atomic-ops.txt + * Documentation/frv/atomic-ops.txt * * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. * Written by David Howells (dhowells@redhat.com) diff --git a/include/asm-frv/bitops.h b/include/asm-frv/bitops.h index e29de7131b7..5f86b876b29 100644 --- a/include/asm-frv/bitops.h +++ b/include/asm-frv/bitops.h @@ -1,7 +1,7 @@ /* bitops.h: bit operations for the Fujitsu FR-V CPUs * * For an explanation of how atomic ops work in this arch, see: - * Documentation/fujitsu/frv/atomic-ops.txt + * Documentation/frv/atomic-ops.txt * * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. * Written by David Howells (dhowells@redhat.com) diff --git a/include/asm-frv/cacheflush.h b/include/asm-frv/cacheflush.h index 02500405a6f..432a69e7f3d 100644 --- a/include/asm-frv/cacheflush.h +++ b/include/asm-frv/cacheflush.h @@ -29,7 +29,7 @@ #define flush_dcache_mmap_unlock(mapping) do {} while(0) /* - * physically-indexed cache managment + * physically-indexed cache management * - see arch/frv/lib/cache.S */ extern void frv_dcache_writeback(unsigned long start, unsigned long size); diff --git a/include/asm-frv/highmem.h b/include/asm-frv/highmem.h index ff4d6cdeb15..26cefcde5ce 100644 --- a/include/asm-frv/highmem.h +++ b/include/asm-frv/highmem.h @@ -4,7 +4,7 @@ * Written by David Howells (dhowells@redhat.com) * - Derived from include/asm-i386/highmem.h * - * See Documentation/fujitsu/frv/mmu-layout.txt for more information. + * See Documentation/frv/mmu-layout.txt for more information. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/include/asm-frv/mem-layout.h b/include/asm-frv/mem-layout.h index aaf2a773d9d..83532252b8b 100644 --- a/include/asm-frv/mem-layout.h +++ b/include/asm-frv/mem-layout.h @@ -39,7 +39,7 @@ #ifdef CONFIG_MMU -/* see Documentation/fujitsu/frv/mmu-layout.txt */ +/* see Documentation/frv/mmu-layout.txt */ #define KERNEL_LOWMEM_START __UL(0xc0000000) #define KERNEL_LOWMEM_END __UL(0xd0000000) #define VMALLOC_START __UL(0xd0000000) diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h index 147e995bec2..3c402afb9e7 100644 --- a/include/asm-frv/pgtable.h +++ b/include/asm-frv/pgtable.h @@ -93,7 +93,7 @@ extern unsigned long empty_zero_page; /* * we use 2-level page tables, folding the PMD (mid-level table) into the PGE (top-level entry) - * [see Documentation/fujitsu/frv/mmu-layout.txt] + * [see Documentation/frv/mmu-layout.txt] * * Page Directory: * - Size: 16KB diff --git a/include/asm-ia64/compat.h b/include/asm-ia64/compat.h index 0f6e5264ab8..dfcf75b8426 100644 --- a/include/asm-ia64/compat.h +++ b/include/asm-ia64/compat.h @@ -181,7 +181,7 @@ struct compat_shmid64_ds { /* * A pointer passed in from user mode. This should not be used for syscall parameters, * just declare them as pointers because the syscall entry code will have appropriately - * comverted them already. + * converted them already. */ typedef u32 compat_uptr_t; diff --git a/include/asm-m68knommu/bitops.h b/include/asm-m68knommu/bitops.h index f43afe1fc3b..c142fbf2f37 100644 --- a/include/asm-m68knommu/bitops.h +++ b/include/asm-m68knommu/bitops.h @@ -262,7 +262,7 @@ static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned lon * tmp = __swab32(*(p++)); * tmp |= ~0UL >> (32-offset); * - * but this would decrease preformance, so we change the + * but this would decrease performance, so we change the * shift: */ tmp = *(p++); diff --git a/include/asm-m68knommu/commproc.h b/include/asm-m68knommu/commproc.h index 0161ebb5d88..36e870b468e 100644 --- a/include/asm-m68knommu/commproc.h +++ b/include/asm-m68knommu/commproc.h @@ -715,7 +715,7 @@ extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ +#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ #define CICR_IEN ((uint)0x00000080) /* Int. enable */ #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ diff --git a/include/asm-m68knommu/delay.h b/include/asm-m68knommu/delay.h index 04a20fd051c..55cbd6294ab 100644 --- a/include/asm-m68knommu/delay.h +++ b/include/asm-m68knommu/delay.h @@ -68,7 +68,7 @@ static inline void _udelay(unsigned long usecs) /* * Moved the udelay() function into library code, no longer inlined. * I had to change the algorithm because we are overflowing now on - * the faster ColdFire parts. The code is a little biger, so it makes + * the faster ColdFire parts. The code is a little bigger, so it makes * sense to library it. */ extern void udelay(unsigned long usecs); diff --git a/include/asm-m68knommu/m5249sim.h b/include/asm-m68knommu/m5249sim.h index 399814f0b21..366eb8602d2 100644 --- a/include/asm-m68knommu/m5249sim.h +++ b/include/asm-m68knommu/m5249sim.h @@ -43,10 +43,10 @@ #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ -#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */ +#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */ +#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ diff --git a/include/asm-m68knommu/m5307sim.h b/include/asm-m68knommu/m5307sim.h index d3ce550f6ef..5886728409c 100644 --- a/include/asm-m68knommu/m5307sim.h +++ b/include/asm-m68knommu/m5307sim.h @@ -64,22 +64,22 @@ #define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */ #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ #else -#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */ +#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */ +#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ -#define MCFSIM_CSAR4 0xb0 /* CS 4 Adress reg (r/w) */ +#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ #define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ -#define MCFSIM_CSAR5 0xbc /* CS 5 Adress reg (r/w) */ +#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ #define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ -#define MCFSIM_CSAR6 0xc8 /* CS 6 Adress reg (r/w) */ +#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ #define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ -#define MCFSIM_CSAR7 0xd4 /* CS 7 Adress reg (r/w) */ +#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ #endif /* CONFIG_OLDMASK */ diff --git a/include/asm-m68knommu/m5407sim.h b/include/asm-m68knommu/m5407sim.h index 75dcdacdb29..cc22c4a5300 100644 --- a/include/asm-m68knommu/m5407sim.h +++ b/include/asm-m68knommu/m5407sim.h @@ -48,22 +48,22 @@ #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ -#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */ +#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */ +#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ -#define MCFSIM_CSAR4 0xb0 /* CS 4 Adress reg (r/w) */ +#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ #define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ -#define MCFSIM_CSAR5 0xbc /* CS 5 Adress reg (r/w) */ +#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ #define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ -#define MCFSIM_CSAR6 0xc8 /* CS 6 Adress reg (r/w) */ +#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ #define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ -#define MCFSIM_CSAR7 0xd4 /* CS 7 Adress reg (r/w) */ +#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ diff --git a/include/asm-m68knommu/m68360_regs.h b/include/asm-m68knommu/m68360_regs.h index a3f8cc8a4a8..d57217ca4f2 100644 --- a/include/asm-m68knommu/m68360_regs.h +++ b/include/asm-m68knommu/m68360_regs.h @@ -138,7 +138,7 @@ #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ +#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ #define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */ #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ diff --git a/include/asm-m68knommu/mcfuart.h b/include/asm-m68knommu/mcfuart.h index 1319a81814b..8a7a67703ac 100644 --- a/include/asm-m68knommu/mcfuart.h +++ b/include/asm-m68knommu/mcfuart.h @@ -71,7 +71,7 @@ struct mcf_platform_uart { #define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ #define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ #define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ -#define MCFUART_UISR 0x14 /* Interrup Status (r) */ +#define MCFUART_UISR 0x14 /* Interrupt Status (r) */ #define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ #define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ #define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h index 568c76cdd90..ac5d541368e 100644 --- a/include/asm-mips/compat.h +++ b/include/asm-mips/compat.h @@ -128,7 +128,7 @@ typedef u32 compat_sigset_word; * A pointer passed in from user mode. This should not * be used for syscall parameters, just declare them * as pointers because the syscall entry code will have - * appropriately comverted them already. + * appropriately converted them already. */ typedef u32 compat_uptr_t; diff --git a/include/asm-mips/mach-excite/excite_fpga.h b/include/asm-mips/mach-excite/excite_fpga.h index 38fcda703a0..0a1ef69bece 100644 --- a/include/asm-mips/mach-excite/excite_fpga.h +++ b/include/asm-mips/mach-excite/excite_fpga.h @@ -3,7 +3,7 @@ /** - * Adress alignment of the individual FPGA bytes. + * Address alignment of the individual FPGA bytes. * The address arrangement of the individual bytes of the FPGA is two * byte aligned at the embedded MK2 platform. */ diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h index 00d8bf6164a..83746b84a5e 100644 --- a/include/asm-mips/mach-wrppmc/mach-gt64120.h +++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h @@ -45,7 +45,7 @@ #define GT_PCI_IO_SIZE 0x02000000UL /* - * PCI interrupts will come in on either the INTA or INTD interrups lines, < |