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authorJack Morgenstein <jackm@dev.mellanox.co.il>2009-06-05 10:36:24 -0700
committerGreg Kroah-Hartman <gregkh@suse.de>2009-07-02 16:31:47 -0700
commitef01dc931edee0aff13604a74c9debb518bcc88c (patch)
treecb9a2a4b92a54fdcd0eea24b636cbc8e84d3aa12 /include
parent447bfafe4836bdb001789f99a456773a6cd25d33 (diff)
IB/mlx4: Add strong ordering to local inval and fast reg work requests
commit 2ac6bf4ddc87c3b6b609f8fa82f6ebbffeac12f4 upstream. The ConnectX Programmer's Reference Manual states that the "SO" bit must be set when posting Fast Register and Local Invalidate send work requests. When this bit is set, the work request will be executed only after all previous work requests on the send queue have been executed. (If the bit is not set, Fast Register and Local Invalidate WQEs may begin execution too early, which violates the defined semantics for these operations) This fixes the issue with NFS/RDMA reported in <http://lists.openfabrics.org/pipermail/general/2009-April/059253.html> Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mlx4/qp.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
index bf8f11982da..9f29d86e5dc 100644
--- a/include/linux/mlx4/qp.h
+++ b/include/linux/mlx4/qp.h
@@ -165,6 +165,7 @@ enum {
MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
MLX4_WQE_CTRL_INS_VLAN = 1 << 6,
+ MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
};
struct mlx4_wqe_ctrl_seg {