[ARM] 3240/2: AT91RM9200 support for 2.6 (Core)

Patch from SAN People

Following changes were made to clock.c:

1) Replaced <asm/hardware/clock.h> with <linux/clk.h>
2) Removed old unused clk_enable & clk_disable.
3) Replaced clk_use/clk_unuse with clk_enable/clk_disable.

Otherwise it's the same as the previous patch.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

17 files changed, 1473 insertions, 0 deletions

diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
new file mode 100644
index 00000000000..58f40931a5c
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -0,0 +1,261 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Common definitions.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_H
+#define AT91RM9200_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS	1	/* System Peripheral */
+#define AT91_ID_PIOA	2	/* Parallel IO Controller A */
+#define AT91_ID_PIOB	3	/* Parallel IO Controller B */
+#define AT91_ID_PIOC	4	/* Parallel IO Controller C */
+#define AT91_ID_PIOD	5	/* Parallel IO Controller D */
+#define AT91_ID_US0	6	/* USART 0 */
+#define AT91_ID_US1	7	/* USART 1 */
+#define AT91_ID_US2	8	/* USART 2 */
+#define AT91_ID_US3	9	/* USART 3 */
+#define AT91_ID_MCI	10	/* Multimedia Card Interface */
+#define AT91_ID_UDP	11	/* USB Device Port */
+#define AT91_ID_TWI	12	/* Two-Wire Interface */
+#define AT91_ID_SPI	13	/* Serial Peripheral Interface */
+#define AT91_ID_SSC0	14	/* Serial Synchronous Controller 0 */
+#define AT91_ID_SSC1	15	/* Serial Synchronous Controller 1 */
+#define AT91_ID_SSC2	16	/* Serial Synchronous Controller 2 */
+#define AT91_ID_TC0	17	/* Timer Counter 0 */
+#define AT91_ID_TC1	18	/* Timer Counter 1 */
+#define AT91_ID_TC2	19	/* Timer Counter 2 */
+#define AT91_ID_TC3	20	/* Timer Counter 3 */
+#define AT91_ID_TC4	21	/* Timer Counter 4 */
+#define AT91_ID_TC5	22	/* Timer Counter 5 */
+#define AT91_ID_UHP	23	/* USB Host port */
+#define AT91_ID_EMAC	24	/* Ethernet MAC */
+#define AT91_ID_IRQ0	25	/* Advanced Interrupt Controller (IRQ0) */
+#define AT91_ID_IRQ1	26	/* Advanced Interrupt Controller (IRQ1) */
+#define AT91_ID_IRQ2	27	/* Advanced Interrupt Controller (IRQ2) */
+#define AT91_ID_IRQ3	28	/* Advanced Interrupt Controller (IRQ3) */
+#define AT91_ID_IRQ4	29	/* Advanced Interrupt Controller (IRQ4) */
+#define AT91_ID_IRQ5	30	/* Advanced Interrupt Controller (IRQ5) */
+#define AT91_ID_IRQ6	31	/* Advanced Interrupt Controller (IRQ6) */
+
+
+/*
+ * Peripheral physical base addresses.
+ */
+#define AT91_BASE_TCB0		0xfffa0000
+#define AT91_BASE_TC0		0xfffa0000
+#define AT91_BASE_TC1		0xfffa0040
+#define AT91_BASE_TC2		0xfffa0080
+#define AT91_BASE_TCB1		0xfffa4000
+#define AT91_BASE_TC3		0xfffa4000
+#define AT91_BASE_TC4		0xfffa4040
+#define AT91_BASE_TC5		0xfffa4080
+#define AT91_BASE_UDP		0xfffb0000
+#define AT91_BASE_MCI		0xfffb4000
+#define AT91_BASE_TWI		0xfffb8000
+#define AT91_BASE_EMAC		0xfffbc000
+#define AT91_BASE_US0		0xfffc0000
+#define AT91_BASE_US1		0xfffc4000
+#define AT91_BASE_US2		0xfffc8000
+#define AT91_BASE_US3		0xfffcc000
+#define AT91_BASE_SSC0		0xfffd0000
+#define AT91_BASE_SSC1		0xfffd4000
+#define AT91_BASE_SSC2		0xfffd8000
+#define AT91_BASE_SPI		0xfffe0000
+#define AT91_BASE_SYS		0xfffff000
+
+
+/*
+ * PIO pin definitions (peripheral A/B multiplexing).
+ */
+#define AT91_PA0_MISO		(1 <<  0)	/* A: SPI Master-In Slave-Out */
+#define AT91_PA0_PCK3		(1 <<  0)	/* B: PMC Programmable Clock Output 3 */
+#define AT91_PA1_MOSI		(1 <<  1)	/* A: SPI Master-Out Slave-In */
+#define AT91_PA1_PCK0		(1 <<  1)	/* B: PMC Programmable Clock Output 0 */
+#define AT91_PA2_SPCK		(1 <<  2)	/* A: SPI Serial Clock */
+#define AT91_PA2_IRQ4		(1 <<  2)	/* B: External Interrupt 4 */
+#define AT91_PA3_NPCS0		(1 <<  3)	/* A: SPI Peripheral Chip Select 0 */
+#define AT91_PA3_IRQ5		(1 <<  3)	/* B: External Interrupt 5 */
+#define AT91_PA4_NPCS1		(1 <<  4)	/* A: SPI Peripheral Chip Select 1 */
+#define AT91_PA4_PCK1		(1 <<  4)	/* B: PMC Programmable Clock Output 1 */
+#define AT91_PA5_NPCS2		(1 <<  5)	/* A: SPI Peripheral Chip Select 2 */
+#define AT91_PA5_TXD3		(1 <<  5)	/* B: USART Transmit Data 3 */
+#define AT91_PA6_NPCS3		(1 <<  6)	/* A: SPI Peripheral Chip Select 3 */
+#define AT91_PA6_RXD3		(1 <<  6)	/* B: USART Receive Data 3 */
+#define AT91_PA7_ETXCK_EREFCK	(1 <<  7)	/* A: Ethernet Reference Clock / Transmit Clock */
+#define AT91_PA7_PCK2		(1 <<  7)	/* B: PMC Programmable Clock Output 2 */
+#define AT91_PA8_ETXEN		(1 <<  8)	/* A: Ethernet Transmit Enable */
+#define AT91_PA8_MCCDB		(1 <<  8)	/* B: MMC Multimedia Card B Command */
+#define AT91_PA9_ETX0		(1 <<  9)	/* A: Ethernet Transmit Data 0 */
+#define AT91_PA9_MCDB0		(1 <<  9)	/* B: MMC Multimedia Card B Data 0 */
+#define AT91_PA10_ETX1		(1 << 10)	/* A: Ethernet Transmit Data 1 */
+#define AT91_PA10_MCDB1		(1 << 10)	/* B: MMC Multimedia Card B Data 1 */
+#define AT91_PA11_ECRS_ECRSDV	(1 << 11)	/* A: Ethernet Carrier Sense / Data Valid */
+#define AT91_PA11_MCDB2		(1 << 11)	/* B: MMC Multimedia Card B Data 2 */
+#define AT91_PA12_ERX0		(1 << 12)	/* A: Ethernet Receive Data 0 */
+#define AT91_PA12_MCDB3		(1 << 12)	/* B: MMC Multimedia Card B Data 3 */
+#define AT91_PA13_ERX1		(1 << 13)	/* A: Ethernet Receive Data 1 */
+#define AT91_PA13_TCLK0		(1 << 13)	/* B: TC External Clock Input 0 */
+#define AT91_PA14_ERXER		(1 << 14)	/* A: Ethernet Receive Error */
+#define AT91_PA14_TCLK1		(1 << 14)	/* B: TC External Clock Input 1 */
+#define AT91_PA15_EMDC		(1 << 15)	/* A: Ethernet Management Data Clock */
+#define AT91_PA15_TCLK2		(1 << 15)	/* B: TC External Clock Input 2 */
+#define AT91_PA16_EMDIO		(1 << 16)	/* A: Ethernet Management Data I/O */
+#define AT91_PA16_IRQ6		(1 << 16)	/* B: External Interrupt 6 */
+#define AT91_PA17_TXD0		(1 << 17)	/* A: USART Transmit Data 0 */
+#define AT91_PA17_TIOA0		(1 << 17)	/* B: TC I/O Line A 0 */
+#define AT91_PA18_RXD0		(1 << 18)	/* A: USART Receive Data 0 */
+#define AT91_PA18_TIOB0		(1 << 18)	/* B: TC I/O Line B 0 */
+#define AT91_PA19_SCK0		(1 << 19)	/* A: USART Serial Clock 0 */
+#define AT91_PA19_TIOA1		(1 << 19)	/* B: TC I/O Line A 1 */
+#define AT91_PA20_CTS0		(1 << 20)	/* A: USART Clear To Send 0 */
+#define AT91_PA20_TIOB1		(1 << 20)	/* B: TC I/O Line B 1 */
+#define AT91_PA21_RTS0		(1 << 21)	/* A: USART Ready To Send 0 */
+#define AT91_PA21_TIOA2		(1 << 21)	/* B: TC I/O Line A 2 */
+#define AT91_PA22_RXD2		(1 << 22)	/* A: USART Receive Data 2 */
+#define AT91_PA22_TIOB2		(1 << 22)	/* B: TC I/O Line B 2 */
+#define AT91_PA23_TXD2		(1 << 23)	/* A: USART Transmit Data 2 */
+#define AT91_PA23_IRQ3		(1 << 23)	/* B: External Interrupt 3 */
+#define AT91_PA24_SCK2		(1 << 24)	/* A: USART Serial Clock 2 */
+#define AT91_PA24_PCK1		(1 << 24)	/* B: PMC Programmable Clock Output 1 */
+#define AT91_PA25_TWD		(1 << 25)	/* A: TWI Two-wire Serial Data */
+#define AT91_PA25_IRQ2		(1 << 25)	/* B: External Interrupt 2 */
+#define AT91_PA26_TWCK		(1 << 26)	/* A: TWI Two-wire Serial Clock */
+#define AT91_PA26_IRQ1		(1 << 26)	/* B: External Interrupt 1 */
+#define AT91_PA27_MCCK		(1 << 27)	/* A: MMC Multimedia Card Clock */
+#define AT91_PA27_TCLK3		(1 << 27)	/* B: TC External Clock Input 3 */
+#define AT91_PA28_MCCDA		(1 << 28)	/* A: MMC Multimedia Card A Command */
+#define AT91_PA28_TCLK4		(1 << 28)	/* B: TC External Clock Input 4 */
+#define AT91_PA29_MCDA0		(1 << 29)	/* A: MMC Multimedia Card A Data 0 */
+#define AT91_PA29_TCLK5		(1 << 29)	/* B: TC External Clock Input 5 */
+#define AT91_PA30_DRXD		(1 << 30)	/* A: DBGU Receive Data */
+#define AT91_PA30_CTS2		(1 << 30)	/* B: USART Clear To Send 2 */
+#define AT91_PA31_DTXD		(1 << 31)	/* A: DBGU Transmit Data */
+#define AT91_PA31_RTS2		(1 << 31)	/* B: USART Ready To Send 2 */
+
+#define AT91_PB0_TF0		(1 <<  0)	/* A: SSC Transmit Frame Sync 0 */
+#define AT91_PB0_RTS3		(1 <<  0)	/* B: USART Ready To Send 3 */
+#define AT91_PB1_TK0		(1 <<  1)	/* A: SSC Transmit Clock 0 */
+#define AT91_PB1_CTS3		(1 <<  1)	/* B: USART Clear To Send 3 */
+#define AT91_PB2_TD0		(1 <<  2)	/* A: SSC Transmit Data 0 */
+#define AT91_PB2_SCK3		(1 <<  2)	/* B: USART Serial Clock 3 */
+#define AT91_PB3_RD0		(1 <<  3)	/* A: SSC Receive Data 0 */
+#define AT91_PB3_MCDA1		(1 <<  3)	/* B: MMC Multimedia Card A Data 1 */
+#define AT91_PB4_RK0		(1 <<  4)	/* A: SSC Receive Clock 0 */
+#define AT91_PB4_MCDA2		(1 <<  4)	/* B: MMC Multimedia Card A Data 2 */
+#define AT91_PB5_RF0		(1 <<  5)	/* A: SSC Receive Frame Sync 0 */
+#define AT91_PB5_MCDA3		(1 <<  5)	/* B: MMC Multimedia Card A Data 3 */
+#define AT91_PB6_TF1		(1 <<  6)	/* A: SSC Transmit Frame Sync 1 */
+#define AT91_PB6_TIOA3		(1 <<  6)	/* B: TC I/O Line A 3 */
+#define AT91_PB7_TK1		(1 <<  7)	/* A: SSC Transmit Clock 1 */
+#define AT91_PB7_TIOB3		(1 <<  7)	/* B: TC I/O Line B 3 */
+#define AT91_PB8_TD1		(1 <<  8)	/* A: SSC Transmit Data 1 */
+#define AT91_PB8_TIOA4		(1 <<  8)	/* B: TC I/O Line A 4 */
+#define AT91_PB9_RD1		(1 <<  9)	/* A: SSC Receive Data 1 */
+#define AT91_PB9_TIOB4		(1 <<  9)	/* B: TC I/O Line B 4 */
+#define AT91_PB10_RK1		(1 << 10)	/* A: SSC Receive Clock 1 */
+#define AT91_PB10_TIOA5		(1 << 10)	/* B: TC I/O Line A 5 */
+#define AT91_PB11_RF1		(1 << 11)	/* A: SSC Receive Frame Sync 1 */
+#define AT91_PB11_TIOB5		(1 << 11)	/* B: TC I/O Line B 5 */
+#define AT91_PB12_TF2		(1 << 12)	/* A: SSC Transmit Frame Sync 2 */
+#define AT91_PB12_ETX2		(1 << 12)	/* B: Ethernet Transmit Data 2 */
+#define AT91_PB13_TK2		(1 << 13)	/* A: SSC Transmit Clock 3 */
+#define AT91_PB13_ETX3		(1 << 13)	/* B: Ethernet Transmit Data 3 */
+#define AT91_PB14_TD2		(1 << 14)	/* A: SSC Transmit Data 2 */
+#define AT91_PB14_ETXER		(1 << 14)	/* B: Ethernet Transmit Coding Error */
+#define AT91_PB15_RD2		(1 << 15)	/* A: SSC Receive Data 2 */
+#define AT91_PB15_ERX2		(1 << 15)	/* B: Ethernet Receive Data 2 */
+#define AT91_PB16_RK2		(1 << 16)	/* A: SSC Receive Clock 2 */
+#define AT91_PB16_ERX3		(1 << 16)	/* B: Ethernet Receive Data 3 */
+#define AT91_PB17_RF2		(1 << 17)	/* A: SSC Receive Frame Sync 2 */
+#define AT91_PB17_ERXDV		(1 << 17)	/* B: Ethernet Receive Data Valid */
+#define AT91_PB18_RI1		(1 << 18)	/* A: USART Ring Indicator 1 */
+#define AT91_PB18_ECOL		(1 << 18)	/* B: Ethernet Collision Detected */
+#define AT91_PB19_DTR1		(1 << 19)	/* A: USART Data Terminal Ready 1 */
+#define AT91_PB19_ERXCK		(1 << 19)	/* B: Ethernet Receive Clock */
+#define AT91_PB20_TXD1		(1 << 20)	/* A: USART Transmit Data 1 */
+#define AT91_PB21_RXD1		(1 << 21)	/* A: USART Receive Data 1 */
+#define AT91_PB22_SCK1		(1 << 22)	/* A: USART Serial Clock 1 */
+#define AT91_PB23_DCD1		(1 << 23)	/* A: USART Data Carrier Detect 1 */
+#define AT91_PB24_CTS1		(1 << 24)	/* A: USART Clear To Send 1 */
+#define AT91_PB25_DSR1		(1 << 25)	/* A: USART Data Set Ready 1 */
+#define AT91_PB25_EF100		(1 << 25)	/* B: Ethernet Force 100 Mbit */
+#define AT91_PB26_RTS1		(1 << 26)	/* A: USART Ready To Send 1 */
+#define AT91_PB27_PCK0		(1 << 27)	/* B: PMC Programmable Clock Output 0 */
+#define AT91_PB28_FIQ		(1 << 28)	/* A: Fast Interrupt */
+#define AT91_PB29_IRQ0		(1 << 29)	/* A: External Interrupt 0 */
+
+#define AT91_PC0_BFCK		(1 <<  0)	/* A: Burst Flash Clock */
+#define AT91_PC1_BFRDY_SMOE	(1 <<  1)	/* A: Burst Flash Ready / SmartMedia Output Enable */
+#define AT91_PC2_BFAVD		(1 <<  2)	/* A: Burst Flash Address Valid */
+#define AT91_PC3_BFBAA_SMWE	(1 <<  3)	/* A: Burst Flash Address Advance / SmartMedia Write Enable */
+#define AT91_PC4_BFOE		(1 <<  4)	/* A: Burst Flash Output Enable */
+#define AT91_PC5_BFWE		(1 <<  5)	/* A: Burst Flash Write Enable */
+#define AT91_PC6_NWAIT		(1 <<  6)	/* A: SMC Wait Signal */
+#define AT91_PC7_A23		(1 <<  7)	/* A: Address Bus 23 */
+#define AT91_PC8_A24		(1 <<  8)	/* A: Address Bus 24 */
+#define AT91_PC9_A25_CFRNW	(1 <<  9)	/* A: Address Bus 25 / Compact Flash Read Not Write */
+#define AT91_PC10_NCS4_CFCS	(1 << 10)	/* A: SMC Chip Select 4 / Compact Flash Chip Select */
+#define AT91_PC11_NCS5_CFCE1	(1 << 11)	/* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */
+#define AT91_PC12_NCS6_CFCE2	(1 << 12)	/* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */
+#define AT91_PC13_NCS7		(1 << 13)	/* A: Chip Select 7 */
+
+#define AT91_PD0_ETX0		(1 <<  0)	/* A: Ethernet Transmit Data 0 */
+#define AT91_PD1_ETX1		(1 <<  1)	/* A: Ethernet Transmit Data 1 */
+#define AT91_PD2_ETX2		(1 <<  2)	/* A: Ethernet Transmit Data 2 */
+#define AT91_PD3_ETX3		(1 <<  3)	/* A: Ethernet Transmit Data 3 */
+#define AT91_PD4_ETXEN		(1 <<  4)	/* A: Ethernet Transmit Enable */
+#define AT91_PD5_ETXER		(1 <<  5)	/* A: Ethernet Transmit Coding Error */
+#define AT91_PD6_DTXD		(1 <<  6)	/* A: DBGU Transmit Data */
+#define AT91_PD7_PCK0		(1 <<  7)	/* A: PMC Programmable Clock Output 0 */
+#define AT91_PD7_TSYNC		(1 <<  7)	/* B: ETM Trace Synchronization Signal */
+#define AT91_PD8_PCK1		(1 <<  8)	/* A: PMC Programmable Clock Output 1 */
+#define AT91_PD8_TCLK		(1 <<  8)	/* B: ETM Trace Clock */
+#define AT91_PD9_PCK2		(1 <<  9)	/* A: PMC Programmable Clock Output 2 */
+#define AT91_PD9_TPS0		(1 <<  9)	/* B: ETM Trace ARM Pipeline Status 0 */
+#define AT91_PD10_PCK3		(1 << 10)	/* A: PMC Programmable Clock Output 3 */
+#define AT91_PD10_TPS1		(1 << 10)	/* B: ETM Trace ARM Pipeline Status 1 */
+#define AT91_PD11_TPS2		(1 << 11)	/* B: ETM Trace ARM Pipeline Status 2 */
+#define AT91_PD12_TPK0		(1 << 12)	/* B: ETM Trace Packet Port 0 */
+#define AT91_PD13_TPK1		(1 << 13)	/* B: ETM Trace Packet Port 1 */
+#define AT91_PD14_TPK2		(1 << 14)	/* B: ETM Trace Packet Port 2 */
+#define AT91_PD15_TD0		(1 << 15)	/* A: SSC Transmit Data 0 */
+#define AT91_PD15_TPK3		(1 << 15)	/* B: ETM Trace Packet Port 3 */
+#define AT91_PD16_TD1		(1 << 16)	/* A: SSC Transmit Data 1 */
+#define AT91_PD16_TPK4		(1 << 16)	/* B: ETM Trace Packet Port 4 */
+#define AT91_PD17_TD2		(1 << 17)	/* A: SSC Transmit Data 2 */
+#define AT91_PD17_TPK5		(1 << 17)	/* B: ETM Trace Packet Port 5 */
+#define AT91_PD18_NPCS1		(1 << 18)	/* A: SPI Peripheral Chip Select 1 */
+#define AT91_PD18_TPK6		(1 << 18)	/* B: ETM Trace Packet Port 6 */
+#define AT91_PD19_NPCS2		(1 << 19)	/* A: SPI Peripheral Chip Select 2 */
+#define AT91_PD19_TPK7		(1 << 19)	/* B: ETM Trace Packet Port 7 */
+#define AT91_PD20_NPCS3		(1 << 20)	/* A: SPI Peripheral Chip Select 3 */
+#define AT91_PD20_TPK8		(1 << 20)	/* B: ETM Trace Packet Port 8 */
+#define AT91_PD21_RTS0		(1 << 21)  	/* A: USART Ready To Send 0 */
+#define AT91_PD21_TPK9		(1 << 21)	/* B: ETM Trace Packet Port 9 */
+#define AT91_PD22_RTS1		(1 << 22)	/* A: USART Ready To Send 1 */
+#define AT91_PD22_TPK10		(1 << 22)	/* B: ETM Trace Packet Port 10 */
+#define AT91_PD23_RTS2		(1 << 23)	/* A: USART Ready To Send 2 */
+#define AT91_PD23_TPK11		(1 << 23)	/* B: ETM Trace Packet Port 11 */
+#define AT91_PD24_RTS3		(1 << 24)	/* A: USART Ready To Send 3 */
+#define AT91_PD24_TPK12		(1 << 24)	/* B: ETM Trace Packet Port 12 */
+#define AT91_PD25_DTR1		(1 << 25)	/* A: USART Data Terminal Ready 1 */
+#define AT91_PD25_TPK13		(1 << 25)	/* B: ETM Trace Packet Port 13 */
+#define AT91_PD26_TPK14		(1 << 26)	/* B: ETM Trace Packet Port 14 */
+#define AT91_PD27_TPK15		(1 << 27)	/* B: ETM Trace Packet Port 15 */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
new file mode 100644
index 00000000000..9bfffdbf1e0
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -0,0 +1,328 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_SYS_H
+#define AT91RM9200_SYS_H
+
+/*
+ * Advanced Interrupt Controller.
+ */
+#define AT91_AIC	0x000
+
+#define AT91_AIC_SMR(n)		(AT91_AIC + ((n) * 4))	/* Source Mode Registers 0-31 */
+#define		AT91_AIC_PRIOR		(7 << 0)		/* Priority Level */
+#define		AT91_AIC_SRCTYPE	(3 << 5)		/* Interrupt Source Type */
+#define			AT91_AIC_SRCTYPE_LOW		(0 << 5)
+#define			AT91_AIC_SRCTYPE_FALLING	(1 << 5)
+#define			AT91_AIC_SRCTYPE_HIGH		(2 << 5)
+#define			AT91_AIC_SRCTYPE_RISING		(3 << 5)
+
+#define AT91_AIC_SVR(n)		(AT91_AIC + 0x80 + ((n) * 4))	/* Source Vector Registers 0-31 */
+#define AT91_AIC_IVR		(AT91_AIC + 0x100)	/* Interrupt Vector Register */
+#define AT91_AIC_FVR		(AT91_AIC + 0x104)	/* Fast Interrupt Vector Register */
+#define AT91_AIC_ISR		(AT91_AIC + 0x108)	/* Interrupt Status Register */
+#define		AT91_AIC_IRQID		(0x1f << 0)		/* Current Interrupt Identifier */
+
+#define AT91_AIC_IPR		(AT91_AIC + 0x10c)	/* Interrupt Pending Register */
+#define AT91_AIC_IMR		(AT91_AIC + 0x110)	/* Interrupt Mask Register */
+#define AT91_AIC_CISR		(AT91_AIC + 0x114)	/* Core Interrupt Status Register */
+#define		AT91_AIC_NFIQ		(1 << 0)		/* nFIQ Status */
+#define		AT91_AIC_NIRQ		(1 << 1)		/* nIRQ Status */
+
+#define AT91_AIC_IECR		(AT91_AIC + 0x120)	/* Interrupt Enable Command Register */
+#define AT91_AIC_IDCR		(AT91_AIC + 0x124)	/* Interrupt Disable Command Register */
+#define AT91_AIC_ICCR		(AT91_AIC + 0x128)	/* Interrupt Clear Command Register */
+#define AT91_AIC_ISCR		(AT91_AIC + 0x12c)	/* Interrupt Set Command Register */
+#define AT91_AIC_EOICR		(AT91_AIC + 0x130)	/* End of Interrupt Command Register */
+#define AT91_AIC_SPU		(AT91_AIC + 0x134)	/* Spurious Interrupt Vector Register */
+#define AT91_AIC_DCR		(AT91_AIC + 0x138)	/* Debug Control Register */
+#define		AT91_AIC_DCR_PROT	(1 << 0)		/* Protection Mode */
+#define		AT91_AIC_DCR_GMSK	(1 << 1)		/* General Mask */
+
+
+/*
+ * Debug Unit.
+ */
+#define AT91_DBGU	0x200
+
+#define AT91_DBGU_CR		(AT91_DBGU + 0x00)	/* Control Register */
+#define AT91_DBGU_MR		(AT91_DBGU + 0x04)	/* Mode Register */
+#define AT91_DBGU_IER		(AT91_DBGU + 0x08)	/* Interrupt Enable Register */
+#define		AT91_DBGU_TXRDY		(1 << 1)		/* Transmitter Ready */
+#define		AT91_DBGU_TXEMPTY	(1 << 9)		/* Transmitter Empty */
+#define AT91_DBGU_IDR		(AT91_DBGU + 0x0c)	/* Interrupt Disable Register */
+#define AT91_DBGU_IMR		(AT91_DBGU + 0x10)	/* Interrupt Mask Register */
+#define AT91_DBGU_SR		(AT91_DBGU + 0x14)	/* Status Register */
+#define AT91_DBGU_RHR		(AT91_DBGU + 0x18)	/* Receiver Holding Register */
+#define AT91_DBGU_THR		(AT91_DBGU + 0x1c)	/* Transmitter Holding Register */
+#define AT91_DBGU_BRGR		(AT91_DBGU + 0x20)	/* Baud Rate Generator Register */
+#define AT91_DBGU_CIDR		(AT91_DBGU + 0x40)	/* Chip ID Register */
+#define AT91_DBGU_EXID		(AT91_DBGU + 0x44)	/* Chip ID Extension Register */
+
+
+/*
+ * PIO Controllers.
+ */
+#define AT91_PIOA	0x400
+#define AT91_PIOB	0x600
+#define AT91_PIOC	0x800
+#define AT91_PIOD	0xa00
+
+#define PIO_PER		0x00	/* Enable Register */
+#define PIO_PDR		0x04	/* Disable Register */
+#define PIO_PSR		0x08	/* Status Register */
+#define PIO_OER		0x10	/* Output Enable Register */
+#define PIO_ODR		0x14	/* Output Disable Register */
+#define PIO_OSR		0x18	/* Output Status Register */
+#define PIO_IFER	0x20	/* Glitch Input Filter Enable */
+#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */
+#define PIO_IFSR	0x28	/* Glitch Input Filter Status */
+#define PIO_SODR	0x30	/* Set Output Data Register */
+#define PIO_CODR	0x34	/* Clear Output Data Register */
+#define PIO_ODSR	0x38	/* Output Data Status Register */
+#define PIO_PDSR	0x3c	/* Pin Data Status Register */
+#define PIO_IER		0x40	/* Interrupt Enable Register */
+#define PIO_IDR		0x44	/* Interrupt Disable Register */
+#define PIO_IMR		0x48	/* Interrupt Mask Register */
+#define PIO_ISR		0x4c	/* Interrupt Status Register */
+#define PIO_MDER	0x50	/* Multi-driver Enable Register */
+#define PIO_MDDR	0x54	/* Multi-driver Disable Register */
+#define PIO_MDSR	0x58	/* Multi-driver Status Register */
+#define PIO_PUDR	0x60	/* Pull-up Disable Register */
+#define PIO_PUER	0x64	/* Pull-up Enable Register */
+#define PIO_PUSR	0x68	/* Pull-up Status Register */
+#define PIO_ASR		0x70	/* Peripheral A Select Register */
+#define PIO_BSR		0x74	/* Peripheral B Select Register */
+#define PIO_ABSR	0x78	/* AB Status Register */
+#define PIO_OWER	0xa0	/* Output Write Enable Register */
+#define PIO_OWDR	0xa4	/* Output Write Disable Register */
+#define PIO_OWSR	0xa8	/* Output Write Status Register */
+
+#define AT91_PIO_P(n)	(1 << (n))
+
+
+/*
+ * Power Management Controller.
+ */
+#define	AT91_PMC	0xc00
+
+#define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */
+#define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */
+
+#define	AT91_PMC_SCSR		(AT91_PMC + 0x08)	/* System Clock Status Register */
+#define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
+#define		AT91_PMC_UDP		(1 <<  1)		/* USB Devcice Port Clock */
+#define		AT91_PMC_MCKUDP		(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend */
+#define		AT91_PMC_UHP		(1 <<  4)		/* USB Host Port Clock */
+#define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */
+#define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */
+#define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */
+#define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */
+
+#define	AT91_PMC_PCER		(AT91_PMC + 0x10)	/* Peripheral Clock Enable Register */
+#define	AT91_PMC_PCDR		(AT91_PMC + 0x14)	/* Peripheral Clock Disable Register */
+#define	AT91_PMC_PCSR		(AT91_PMC + 0x18)	/* Peripheral Clock Status Register */
+
+#define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register */
+#define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
+#define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
+
+#define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */
+#define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
+#define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
+
+#define	AT91_CKGR_PLLAR		(AT91_PMC + 0x28)	/* PLL A Register */
+#define	AT91_CKGR_PLLBR		(AT91_PMC + 0x2c)	/* PLL B Register */
+#define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
+#define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
+#define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
+#define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */
+#define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
+
+#define	AT91_PMC_MCKR		(AT91_PMC + 0x30)	/* Master Clock Register */
+#define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
+#define			AT91_PMC_CSS_SLOW		(0 << 0)
+#define			AT91_PMC_CSS_MAIN		(1 << 0)
+#define			AT91_PMC_CSS_PLLA		(2 << 0)
+#define			AT91_PMC_CSS_PLLB		(3 << 0)
+#define		AT91_PMC_PRES		(7 <<  2)		/* Master Clock Prescaler */
+#define 		AT91_PMC_PRES_1			(0 << 2)
+#define			AT91_PMC_PRES_2			(1 << 2)
+#define			AT91_PMC_PRES_4			(2 << 2)
+#define			AT91_PMC_PRES_8			(3 << 2)
+#define			AT91_PMC_PRES_16		(4 << 2)
+#define			AT91_PMC_PRES_32		(5 << 2)
+#define			AT91_PMC_PRES_64		(6 << 2)
+#define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
+#define			AT91_PMC_MDIV_1			(0 << 8)
+#define			AT91_PMC_MDIV_2			(1 << 8)
+#define			AT91_PMC_MDIV_3			(2 << 8)
+#define			AT91_PMC_MDIV_4			(3 << 8)
+
+#define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-3 Registers */
+#define	AT91_PMC_IER		(AT91_PMC + 0x60)	/* Interrupt Enable Register */
+#define	AT91_PMC_IDR		(AT91_PMC + 0x64)	/* Interrupt Disable Register */
+#define	AT91_PMC_SR		(AT91_PMC + 0x68)	/* Status Register */
+#define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
+#define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
+#define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
+#define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
+#define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
+#define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
+#define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
+#define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
+#define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */
+
+
+/*
+ * System Timer.
+ */
+#define	AT91_ST		0xd00
+
+#define	AT91_ST_CR		(AT91_ST + 0x00)	/* Control Register */
+#define 	AT91_ST_WDRST		(1 << 0)		/* Watchdog Timer Restart */
+#define	AT91_ST_PIMR		(AT91_ST + 0x04)	/* Period Interval Mode Register */
+#define		AT91_ST_PIV		(0xffff <<  0)		/* Period Interval Value */
+#define	AT91_ST_WDMR		(AT91_ST + 0x08)	/* Watchdog Mode Register */
+#define		AT91_ST_WDV		(0xffff <<  0)		/* Watchdog Counter Value */
+#define		AT91_ST_RSTEN		(1	<< 16)		/* Reset Enable */
+#define		AT91_ST_EXTEN		(1	<< 17)		/* External Signal Assertion Enable */
+#define	AT91_ST_RTMR		(AT91_ST + 0x0c)	/* Real-time Mode Register */
+#define		AT91_ST_RTPRES		(0xffff <<  0)		/* Real-time Prescalar Value */
+#define	AT91_ST_SR		(AT91_ST + 0x10)	/* Status Register */
+#define		AT91_ST_PITS		(1 << 0)		/* Period Interval Timer Status */
+#define		AT91_ST_WDOVF		(1 << 1) 		/* Watchdog Overflow */
+#define		AT91_ST_RTTINC		(1 << 2) 		/* Real-time Timer Increment */
+#define		AT91_ST_ALMS		(1 << 3) 		/* Alarm Status */
+#define	AT91_ST_IER		(AT91_ST + 0x14)	/* Interrupt Enable Register */
+#define	AT91_ST_IDR		(AT91_ST + 0x18)	/* Interrupt Disable Register */
+#define	AT91_ST_IMR		(AT91_ST + 0x1c)	/* Interrupt Mask Register */
+#define	AT91_ST_RTAR		(AT91_ST + 0x20)	/* Real-time Alarm Register */
+#define		AT91_ST_ALMV		(0xfffff << 0)		/* Alarm Value */
+#define	AT91_ST_CRTR		(AT91_ST + 0x24)	/* Current Real-time Register */
+#define		AT91_ST_CRTV		(0xfffff << 0)		/* Current Real-Time Value */
+
+
+/*
+ * Real-time Clock.
+ */
+#define	AT91_RTC	0xe00
+
+#define	AT91_RTC_CR		(AT91_RTC + 0x00)	/* Control Register */
+#define		AT91_RTC_UPDTIM		(1 <<  0)		/* Update Request Time Register */
+#define		AT91_RTC_UPDCAL		(1 <<  1)		/* Update Request Calendar Register */
+#define		AT91_RTC_TIMEVSEL	(3 <<  8)		/* Time Event Selection */
+#define			AT91_RTC_TIMEVSEL_MINUTE	(0 << 8)
+#define 		AT91_RTC_TIMEVSEL_HOUR		(1 << 8)
+#define 		AT91_RTC_TIMEVSEL_DAY24		(2 << 8)
+#define 		AT91_RTC_TIMEVSEL_DAY12		(3 << 8)
+#define		AT91_RTC_CALEVSEL	(3 << 16)		/* Calendar Event Selection */
+#define 		AT91_RTC_CALEVSEL_WEEK		(0 << 16)
+#define 		AT91_RTC_CALEVSEL_MONTH		(1 << 16)
+#define 		AT91_RTC_CALEVSEL_YEAR		(2 << 16)
+
+#define	AT91_RTC_MR		(AT91_RTC + 0x04)	/* Mode Register */
+#define 	AT91_RTC_HRMOD		(1 <<  0)		/* 12/24 Hour Mode */
+
+#define	AT91_RTC_TIMR		(AT91_RTC + 0x08)	/* Time Register */
+#define		AT91_RTC_SEC		(0x7f <<  0)		/* Current Second */
+#define		AT91_RTC_MIN		(0x7f <<  8)		/* Current Minute */
+#define		AT91_RTC_HOUR 		(0x3f << 16)		/* Current Hour */
+#define		At91_RTC_AMPM		(1    << 22)		/* Ante Meridiem Post Meridiem Indicator */
+
+#define	AT91_RTC_CALR		(AT91_RTC + 0x0c)	/* Calendar Register */
+#define		AT91_RTC_CENT		(0x7f <<  0)		/* Current Century */
+#define		AT91_RTC_YEAR		(0xff <<  8)		/* Current Year */
+#define		AT91_RTC_MONTH		(0x1f << 16)		/* Current Month */
+#define		AT91_RTC_DAY		(7    << 21)		/* Current Day */
+#define		AT91_RTC_DATE		(0x3f << 24)		/* Current Date */
+
+#define	AT91_RTC_TIMALR		(AT91_RTC + 0x10)	/* Time Alarm Register */
+#define		AT91_RTC_SECEN		(1 <<  7)		/* Second Alarm Enable */
+#define		AT91_RTC_MINEN		(1 << 15)		/* Minute Alarm Enable */
+#define		AT91_RTC_HOUREN		(1 << 23)		/* Hour Alarm Enable */
+
+#define	AT91_RTC_CALALR		(AT91_RTC + 0x14)	/* Calendar Alarm Register */
+#define		AT91_RTC_MTHEN		(1 << 23)		/* Month Alarm Enable */
+#define		AT91_RTC_DATEEN		(1 << 31)		/* Date Alarm Enable */
+
+#define	AT91_RTC_SR		(AT91_RTC + 0x18)	/* Status Register */
+#define		AT91_RTC_ACKUPD		(1 <<  0)		/* Acknowledge for Update */
+#define		AT91_RTC_ALARM		(1 <<  1)		/* Alarm Flag */
+#define		AT91_RTC_SECEV		(1 <<  2)		/* Second Event */
+#define		AT91_RTC_TIMEV		(1 <<  3)		/* Time Event */
+#define		AT91_RTC_CALEV		(1 <<  4)		/* Calendar Event */
+
+#define	AT91_RTC_SCCR		(AT91_RTC + 0x1c)	/* Status Clear Command Register */
+#define	AT91_RTC_IER		(AT91_RTC + 0x20)	/* Interrupt Enable Register */
+#define	AT91_RTC_IDR		(AT91_RTC + 0x24)	/* Interrupt Disable Register */
+#define	AT91_RTC_IMR		(AT91_RTC + 0x28)	/* Interrupt Mask Register */
+
+#define	AT91_RTC_VER		(AT91_RTC + 0x2c)	/* Valid Entry Register */
+#define		AT91_RTC_NVTIM		(1 <<  0)		/* Non valid Time */
+#define		AT91_RTC_NVCAL		(1 <<  1)		/* Non valid Calendar */
+#define		AT91_RTC_NVTIMALR	(1 <<  2)		/* Non valid Time Alarm */
+#define		AT91_RTC_NVCALALR	(1 <<  3)		/* Non valid Calendar Alarm */
+
+
+/*
+ * Memory Controller.
+ */
+#define AT91_MC		0xf00
+
+#define AT91_MC_RCR		(AT91_MC + 0x00)	/* MC Remap Control Register */
+#define		AT91_MC_RCB		(1 <<  0)		/* Remap Command Bit */
+
+#define AT91_MC_ASR		(AT91_MC + 0x04)	/* MC Abort Status Register */
+#define AT91_MC_AASR		(AT91_MC + 0x08)	/* MC Abort Address Status Register */
+#define AT91_MC_MPR		(AT91_MC + 0x0c)	/* MC Master Priority Register */
+
+/* External Bus Interface (EBI) registers */
+#define AT91_EBI_CSA		(AT91_MC + 0x60)	/* Chip Select Assignment Register */
+#define		AT91_EBI_CS0A		(1 << 0)		/* Chip Select 0 Assignment */
+#define			AT91_EBI_CS0A_SMC		(0 << 0)
+#define			AT91_EBI_CS0A_BFC		(1 << 0)
+#define		AT91_EBI_CS1A		(1 << 1)		/* Chip Select 1 Assignment */
+#define			AT91_EBI_CS1A_SMC		(0 << 1)
+#define			AT91_EBI_CS1A_SDRAMC		(1 << 1)
+#define		AT91_EBI_CS3A		(1 << 3)		/* Chip Select 2 Assignment */
+#define			AT91_EBI_CS3A_SMC		(0 << 3)
+#define			AT91_EBI_CS3A_SMC_SMARTMEDIA	(1 << 3)
+#define		AT91_EBI_CS4A		(1 << 4)		/* Chip Select 3 Assignment */
+#define			AT91_EBI_CS4A_SMC		(0 << 4)
+#define			AT91_EBI_CS4A_SMC_COMPACTFLASH	(1 << 4)
+#define AT91_EBI_CFGR		(AT91_MC + 0x64)	/* Configuration Register */
+#define		AT91_EBI_DBPUC		(1 << 0)		/* Data Bus Pull-Up Configuration */
+
+/* Static Memory Controller (SMC) registers */
+#define	AT91_SMC_CSR(n)		(AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
+#define		AT91_SMC_NWS		(0x7f <<  0)		/* Number of Wait States */
+#define		AT91_SMC_WSEN		(1    <<  7)		/* Wait State Enable */
+#define		AT91_SMC_TDF		(0xf  <<  8)		/* Data Float Time */
+#define		AT91_SMC_BAT		(1    << 12)		/* Byte Access Type */
+#define		AT91_SMC_DBW		(3    << 13)		/* Data Bus Width */
+#define			AT91_SMC_DBW_16		(1 << 13)
+#define			AT91_SMC_DBW_8		(2 << 13)
+#define		AT91_SMC_DPR		(1 << 15)		/* Data Read Protocol */
+#define		AT91_SMC_ACSS		(3 << 16)		/* Address to Chip Select Setup */
+#define			AT91_SMC_ACSS_STD	(0 << 16)
+#define			AT91_SMC_ACSS_1		(1 << 16)
+#define			AT91_SMC_ACSS_2		(2 << 16)
+#define			AT91_SMC_ACSS_3		(3 << 16)
+#define		AT91_SMC_RWSETUP	(7 << 24)		/* Read & Write Signal Time Setup */
+#define		AT91_SMC_RWHOLD		(7 << 28)		/* Read & Write Signal Hold Time */
+
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h
new file mode 100644
index 00000000000..2e7d1139a79
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/board.h
@@ -0,0 +1,80 @@
+/*
+ * include/asm-arm/arch-at91rm9200/board.h
+ *
+ *  Copyright (C) 2005 HP Labs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * These are data structures found in platform_device.dev.platform_data,
+ * and describing board-specfic data needed by drivers.  For example,
+ * which pin is used for a given GPIO role.
+ *
+ * In 2.6, drivers should strongly avoid board-specific knowledge so
+ * that supporting new boards normally won't require driver patches.
+ * Most board-specific knowledge should be in arch/.../board-*.c files.
+ */
+
+#ifndef __ASM_ARCH_BOARD_H
+#define __ASM_ARCH_BOARD_H
+
+ /* Clocks */
+extern unsigned long at91_master_clock;
+
+ /* Serial Port */
+extern int at91_serial_map[AT91_NR_UART];
+extern int at91_console_port;
+
+ /* USB Device */
+struct at91_udc_data {
+	u8	vbus_pin;		/* high == host powering us */
+	u8	pullup_pin;		/* high == D+ pulled up */
+};
+extern void __init at91_add_device_udc(struct at91_udc_data *data);
+
+ /* Compact Flash */
+struct at91_cf_data {
+	u8	irq_pin;		/* I/O IRQ */
+	u8	det_pin;		/* Card detect */
+	u8	vcc_pin;		/* power switching */
+	u8	rst_pin;		/* card reset */
+};
+extern void __init at91_add_device_cf(struct at91_cf_data *data);
+
+ /* MMC / SD */
+struct at91_mmc_data {
+	u8		det_pin;	/* card detect IRQ */
+	unsigned	is_b:1;		/* uses B side (vs A) */
+	unsigned	wire4:1;	/* (SD) supports DAT0..DAT3 */
+	u8		wp_pin;		/* (SD) writeprotect detect */
+	u8		vcc_pin;	/* power switching (high == on) */
+};
+extern void __init at91_add_device_mmc(struct at91_mmc_data *data);
+
+ /* Ethernet */
+struct at91_eth_data {
+	u8		phy_irq_pin;	/* PHY IRQ */
+	u8		is_rmii;	/* using RMII interface? */
+};
+extern void __init at91_add_device_eth(struct at91_eth_data *data);
+
+ /* USB Host */
+struct at91_usbh_data {
+	u8		ports;		/* number of ports on root hub */
+};
+extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/debug-macro.S b/include/asm-arm/arch-at91rm9200/debug-macro.S
new file mode 100644
index 00000000000..f496b54c4c3
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/debug-macro.S
@@ -0,0 +1,38 @@
+/*
+ * include/asm-arm/arch-at91rm9200/debug-macro.S
+ *
+ *  Copyright (C) 2003-2005 SAN People