diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-10-28 14:20:44 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-10-28 14:20:44 -0700 |
commit | 0e59e7e7feb5a12938fbf9135147eeda3238c6c4 (patch) | |
tree | dbe994369ca9cad6893f0fd710f75791bc84b816 /include | |
parent | 46b51ea2099fa2082342e52b8284aa828429b80b (diff) | |
parent | a513a99a7cebfb452839cc09c9c0586f72d96414 (diff) |
Merge branch 'next-rebase' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci
* 'next-rebase' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci:
PCI: Clean-up MPS debug output
pci: Clamp pcie_set_readrq() when using "performance" settings
PCI: enable MPS "performance" setting to properly handle bridge MPS
PCI: Workaround for Intel MPS errata
PCI: Add support for PASID capability
PCI: Add implementation for PRI capability
PCI: Export ATS functions to modules
PCI: Move ATS implementation into own file
PCI / PM: Remove unnecessary error variable from acpi_dev_run_wake()
PCI hotplug: acpiphp: Prevent deadlock on PCI-to-PCI bridge remove
PCI / PM: Extend PME polling to all PCI devices
PCI quirk: mmc: Always check for lower base frequency quirk for Ricoh 1180:e823
PCI: Make pci_setup_bridge() non-static for use by arch code
x86: constify PCI raw ops structures
PCI: Add quirk for known incorrect MPSS
PCI: Add Solarflare vendor ID and SFC4000 device IDs
Diffstat (limited to 'include')
-rw-r--r-- | include/acpi/acpiosxf.h | 2 | ||||
-rw-r--r-- | include/linux/pci-ats.h | 75 | ||||
-rw-r--r-- | include/linux/pci.h | 2 | ||||
-rw-r--r-- | include/linux/pci_ids.h | 5 | ||||
-rw-r--r-- | include/linux/pci_regs.h | 20 |
5 files changed, 104 insertions, 0 deletions
diff --git a/include/acpi/acpiosxf.h b/include/acpi/acpiosxf.h index 4543b6f7586..83062ed0ef2 100644 --- a/include/acpi/acpiosxf.h +++ b/include/acpi/acpiosxf.h @@ -189,6 +189,8 @@ void acpi_os_fixed_event_count(u32 fixed_event_number); /* * Threads and Scheduling */ +extern struct workqueue_struct *kacpi_hotplug_wq; + acpi_thread_id acpi_os_get_thread_id(void); acpi_status diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h index 655824fa4c7..e3d0b389024 100644 --- a/include/linux/pci-ats.h +++ b/include/linux/pci-ats.h @@ -1,6 +1,8 @@ #ifndef LINUX_PCI_ATS_H #define LINUX_PCI_ATS_H +#include <linux/pci.h> + /* Address Translation Service */ struct pci_ats { int pos; /* capability position */ @@ -15,6 +17,7 @@ struct pci_ats { extern int pci_enable_ats(struct pci_dev *dev, int ps); extern void pci_disable_ats(struct pci_dev *dev); extern int pci_ats_queue_depth(struct pci_dev *dev); + /** * pci_ats_enabled - query the ATS status * @dev: the PCI device @@ -49,4 +52,76 @@ static inline int pci_ats_enabled(struct pci_dev *dev) #endif /* CONFIG_PCI_IOV */ +#ifdef CONFIG_PCI_PRI + +extern int pci_enable_pri(struct pci_dev *pdev, u32 reqs); +extern void pci_disable_pri(struct pci_dev *pdev); +extern bool pci_pri_enabled(struct pci_dev *pdev); +extern int pci_reset_pri(struct pci_dev *pdev); +extern bool pci_pri_stopped(struct pci_dev *pdev); +extern int pci_pri_status(struct pci_dev *pdev); + +#else /* CONFIG_PCI_PRI */ + +static inline int pci_enable_pri(struct pci_dev *pdev, u32 reqs) +{ + return -ENODEV; +} + +static inline void pci_disable_pri(struct pci_dev *pdev) +{ +} + +static inline bool pci_pri_enabled(struct pci_dev *pdev) +{ + return false; +} + +static inline int pci_reset_pri(struct pci_dev *pdev) +{ + return -ENODEV; +} + +static inline bool pci_pri_stopped(struct pci_dev *pdev) +{ + return true; +} + +static inline int pci_pri_status(struct pci_dev *pdev) +{ + return -ENODEV; +} +#endif /* CONFIG_PCI_PRI */ + +#ifdef CONFIG_PCI_PASID + +extern int pci_enable_pasid(struct pci_dev *pdev, int features); +extern void pci_disable_pasid(struct pci_dev *pdev); +extern int pci_pasid_features(struct pci_dev *pdev); +extern int pci_max_pasids(struct pci_dev *pdev); + +#else /* CONFIG_PCI_PASID */ + +static inline int pci_enable_pasid(struct pci_dev *pdev, int features) +{ + return -EINVAL; +} + +static inline void pci_disable_pasid(struct pci_dev *pdev) +{ +} + +static inline int pci_pasid_features(struct pci_dev *pdev) +{ + return -EINVAL; +} + +static inline int pci_max_pasids(struct pci_dev *pdev) +{ + return -EINVAL; +} + +#endif /* CONFIG_PCI_PASID */ + + #endif /* LINUX_PCI_ATS_H*/ diff --git a/include/linux/pci.h b/include/linux/pci.h index f1b1ca1a09e..337df0d5d5f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -275,6 +275,7 @@ struct pci_dev { unsigned int pme_support:5; /* Bitmask of states from which PME# can be generated */ unsigned int pme_interrupt:1; + unsigned int pme_poll:1; /* Poll device's PME status bit */ unsigned int d1_support:1; /* Low power state D1 is supported */ unsigned int d2_support:1; /* Low power state D2 is supported */ unsigned int no_d1d2:1; /* Only allow D0 and D3 */ @@ -957,6 +958,7 @@ void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), int pci_cfg_space_size_ext(struct pci_dev *dev); int pci_cfg_space_size(struct pci_dev *dev); unsigned char pci_bus_max_busnr(struct pci_bus *bus); +void pci_setup_bridge(struct pci_bus *bus); #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index ae96bbe5451..1679ff6931f 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2302,6 +2302,11 @@ #define PCI_DEVICE_ID_RENESAS_SH7785 0x0007 #define PCI_DEVICE_ID_RENESAS_SH7786 0x0010 +#define PCI_VENDOR_ID_SOLARFLARE 0x1924 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0 0x0703 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1 0x6703 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000B 0x0710 + #define PCI_VENDOR_ID_TDI 0x192E #define PCI_DEVICE_ID_TDI_EHCI 0x0101 diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index e8840964aca..b5d9657f310 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -663,6 +663,26 @@ #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ #define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ +/* Page Request Interface */ +#define PCI_PRI_CAP 0x13 /* PRI capability ID */ +#define PCI_PRI_CONTROL_OFF 0x04 /* Offset of control register */ +#define PCI_PRI_STATUS_OFF 0x06 /* Offset of status register */ +#define PCI_PRI_ENABLE 0x0001 /* Enable mask */ +#define PCI_PRI_RESET 0x0002 /* Reset bit mask */ +#define PCI_PRI_STATUS_RF 0x0001 /* Request Failure */ +#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */ +#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */ +#define PCI_PRI_MAX_REQ_OFF 0x08 /* Cap offset for max reqs supported */ +#define PCI_PRI_ALLOC_REQ_OFF 0x0c /* Cap offset for max reqs allowed */ + +/* PASID capability */ +#define PCI_PASID_CAP 0x1b /* PASID capability ID */ +#define PCI_PASID_CAP_OFF 0x04 /* PASID feature register */ +#define PCI_PASID_CONTROL_OFF 0x06 /* PASID control register */ +#define PCI_PASID_ENABLE 0x01 /* Enable/Supported bit */ +#define PCI_PASID_EXEC 0x02 /* Exec permissions Enable/Supported */ +#define PCI_PASID_PRIV 0x04 /* Priviledge Mode Enable/Support */ + /* Single Root I/O Virtualization */ #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ #define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ |