Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6

15 files changed, 1504 insertions, 1504 deletions

diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index e828377ad29..7708ec669a3 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -927,7 +927,7 @@ static inline s64
 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
 {
 	struct ia64_pal_retval iprv;
-	PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
+	PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
 	if (vector)
 		*vector = iprv.v0;
 	*progress = iprv.v1;
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index 8c648bf72bb..09b99029ac1 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -25,8 +25,8 @@
  * Limits for PMC and PMD are set to less than maximum architected values
  * but should be sufficient for a while
  */
-#define IA64_NUM_PMC_REGS	32
-#define IA64_NUM_PMD_REGS	32
+#define IA64_NUM_PMC_REGS	64
+#define IA64_NUM_PMD_REGS	64
 
 #define DEFAULT_MAP_BASE	__IA64_UL_CONST(0x2000000000000000)
 #define DEFAULT_TASK_SIZE	__IA64_UL_CONST(0xa000000000000000)
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
index e35074f526d..a3431372c6e 100644
--- a/include/asm-ia64/sn/intr.h
+++ b/include/asm-ia64/sn/intr.h
@@ -40,7 +40,7 @@ struct sn_irq_info {
 	int		irq_cpuid;	/* kernel logical cpuid	     */
 	int		irq_irq;	/* the IRQ number */
 	int		irq_int_bit;	/* Bridge interrupt pin */
-	uint64_t	irq_xtalkaddr;	/* xtalkaddr IRQ is sent to  */
+	u64	irq_xtalkaddr;	/* xtalkaddr IRQ is sent to  */
 	int		irq_bridge_type;/* pciio asic type (pciio.h) */
 	void	       *irq_bridge;	/* bridge generating irq     */
 	void	       *irq_pciioinfo;	/* associated pciio_info_t   */
diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h
index 2b42d9ece26..9334078b089 100644
--- a/include/asm-ia64/sn/pcibr_provider.h
+++ b/include/asm-ia64/sn/pcibr_provider.h
@@ -44,9 +44,9 @@
 #define PCI32_MAPPED_BASE               0x40000000
 #define PCI32_DIRECT_BASE               0x80000000
 
-#define IS_PCI32_MAPPED(x)              ((uint64_t)(x) < PCI32_DIRECT_BASE && \
-                                         (uint64_t)(x) >= PCI32_MAPPED_BASE)
-#define IS_PCI32_DIRECT(x)              ((uint64_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI32_MAPPED(x)              ((u64)(x) < PCI32_DIRECT_BASE && \
+                                         (u64)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI32_DIRECT(x)              ((u64)(x) >= PCI32_MAPPED_BASE)
 
 
 /*
@@ -63,7 +63,7 @@
 	(IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
 
 #define MINIMAL_ATE_FLAG(addr, size) \
-	(MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0)
+	(MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
 
 /* bit 29 of the pci address is the SWAP bit */
 #define ATE_SWAPSHIFT                   29
@@ -90,27 +90,27 @@
  * PMU resources.
  */
 struct ate_resource{
-	uint64_t *ate;
-	uint64_t num_ate;
-	uint64_t lowest_free_index;
+	u64 *ate;
+	u64 num_ate;
+	u64 lowest_free_index;
 };
 
 struct pcibus_info {
 	struct pcibus_bussoft	pbi_buscommon;   /* common header */
-	uint32_t                pbi_moduleid;
+	u32                pbi_moduleid;
 	short                   pbi_bridge_type;
 	short                   pbi_bridge_mode;
 
 	struct ate_resource     pbi_int_ate_resource;
-	uint64_t                pbi_int_ate_size;
+	u64                pbi_int_ate_size;
 
-	uint64_t                pbi_dir_xbase;
+	u64                pbi_dir_xbase;
 	char                    pbi_hub_xid;
 
-	uint64_t                pbi_devreg[8];
+	u64                pbi_devreg[8];
 
-	uint32_t		pbi_valid_devices;
-	uint32_t		pbi_enabled_devices;
+	u32		pbi_valid_devices;
+	u32		pbi_enabled_devices;
 
 	spinlock_t              pbi_lock;
 };
@@ -136,22 +136,22 @@ extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
 /*
  * prototypes for the bridge asic register access routines in pcibr_reg.c
  */
-extern void             pcireg_control_bit_clr(struct pcibus_info *, uint64_t);
-extern void             pcireg_control_bit_set(struct pcibus_info *, uint64_t);
-extern uint64_t         pcireg_tflush_get(struct pcibus_info *);
-extern uint64_t         pcireg_intr_status_get(struct pcibus_info *);
-extern void             pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t);
-extern void             pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t);
-extern void             pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t);
+extern void             pcireg_control_bit_clr(struct pcibus_info *, u64);
+extern void             pcireg_control_bit_set(struct pcibus_info *, u64);
+extern u64         pcireg_tflush_get(struct pcibus_info *);
+extern u64         pcireg_intr_status_get(struct pcibus_info *);
+extern void             pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
+extern void             pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
+extern void             pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
 extern void             pcireg_force_intr_set(struct pcibus_info *, int);
-extern uint64_t         pcireg_wrb_flush_get(struct pcibus_info *, int);
-extern void             pcireg_int_ate_set(struct pcibus_info *, int, uint64_t);
-extern uint64_t *	pcireg_int_ate_addr(struct pcibus_info *, int);
+extern u64         pcireg_wrb_flush_get(struct pcibus_info *, int);
+extern void             pcireg_int_ate_set(struct pcibus_info *, int, u64);
+extern u64 *	pcireg_int_ate_addr(struct pcibus_info *, int);
 extern void 		pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
 extern void 		pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
 extern int 		pcibr_ate_alloc(struct pcibus_info *, int);
 extern void 		pcibr_ate_free(struct pcibus_info *, int);
-extern void 		ate_write(struct pcibus_info *, int, int, uint64_t);
+extern void 		ate_write(struct pcibus_info *, int, int, u64);
 extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
 				 void *resp);
 extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h
index ad0e8e8ae53..ce3f6c32824 100644
--- a/include/asm-ia64/sn/pcibus_provider_defs.h
+++ b/include/asm-ia64/sn/pcibus_provider_defs.h
@@ -29,13 +29,13 @@
  */
 
 struct pcibus_bussoft {
-	uint32_t		bs_asic_type;	/* chipset type */
-	uint32_t		bs_xid;		/* xwidget id */
-	uint32_t		bs_persist_busnum; /* Persistent Bus Number */
-	uint32_t		bs_persist_segment; /* Segment Number */
-	uint64_t		bs_legacy_io;	/* legacy io pio addr */
-	uint64_t		bs_legacy_mem;	/* legacy mem pio addr */
-	uint64_t		bs_base;	/* widget base */
+	u32		bs_asic_type;	/* chipset type */
+	u32		bs_xid;		/* xwidget id */
+	u32		bs_persist_busnum; /* Persistent Bus Number */
+	u32		bs_persist_segment; /* Segment Number */
+	u64		bs_legacy_io;	/* legacy io pio addr */
+	u64		bs_legacy_mem;	/* legacy mem pio addr */
+	u64		bs_base;	/* widget base */
 	struct xwidget_info	*bs_xwidget_info;
 };
 
diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h
index f65d222ca5e..38cdffbc4c7 100644
--- a/include/asm-ia64/sn/pcidev.h
+++ b/include/asm-ia64/sn/pcidev.h
@@ -55,8 +55,8 @@ struct sn_pci_controller {
 #define PCIIO_VENDOR_ID_NONE	(-1)
 
 struct pcidev_info {
-	uint64_t		pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
-	uint64_t		pdi_slot_host_handle;	/* Bus and devfn Host pci_dev */
+	u64		pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
+	u64		pdi_slot_host_handle;	/* Bus and devfn Host pci_dev */
 
 	struct pcibus_bussoft	*pdi_pcibus_info;	/* Kernel common bus soft */
 	struct pcidev_info	*pdi_host_pcidev_info;	/* Kernel Host pci_dev */
diff --git a/include/asm-ia64/sn/pic.h b/include/asm-ia64/sn/pic.h
index 0de82e6b089..5f9da5fd6e5 100644
--- a/include/asm-ia64/sn/pic.h
+++ b/include/asm-ia64/sn/pic.h
@@ -74,120 +74,120 @@ struct pic {
     /* 0x000000-0x00FFFF -- Local Registers */
 
     /* 0x000000-0x000057 -- Standard Widget Configuration */
-    uint64_t		p_wid_id;			/* 0x000000 */
-    uint64_t		p_wid_stat;			/* 0x000008 */
-    uint64_t		p_wid_err_upper;		/* 0x000010 */
-    uint64_t		p_wid_err_lower;		/* 0x000018 */
+    u64		p_wid_id;			/* 0x000000 */
+    u64		p_wid_stat;			/* 0x000008 */
+    u64		p_wid_err_upper;		/* 0x000010 */
+    u64		p_wid_err_lower;		/* 0x000018 */
     #define p_wid_err p_wid_err_lower
-    uint64_t		p_wid_control;			/* 0x000020 */
-    uint64_t		p_wid_req_timeout;		/* 0x000028 */
-    uint64_t		p_wid_int_upper;		/* 0x000030 */
-    uint64_t		p_wid_int_lower;		/* 0x000038 */
+    u64		p_wid_control;			/* 0x000020 */
+    u64		p_wid_req_timeout;		/* 0x000028 */
+    u64		p_wid_int_upper;		/* 0x000030 */
+    u64		p_wid_int_lower;		/* 0x000038 */
     #define p_wid_int p_wid_int_lower
-    uint64_t		p_wid_err_cmdword;		/* 0x000040 */
-    uint64_t		p_wid_llp;			/* 0x000048 */
-    uint64_t		p_wid_tflush;			/* 0x000050 */
+    u64		p_wid_err_cmdword;		/* 0x000040 */
+    u64		p_wid_llp;			/* 0x000048 */
+    u64		p_wid_tflush;			/* 0x000050 */
 
     /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
-    uint64_t		p_wid_aux_err;			/* 0x000058 */
-    uint64_t		p_wid_resp_upper;		/* 0x000060 */
-    uint64_t		p_wid_resp_lower;		/* 0x000068 */
+    u64		p_wid_aux_err;			/* 0x000058 */
+    u64		p_wid_resp_upper;		/* 0x000060 */
+    u64		p_wid_resp_lower;		/* 0x000068 */
     #define p_wid_resp p_wid_resp_lower
-    uint64_t		p_wid_tst_pin_ctrl;		/* 0x000070 */
-    uint64_t		p_wid_addr_lkerr;		/* 0x000078 */
+    u64		p_wid_tst_pin_ctrl;		/* 0x000070 */
+    u64		p_wid_addr_lkerr;		/* 0x000078 */
 
     /* 0x000080-0x00008F -- PMU & MAP */
-    uint64_t		p_dir_map;			/* 0x000080 */
-    uint64_t		_pad_000088;			/* 0x000088 */
+    u64		p_dir_map;			/* 0x000080 */
+    u64		_pad_000088;			/* 0x000088 */
 
     /* 0x000090-0x00009F -- SSRAM */
-    uint64_t		p_map_fault;			/* 0x000090 */
-    uint64_t		_pad_000098;			/* 0x000098 */
+    u64		p_map_fault;			/* 0x000090 */
+    u64		_pad_000098;			/* 0x000098 */
 
     /* 0x0000A0-0x0000AF -- Arbitration */
-    uint64_t		p_arb;				/* 0x0000A0 */
-    uint64_t		_pad_0000A8;			/* 0x0000A8 */
+    u64		p_arb;				/* 0x0000A0 */
+    u64		_pad_0000A8;			/* 0x0000A8 */
 
     /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
-    uint64_t		p_ate_parity_err;		/* 0x0000B0 */
-    uint64_t		_pad_0000B8;			/* 0x0000B8 */
+    u64		p_ate_parity_err;		/* 0x0000B0 */
+    u64		_pad_0000B8;			/* 0x0000B8 */
 
     /* 0x0000C0-0x0000FF -- PCI/GIO */
-    uint64_t		p_bus_timeout;			/* 0x0000C0 */
-    uint64_t		p_pci_cfg;			/* 0x0000C8 */
-    uint64_t		p_pci_err_upper;		/* 0x0000D0 */
-    uint64_t		p_pci_err_lower;		/* 0x0000D8 */
+    u64		p_bus_timeout;			/* 0x0000C0 */
+    u64		p_pci_cfg;			/* 0x0000C8 */
+    u64		p_pci_err_upper;		/* 0x0000D0 */
+    u64		p_pci_err_lower;		/* 0x0000D8 */
     #define p_pci_err p_pci_err_lower
-    uint64_t		_pad_0000E0[4];			/* 0x0000{E0..F8} */
+    u64		_pad_0000E0[4];			/* 0x0000{E0..F8} */
 
     /* 0x000100-0x0001FF -- Interrupt */
-    uint64_t		p_int_status;			/* 0x000100 */
-    uint64_t		p_int_enable;			/* 0x000108 */
-    uint64_t		p_int_rst_stat;			/* 0x000110 */
-    uint64_t		p_int_mode;			/* 0x000118 */
-    uint64_t		p_int_device;			/* 0x000120 */
-    uint64_t		p_int_host_err;			/* 0x000128 */
-    uint64_t		p_int_addr[8];			/* 0x0001{30,,,68} */
-    uint64_t		p_err_int_view;			/* 0x000170 */
-    uint64_t		p_mult_int;			/* 0x000178 */
-    uint64_t		p_force_always[8];		/* 0x0001{80,,,B8} */
-    uint64_t		p_force_pin[8];			/* 0x0001{C0,,,F8} */
+    u64		p_int_status;			/* 0x000100 */
+    u64		p_int_enable;			/* 0x000108 */
+    u64		p_int_rst_stat;			/* 0x000110 */
+    u64		p_int_mode;			/* 0x000118 */
+    u64		p_int_device;			/* 0x000120 */
+    u64		p_int_host_err;			/* 0x000128 */
+    u64		p_int_addr[8];			/* 0x0001{30,,,68} */
+    u64		p_err_int_view;			/* 0x000170 */
+    u64		p_mult_int;			/* 0x000178 */
+    u64		p_force_always[8];		/* 0x0001{80,,,B8} */
+    u64		p_force_pin[8];			/* 0x0001{C0,,,F8} */
 
     /* 0x000200-0x000298 -- Device */
-    uint64_t		p_device[4];			/* 0x0002{00,,,18} */
-    uint64_t		_pad_000220[4];			/* 0x0002{20,,,38} */
-    uint64_t		p_wr_req_buf[4];		/* 0x0002{40,,,58} */
-    uint64_t		_pad_000260[4];			/* 0x0002{60,,,78} */
-    uint64_t		p_rrb_map[2];			/* 0x0002{80,,,88} */
+    u64		p_device[4];			/* 0x0002{00,,,18} */
+    u64		_pad_000220[4];			/* 0x0002{20,,,38} */
+    u64		p_wr_req_buf[4];		/* 0x0002{40,,,58} */
+    u64		_pad_000260[4];			/* 0x0002{60,,,78} */
+    u64		p_rrb_map[2];			/* 0x0002{80,,,88} */
     #define p_even_resp p_rrb_map[0]			/* 0x000280 */
     #define p_odd_resp  p_rrb_map[1]			/* 0x000288 */
-    uint64_t		p_resp_status;			/* 0x000290 */
-    uint64_t		p_resp_clear;			/* 0x000298 */
+    u64		p_resp_status;			/* 0x000290 */
+    u64		p_resp_clear;			/* 0x000298 */
 
-    uint64_t		_pad_0002A0[12];		/* 0x0002{A0..F8} */
+    u64		_pad_0002A0[12];		/* 0x0002{A0..F8} */
 
     /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
     struct {
-	uint64_t	upper;				/* 0x0003{00,,,F0} */
-	uint64_t	lower;				/* 0x0003{08,,,F8} */
+	u64	upper;				/* 0x0003{00,,,F0} */
+	u64	lower;				/* 0x0003{08,,,F8} */
     } p_buf_addr_match[16];
 
     /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
     struct {
-	uint64_t	flush_w_touch;			/* 0x000{400,,,5C0} */
-	uint64_t	flush_wo_touch;			/* 0x000{408,,,5C8} */
-	uint64_t	inflight;			/* 0x000{410,,,5D0} */
-	uint64_t	prefetch;			/* 0x000{418,,,5D8} */
-	uint64_t	total_pci_retry;		/* 0x000{420,,,5E0} */
-	uint64_t	max_pci_retry;			/* 0x000{428,,,5E8} */
-	uint64_t	max_latency;			/* 0x000{430,,,5F0} */
-	uint64_t	clear_all;			/* 0x000{438,,,5F8} */
+	u64	flush_w_touch;			/* 0x000{400,,,5C0} */
+	u64	flush_wo_touch;			/* 0x000{408,,,5C8} */
+	u64	inflight;			/* 0x000{410,,,5D0} */
+	u64	prefetch;			/* 0x000{418,,,5D8} */
+	u64	total_pci_retry;		/* 0x000{420,,,5E0} */
+	u64	max_pci_retry;			/* 0x000{428,,,5E8} */
+	u64	max_latency;			/* 0x000{430,,,5F0} */
+	u64	clear_all;			/* 0x000{438,,,5F8} */
     } p_buf_count[8];
 
 
     /* 0x000600-0x0009FF -- PCI/X registers */
-    uint64_t		p_pcix_bus_err_addr;		/* 0x000600 */
-    uint64_t		p_pcix_bus_err_attr;		/* 0x000608 */
-    uint64_t		p_pcix_bus_err_data;		/* 0x000610 */
-    uint64_t		p_pcix_pio_split_addr;		/* 0x000618 */
-    uint64_t		p_pcix_pio_split_attr;		/* 0x000620 */
-    uint64_t		p_pcix_dma_req_err_attr;	/* 0x000628 */
-    uint64_t		p_pcix_dma_req_err_addr;	/* 0x000630 */
-    uint64_t		p_pcix_timeout;			/* 0x000638 */
+    u64		p_pcix_bus_err_addr;		/* 0x000600 */
+    u64		p_pcix_bus_err_attr;		/* 0x000608 */
+    u64		p_pcix_bus_err_data;		/* 0x000610 */
+    u64		p_pcix_pio_split_addr;		/* 0x000618 */
+    u64		p_pcix_pio_split_attr;		/* 0x000620 */
+    u64		p_pcix_dma_req_err_attr;	/* 0x000628 */
+    u64		p_pcix_dma_req_err_addr;	/* 0x000630 */
+    u64		p_pcix_timeout;			/* 0x000638 */
 
-    uint64_t		_pad_000640[120];		/* 0x000{640,,,9F8} */
+    u64		_pad_000640[120];		/* 0x000{640,,,9F8} */
 
     /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
     struct {
-	uint64_t	p_buf_addr;			/* 0x000{A00,,,AF0} */
-	uint64_t	p_buf_attr;			/* 0X000{A08,,,AF8} */
+	u64	p_buf_addr;			/* 0x000{A00,,,AF0} */
+	u64	p_buf_attr;			/* 0X000{A08,,,AF8} */
     } p_pcix_read_buf_64[16];
 
     struct {
-	uint64_t	p_buf_addr;			/* 0x000{B00,,,BE0} */
-	uint64_t	p_buf_attr;			/* 0x000{B08,,,BE8} */
-	uint64_t	p_buf_valid;			/* 0x000{B10,,,BF0} */
-	uint64_t	__pad1;				/* 0x000{B18,,,BF8} */
+	u64	p_buf_addr;			/* 0x000{B00,,,BE0} */
+	u64	p_buf_attr;			/* 0x000{B08,,,BE8} */
+	u64	p_buf_valid;			/* 0x000{B10,,,BF0} */
+	u64	__pad1;				/* 0x000{B18,,,BF8} */
     } p_pcix_write_buf_64[8];
 
     /* End of Local Registers -- Start of Address Map space */
@@ -195,45 +195,45 @@ struct pic {
     char		_pad_000c00[0x010000 - 0x000c00];
 
     /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
-    uint64_t		p_int_ate_ram[1024];		/* 0x010000-0x011fff */
+    u64		p_int_ate_ram[1024];		/* 0x010000-0x011fff */
 
     /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
-    uint64_t		p_int_ate_ram_mp[1024];		/* 0x012000-0x013fff */
+    u64		p_int_ate_ram_mp[1024];		/* 0x012000-0x013fff */
 
     char		_pad_014000[0x18000 - 0x014000];
 
     /* 0x18000-0x197F8 -- PIC Write Request Ram */
-    uint64_t		p_wr_req_lower[256];		/* 0x18000 - 0x187F8 */
-    uint64_t		p_wr_req_upper[256];		/* 0x18800 - 0x18FF8 */
-    uint64_t		p_wr_req_parity[256];		/* 0x19000 - 0x197F8 */
+    u64		p_wr_req_lower[256];		/* 0x18000 - 0x187F8 */
+    u64		p_wr_req_upper[256];		/* 0x18800 - 0x18FF8 */
+    u64		p_wr_req_parity[256];		/* 0x19000 - 0x197F8 */
 
     char		_pad_019800[0x20000 - 0x019800];
 
     /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
     union {
-	uint8_t		c[0x1000 / 1];			/* 0x02{0000,,,7FFF} */
-	uint16_t	s[0x1000 / 2];			/* 0x02{0000,,,7FFF} */
-	uint32_t	l[0x1000 / 4];			/* 0x02{0000,,,7FFF} */
-	uint64_t	d[0x1000 / 8];			/* 0x02{0000,,,7FFF} */
+	u8		c[0x1000 / 1];			/* 0x02{0000,,,7FFF} */
+	u16	s[0x1000 / 2];			/* 0x02{0000,,,7FFF} */
+	u32	l[0x1000 / 4];			/* 0x02{0000,,,7FFF} */
+	u64	d[0x1000 / 8];			/* 0x02{0000,,,7FFF} */
 	union {
-	    uint8_t	c[0x100 / 1];
-	    uint16_t	s[0x100 / 2];
-	    uint32_t	l[0x100 / 4];
-	    uint64_t	d[0x100 / 8];
+	    u8	c[0x100 / 1];
+	    u16	s[0x100 / 2];
+	    u32	l[0x100 / 4];
+	    u64	d[0x100 / 8];
 	} f[8];
     } p_type0_cfg_dev[8];				/* 0x02{0000,,,7FFF} */
 
     /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
     union {
-	uint8_t		c[0x1000 / 1];			/* 0x028000-0x029000 */
-	uint16_t	s[0x1000 / 2];			/* 0x028000-0x029000 */
-	uint32_t	l[0x1000 / 4];			/* 0x028000-0x029000 */
-	uint64_t	d[0x1000 / 8];			/* 0x028000-0x029000 */
+	u8		c[0x1000 / 1];			/* 0x028000-0x029000 */
+	u16	s[0x1000 / 2];			/* 0x028000-0x029000 */
+	u32	l[0x1000 / 4];			/* 0x028000-0x029000 */
+	u64	d[0x1000 / 8];			/* 0x028000-0x029000 */
 	union {
-	    uint8_t	c[0x100 / 1];
-	    uint16_t	s[0x100 / 2];
-	    uint32_t	l[0x100 / 4];
-	    uint64_t	d[0x100 / 8];
+	    u8	c[0x100 / 1];
+	    u16	s[0x100 / 2];
+	    u32	l[0x100 / 4];
+	    u64	d[0x100 / 8];
 	} f[8];
     } p_type1_cfg;					/* 0x028000-0x029000 */
 
@@ -241,20 +241,20 @@ struct pic {
 
     /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
     union {
-	uint8_t		c[8 / 1];
-	uint16_t	s[8 / 2];
-	uint32_t	l[8 / 4];
-	uint64_t	d[8 / 8];
+	u8		c[8 / 1];
+	u16	s[8 / 2];
+	u32	l[8 / 4];
+	u64	d[8 / 8];
     } p_pci_iack;					/* 0x030000-0x030007 */
 
     char		_pad_030007[0x040000-0x030008];
 
     /* 0x040000-0x030007 -- PCIX Special Cycle */
     union {
-	uint8_t		c[8 / 1];
-	uint16_t	s[8 / 2];
-	uint32_t	l[8 / 4];
-	uint64_t	d[8 / 8];
+	u8		c[8 / 1];
+	u16	s[8 / 2];
+	u32	l[8 / 4];
+	u64	d[8 / 8];
     } p_pcix_cycle;					/* 0x040000-0x040007 */
 };
 
diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h
index 831b72111fd..22a6f18a531 100644
--- a/include/asm-ia64/sn/shubio.h
+++ b/include/asm-ia64/sn/shubio.h
@@ -227,13 +227,13 @@
  ************************************************************************/
 
 typedef union ii_wid_u {
-	uint64_t ii_wid_regval;
+	u64 ii_wid_regval;
 	struct {
-		uint64_t w_rsvd_1:1;
-		uint64_t w_mfg_num:11;
-		uint64_t w_part_num:16;
-		uint64_t w_rev_num:4;
-		uint64_t w_rsvd:32;
+		u64 w_rsvd_1:1;
+		u64 w_mfg_num:11;
+		u64 w_part_num:16;
+		u64 w_rev_num:4;
+		u64 w_rsvd:32;
 	} ii_wid_fld_s;
 } ii_wid_u_t;
 
@@ -246,18 +246,18 @@ typedef union ii_wid_u {
  ************************************************************************/
 
 typedef union ii_wstat_u {
-	uint64_t ii_wstat_regval;
-	struct {
-		uint64_t w_pending:4;
-		uint64_t w_xt_crd_to:1;
-		uint64_t w_xt_tail_to:1;
-		uint64_t w_rsvd_3:3;
-		uint64_t w_tx_mx_rty:1;
-		uint64_t w_rsvd_2:6;
-		uint64_t w_llp_tx_cnt:8;
-		uint64_t w_rsvd_1:8;
-		uint64_t w_crazy:1;
-		uint64_t w_rsvd:31;
+	u64 ii_wstat_regval;
+	struct {
+		u64 w_pending:4;
+		u64 w_xt_crd_to:1;
+		u64 w_xt_tail_to:1;
+		u64 w_rsvd_3:3;
+		u64 w_tx_mx_rty:1;
+		u64 w_rsvd_2:6;
+		u64 w_llp_tx_cnt:8;
+		u64 w_rsvd_1:8;
+		u64 w_crazy:1;
+		u64 w_rsvd:31;
 	} ii_wstat_fld_s;
 } ii_wstat_u_t;
 
@@ -269,16 +269,16 @@ typedef union ii_wstat_u {
  ************************************************************************/
 
 typedef union ii_wcr_u {
-	uint64_t ii_wcr_regval;
-	struct {
-		uint64_t w_wid:4;
-		uint64_t w_tag:1;
-		uint64_t w_rsvd_1:8;
-		uint64_t w_dst_crd:3;
-		uint64_t w_f_bad_pkt:1;
-		uint64_t w_dir_con:1;
-		uint64_t w_e_thresh:5;
-		uint64_t w_rsvd:41;
+	u64 ii_wcr_regval;
+	struct {
+		u64 w_wid:4;
+		u64 w_tag:1;
+		u64 w_rsvd_1:8;
+		u64 w_dst_crd:3;
+		u64 w_f_bad_pkt:1;
+		u64 w_dir_con:1;
+		u64 w_e_thresh:5;
+		u64 w_rsvd:41;
 	} ii_wcr_fld_s;
 } ii_wcr_u_t;
 
@@ -310,9 +310,9 @@ typedef union ii_wcr_u {
  ************************************************************************/
 
 typedef union ii_ilapr_u {
-	uint64_t ii_ilapr_regval;
+	u64 ii_ilapr_regval;
 	struct {
-		uint64_t i_region:64;
+		u64 i_region:64;
 	} ii_ilapr_fld_s;
 } ii_ilapr_u_t;
 
@@ -330,9 +330,9 @@ typedef union ii_ilapr_u {
  ************************************************************************/
 
 typedef union ii_ilapo_u {
-	uint64_t ii_ilapo_regval;
+	u64 ii_ilapo_regval;
 	struct {
-		uint64_t i_io_ovrride:64;
+		u64 i_io_ovrride:64;
 	} ii_ilapo_fld_s;
 } ii_ilapo_u_t;
 
@@ -344,12 +344,12 @@ typedef union ii_ilapo_u {
  ************************************************************************/
 
 typedef union ii_iowa_u {
-	uint64_t ii_iowa_regval;
+	u64 ii_iowa_regval;
 	struct {
-		uint64_t i_w0_oac:1;
-		uint64_t i_rsvd_1:7;
-		uint64_t i_wx_oac:8;
-		uint64_t i_rsvd:48;
+		u64 i_w0_oac:1;
+		u64 i_rsvd_1:7;
+		u64 i_wx_oac:8;
+		u64 i_rsvd:48;
 	} ii_iowa_fld_s;
 } ii_iowa_u_t;
 
@@ -363,12 +363,12 @@ typedef union ii_iowa_u {
  ************************************************************************/
 
 typedef union ii_iiwa_u {
-	uint64_t ii_iiwa_regval;
+	u64 ii_iiwa_regval;
 	struct {
-		uint64_t i_w0_iac:1;
-		uint64_t i_rsvd_1:7;
-		uint64_t i_wx_iac:8;
-		uint64_t i_rsvd:48;
+		u64 i_w0_iac:1;
+		u64 i_rsvd_1:7;
+		u64 i_wx_iac:8;
+		u64 i_rsvd:48;
 	} ii_iiwa_fld_s;
 } ii_iiwa_u_t;
 
@@ -392,16 +392,16 @@ typedef union ii_iiwa_u {
  ************************************************************************/
 
 typedef union ii_iidem_u {
-	uint64_t ii_iidem_regval;
-	struct {
-		uint64_t i_w8_dxs:8;
-		uint64_t i_w9_dxs:8;
-		uint64_t i_wa_dxs:8;
-		uint64_t i_wb_dxs:8;
-		uint64_t i_wc_dxs:8;
-		uint64_t i_wd_dxs:8;
-		uint64_t i_we_dxs:8;
-		uint64_t i_wf_dxs:8;
+	u64 ii_iidem_regval;
+	struct {
+		u64 i_w8_dxs:8;
+		u64 i_w9_dxs:8;
+		u64 i_wa_dxs:8;
+		u64 i_wb_dxs:8;
+		u64 i_wc_dxs:8;
+		u64 i_wd_dxs:8;
+		u64 i_we_dxs:8;
+		u64 i_wf_dxs:8;
 	} ii_iidem_fld_s;
 } ii_iidem_u_t;
 
@@ -413,22 +413,22 @@ typedef union ii_iidem_u {
  ************************************************************************/
 
 typedef union ii_ilcsr_u {
-	uint64_t ii_ilcsr_regval;
-	struct {
-		uint64_t i_nullto:6;
-		uint64_t i_rsvd_4:2;
-		uint64_t i_wrmrst:1;
-		uint64_t i_rsvd_3:1;
-		uint64_t i_llp_en:1;
-		uint64_t i_bm8:1;
-		uint64_t i_llp_stat:2;
-		uint64_t i_remote_power:1;
-		uint64_t i_rsvd_2:1;
-		uint64_t i_maxrtry:10;
-		uint64_t i_d_avail_sel:2;
-		uint64_t i_rsvd_1:4;
-		uint64_t i_maxbrst:10;
-		uint64_t i_rsvd:22;
+	u64 ii_ilcsr_regval;
+	struct {
+		u64 i_nullto:6;
+		u64 i_rsvd_4:2;
+		u64 i_wrmrst:1;
+		u64 i_rsvd_3:1;
+		u64 i_llp_en:1;
+		u64 i_bm8:1;
+		u64 i_llp_stat:2;
+		u64 i_remote_power:1;
+		u64 i_rsvd_2:1;
+		u64 i_maxrtry:10;
+		u64 i_d_avail_sel:2;
+		u64 i_rsvd_1:4;
+		u64 i_maxbrst:10;
+		u64 i_rsvd:22;
 
 	} ii_ilcsr_fld_s;
 } ii_ilcsr_u_t;
@@ -441,11 +441,11 @@ typedef union ii_ilcsr_u {
  ************************************************************************/
 
 typedef union ii_illr_u {
-	uint64_t ii_illr_regval;
+	u64 ii_illr_regval;
 	struct {
-		uint64_t i_sn_cnt:16;
-		uint64_t i_cb_cnt:16;
-		uint64_t i_rsvd:32;
+		u64 i_sn_cnt:16;
+		u64 i_cb_cnt:16;
+		u64 i_rsvd:32;
 	} ii_illr_fld_s;
 } ii_illr_u_t;
 
@@ -464,19 +464,19 @@ typedef union ii_illr_u {
  ************************************************************************/
 
 typedef union ii_iidsr_u {
-	uint64_t ii_iidsr_regval;
-	struct {
-		uint64_t i_level:8;
-		uint64_t i_pi_id:1;
-		uint64_t i_node:11;
-		uint64_t i_rsvd_3:4;
-		uint64_t i_enable:1;
-		uint64_t i_rsvd_2:3;
-		uint64_t i_int_sent:2;
-		uint64_t i_rsvd_1:2;
-		uint64_t i_pi0_forward_int:1;
-		uint64_t i_pi1_forward_int:1;
-		uint64_t i_rsvd:30;
+	u64 ii_iidsr_regval;
+	struct {
+		u64 i_level:8;
+		u64 i_pi_id:1;
+		u64 i_node:11;
+		u64 i_rsvd_3:4;
+		u64 i_enable:1;
+		u64 i_rsvd_2:3;
+		u64 i_int_sent:2;
+		u64 i_rsvd_1:2;
+		u64 i_pi0_forward_int:1;
+		u64 i_pi1_forward_int:1;
+		u64 i_rsvd:30;
 	} ii_iidsr_fld_s;
 } ii_iidsr_u_t;
 
@@ -492,13 +492,13 @@ typedef union ii_iidsr_u {
  ************************************************************************/
 
 typedef union ii_igfx0_u {
-	uint64_t ii_igfx0_regval;
+	u64 ii_igfx0_regval;
 	struct {
-		uint64_t i_w_num:4;
-		uint64_t i_pi_id:1;
-		uint64_t i_n_num:12;
-		uint64_t i_p_num:1;
-		uint64_t i_rsvd:46;
+		u64 i_w_num:4;
+		u64 i_pi_id:1;
+		u64 i_n_num:12;
+		u64 i_p_num:1;
+		u64 i_rsvd:46;
 	} ii_igfx0_fld_s;
 } ii_igfx0_u_t;
 
@@ -514,13 +514,13 @@ typedef union ii_igfx0_u {
  ************************************************************************/
 
 typedef union ii_igfx1_u {
-	uint64_t ii_igfx1_regval;
+	u64 ii_igfx1_regval;
 	struct {
-		uint64_t i_w_num:4;
-		uint64_t i_pi_id:1;
-		uint64_t i_n_num:12;
-		uint64_t i_p_num:1;
-		uint64_t i_rsvd:46;
+		u64 i_w_num:4;
+		u64 i_pi_id:1;
+		u64 i_n_num:12;
+		u64 i_p_num:1;
+		u64 i_rsvd:46;
 	} ii_igfx1_fld_s;
 } ii_igfx1_u_t;
 
@@ -532,9 +532,9 @@ typedef union ii_igfx1_u {
  ************************************************************************/
 
 typedef union ii_iscr0_u {
-	uint64_t ii_iscr0_regval;
+	u64 ii_iscr0_regval;
 	struct {
-		uint64_t i_scratch:64;
+		u64 i_scratch:64;
 	} ii_iscr0_fld_s;
 } ii_iscr0_u_t;
 
@@ -546,9 +546,9 @@ typedef union ii_iscr0_u {
  ************************************************************************/
 
 typedef union ii_iscr1_u {
-	uint64_t ii_iscr1_regval;
+	u64 ii_iscr1_regval;
 	struct {
-		uint64_t i_scratch:64;
+		u64 i_scratch:64;
 	} ii_iscr1_fld_s;
 } ii_iscr1_u_t;
 
@@ -580,13 +580,13 @@ typedef union ii_iscr1_u {
  ************************************************************************/
 
 typedef union ii_itte1_u {
-	uint64_t ii_itte1_regval;
+	u64 ii_itte1_regval;
 	struct {
-		uint64_t i_offset:5;
-		uint64_t i_rsvd_1:3;
-		uint64_t i_w_num:4;
-		uint64_t i_iosp:1;
-		uint64_t i_rsvd:51;
+		u64 i_offset:5;
+		u64 i_rsvd_1:3;
+		u64 i_w_num:4;
+		u64 i_iosp:1;
+		u64 i_rsvd:51;
 	} ii_itte1_fld_s;
 } ii_itte1_u_t;
 
@@ -618,13 +618,13 @@ typedef union ii_itte1_u {
  ************************************************************************/
 
 typedef union ii_itte2_u {
-	uint64_t ii_itte2_regval;
+	u64 ii_itte2_regval;
 	struct {
-		uint64_t i_offset:5;
-		uint64_t i_rsvd_1:3;
-		uint64_t i_w_num:4;
-		uint64_t i_iosp:1;
-		uint64_t i_rsvd:51;
+		u64 i_offset:5;
+		u64 i_rsvd_1:3;
+		u64 i_w_num:4;
+		u64 i_iosp:1;
+		u64 i_rsvd:51;
 	} ii_itte2_fld_s;
 } ii_itte2_u_t;
 
@@ -656,13 +656,13 @@ typedef union ii_itte2_u {
  ************************************************************************/
 
 typedef union ii_itte3_u {
-	uint64_t ii_itte3_regval;
+	u64 ii_itte3_regval;
 	struct {
-		uint64_t i_offset:5;
-		uint64_t i_rsvd_1:3;
-		uint64_t i_w_num:4;
-		uint64_t i_iosp:1;
-		uint64_t i_rsvd:51;
+		u64 i_offset:5;
+		u64 i_rsvd_1:3;
+		u64 i_w_num:4;
+		u64 i_iosp:1;
+		u64 i_rsvd:51;
 	} ii_itte3_fld_s;
 } ii_itte3_u_t;
 
@@ -694,13 +694,13 @@ typedef union ii_itte3_u {
  ************************************************************************/
 
 typedef union ii_itte4_u {
-	uint64_t ii_itte4_regval;
+	u64 ii_itte4_regval;
 	struct {
-		uint64_t i_offset:5;
-		uint64_t i_rsvd_1:3;
-		uint64_t i_w_num:4;
-		uint64_t i_iosp:1;
-		uint64_t i_rsvd:51;
+		u64 i_offset:5;
+		u64 i_rsvd_1:3;
+		u64 i_w_num:4;
+		u64 i_iosp:1;
+		u64 i_rsvd:51;
 	} ii_itte4_fld_s;
 } ii_itte4_u_t;
 
@@ -732,13 +732,13 @@ typedef union ii_itte4_u {
  ************************************************************************/
 
 typedef union ii_itte5_u {
-	uint64_t ii_itte5_regval;
+	u64 ii_itte5_regval;
 	struct {
-		uint64_t i_offset:5;
-		uint64_t i_rsvd_1:3;
-		uint64_t i_w_num:4;
-		uint64_t i_iosp:1;
-		uint64_t i_rsvd:51;
+		u64 i_offset:5;
+		u64 i_rsvd_1:3;
+		u64 i_w_num:4;
+		u64 i_iosp:1;
+		u64 i_rsvd:51;
 	} ii_itte5_fld_s;
 } ii_itte5_u_t;
 
@@ -770,13 +770,13 @@ typedef union ii_itte5_u {
  ************************************************************************/
 
 typedef union ii_itte6_u {
-	uint64_t ii_itte6_regval;
+	u64 ii_itte6_regval;
 	struct {
-		uint64_t i_offset:5;
-		uint64_t i_rsvd_1:3;
-		uint64_t i_w_num:4;
-		uint64_t i_iosp:1;
-		uint64_t i_rsvd:51;
+		u64 i_offset:5;
+		u64 i_rsvd_1:3;
+		u64 i_w_num:4;
+		u64 i_iosp:1;
+		u64 i_rsvd:51;
 	} ii_itte6_fld_s;
 } ii_itte6_u_t;
 
@@ -808,13 +808,13 @@ typedef union ii_itte6_u {
  ************************************************************************/
 
 typedef union ii_itte7_u {
-	uint64_t ii_itte7_regval;
+	u64 ii_itte7_regval;
 	struct {
-		uint64_t i_offset:5;
-		uint64_t i_rsvd_1:3;
-		uint64_t i_w_num:4;
-		uint64_t i_iosp:1;
-		uint64_t i_rsvd:51;
+		u64 i_offset:5;
+		u64 i_rsvd_1:3;
+		u64 i_w_num:4;
+		u64 i_iosp:1;
+		u64 i_rsvd:51;
 	} ii_itte7_fld_s;
 } ii_itte7_u_t;
 
@@ -843,22 +843,22 @@ typedef union ii_itte7_u {
  ************************************************************************/
 
 typedef union ii_iprb0_u {
-	uint64_t ii_iprb0_regval;
-	struct {
-		uint64_t i_c:8;
-		uint64_t i_na:14;
-		uint64_t i_rsvd_2:2;
-		uint64_t i_nb:14;
-		uint64_t i_rsvd_1:2;
-		uint64_t i_m:2;
-		uint64_t i_f:1;
-		uint64_t i_of_cnt:5;
-		uint64_t i_error:1;
-		uint64_t i_rd_to:1;
-		uint64_t i_spur_wr:1;
-		uint64_t i_spur_rd:1;
-		uint64_t i_rsvd:11;
-		uint64_t i_mult_er