diff options
| author | Hans Verkuil <hans.verkuil@cisco.com> | 2013-03-11 03:47:25 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2013-03-24 12:10:18 -0300 |
| commit | 1589037f8716a605a36ee6dda6f7cdd4d043522b (patch) | |
| tree | 00f6593d07cea0e5879ebb70c0242add78966134 /include/media | |
| parent | c875dee536ee2a95a353f5ef991717383baf8d60 (diff) | |
[media] saa7115: add support for double-rate ASCLK
Some devices expect a double rate ASCLK. Add a flag to let the driver know
through the s_crystal_freq call.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'include/media')
| -rw-r--r-- | include/media/saa7115.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/include/media/saa7115.h b/include/media/saa7115.h index 8b2ecc69a70..407918625c8 100644 --- a/include/media/saa7115.h +++ b/include/media/saa7115.h @@ -59,9 +59,10 @@ #define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */ /* SAA7115 v4l2_crystal_freq audio clock control flags */ -#define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */ -#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */ -#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */ +#define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */ +#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */ +#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */ +#define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */ #endif |