diff options
| author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 15:20:36 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 15:20:36 -0700 |
| commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
| tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-v850/v850e_cache.h | |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/asm-v850/v850e_cache.h')
| -rw-r--r-- | include/asm-v850/v850e_cache.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/include/asm-v850/v850e_cache.h b/include/asm-v850/v850e_cache.h new file mode 100644 index 00000000000..aa7d7eb9da5 --- /dev/null +++ b/include/asm-v850/v850e_cache.h @@ -0,0 +1,48 @@ +/* + * include/asm-v850/v850e_cache.h -- Cache control for V850E cache memories + * + * Copyright (C) 2001,03 NEC Electronics Corporation + * Copyright (C) 2001,03 Miles Bader <miles@gnu.org> + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader <miles@gnu.org> + */ + +/* This file implements cache control for the rather simple cache used on + some V850E CPUs, specifically the NB85E/TEG CPU-core and the V850E/ME2 + CPU. V850E2 processors have their own (better) cache + implementation. */ + +#ifndef __V850_V850E_CACHE_H__ +#define __V850_V850E_CACHE_H__ + +#include <asm/types.h> + + +/* Cache control registers. */ +#define V850E_CACHE_BHC_ADDR 0xFFFFF06A +#define V850E_CACHE_BHC (*(volatile u16 *)V850E_CACHE_BHC_ADDR) +#define V850E_CACHE_ICC_ADDR 0xFFFFF070 +#define V850E_CACHE_ICC (*(volatile u16 *)V850E_CACHE_ICC_ADDR) +#define V850E_CACHE_ISI_ADDR 0xFFFFF072 +#define V850E_CACHE_ISI (*(volatile u16 *)V850E_CACHE_ISI_ADDR) +#define V850E_CACHE_DCC_ADDR 0xFFFFF078 +#define V850E_CACHE_DCC (*(volatile u16 *)V850E_CACHE_DCC_ADDR) + +/* Size of a cache line in bytes. */ +#define V850E_CACHE_LINE_SIZE 16 + +/* For <asm/cache.h> */ +#define L1_CACHE_BYTES V850E_CACHE_LINE_SIZE + + +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +/* Set caching params via the BHC, ICC, and DCC registers. */ +void v850e_cache_enable (u16 bhc, u16 icc, u16 dcc); +#endif /* __KERNEL__ && !__ASSEMBLY__ */ + + +#endif /* __V850_V850E_CACHE_H__ */ |