sparc: copy sparc64 specific files to asm-sparc

Used the following script to copy the files:
cd include
set -e
SPARC64=`ls asm-sparc64`
for FILE in ${SPARC64}; do
	if [ -f asm-sparc/$FILE ]; then
		echo $FILE exist in asm-sparc
	else
		git mv asm-sparc64/$FILE asm-sparc/$FILE
		printf "#include <asm-sparc/$FILE>\n" > asm-sparc64/$FILE
		git add asm-sparc64/$FILE
	fi
done

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

44 files changed, 44 insertions, 7232 deletions

diff --git a/include/asm-sparc64/agp.h b/include/asm-sparc64/agp.h
index e9fcf0e781e..eb8d4b3f516 100644
--- a/include/asm-sparc64/agp.h
+++ b/include/asm-sparc64/agp.h
@@ -1,20 +1 @@
-#ifndef AGP_H
-#define AGP_H 1
-
-/* dummy for now */
-
-#define map_page_into_agp(page) 
-#define unmap_page_from_agp(page) 
-#define flush_agp_cache() mb()
-
-/* Convert a physical address to an address suitable for the GART. */
-#define phys_to_gart(x) (x)
-#define gart_to_phys(x) (x)
-
-/* GATT allocation. Returns/accepts GATT kernel virtual address. */
-#define alloc_gatt_pages(order)		\
-	((char *)__get_free_pages(GFP_KERNEL, (order)))
-#define free_gatt_pages(table, order)	\
-	free_pages((unsigned long)(table), (order))
-
-#endif
+#include <asm-sparc/agp.h>
diff --git a/include/asm-sparc64/apb.h b/include/asm-sparc64/apb.h
index 8f3b57db810..5e236ca6e49 100644
--- a/include/asm-sparc64/apb.h
+++ b/include/asm-sparc64/apb.h
@@ -1,36 +1 @@
-/*
- * apb.h: Advanced PCI Bridge Configuration Registers and Bits
- *
- * Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
- */
-
-#ifndef _SPARC64_APB_H
-#define _SPARC64_APB_H
-
-#define APB_TICK_REGISTER			0xb0
-#define APB_INT_ACK				0xb8
-#define APB_PRIMARY_MASTER_RETRY_LIMIT		0xc0
-#define APB_DMA_ASFR				0xc8
-#define APB_DMA_AFAR				0xd0
-#define APB_PIO_TARGET_RETRY_LIMIT		0xd8
-#define APB_PIO_TARGET_LATENCY_TIMER		0xd9
-#define APB_DMA_TARGET_RETRY_LIMIT		0xda
-#define APB_DMA_TARGET_LATENCY_TIMER		0xdb
-#define APB_SECONDARY_MASTER_RETRY_LIMIT	0xdc
-#define APB_SECONDARY_CONTROL			0xdd
-#define APB_IO_ADDRESS_MAP			0xde
-#define APB_MEM_ADDRESS_MAP			0xdf
-
-#define APB_PCI_CONTROL_LOW			0xe0
-#  define APB_PCI_CTL_LOW_ARB_PARK			(1 << 21)
-#  define APB_PCI_CTL_LOW_ERRINT_EN			(1 << 8)
-
-#define APB_PCI_CONTROL_HIGH			0xe4
-#  define APB_PCI_CTL_HIGH_SERR				(1 << 2)
-#  define APB_PCI_CTL_HIGH_ARBITER_EN			(1 << 0)
-
-#define APB_PIO_ASFR				0xe8
-#define APB_PIO_AFAR				0xf0
-#define APB_DIAG_REGISTER			0xf8
-
-#endif /* !(_SPARC64_APB_H) */
+#include <asm-sparc/apb.h>
diff --git a/include/asm-sparc64/backoff.h b/include/asm-sparc64/backoff.h
index fa1fdf67e35..8ee26d947e0 100644
--- a/include/asm-sparc64/backoff.h
+++ b/include/asm-sparc64/backoff.h
@@ -1,31 +1 @@
-#ifndef _SPARC64_BACKOFF_H
-#define _SPARC64_BACKOFF_H
-
-#define BACKOFF_LIMIT	(4 * 1024)
-
-#ifdef CONFIG_SMP
-
-#define BACKOFF_SETUP(reg)	\
-	mov	1, reg
-
-#define BACKOFF_SPIN(reg, tmp, label)	\
-	mov	reg, tmp; \
-88:	brnz,pt	tmp, 88b; \
-	 sub	tmp, 1, tmp; \
-	set	BACKOFF_LIMIT, tmp; \
-	cmp	reg, tmp; \
-	bg,pn	%xcc, label; \
-	 nop; \
-	ba,pt	%xcc, label; \
-	 sllx	reg, 1, reg;
-
-#else
-
-#define BACKOFF_SETUP(reg)
-#define BACKOFF_SPIN(reg, tmp, label) \
-	ba,pt	%xcc, label; \
-	 nop;
-
-#endif
-
-#endif /* _SPARC64_BACKOFF_H */
+#include <asm-sparc/backoff.h>
diff --git a/include/asm-sparc64/bbc.h b/include/asm-sparc64/bbc.h
index 423a85800aa..06e8b630651 100644
--- a/include/asm-sparc64/bbc.h
+++ b/include/asm-sparc64/bbc.h
@@ -1,225 +1 @@
-/*
- * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
- *        systems.
- *
- * Copyright (C) 2000 David S. Miller (davem@redhat.com)
- */
-
-#ifndef _SPARC64_BBC_H
-#define _SPARC64_BBC_H
-
-/* Register sizes are indicated by "B" (Byte, 1-byte),
- * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
- * "Q" (Quad, 8 bytes) inside brackets.
- */
-
-#define BBC_AID		0x00	/* [B] Agent ID			*/
-#define BBC_DEVP	0x01	/* [B] Device Present		*/
-#define BBC_ARB		0x02	/* [B] Arbitration		*/
-#define BBC_QUIESCE	0x03	/* [B] Quiesce			*/
-#define BBC_WDACTION	0x04	/* [B] Watchdog Action		*/
-#define BBC_SPG		0x06	/* [B] Soft POR Gen		*/
-#define BBC_SXG		0x07	/* [B] Soft XIR Gen		*/
-#define BBC_PSRC	0x08	/* [W] POR Source		*/
-#define BBC_XSRC	0x0c	/* [B] XIR Source		*/
-#define BBC_CSC		0x0d	/* [B] Clock Synthesizers Control*/
-#define BBC_ES_CTRL	0x0e	/* [H] Energy Star Control	*/
-#define BBC_ES_ACT	0x10	/* [W] E* Assert Change Time	*/
-#define BBC_ES_DACT	0x14	/* [B] E* De-Assert Change Time	*/
-#define BBC_ES_DABT	0x15	/* [B] E* De-Assert Bypass Time	*/
-#define BBC_ES_ABT	0x16	/* [H] E* Assert Bypass Time	*/
-#define BBC_ES_PST	0x18	/* [W] E* PLL Settle Time	*/
-#define BBC_ES_FSL	0x1c	/* [W] E* Frequency Switch Latency*/
-#define BBC_EBUST	0x20	/* [Q] EBUS Timing		*/
-#define BBC_JTAG_CMD	0x28	/* [W] JTAG+ Command		*/
-#define BBC_JTAG_CTRL	0x2c	/* [B] JTAG+ Control		*/
-#define BBC_I2C_SEL	0x2d	/* [B] I2C Selection		*/
-#define BBC_I2C_0_S1	0x2e	/* [B] I2C ctrlr-0 reg S1	*/
-#define BBC_I2C_0_S0	0x2f	/* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
-#define BBC_I2C_1_S1	0x30	/* [B] I2C ctrlr-1 reg S1	*/
-#define BBC_I2C_1_S0	0x31	/* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
-#define BBC_KBD_BEEP	0x32	/* [B] Keyboard Beep		*/
-#define BBC_KBD_BCNT	0x34	/* [W] Keyboard Beep Counter	*/
-
-#define BBC_REGS_SIZE	0x40
-
-/* There is a 2K scratch ram area at offset 0x80000 but I doubt
- * we will use it for anything.
- */
-
-/* Agent ID register.  This register shows the Safari Agent ID
- * for the processors.  The value returned depends upon which
- * cpu is reading the register.
- */
-#define BBC_AID_ID	0x07	/* Safari ID		*/
-#define BBC_AID_RESV	0xf8	/* Reserved		*/
-
-/* Device Present register.  One can determine which cpus are actually
- * present in the machine by interrogating this register.
- */
-#define BBC_DEVP_CPU0	0x01	/* Processor 0 present	*/
-#define BBC_DEVP_CPU1	0x02	/* Processor 1 present	*/
-#define BBC_DEVP_CPU2	0x04	/* Processor 2 present	*/
-#define BBC_DEVP_CPU3	0x08	/* Processor 3 present	*/
-#define BBC_DEVP_RESV	0xf0	/* Reserved		*/
-
-/* Arbitration register.  This register is used to block access to
- * the BBC from a particular cpu.
- */
-#define BBC_ARB_CPU0	0x01	/* Enable cpu 0 BBC arbitratrion */
-#define BBC_ARB_CPU1	0x02	/* Enable cpu 1 BBC arbitratrion */
-#define BBC_ARB_CPU2	0x04	/* Enable cpu 2 BBC arbitratrion */
-#define BBC_ARB_CPU3	0x08	/* Enable cpu 3 BBC arbitratrion */
-#define BBC_ARB_RESV	0xf0	/* Reserved			 */
-
-/* Quiesce register.  Bus and BBC segments for cpus can be disabled
- * with this register, ie. for hot plugging.
- */
-#define BBC_QUIESCE_S02	0x01	/* Quiesce Safari segment for cpu 0 and 2 */
-#define BBC_QUIESCE_S13	0x02	/* Quiesce Safari segment for cpu 1 and 3 */
-#define BBC_QUIESCE_B02	0x04	/* Quiesce BBC segment for cpu 0 and 2    */
-#define BBC_QUIESCE_B13	0x08	/* Quiesce BBC segment for cpu 1 and 3    */
-#define BBC_QUIESCE_FD0 0x10	/* Disable Fatal_Error[0] reporting	  */
-#define BBC_QUIESCE_FD1 0x20	/* Disable Fatal_Error[1] reporting	  */
-#define BBC_QUIESCE_FD2 0x40	/* Disable Fatal_Error[2] reporting	  */
-#define BBC_QUIESCE_FD3 0x80	/* Disable Fatal_Error[3] reporting	  */
-
-/* Watchdog Action register.  When the watchdog device timer expires
- * a line is enabled to the BBC.  The action BBC takes when this line
- * is asserted can be controlled by this regiser.
- */
-#define BBC_WDACTION_RST  0x01	/* When set, watchdog causes system reset.
-				 * When clear, BBC ignores watchdog signal.
-				 */
-#define BBC_WDACTION_RESV 0xfe	/* Reserved */
-
-/* Soft_POR_GEN register.  The POR (Power On Reset) signal may be asserted
- * for specific processors or all processors via this register.
- */
-#define BBC_SPG_CPU0	0x01 /* Assert POR for processor 0	*/
-#define BBC_SPG_CPU1	0x02 /* Assert POR for processor 1	*/
-#define BBC_SPG_CPU2	0x04 /* Assert POR for processor 2	*/
-#define BBC_SPG_CPU3	0x08 /* Assert POR for processor 3	*/
-#define BBC_SPG_CPUALL	0x10 /* Reset all processors and reset
-			      * the entire system.
-			      */
-#define BBC_SPG_RESV	0xe0 /* Reserved			*/
-
-/* Soft_XIR_GEN register.  The XIR (eXternally Initiated Reset) signal
- * may be asserted to specific processors via this register.
- */
-#define BBC_SXG_CPU0	0x01 /* Assert XIR for processor 0	*/
-#define BBC_SXG_CPU1	0x02 /* Assert XIR for processor 1	*/
-#define BBC_SXG_CPU2	0x04 /* Assert XIR for processor 2	*/
-#define BBC_SXG_CPU3	0x08 /* Assert XIR for processor 3	*/
-#define BBC_SXG_RESV	0xf0 /* Reserved			*/
-
-/* POR Source register.  One may identify the cause of the most recent
- * reset by reading this register.
- */
-#define BBC_PSRC_SPG0	0x0001 /* CPU 0 reset via BBC_SPG register	*/
-#define BBC_PSRC_SPG1	0x0002 /* CPU 1 reset via BBC_SPG register	*/
-#define BBC_PSRC_SPG2	0x0004 /* CPU 2 reset via BBC_SPG register	*/
-#define BBC_PSRC_SPG3	0x0008 /* CPU 3 reset via BBC_SPG register	*/
-#define BBC_PSRC_SPGSYS	0x0010 /* System reset via BBC_SPG register	*/
-#define BBC_PSRC_JTAG	0x0020 /* System reset via JTAG+		*/
-#define BBC_PSRC_BUTTON	0x0040 /* System reset via push-button dongle	*/
-#define BBC_PSRC_PWRUP	0x0080 /* System reset via power-up		*/
-#define BBC_PSRC_FE0	0x0100 /* CPU 0 reported Fatal_Error		*/
-#define BBC_PSRC_FE1	0x0200 /* CPU 1 reported Fatal_Error		*/
-#define BBC_PSRC_FE2	0x0400 /* CPU 2 reported Fatal_Error		*/
-#define BBC_PSRC_FE3	0x0800 /* CPU 3 reported Fatal_Error		*/
-#define BBC_PSRC_FE4	0x1000 /* Schizo reported Fatal_Error		*/
-#define BBC_PSRC_FE5	0x2000 /* Safari device 5 reported Fatal_Error	*/
-#define BBC_PSRC_FE6	0x4000 /* CPMS reported Fatal_Error		*/
-#define BBC_PSRC_SYNTH	0x8000 /* System reset when on-board clock synthesizers
-				* were updated.
-				*/
-#define BBC_PSRC_WDT   0x10000 /* System reset via Super I/O watchdog	*/
-#define BBC_PSRC_RSC   0x20000 /* System reset via RSC remote monitoring
-				* device
-				*/
-
-/* XIR Source register.  The source of an XIR event sent to a processor may
- * be determined via this register.
- */
-#define BBC_XSRC_SXG0	0x01	/* CPU 0 received XIR via Soft_XIR_GEN reg */
-#define BBC_XSRC_SXG1	0x02	/* CPU 1 received XIR via Soft_XIR_GEN reg */
-#define BBC_XSRC_SXG2	0x04	/* CPU 2 received XIR via Soft_XIR_GEN reg */
-#define BBC_XSRC_SXG3	0x08	/* CPU 3 received XIR via Soft_XIR_GEN reg */
-#define BBC_XSRC_JTAG	0x10	/* All CPUs received XIR via JTAG+         */
-#define BBC_XSRC_W_OR_B	0x20	/* All CPUs received XIR either because:
-				 * a) Super I/O watchdog fired, or
-				 * b) XIR push button was activated
-				 */
-#define BBC_XSRC_RESV	0xc0	/* Reserved				   */
-
-/* Clock Synthesizers Control register.  This register provides the big-bang
- * programming interface to the two clock synthesizers of the machine.
- */
-#define BBC_CSC_SLOAD	0x01	/* Directly connected to S_LOAD pins	*/
-#define BBC_CSC_SDATA	0x02	/* Directly connected to S_DATA pins	*/
-#define BBC_CSC_SCLOCK	0x04	/* Directly connected to S_CLOCK pins	*/
-#define BBC_CSC_RESV	0x78	/* Reserved				*/
-#define BBC_CSC_RST	0x80	/* Generate system reset when S_LOAD==1	*/
-
-/* Energy Star Control register.  This register is used to generate the
- * clock frequency change trigger to the main system devices (Schizo and
- * the processors).  The transition occurs when bits in this register
- * go from 0 to 1, only one bit must be set at once else no action
- * occurs.  Basically the sequence of events is:
- * a) Choose new frequency: full, 1/2 or 1/32
- * b) Program this desired frequency into the cpus and Schizo.
- * c) Set the same value in this register.
- * d) 16 system clocks later, clear this register.
- */
-#define BBC_ES_CTRL_1_1		0x01	/* Full frequency	*/
-#define BBC_ES_CTRL_1_2		0x02	/* 1/2 frequency	*/
-#define BBC_ES_CTRL_1_32	0x20	/* 1/32 frequency	*/
-#define BBC_ES_RESV		0xdc	/* Reserved		*/
-
-/* Energy Star Assert Change Time register.  This determines the number
- * of BBC clock cycles (which is half the system frequency) between
- * the detection of FREEZE_ACK being asserted and the assertion of
- * the CLK_CHANGE_L[2:0] signals.
- */
-#define BBC_ES_ACT_VAL	0xff
-
-/* Energy Star Assert Bypass Time register.  This determines the number
- * of BBC clock cycles (which is half the system frequency) between
- * the assertion of the CLK_CHANGE_L[2:0] signals and the assertion of
- * the ESTAR_PLL_BYPASS signal.
- */
-#define BBC_ES_ABT_VAL	0xffff
-
-/* Energy Star PLL Settle Time register.  This determines the number of
- * BBC clock cycles (which is half the system frequency) between the
- * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L
- * signal.
- */
-#define BBC_ES_PST_VAL	0xffffffff
-
-/* Energy Star Frequency Switch Latency register.  This is the number of
- * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first
- * edge of the Safari clock at the new frequency.
- */
-#define BBC_ES_FSL_VAL	0xffffffff
-
-/* Keyboard Beep control register.  This is a simple enabler for the audio
- * beep sound.
- */
-#define BBC_KBD_BEEP_ENABLE	0x01 /* Enable beep	*/
-#define BBC_KBD_BEEP_RESV	0xfe /* Reserved	*/
-
-/* Keyboard Beep Counter register.  There is a free-running counter inside
- * the BBC which runs at half the system clock.  The bit set in this register
- * determines when the audio sound is generated.  So for example if bit
- * 10 is set, the audio beep will oscillate at 1/(2**12).  The keyboard beep
- * generator automatically selects a different bit to use if the system clock
- * is changed via Energy Star.
- */
-#define BBC_KBD_BCNT_BITS	0x0007fc00
-#define BBC_KBC_BCNT_RESV	0xfff803ff
-
-#endif /* _SPARC64_BBC_H */
-
+#include <asm-sparc/bbc.h>
diff --git a/include/asm-sparc64/chafsr.h b/include/asm-sparc64/chafsr.h
index 85c69b38220..aaab97562a3 100644
--- a/include/asm-sparc64/chafsr.h
+++ b/include/asm-sparc64/chafsr.h
@@ -1,241 +1 @@
-#ifndef _SPARC64_CHAFSR_H
-#define _SPARC64_CHAFSR_H
-
-/* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
-
-/* Comments indicate which processor variants on which the bit definition
- * is valid.  Codes are:
- * ch	-->	cheetah
- * ch+	-->	cheetah plus
- * jp	-->	jalapeno
- */
-
-/* All bits of this register except M_SYNDROME and E_SYNDROME are
- * read, write 1 to clear.  M_SYNDROME and E_SYNDROME are read-only.
- */
-
-/* Software bit set by linux trap handlers to indicate that the trap was
- * signalled at %tl >= 1.
- */
-#define CHAFSR_TL1		(1UL << 63UL) /* n/a */
-
-/* Unmapped error from system bus for prefetch queue or
- * store queue read operation
- */
-#define CHPAFSR_DTO		(1UL << 59UL) /* ch+ */
-
-/* Bus error from system bus for prefetch queue or store queue
- * read operation
- */
-#define CHPAFSR_DBERR		(1UL << 58UL) /* ch+ */
-
-/* Hardware corrected E-cache Tag ECC error */
-#define CHPAFSR_THCE		(1UL << 57UL) /* ch+ */
-/* System interface protocol error, hw timeout caused */
-#define JPAFSR_JETO		(1UL << 57UL) /* jp */
-
-/* SW handled correctable E-cache Tag ECC error */
-#define CHPAFSR_TSCE		(1UL << 56UL) /* ch+ */
-/* Parity error on system snoop results */
-#define JPAFSR_SCE		(1UL << 56UL) /* jp */
-
-/* Uncorrectable E-cache Tag ECC error */
-#define CHPAFSR_TUE		(1UL << 55UL) /* ch+ */
-/* System interface protocol error, illegal command detected */
-#define JPAFSR_JEIC		(1UL << 55UL) /* jp */
-
-/* Uncorrectable system bus data ECC error due to prefetch
- * or store fill request
- */
-#define CHPAFSR_DUE		(1UL << 54UL) /* ch+ */
-/* System interface protocol error, illegal ADTYPE detected */
-#define JPAFSR_JEIT		(1UL << 54UL) /* jp */
-
-/* Multiple errors of the same type have occurred.  This bit is set when
- * an uncorrectable error or a SW correctable error occurs and the status
- * bit to report that error is already set.  When multiple errors of
- * different types are indicated by setting multiple status bits.
- *
- * This bit is not set if multiple HW corrected errors with the same
- * status bit occur, only uncorrectable and SW correctable ones have
- * this behavior.
- *
- * This bit is not set when multiple ECC errors happen within a single
- * 64-byte system bus transaction.  Only the first ECC error in a 16-byte
- * subunit will be logged.  All errors in subsequent 16-byte subunits
- * from the same 64-byte transaction are ignored.
- */
-#define CHAFSR_ME		(1UL << 53UL) /* ch,ch+,jp */
-
-/* Privileged state error has occurred.  This is a capture of PSTATE.PRIV
- * at the time the error is detected.
- */
-#define CHAFSR_PRIV		(1UL << 52UL) /* ch,ch+,jp */
-
-/* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error
- * bits and record the most recently detected errors.  Bits accumulate
- * errors that have been detected since the last write to clear the bit.
- */
-
-/* System interface protocol error.  The processor asserts its' ERROR
- * pin when this event occurs and it also logs a specific cause code
- * into a JTAG scannable flop.
- */
-#define CHAFSR_PERR		(1UL << 51UL) /* ch,ch+,jp */
-
-/* Internal processor error.  The processor asserts its' ERROR
- * pin when this event occurs and it also logs a specific cause code
- * into a JTAG scannable flop.
- */
-#define CHAFSR_IERR		(1UL << 50UL) /* ch,ch+,jp */
-
-/* System request parity error on incoming address */
-#define CHAFSR_ISAP		(1UL << 49UL) /* ch,ch+,jp */
-
-/* HW Corrected system bus MTAG ECC error */
-#define CHAFSR_EMC		(1UL << 48UL) /* ch,ch+ */
-/* Parity error on L2 cache tag SRAM */
-#define JPAFSR_ETP		(1UL << 48UL) /* jp */
-
-/* Uncorrectable system bus MTAG ECC error */
-#define CHAFSR_EMU		(1UL << 47UL) /* ch,ch+ */
-/* Out of range memory error has occurred */
-#define JPAFSR_OM		(1UL << 47UL) /* jp */
-
-/* HW Corrected system bus data ECC error for read of interrupt vector */
-#define CHAFSR_IVC		(1UL << 46UL) /* ch,ch+ */
-/* Error due to unsupported store */
-#define JPAFSR_UMS		(1UL << 46UL) /* jp */
-
-/* Uncorrectable system bus data ECC error for read of interrupt vector */
-#define CHAFSR_IVU		(1UL << 45UL) /* ch,ch+,jp */
-
-/* Unmapped error from system bus */
-#define CHAFSR_TO		(1UL << 44UL) /* ch,ch+,jp */
-
-/* Bus error response from system bus */
-#define CHAFSR_BERR		(1UL << 43UL) /* ch,ch+,jp */
-
-/* SW Correctable E-cache ECC error for instruction fetch or data access
- * other than block load.
- */
-#define CHAFSR_UCC		(1UL << 42UL) /* ch,ch+,jp */
-
-/* Uncorrectable E-cache ECC error for instruction fetch or data access
- * other than block load.
- */
-#define CHAFSR_UCU		(1UL << 41UL) /* ch,ch+,jp */
-
-/* Copyout HW Corrected ECC error */
-#define CHAFSR_CPC		(1UL << 40UL) /* ch,ch+,jp */
-
-/* Copyout Uncorrectable ECC error */
-#define CHAFSR_CPU		(1UL << 39UL) /* ch,ch+,jp */
-
-/* HW Corrected ECC error from E-cache for writeback */
-#define CHAFSR_WDC		(1UL << 38UL) /* ch,ch+,jp */
-
-/* Uncorrectable ECC error from E-cache for writeback */
-#define CHAFSR_WDU		(1UL << 37UL) /* ch,ch+,jp */
-
-/* HW Corrected ECC error from E-cache for store merge or block load */
-#define CHAFSR_EDC		(1UL << 36UL) /* ch,ch+,jp */
-
-/* Uncorrectable ECC error from E-cache for store merge or block load */
-#define CHAFSR_EDU		(1UL << 35UL) /* ch,ch+,jp */
-
-/* Uncorrectable system bus data ECC error for read of memory or I/O */
-#define CHAFSR_UE		(1UL << 34UL) /* ch,ch+,jp */
-
-/* HW Corrected system bus data ECC error for read of memory or I/O */
-#define CHAFSR_CE		(1UL << 33UL) /* ch,ch+,jp */
-
-/* Uncorrectable ECC error from remote cache/memory */
-#define JPAFSR_RUE		(1UL << 32UL) /* jp */
-
-/* Correctable ECC error from remote cache/memory */
-#define JPAFSR_RCE		(1UL << 31UL) /* jp */
-
-/* JBUS parity error on returned read data */
-#define JPAFSR_BP		(1UL << 30UL) /* jp */
-
-/* JBUS parity error on data for writeback or block store */
-#define JPAFSR_WBP		(1UL << 29UL) /* jp */
-
-/* Foreign read to DRAM incurring correctable ECC error */
-#define JPAFSR_FRC		(1UL << 28UL) /* jp */
-
-/* Foreign read to DRAM incurring uncorrectable ECC error */
-#define JPAFSR_FRU		(1UL << 27UL) /* jp */
-
-#define CHAFSR_ERRORS		(CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
-				 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
-				 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
-				 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
-				 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
-#define CHPAFSR_ERRORS		(CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \
-				 CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \
-				 CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
-				 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
-				 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
-				 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
-				 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
-#define JPAFSR_ERRORS		(JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \
-				 JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \
-				 CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \
-				 JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \
-				 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \
-				 CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \
-				 CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \
-				 CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \
-				 JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \
-				 JPAFSR_FRC | JPAFSR_FRU)
-
-/* Active JBUS request signal when error occurred */
-#define JPAFSR_JBREQ		(0x7UL << 24UL) /* jp */
-#define JPAFSR_JBREQ_SHIFT	24UL
-
-/* L2 cache way information */
-#define JPAFSR_ETW		(0x3UL << 22UL) /* jp */
-#define JPAFSR_ETW_SHIFT	22UL
-
-/* System bus MTAG ECC syndrome.  This field captures the status of the
- * first occurrence of the highest-priority error according to the M_SYND
- * overwrite policy.  After the AFSR sticky bit, corresponding to the error
- * for which the M_SYND is reported, is cleared, the contents of the M_SYND
- * field will be unchanged by will be unfrozen for further error capture.
- */
-#define CHAFSR_M_SYNDROME	(0xfUL << 16UL) /* ch,ch+,jp */
-#define CHAFSR_M_SYNDROME_SHIFT	16UL
-
-/* Agenid Id of the foreign device causing the UE/CE errors */
-#define JPAFSR_AID		(0x1fUL << 9UL) /* jp */
-#define JPAFSR_AID_SHIFT	9UL
-
-/* System bus or E-cache data ECC syndrome.  This field captures the status
- * of the first occurrence of the highest-priority error according to the
- * E_SYND overwrite policy.  After the AFSR sticky bit, corresponding to the
- * error for which the E_SYND is reported, is cleare, the contents of the E_SYND
- * field will be unchanged but will be unfrozen for further error capture.
- */
-#define CHAFSR_E_SYNDROME	(0x1ffUL << 0UL) /* ch,ch+,jp */
-#define CHAFSR_E_SYNDROME_SHIFT	0UL
-
-/* The AFSR must be explicitly cleared by software, it is not cleared automatically
- * by a read.  Writes to bits <51:33> with bits set will clear the corresponding
- * bits in the AFSR.  Bits associated with disrupting traps must be cleared before
- * interrupts are re-enabled to prevent multiple traps for the same error.  I.e.
- * PSTATE.IE and AFSR bits control delivery of disrupting traps.
- *
- * Since there is only one AFAR, when multiple events have been logged by the
- * bits in the AFSR, at most one of these events will have its status captured
- * in the AFAR.  The highest priority of those event bits will get AFAR logging.
- * The AFAR will be unlocked and available to capture the address of another event
- * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is
- * cleared.  For example, if AFSR.CE is detected, then AFSR.UE (which overwrites
- * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked
- * and ready for another event, even though AFSR.CE is still set.  The same rules
- * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR.
- */
-
-#endif /* _SPARC64_CHAFSR_H */
+#include <asm-sparc/chafsr.h>
diff --git a/include/asm-sparc64/chmctrl.h b/include/asm-sparc64/chmctrl.h
index 859b4a4b0d3..eb757b483b3 100644
--- a/include/asm-sparc64/chmctrl.h
+++ b/include/asm-sparc64/chmctrl.h
@@ -1,183 +1 @@
-#ifndef _SPARC64_CHMCTRL_H
-#define _SPARC64_CHMCTRL_H
-
-/* Cheetah memory controller programmable registers. */
-#define CHMCTRL_TCTRL1		0x00 /* Memory Timing Control I		*/
-#define CHMCTRL_TCTRL2		0x08 /* Memory Timing Control II	*/
-#define CHMCTRL_TCTRL3		0x38 /* Memory Timing Control III	*/
-#define CHMCTRL_TCTRL4		0x40 /* Memory Timing Control IV	*/
-#define CHMCTRL_DECODE1		0x10 /* Memory Address Decode I		*/
-#define CHMCTRL_DECODE2		0x18 /* Memory Address Decode II	*/
-#define CHMCTRL_DECODE3		0x20 /* Memory Address Decode III	*/
-#define CHMCTRL_DECODE4		0x28 /* Memory Address Decode IV	*/
-#define CHMCTRL_MACTRL		0x30 /* Memory Address Control		*/
-
-/* Memory Timing Control I */
-#define TCTRL1_SDRAMCTL_DLY	0xf000000000000000UL
-#define TCTRL1_SDRAMCTL_DLY_SHIFT     60
-#define TCTRL1_SDRAMCLK_DLY	0x0e00000000000000UL
-#define TCTRL1_SDRAMCLK_DLY_SHIFT     57
-#define TCTRL1_R		0x0100000000000000UL
-#define TCTRL1_R_SHIFT 		      56
-#define TCTRL1_AUTORFR_CYCLE	0x00fe000000000000UL
-#define TCTRL1_AUTORFR_CYCLE_SHIFT    49
-#define TCTRL1_RD_WAIT		0x0001f00000000000UL
-#define TCTRL1_RD_WAIT_SHIFT	      44
-#define TCTRL1_PC_CYCLE		0x00000fc000000000UL
-#define TCTRL1_PC_CYCLE_SHIFT	      38
-#define TCTRL1_WR_MORE_RAS_PW	0x0000003f00000000UL
-#define TCTRL1_WR_MORE_RAS_PW_SHIFT   32
-#define TCTRL1_RD_MORE_RAW_PW	0x00000000fc000000UL
-#define TCTRL1_RD_MORE_RAS_PW_SHIFT   26
-#define TCTRL1_ACT_WR_DLY	0x0000000003f00000UL
-#define TCTRL1_ACT_WR_DLY_SHIFT	      20
-#define TCTRL1_ACT_RD